MK1726-01A RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 8

Technical content

Features

  • Packaged in 8-pin SOIC
  • Provides a spread spectrum output clock
  • Supports flat panel controllers
  • Accepts a clock or crystal input (provides same fr equency dithered output)
  • Input frequency range of 4 to 32 MHz
  • Output frequency range of 4 to 32 MHz
  • Center and down spread
  • Peak reduction by 8 dB to 16 dB typical on 3rd through 19t h odd harmonics
  • Low EMI feature can be disabled
  • Includes power down
  • Operating voltage of 3.3 V
  • Advanced, low-power CMOS process Block Diagram PLL Clock Synthesis and Spread Spectrum Circuitry S1:0 Spread Direction FRSEL SSCLK GND VDD Clock Buffer/ Crystal Ocsillator X1/CLK External caps required for with crystal for accurate tuning of the clock

LOW EMI CLOCK GENERATOR SSCG IDT™ / ICS™ LOW EMI CLOCK GENERATOR 2 MK1726-01A REV D 071207 Pin Assignment Spread Direction and Percentage Select Table 0 = connect to GND M = unconnected (floating) 1 = connect directly to VDD Pin Descriptions X1/ICLK GND VDD FRSEL SSCLK X21 8 pin (150 mil) SOIC Pin 3 Pin 4 Spread Direction Spread Percentage 0 0 Center ±1.4 0 M Center ±1.1 0 1 Center ±0.6 M 0 Center ±0.5 MM N o S p r e a d - M1 D o w n - 1 . 6

10 D o w n -

2 . 0 1M D o w n - 0 . 7 11 D o w n - 3 . 0 FRSEL (pin 6) Input Freq. Range Multiplier Output Freq. Range 0 4.0 to 8.0 MHz X1 4.0 to 8.0 MHz 1 8.0 to 16.0MHz X1 8.0 to 16.0MHz M 16.0 to 32.0MHz X1 16.0 to 32.0MHz Pin Number Pin Name Pin Type Pin Description 1 X1/ICLK Input Connect to a 4 to 32 MHz crystal or clock. 2 GND Power Connect to ground. 3 S1 Input Function select 1 input. Selects spread amount and direction per table above. (default-internal mid-level). 4 S0 Input Function select 0 input. Selects spread amount and direction per table above. (default-internal mid-level).

5 SSCLK Output Clock output with Spread spectrum

6 FRSEL Input Function select for input frequency range. Default to mid level “M”. 7 VDD Power Connect to +3.3 V. 8 X2 XO Crystal connection to a 4 to 32 MHz crystal. Leave unconnected for clock

LOW EMI CLOCK GENERATOR SSCG IDT™ / ICS™ LOW EMI CLOCK GENERATOR 3 MK1726-01A REV D 071207 External Components The MK1726-01A requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 7 and 2, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Tri-level Select Pin Operation The S1, S0 select pins are tri-level, meaning they have three separate states to make the selections shown in the table on page 2. To select the M (mid) level, the connection to these pins must be eliminated by either floating them originally, or tri-stating the GPIO pins which drive the select pins. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the MK1726-01A. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Crystal Information The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (C L - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used. Spread Spectrum Profile The MK1726-01A low EMI clock generator uses an optimized frequency slew rate algorithm to facilitate down stream tracking of zero delay buffers and other PLL devices. The frequency modulation amplitude is constant with variations of the input frequency. Time Frequency Modulation Rate

LOW EMI CLOCK GENERATOR SSCG IDT™ / ICS™ LOW EMI CLOCK GENERATOR 4 MK1726-01A REV D 071207 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1726-01A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 125 ° C Soldering Temperature 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 ° C Power Supply Voltage (measured in respect to GND) +3.0 3.63 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 3.3 3.63 V Supply Current IDD No load, at 3.3 V, Fin=24 MHz 23 30 mA No load, at 3.3 V, Fin=12 MHz 25 mA No load, at 3.3 V, Fin=32 MHz 35 mA Input High Voltage V IH 0.85VDD VDD VDD V Input middle Voltage V IHM 0.4VDD 0.5VDD 0.6VDD V Input Low Voltage V IL 0.0 0.0 0.15VDD V Output High Voltage V OH CMOS, IOH = -4 mA 2.4 V Output High Voltage V OH IOH = -6 mA 2.0 V

LOW EMI CLOCK GENERATOR SSCG IDT™ / ICS™ LOW EMI CLOCK GENERATOR 5 MK1726-01A REV D 071207 Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Thermal Characteristics Output Low Voltage V OL IOL = -4 mA 0.4 V IOL = -10 mA 1.2 V Input Capacitance C IN1 S0, S1, FRSEL pins 4 6 pF CIN2 X1, X2 pins 6 9 pF Parameter Symbol Conditions Min. Typ. Max. Units Input Clock Frequency 4 32 MHz Output Clock Frequency 4 32 MHz Input Clock Duty Cycle Time above VDD/2 40 60 % Output Clock Duty Cycle Time above 1.5 V 45 50 55 % Cycle to cycle Jitter Fin=4 MHz, Fout=4 MHz 675 800 ps Cycle to cycle Jitter Fin=8 MHz, Fout=8 MHz 260 450 ps Output Rise Time t EMI Peak Frequency Reduction 8 to 16 dB Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W Thermal Resistance Junction to Case θJC 40 ° C/W Parameter Symbol Conditions Min. Typ. Max. Units

LOW EMI CLOCK GENERATOR SSCG IDT™ / ICS™ LOW EMI CLOCK GENERATOR 6 MK1726-01A REV D 071207 Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK1726-01ASLF 172601ASL Tubes 8-pin SOIC 0 to +85 ° C MK1726-01ASLFTR 172601ASL Tape and Reel 8-pin SOIC 0 to +85 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

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