MK1716-01

MK1716-01 RENESAS | Alldatasheet

Document overview

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Technical content

Features

• Packaged in 28-pin SSOP
• Operating voltage 3.3 V
• Serially programmable: user determines the output frequency via a 3-wire interface
• Highly accurate frequency generation
• M/N Multiplier PLL: M = 1..2048, N = 1..1024
• Eliminates the need for custom Quartz Oscillators
• Input crystal frequency of 5-27 MHz
• Input clock frequency of 3-50 MHz
• Output clock frequencies of 250 kHz to 133.33 MHz
• Spread Spectrum frequency modulation for reduced s ystem EMI
• Center or down spread ±0.5% min to 4% total
• Selectable 32 kHz and 120 kHz modulation rate
• Advanced, low power, sub-micron CMOS process
• Separate VDD ‘s for each bank of 4 outputs
• Output skew <250 ps within output bank
• OE control on outputs Block Diagram Clock Buffer/ Crystal Ocsillator VDD GND PLL with Spread SpectrumCircuit REF OUT CLKA CLKB VDDIOA VDDIOB DIV A DIV B OE Crystal or clock input External capacitors are required with a crystal input. X1/ICLK SCLK DATA STROBE

SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER SSCG IDT™ SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER 2 MK1716-01 REV H 051310 Pin Assignment Note: Clock A and Clock B can be at the same frequency or not, but must be powered by separate VDDs. Pin Descriptions GND GND GND GND CLKA CLKA GND CLKB CLKB CLKA CLKB VDDIOB CLKA CLKB VDDIOA VDD VDD VDD VDD VDD X1/ICLK REFOUT OE SCLK DATA X2 STROBE GND Pin Number Pin Name Pin Type Pin Description 1 DATA Input Serial shift register data input. 2 X2 XO Connect to crystal. Leave open for clock input. 3 X1/ICLK XI Connect this pin to a crystal or external clock input. 4 REFOUT Output Reference clock output. 5-6 VDD P Connect to +3.3 V. 7-9 GND P Connect to ground. 10-13 CLKA Output Output clock. 14 VDDIOA P Power supply to CLKA. 15 VDDIOB P Power supply to CLKB. 16-19 CLKB Output Output clock. 20-21 GND P Connect to ground. 22-24 VDD P Connect to +3.3 V. 25 OE Input Output enable active high. 26 SRCLK Input Serial shift register clock. 27 STROBE Input Strobe to load data. See timing diagram. Use external 250 kOhm pull-up. 28 GND Input Connect to ground.

The STROBE pin must have an external 250 kOhm pull-up resistor to acheive the Initial State. The input crystal range for the MK1716-01 is 5 MHz to 27 MHz. TM software are written in DATA pin in this order: MSB (left most bit) first. to the internal latch and the CLK output will lock within 10 ms. SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will change accordingly. clocked into the MK1716-01 in order to avoid unintended changes on the output clocks. Figure 2. Timing Diagram for Programming the MK1716-01

SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER SSCG IDT™ SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER 4 MK1716-01 REV H 051310 External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. STROBE Pull-up Resistor In order for the device to start up in the default state, a 250 kOhm pull-up resistor is required. Decoupling Capacitors As with any high-performance mixed-signal IC, the MK1716-01 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (C L -6 pF)*2. In this equation, CL= crystal load capacitance in pF . Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Ea ch 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to th e g round via. 2) The external crystal should be mounted just next to the de vice with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead t hey should be separated and away from other traces. 3) T o minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to each clock output. 4) An opt imum layout is one with all components on the same side of the board, minimizing vias through other signal la yers. MK1716-01 Configuration Capabilities The architecture of the MK1716-01 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The MK1716-01 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as: Output Freq. = (Ref. Freq)*(M/N)/Output Divide Each output clock bank has an separate voltage drive control pin (VDDIOA and VDDIOB) that sets the output clock voltage swing. IDT VersaClock Software IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output

SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER SSCG IDT™ SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER 5 MK1716-01 REV H 051310 frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. Spread Spectrum Modulation The MK1716-01 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system’s electro-magnetic interference (EMI). The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. Spread Spectrum Modulation can be applied as either “center spread” or “down spread”. During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. The MK1716-01 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between ±0.125% to ±2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%. Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified. Spread Spectrum Modulation Rate The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of “down-circuit” PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30-33 kHz. For other applications, a 120 kHz modulation option is available. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1716-01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Condition Min. Typ. Max. Units Supply Voltage, VDD Referenced to GND 7 V Inputs Referenced to GND -0.5 VDD + 0.5 V Clock Outputs Referenced to GND -0.5 VDD + 0.5 V Storage Temperature -65 150 ° C Soldering Temperature Max 10 seconds 260 ° C

SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER SSCG IDT™ SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER 6 MK1716-01 REV H 051310 Recommended Operation Conditions VDD=3.3 V ±10% Ambient temperature 0 to +70° C, unless stated otherwise Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 ° C Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V Power Supply Ramp Time 4 ms Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.00 3.60 V Operating Supply Current Input High Voltage IDD Configuration Dependent See VersaClockTM mA Ex. 14.31818 MHz crystal, VDD=VDDIO=3.3V, 55 mA OE = 0 15 mA VDDIO Voltage VDDIOA and VDDIOB 2.25 VDD V Input High Voltage V IH ICLK only (VDD/2)+1 V Input Low Voltage V IL ICLK only (VDD/2)-1 V Input High Voltage V IH VDD-0.5 V Input Low Voltage V IL OE, SCLK, DATA, STROBE 0.8 V Output High Voltage V OH IOH = -8 mA 2.4 V Output Low Voltage V OL IOL = 8 mA 0.4 V Output High Voltage, CMOS level VOH IOH = -4 mA VDD-0.4 V Short Circuit Current CLK outputs + 70 mA Nominal Output Impedance ZOUT 20 Ω Input Capacitance C IN OE pin 4 pF Internal Pull-down Resistor RPD CLK outputs 510 k Ω Internal Pull-up Resistor R PU OE pin 240 k Ω

SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER SSCG IDT™ SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER 7 MK1716-01 REV H 051310 VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C, unless stated otherwise Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55% Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency F IN Fundamental crystal 5 27 MHz Input clock 2 50 MHz Output Frequency VDD=3.3 V 0.25 133.33 MHz Output Clock Rise Time t OR 20% to 80%, Note 1 0.8 ns Output Clock Fall Time t OF 80% to 20%, Note 1 0.8 ns Output Clock Duty Cycle Note 2 40 49-51 60 % Power-up Time STROBE goes high until stable CLK out 31 0 m s OE goes high until stable CLK out, PLL already running 50 ns Maximum Output Jitter, short term t j Reference clock, Note 1 ±300 ps Maximum Output Jitter, short term tj All other clocks, Note 1 configuration dependent ±200 ps Skew on the same bank Same voltage and frequency 150 ps Skew bank to bank Same voltage and frequency 150 ps Spread Spectrum Modulation Amount Center or down spread 0.5 4.0 % Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 135 ° C/W θJA 1 m/s air flow 93 ° C/W θJA 3 m/s air flow 78 ° C/W Thermal Resistance Junction to Case θJC 60 ° C/W

SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER SSCG IDT™ SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER 8 MK1716-01 REV H 051310 Package Outline and Package Dimensions (28-pin SSOP, 150 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK1716-01RLF Tubes 28-pin SSOP 0 to +70 ° C MK1716-01RLFT Tape and Reel 28-pin SSOP 0 to +70 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 D 9.80 10.00 .386 .394 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e .635 Basic .025 Basic L 0.40 1.27 0.016 0.050 α 0° 8° 0° 8°

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