MK1714-01 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 10

Technical content

Features

  • Packaged in 20 pin tiny SSOP
  • Operating voltage of 3.3V or 5V
  • Multiplier modes of x1, x2, x3, x4, x5, and x6
  • Inexpensive 10 - 25 MHz crystal or clock input
  • OE pin tri-states the outputs for board testing
  • Power down pin stops the outputs low
  • Selectable frequency spread
  • Spread can be turned on or off
  • Advanced, low power CMOS process
  • Duty cycle of 40/60
  • Industrial temperature range available
  • Available in Pb (lead) free package
  • Input frequency of 5 - 140 MHz (depending on mode)
  • Output frequency of 20 - 150 MHz (depending on mode) Block Diagram PLL Clock Multiplier and Spread Spectrum Circuitry Input Crystal or Clock OE (both outputs) REF Crystal Oscillator S4:0 PD Low EMI Enable Clock Out XSEL GND VDD

SPREAD SPECTRUM MULTIPLIER CLOCK SSCG IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK 2 MK1714-01 REV L 051310 Pin Assignment Pin Descriptions Note: When changing the input frequency, the LEE pin must be set low for minimum of 10µs to allow the PLL to lock to the new frequency. Alternatively, the PD pin may be set low while changing frequencies. GND GND XSEL S2 LEE CLK 3VDD VDD GND 18 PD 1X2 X1 OE

20 REF

20 pin (150 mil) SSOP (QSOP) Pin Number Pin Name Pin Type Pin Description 1 X2 XO Crystal connection. Connect to parallel mode crystal. Leave open for clock. 2 X1 XI Crystal connection. Connect to parallel mode crystal or clock. 3 VDD Power Connect to VDD. Must be same value as other VDD. 4 VDD Power Connect to VDD. Must be same value as other VDD. 5 S4 Input Select pin 4. Determines multiplier and spread amount per table on following page. Internal pull-down. 6 S3 Input Select pin 3. Determines multiplier and spread amount per table on following page. Internal pull-up. 7 GND Power Connect to ground. 8 GND Power Connect to ground. 9 S2 Input Select pin 2. Determines multiplier and spread amount per table on following page. Internal pull-up. 10 CLK Output Clock output dependent on input, multip lier, and spread amount per table on following page. 11 XSEL Input Connect to VDD for crystal input, or GND for CLK input. Internal pull-down. 12 LEE Input Low EMI Enable. Turns on spread spectrum on CLK when high. Internal pull-up. 13 GND Power Connect to ground. 14 S1 Input Select pin 1. Determines multiplier and spr ead amount per table on following page. Internal pull-up. 15 NC - No connect. Do not connect anything to this pin. 16 S0 Input Select pin 0. Determines multiplier and spr ead amount per table on following page. Internal pull-up. 17 GND Power Connect to ground. 18 PD Input Power down. Turns off chip when low. Outputs stop low. Leave open or connected to VDD if power down is not required. 19 OE Input Output enable. Tri-states a ll outputs when low. Internal pull-up. 20 REF Output Reference clock output from cryst al oscillator. This clock is not spread.

SPREAD SPECTRUM MULTIPLIER CLOCK SSCG IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK 3 MK1714-01 REV L 051310 Clock Output Select Table (MHz) For S4:S0, 0 = connect to GND, 1 = connect to VDD. Direction: C = center spread, D = down spread, DC = down + center spread. Amount = spread amount. For example, for a 40 MHz output clock spread down 1%, the lowest frequency is 39.60 MHz. Contact IDT (www.idt.com/go/clockhelp) with your exact output frequency for details on spread direction and amount. S4 S3 S2 S1 S0 Input Range Multiplier Output Range Direction Amount (%) 00 0 0 0 40 - 140 x1 40 - 140 C ±1.25 00 0 0 1 60 - 140 x1 60 -140 C ±0.5 00 010 - t e s t - - - 00 0 1 1 40 - 100 x1 40 - 80 C ±1 00 1 0 0 10 - 25 x2 20 - 50 C ±1 00 1 0 1 20 - 50 x2 40 - 80 C ±0.5 00 1 1 0 10 - 30 x2 20 - 60 DC +0.25, -1.25 00 1 1 1 30 - 40 x2 60 - 80 DC +0.5, -1 01 0 0 0 10 - 50 x3 30 - 150 C ±1 01 0 0 1 15 - 35 x4 60 - 140 C ±0.5 01 0 1 0 40 - 60 x1 40 - 60 DC +0.5, -1.5 01 0 1 1 60 - 120 x1 60 - 120 D -1 01 1 0 0 60 - 140 x1 60 - 140 DC +0.5, -1.5 01 1 0 1 60 - 120 x1 60 - 120 DC +0.5, -1.5 01 1 1 0 30 - 60 x1 30 - 60 D -2.5 01 1 1 1 40 - 100 x1 40 - 100 DC +0.5, -1.5 10 0 0 0 15 -25 x4 60 - 100 D -1 10 0 0 1 10 - 13.33 x3 30 - 40 D -1.5 10 0 1 0 30 - 100 x1 30 - 100 C ±0.5 10 0 1 1 30 - 80 x1 30 - 80 DC +0.25, -1.25 10 100 - t e s t - - - 10 1 0 1 5 - 20 x4 20 - 80 DC +0.5, -3 10 110 - t e s t - - - 10 1 1 1 10 - 17 x8 80 - 136 DC +0.5, -1 11 0 0 0 10 - 25 x4 40 - 100 C ±1 11 0 0 1 8 - 20 x5 40 - 100 C ±1 11 0 1 0 10 - 20 x6 60 - 120 C ±1 11 0 1 1 10 - 15 x8 80 - 120 C ±1 11 1 0 0 10 - 20 x4 40 - 80 DC +0.25, -1.25 11 1 0 1 8 - 16 x5 40 - 80 DC +0.5, -1.5 11 1 1 0 8 - 23 x6 48 - 138 DC +0.5, -2 11 1 1 1 8 - 16 x8 64 - 128 DC +0.5, -1.5

SPREAD SPECTRUM MULTIPLIER CLOCK SSCG IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK 4 MK1714-01 REV L 051310 External Components The MK1714-01 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Tuning Load Capacitors Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal L-6)*2. In this equation, CL= crystal load capacitance in pF . Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be If the output frequency is not critical, external load capacitors are not necessary. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as po ssible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the de vice is less critical. 2) The external crystal should be mounted just next to the de vice with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead t hey should be separated and away from other traces. 3) T o minimize EMI the 33Ω series termination resistor, if ne eded, should be placed close to the clock output. 4) An opt imum layout is one with all components on the same side of the board, minimizing vias through other signal la yers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK1714-01. This includes signal traces just underneath the device, or on layers adjacent to the groun d p lane layer used by the device. Powerup Considerations To insure proper operation of the spread spectrum generation circuit, some precautions must be taken in the implementation of the MK1714-01. An inpu t signal should not be applied to X1 until VDD is sta ble (within 10% of its final value). This requirement can be easily met by operating the MK1714-01 and the X1 sour ce from the same power supply. This requirement is not applicable if a crystal is used. LEE should not be enabled (taken high) until after the power supplies and input clock are stable. This requirement ca n be met by direct control of LEE by system logic; for example, a “power good” signal. Another solution is to leave LEE unconnected but place a 0.01µF capacitor to ground. The pull-up resistor on LEE will charge the capacitor and pr ovide approximately a 700µs delay until spread spectrum is en abled. 3) If the input frequency is changed during operation, disable spread spectrum until the input clock stabilizes at t he new frequency.

SPREAD SPECTRUM MULTIPLIER CLOCK SSCG IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK 5 MK1714-01 REV L 051310 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1714-01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Unless stated otherwise, VDD = 3.3V or 5V, Ambient Temperature -40 to +85° C Item Rating Supply Voltage, VDD -0.5 to 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 175 ° C Soldering Temperature 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.0 +5.5 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 5.5 V Supply Current IDD No load, at 3.3V 26 mA IDD No load, at 5V 40 mA Input High Voltage V IH Select inputs, OE, PD 2V Input Low Voltage V IL Select inputs, OE, PD 0.8 V Output High Voltage V OH IOH = -8 mA VDD-0.4 V Output Low Voltage V OL IOL = 8mA 0.4 V Short Circuit Current I OS Each output ±50 mA On Chip Pull-up Resistor, inputs RPU Except X1, S4 500 k Ω On-Chip Pull-down Resistor, input RPD S4 pin only 500 k Ω Input Capacitance Except X1, X2 7 pF

SPREAD SPECTRUM MULTIPLIER CLOCK SSCG IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK 6 MK1714-01 REV L 051310 Unless stated otherwise, VDD = 3.3V or 5V, Ambient Temperature -40 to +85° C Thermal Characteristics Marking Diagram (MK1714-01RLF) Marking Diagram (MK1714-01RILF) Notes: 1. ## 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. “I” designates industrial temperaure range. 4. “L ” designates Pb (lead) free package. Parameter Symbol Conditions Min. Typ. Max. Units Input Crystal Frequency 10 25 MHz Input Clock Frequency 10 150 MHz Output Rise Time tOR 0.8 to 2.0V 1.5 ns Output Fall Time tOF 2.0 to 0.8V 1.5 ns One Sigma Jitter CLK 40 ps Absolute Jitter CLK ±150 Output Clock Duty Cycle at VDD/2 40 50 60 % Output Frequency 2 200 MHz Output Frequency Synthesis Error 1p pm Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θ JA Still air 135 ° C/W θJA 1 m/s air flow 93 ° C/W θJA 3 m/s air flow 78 ° C/W Thermal Resistance Junction to Case θJC 60 ° C/W 20 11 MK1714-01RL YYWW 1 10 20 11 MK171401RIL YYWW

SPREAD SPECTRUM MULTIPLIER CLOCK SSCG IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK 7 MK1714-01 REV L 051310 5. Bottom marking: (origin). Origin = country of origin of not USA.

SPREAD SPECTRUM MULTIPLIER CLOCK SSCG IDT™ SPREAD SPECTRUM MULTIPLIER CLOCK 8 MK1714-01 REV L 051310 Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK1714-01RLF see page 7 Tubes 20-pin SSOP 0 to +70 ° C MK1714-01RLFTR Tape and Reel 20-pin SSOP 0 to +70 ° C MK1714-01RILF Tubes 20-pin SSOP -40 to 85 ° C MK1714-01RILFTR Tape and Reel 20-pin SSOP -40 to 85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE A AA e - C - b .10 (.004) C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1 . 3 51 . 7 5. 0 5 3. 0 6 9 A1 0.10 0.25 .0040 .010 A2 -- 1.50 -- .059 b 0.20 0.30 0.008 0.012 C 0 . 1 80 . 2 5. 0 0 7. 0 1 0 D 8 . 5 58 . 7 5. 3 3 7. 3 4 4 E 5 . 8 06 . 2 0. 2 2 8. 2 4 4 E1 3.80 4.00 .150 .157 e 0.635 Basic 0.025 Basic L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com MK1714-01 SPREAD SPECTRUM MULTIPLIER CLOCK SSCG

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.