MK1707 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: mamiller
  • PDF pages: 8

Technical content

Features

  • Packaged in 8-pin SOIC
  • Pb-free package
  • Industrial temperature range available
  • Provides a spread spectrum output clock
  • Supports ATI’s flat panel controllers
  • Guaranteed to +85° C operation
  • Accepts a clock input, provides same frequency dithered output
  • Good for all VGA modes from 80 to 167 MHz
  • Peak reduction by 7dB - 14dB typical on 3rd - 19th odd har monics
  • Low EMI feature can be disabled
  • Includes Power-down
  • Operating voltage of 3.3 V or 5 V
  • Advanced, low-power CMOS process Block Diagram PLL Clock Synthesis and Spread Spectrum Circuitry ICLK Input Buffer S1:0 Spread Direction Low EMI Enable Clock Out GND VDD

LOW EMI CLOCK GENERATOR SSCG IDT® LOW EMI CLOCK GENERATOR 2 MK1707 REV L 072312 Pin Assignment Spread Di rection and Percentage Select Table 0 = connect to GND M = unconnected (floating) 1 = connect directly to VDD Pin Descriptions ICLK VDD GND CLK LEE SD1 8 pin (150 mil) SOIC SD Pin 8 Pin 7 Pin 6 Spread Direction Spread Percentage (%) 00 0D o w n 0 . 6 00 MD o w n 0 . 8 00 1D o w n 1 . 2 5 0M 0 Down Center +0.5, -1.5 0M MD o w n 2 0M 1 Down Center +0.5, -2.5 01 0 Down Center +0.5, -3

01 MD o w n 5

10 0 Center ±0.35 10 MC e n t e r ± 0 . 5 10 1C e n t e r ± 0 . 7 1M 0C e n t e r ± 0 . 8 1M MC e n t e r ± 1 . 1 1M 1C e n t e r ± 1 . 4 11 0T e s t T e s t 11 MC e n t e r ± 2 . 5 11 1 Power Down - Pin Number Pin Name Pin Type Pin Description 1 ICLK Input Connect to graphics input clock. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 CLK Output Spread spectrum clock output per table above. 5 LEE Input Low EMI enable. Turns on spread spectrum when high. Internal pull-up resistor. 6 S0 Input Function select 0 input. Selects spread amount and direction per table above. Internal mid-level. 7 S1 Input Function select 1input. Selects spread amount and direction per table above. Internal mid-level. 8 SD Input Spread direction select input. Selects the direction of spread per table above. Internal pull-up resistor.

LOW EMI CLOCK GENERATOR SSCG IDT® LOW EMI CLOCK GENERATOR 3 MK1707 REV L 072312 External Components The MK1707 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 2 and 3, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50 Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 Tri-level Select Pin Operation The S1, S0 select pins are tri-level, meaning they have three separate states to make the selections shown in the table on page 2. To select the M (mid) level, the connection to these pins must be eliminated by either floating them originally, or tri-stating the GPIO pins which drive the select pins. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Th e 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to th e g round via. 2) T o minimize EMI, the 33Ω series termination resistor (if n eeded) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the MK1 707. This includes signal traces just underneath the d evice, or on layers adjacent to the ground plane layer used b y the device. Powerup Considerations To insure proper operation of the spread spectrum generation circuit, some precautions must be taken while utilizing the MK1707. 1. An input signal should not be applied to ICLK until VDD is sta ble (within 10% of its final value). This requirement can ea sily be met by operating the MK1707 and then ICLK sour ce from the same power supply. 2. LEE sh ould not be enabled (taken high) until after the po wer supplies and input clock are stable. This requirement can b e met by direct control of LEE by system logic - for example, a “power good” signal. Another solution is to leave LEE unconnected to anything but a 0.01 μF capacitor to g round. The internal pullup resistor on LEE will charge the capa citor and provide approximately a 700μs delay until spr ead spectrum is enabled. 3. If the inp ut frequency is changed during operation, disab le spread spectrum until the input clock stabilizes at the n ew frequency.

LOW EMI CLOCK GENERATOR SSCG IDT® LOW EMI CLOCK GENERATOR 4 MK1707 REV L 072312 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1707. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature, Commercial 0 to +85 ° C Ambient Operating Temperature, Industrial -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 125 ° C Soldering Temperature 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +85 ° C Power Supply Voltage (measured in respect to GND) +3.135 +5.5 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.135 5.5 V Supply Current IDD No load, at 3.3 V 20 mA IDD No load, at 5 V 31 mA IDDPD S0=S1=SD=1 60 μA Input High Voltage V IH ICLK (VDD/2) + 1 VDD/2 V Input Low Voltage V IL ICLK VDD/2 (VDD/2) - 1 V Input High Voltage V IH S1, S0 VDD-0.5 V Input High Voltage V IH other inputs 2.5 V Input Low Voltage V IL S0, S1, SD, LEE pins 0.5 V Output High Voltage V OH CMOS, IOH = -4 mA VDD-0.4 V Output High Voltage V OH IOH = -12 mA 2.4 V Output Low Voltage V OL IOL = -12 mA 0.4 V Input Capacitance C IN S0, S1, SD, LEE pins 5 pF

LOW EMI CLOCK GENERATOR SSCG IDT® LOW EMI CLOCK GENERATOR 5 MK1707 REV L 072312 Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input/Output Clock Frequency 80 167 MHz Input Clock Duty Cycle Time above VDD/2 20 80 % Output Clock Duty Cycle Time above 1.5 V 40 50 60 % Output Rise Time t OR 0.8 to 2.0 V 1.5 ns Output Fall Time t OF 2.0 to 0.8 V 1.5 ns Modulation Frequency 19 41 kHz EMI Peak Frequency Reduction 3rd - 19th odd harmonics 7 to 14 dB Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W Thermal Resistance Junction to Case θJC 40 ° C/W

LOW EMI CLOCK GENERATOR SSCG IDT® LOW EMI CLOCK GENERATOR 6 MK1707 REV L 072312 Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

Note: “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK1707SLF MK1707SL Tubes 8-pin SOIC 0 to +85 ° C MK1707SLFTR MK1707SL Tape and Reel 8-pin SOIC 0 to +85 ° C MK1707SILF MK1707IL Tubes 8-pin SOIC -40 to +85 ° C MK1707SILFTR MK1707IL Tape and Reel 8-pin SOIC -40 to +85 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

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