MK1413 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 8

Technical content

Features

  • Packaged in 8-pin SOIC
  • Pb (lead) free package
  • Input crystal or clock frequency of 14.31818 MHz
  • Provides master MPEG clocks for 32 kHz, 44.1 kHz, and 48 kHz samp ling rates
  • Output clock frequencies of 8.192 MHz, 11.2896 MHz, 12.288 MHz, and 16.9344 MHz
  • Low jitter
  • 25 mA drive capability at TTL levels (at 5.0 V)
  • 3.3 V or 5.0 V (±10%) supply voltage
  • Advanced, low-power CMOS process Block Diagram CLKClock Synthesis and Control Circuitry14.31818 MHz crystal or clock input VDD Crystal Buffer/ Crystal Oscillator S1:0 GND Optional crystal load capacitors (see page 3 for details)

MPEG AUDIO CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ MPEG AUDIO CLOCK SOURCE 2 MK1413 REV G 051310 Pin Assignment Audio Clock Output Selection Table Pin Descriptions VDD NC GND S1 CLK X21 8-pin SOIC S1 S0 Audio Clock (pin 5) Accuracy (ppm) 0 0 8.192 MHz -2 ppm 0 1 11.2896 MHz -24 ppm 1 0 12.288 MHz -2 ppm 1 1 16.9344 MHz -24 ppm Pin Number Pin Name Pin Type Pin Description 1 X1 Input Crystal connection. Connect this pin to a 14.31818 MHz crystal or clock. 2 VDD Power Connect to 3.3 V or 5 V. 3 GND Power Connect to ground. 4 NC — No connect. 5 CLK Output Audio clock output as per table above. 6 S1 Input Frequency Select 1 input. Determines CLK output as per table above. 7 S0 Input Frequency Select 0 input. Determines CLK output as per table above. 8 X2 Output Crystal connection to a 14.31818 MHz crystal or leave unconnected for clock input.

MPEG AUDIO CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ MPEG AUDIO CLOCK SOURCE 3 MK1413 REV G 051310

Application Information

Series Termination Resistor Clock output traces should use series termination. For series terminating a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line and as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Load Capacitors The device crystal connections should include pads for capacitors from X1 to ground and from X2 to ground, and a parallel rsonant 14.31818 MHz crystal is recommended. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. To reduce possible noise pickup, use very short PCB traces (and no vias) been the crystal and device. The value (in pF) of each crystal load capacitor should equal L -4) x2, where CL is the crystal’s load (correlation) capacitance in pF . The frequency tolerance of the crystal should be 50 ppm or better.For a clock input, connect X1 and leave X2 unconnected. Because these capacitors adjust the stray capacitance of the PCB, check the output frequency using your final layout to see if the value of C should be changed. PCB Layout Recommendations Observe the following guidelines for optimum device performance and lowest output phase noise: 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as po ssible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the de vice is less critical. 2) The external crystal should be mounted next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instea d t hey should be separated and away from other traces. 3) T o minimize EMI, and obtain the best signal integrity, the 33Ω series termination resistor should be placed close to the clock output. 4) An opt imum layout is one with all components on the same side of the board, minimizing vias through other signal la yers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK1413. This includes signal traces just un derneath the device, or on layers adjacent to the ground p lane layer used by the device.

MPEG AUDIO CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ MPEG AUDIO CLOCK SOURCE 4 MK1413 REV G 051310 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1413. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Unless stated otherwise, VDD = 5.0 V ±10%, Ambient Temperature 0 to +70° C Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70 ° C Storage Temperature -65 to +150 ° C Junction Temperature 125 ° C Soldering Temperature (max of 10 seconds) 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 ° C Power Supply Voltage (measured in respect to GND) +3.0 +5.5 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 5.5 V Input High Voltage V IH input clock only (VDD/2)+1 VDD/2 V Input Low Voltage V IL input clock only VDD/2 (VDD/2)-1 V Output High Voltage V OH IOH = -4 mA VDD-0.4 V Output High Voltage V OH IOH = -25 mA 2.4 V Output Low Voltage V OL IOL = 25 mA 0.4 V Supply Current IDD 5 V, no Load 12 mA Supply Current IDD 3.3 V, no Load 7 mA Input Capacitance C IN S0, S1 pins 7 pF Synthesize Frequency Error With exact crystal 25 ppm

MPEG AUDIO CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ MPEG AUDIO CLOCK SOURCE 5 MK1413 REV G 051310 Unless stated otherwise, VDD = 5.0 V ±10%, Ambient Temperature 0 to +70° C Note: Typical values are at 25°C Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input Clock or Crystal Frequency 14.31818 MHz Input Crystal Accuracy 50 ppm Input Clock Duty Cycle Time above VDD/2 20 80 % Output Clock Rise Time t OR 0.8 to 2.0 V 1.5 ns Output Clock Fall Time t OF 2.0 to 0.8 V 1.5 ns Output Clock Duty Cycle Time above VDD/2 40 50 60 % Absolute Clock Period Jitter 200 ps One Sigma, Clock Period Jitter 70 ps Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W Thermal Resistance Junction to Case θJC 40 ° C/W

MPEG AUDIO CLOCK SOURCE CLOCK SYNTHESIZER IDT™ / ICS™ MPEG AUDIO CLOCK SOURCE 6 MK1413 REV G 051310 Package Outline and Package Dimensions (8-pin SOIC, 150 mil Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK1413SLF MK1413SL Tubes 8-pin SOIC 0 to +70 ° C MK1413SLFTR MK1413SL Tape and Reel 8-pin SOIC 0 to +70 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com MK1413 MPEG AUDIO CLOCK SOURCE CLOCK SYNTHESIZER

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.