K12P80M50SF4_V01 NXP | Alldatasheet
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Technical content
Kinetis K12D Sub-Family Data Sheet
50 MHz ARM® Cortex®-M4-based Microcontroller
The K12 product family members are optimized for cost-sensitive applications requiring low-power, and processing efficiency. These devices share the comprehensive enablement and scalability of the Kinetis family. This product offers:
- Up to 512 KB of flash memory with up to 64 KB of SRAM
- Run power consumption down to 189 μA/MHz and Static power consumption down to 3.1 μA with full state retention and 6 μs wakeup. Lowest Static mode down to 359 nA Performance
- Up to 50 MHz ARM® Cortex®-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz Memories and memory interfaces
- Up to 512 KB of program flash
- Up to 64 KB RAM
- 64 KB FlexNVM and 4 KB FlexRAM on FlexMemory devices System peripherals
- Multiple low-power modes
- 16-channel DMA controller
- External watchdog monitor
- Software watchdog Clocks
- 32 kHz and 3-32 MHz crystal oscillator
- Multipurpose clock generator Security and integrity modules
- Hardware CRC module
- 128-bit unique identification (ID) number per chip Communication interfaces
- Two SPI modules
- Two I2C modules
- Four UART modules
- I2S module Timers
- 8-channel motor control/general purpose/PWM timers
- Two 2-channel general purpose timers
- 32-bit PITs and 16-bit low-power timer
- Carrier modulator transmitter
- Real-time clock
- Programmable delay block Analog modules
- 16-bit SAR ADC
- Two analog comparators (CMP) Operating Characteristics
- Voltage range: 1.71 to 3.6 V
- Flash write voltage range: 1.71 to 3.6 V
- Temperature range (ambient): –40 to 105°C MK12DX128VLK5 MK12DX256VLK5 MK12DN512VLK5
80 QFP
12 x 12 x 1.4 mm Pitch 0.5 mm NXP Semiconductors K12P80M50SF4 Data Sheet: Technical Data Rev. 5, 10/2023 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
Part Number Memory Maximum number of I\\O's Flash (KB) SRAM (KB) MK12DX128VLK5 128 KB 32 60 MK12DX256VLK5 256 KB 32 60 MK12DX512VLK5 512 KB 64 60 Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. K10PB-1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K12P80M50SF4RM-1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. K12P80M50SF4-1 Package drawing Package dimensions are provided in package drawings. • QFP 80-pin: 98ASS23174W-1 2 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
Figure 1. K12 block diagram
3.6 Relationship between ratings and operating requirements...9
6.8.1 DSPI switching specifications (limited voltage
6.8.2 DSPI switching specifications (full voltage range)..50
6.8.5 Normal Run, Wait and Stop mode performance
6.8.6 VLPR, VLPW, and VLPS mode performance over
4 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: PK12 and MK12
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification K## Kinetis family • K12 A Key attribute • D = Cortex-M4 w/ DSP
- F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
- X = Program flash and FlexMemory Table continues on the next page... Ordering parts Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 5 NXP Semiconductors
FFF Program flash memory size • 32 = 32 KB
- 64 = 64 KB
- 128 = 128 KB
- 256 = 256 KB
- 512 = 512 KB
- 1M0 = 1 MB
- 2M0 = 2 MB R Silicon revision • Z = Initial
- (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105
- C = –40 to 85
- FT = 48 QFN (7 mm x 7 mm)
- LF = 48 LQFP (7 mm x 7 mm)
- LH = 64 LQFP (10 mm x 10 mm)
- MP = 64 MAPBGA (5 mm x 5 mm)
- LK = 80 LQFP (12 mm x 12 mm)
- LL = 100 LQFP (14 mm x 14 mm)
- MC = 121 MAPBGA (8 mm x 8 mm)
- LQ = 144 LQFP (20 mm x 20 mm)
- MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
- 7 = 72 MHz
- 10 = 100 MHz
- 12 = 120 MHz
- 15 = 150 MHz
- 16 = 168 MHz
- 18 = 180 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
2.4 Example
This is an example part number: MK12DX128VLK5
2.5 Small package marking
In an effort to save space, small package devices use special marking on the chip. These markings have the following format: Q ## C F T PP Part identification 6 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
This table lists the possible values for each field in the part number for small packages (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification C Speed • G = 50 MHz F Flash memory configuration • G = 128 KB + Flex
- H = 256 KB + Flex
- 9 = 512 KB T Temperature range (°C) • V = –40 to 105 This tables lists some examples of small package marking along with the original part numbers: Original part number Alternate part number MK12DX256VLF5 M12GHVLF MK12DN512VLH5 M12G9VLH
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V Terminology and guidelines Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 7 NXP Semiconductors
3.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered. Terminology and guidelines 8 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
3.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V
3.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.
3.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation Terminology and guidelines Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 9 NXP Semiconductors
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: Terminology and guidelines 10 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Ratings Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 11 NXP Semiconductors
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 155 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 3.8 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 3.8 V ID Maximum current single pin limit (applies to all digital pins) –25 25 mA VDDA Analog supply voltage VDD – 0.3 3.8 V VREGIN USB regulator input –0.3 6.0 V VBAT RTC battery supply voltage –0.3 3.8 V 1. Analog pins are defined as pins that do not have an associated general-purpose I/O port function. Ratings 12 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
5 General
5.1 AC electrical characteristics
Figure 2. Input signal measurement reference
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.71 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage 0.35 × VDD V Table continues on the next page... General Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 13 NXP Semiconductors
Table 1. Voltage and current operating requirements (continued)
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.71 V ≤ V DD ≤ 2.7 V — 0.3 × VDD V VHYS Input hysteresis 0.06 × VDD — V IICIO I/O pin DC injection current — single pin
- V IN < VSS-0.3V (Negative current injection)
- V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
- Negative current injection
- Positive current injection -25 +25 mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/| IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
5.2.2 LVD and POR operating requirements
Table 2. V DD supply LVD and POR operating requirements
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L Low-voltage warning thresholds — low range 1.74 1.80 1.86 V Table continues on the next page... General 14 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
Table 2. V DD supply LVD and POR operating requirements (continued)
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 1.84 1.94 2.04 1.90 2.00 2.10 1.96 2.06 2.16 V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage.
Table 3. VBAT power operating requirements
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = - 9 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3 mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — high drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 9 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3 mA 0.5 0.5 V V Output low voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) Table continues on the next page... General Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 15 NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
- @ full temperature range
- @ 25 °C 1.0 0.1 μA μA IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA IOZ Total Hi-Z (off-state) leakage current (all input pins) — 4 μA RPU Internal pullup resistors 22 50 kΩ 2 RPD Internal pulldown resistors 22 50 kΩ 3 1. Tested by ganged leakage method 2. Measured at Vinput = VSS 3. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
- CPU and system clocks = 50 MHz
- Bus clock = 50 MHz
- Flash clock = 25 MHz
- MCG mode: FEI
Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.
- 1.71 V/(V DD slew rate) ≤ 300 μs
- 1.71 V/(V DD slew rate) > 300 μs 300
1.7 V / (VDD
- VLLS0 → RUN — 135 μs
- VLLS1 → RUN — 135 μs
- VLLS2 → RUN — 85 μs
- VLLS3 → RUN — 85 μs
- LLS → RUN — 6 μs
- VLPS → RUN — 5.2 μs Table continues on the next page... General 16 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
Table 5. Power mode transition operating behaviors (continued)
- STOP → RUN — 5.2 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
- @ 1.8 V
- @ 3.0 V 12.98 12.93 13.8 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
- @ 1.8 V
- @ 3.0 V
- @ 25°C
- @ 125°C 17.04 17.01 19.8 19.3 18.9 21.3 mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 7.95 9.5 mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 5.88 7.4 mA 5 IDD_STOP Stop mode current at 3.0 V
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 320 360 410 610 436 489 620 1100 μA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 754 — μA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.1 — mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — 437 — μA 8 IDD_VLPS Very-low-power stop mode current at 3.0 V
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 7.33 110 24.2 280 μA Table continues on the next page... General Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 17 NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 3.14 6.48 13.85 55.53 4.8 28.3 44.6 71.3 μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 2.19 4.35 8.92 35.33 3.4 4.35 24.6 45.3 μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 1.77 2.81 5.20 19.88 3.1 13.8 22.3 34.2 μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 1.03 1.92 4.03 17.43 1.8 7.5 15.9 28.7 μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 0.543 1.36 3.39 16.52 1.1 7.58 14.3 24.1 μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 0.359 1.03 2.87 15.20 0.95 6.8 15.4 25.3 μA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V
- @ –40 to 25°C
- @ 50°C
- @ 70°C
- @ 105°C — 0.91 1.1 1.5 4.3 1.1 1.35 1.85 5.7 μA 9 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral clocks disabled. 3. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 4. Max values are measured with CPU executing DSP instructions 5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz flash clock. MCG configured for FEI mode. General 18 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
- 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
- 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
- 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
- Includes 32 kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG in FBE mode
- USB regulator disabled
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALLOFF curve, all peripheral clocks are disabled except FTFL
Figure 3. Run mode supply current vs. core frequency
Figure 4. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors 1
- This data was collected on a MK20DN128VLH5 64pin LQFP device.
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. from among the measured orientations in each frequency range.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
5.2.7 Designing with radiated emissions in mind
- Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications Table continues on the next page...
Table 9. Device clock specifications (continued)
- The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
5.3.2 General switching specifications
- GPIO signaling
- Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
- Slew disabled
- 1.71 ≤ V DD ≤ 2.7V
- Slew enabled
- 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength)
- Slew disabled
- 1.71 ≤ V DD ≤ 2.7V
- Slew enabled
- 1.71 ≤ V DD ≤ 2.7V ns ns ns ns General 22 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
- This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
pulses can be recognized in that case.
- The greater synchronous and asynchronous timing must be met.
- This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
- Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
5.4.2 Thermal attributes
Table continues on the next page...
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
- Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
- Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
the top of the package and the cold plate.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 JTAG electricals
Table 12. JTAG limited voltage range electricals
- Boundary Scan MHz Table continues on the next page... Peripheral operating requirements and behaviors 24 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
Table 12. JTAG limited voltage range electricals (continued)
- JTAG and CJTAG
- Serial Wire Debug J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns
Table 13. JTAG full voltage range electricals
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug 12.5 ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 25 NXP Semiconductors
Figure 7. Test Access Port timing Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 14. MCG specifications Table continues on the next page...
Table 14. MCG specifications (continued)
- f DCO = 48 MHz
- f DCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 7 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current
- PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
- PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
- f vco = 48 MHz
- f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
- f vco = 48 MHz
- f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 29 NXP Semiconductors
6.3.2 Oscillator electrical specifications
6.3.2.1 Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high-gain mode (HGO=1)
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) Table continues on the next page... Peripheral operating requirements and behaviors 30 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
Table 15. Oscillator DC electrical specifications (continued)
- VDD=3.3 V, Temperature =25 °C
- See crystal or resonator manufacturer's recommendation.
- Cx and Cy can be provided by using either integrated capacitors or external components.
- When low-power mode is selected, RF is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
6.3.2.2 Oscillator frequency specifications
Table 16. Oscillator frequency specifications
- Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
- When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
and cannot be moved into high power/gain mode. Table 17. 32 kHz oscillator DC electrical specifications
- When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices. Table 18. 32 kHz oscillator frequency specifications
- Proper PC board layout procedures must be followed to achieve specifications.
- This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
- The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
are active and do not include command overhead. Table 19. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 20. Flash command timing specifications
- 64 KB data flash
- 256 KB program flash 0.9 1.7 ms ms trd1sec2k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersblk64k tersblk256k Erase Flash Block execution time
- 64 KB data flash
- 256 KB program flash 122 580 985 ms ms tersscr Erase Flash Sector execution time — 14 114 ms 2 tpgmsec512 tpgmsec1k tpgmsec2k Program Section execution time
- 512 bytes flash
- 1 KB flash
- 2 KB flash 2.4 4.7 9.3 ms ms ms trd1all Read 1s All Blocks execution time — — 1.8 ms 1 trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 250 2000 ms 2 Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 33 NXP Semiconductors
Table 20. Flash command timing specifications (continued)
- control code 0x01
- control code 0x02
- control code 0x04
- control code 0x08 200 150 150 μs μs μs μs tpgmpart64k Program Partition for EEPROM execution time
- 64 KB FlexNVM 138 ms tsetramff tsetram32k tsetram64k Set FlexRAM Function execution time:
- Control Code 0xFF
- 32 KB EEPROM backup
- 64 KB EEPROM backup 0.8 1.3 1.2 1.9 μs ms ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time — 175 260 μs 3 teewr8b32k teewr8b64k Byte-write to FlexRAM execution time:
- 32 KB EEPROM backup
- 64 KB EEPROM backup 385 475 1800 2000 μs μs Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 175 260 μs — teewr16b32k teewr16b64k Word-write to FlexRAM execution time:
- 32 KB EEPROM backup
- 64 KB EEPROM backup 385 475 1800 2000 μs μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 360 540 μs — teewr32b32k teewr32b64k Longword-write to FlexRAM execution time:
- 32 KB EEPROM backup
- 64 KB EEPROM backup 630 810 2050 2250 μs μs 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. Peripheral operating requirements and behaviors 34 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
6.4.1.3 Flash high voltage current behaviors
Table 21. Flash high voltage current behaviors
6.4.1.4 Reliability specifications
Table 22. NVM reliability specifications
- EEPROM backup to FlexRAM ratio = 16
- EEPROM backup to FlexRAM ratio = 128
- EEPROM backup to FlexRAM ratio = 512
- EEPROM backup to FlexRAM ratio = 4096 35 K 315 K 1.27 M 10 M 175 K 1.6 M 6.4 M 50 M writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ °C. 3. Write endurance represents the number of writes to each FlexRAM location at –40 °C ≤Tj ≤ °C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM. Peripheral operating requirements and behaviors Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 35 NXP Semiconductors
6.4.2 EzPort switching specifications
Table 23. EzPort switching specifications Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
the differential pins ADCx_DP0, ADCx_DM0. Table 24. 16-bit ADC operating conditions
1.13 VDDA VDDA V
- All other modes VREFL VREFL 31/32 × VREFH VREFH V CADIN Input capacitance
- 16-bit mode
- 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency <13-bit mode 1.0 — 4.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode — — 2.0 MHz 4 fADCK ADC conversion clock frequency <13-bit mode 1.0 — 8.0 MHz 5 fADCK ADC conversion clock frequency 16-bit mode 2 — 4.0 MHz 5 fADCK ADC conversion clock frequency <13-bit mode 1.0 — 16.0 MHz 6 Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 37 NXP Semiconductors
Table 24. 16-bit ADC operating conditions (continued)
- Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
- This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
RAS/CAS time constant should be kept to < 1 ns.
- To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be clear and CFG1[ADLPC] must be set.
- To use the maximum ADC conversion clock frequency, both CFG2[ADHSC] and CFG1[ADLPC] must be set.
- To use the maximum ADC conversion clock frequency, both CFG2[ADHSC] and CFG1[ADLPC] must be cleared.
- To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
- For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Figure 10. ADC input impedance equivalency diagram Table 25. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC = 1, ADHSC = 0
- ADLPC = 1, ADHSC = 1
- ADLPC = 0, ADHSC = 0
- ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
- 12-bit modes
- <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
- 12-bit modes
- <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non-linearity • 12-bit modes — ±1.0 –2.7 to +1.9 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 39 NXP Semiconductors
Table 25. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- <12-bit modes — ±0.5 –0.7 to +0.5 EFS Full-scale error • 12-bit modes
- <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
- ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
- Avg = 32
- Avg = 4 16-bit single-ended mode
- Avg = 32
- Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
- Avg = 32 16-bit single-ended mode
- Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
- Avg = 32 16-bit single-ended mode
- Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. Peripheral operating requirements and behaviors 40 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 26. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00
- CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors 42 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 27. 12-bit DAC operating requirements
- The DAC reference can be selected to be VDDA or VREF_OUT.
- A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Table 28. 12-bit DAC operating behaviors
- High power (SP HP)
- Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
- High power (SP HP)
- Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 45 NXP Semiconductors
Figure 15. Typical INL error vs. digital code
Figure 16. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 29. VREF full-range operating requirements
- CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
- The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
Table 30. VREF full-range operating behaviors
- current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 31. VREF limited-range operating requirements Table 32. VREF limited-range operating behaviors
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
6.8.1 DSPI switching specifications (limited voltage range)
formats used for communicating with slower peripheral devices. Table 33. Master mode DSPI timing (limited voltage range)
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Figure 17. DSPI classic DSPI timing — master mode Table 34. Slave mode DSPI timing (limited voltage range) Table continues on the next page...
Table 34. Slave mode DSPI timing (limited voltage range) (continued) Figure 18. DSPI classic DSPI timing — slave mode
6.8.2 DSPI switching specifications (full voltage range)
formats used for communicating with slower peripheral devices. Table 35. Master mode DSPI timing (full voltage range) Table continues on the next page...
Table 35. Master mode DSPI timing (full voltage range) (continued)
- The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Figure 19. DSPI classic SPI timing — master mode Table 36. Slave mode DSPI timing (full voltage range)
Figure 20. DSPI classic SPI timing — slave mode
6.8.3 I2C switching specifications
See General switching specifications.
6.8.4 UART switching specifications
See General switching specifications.
6.8.5 Normal Run, Wait and Stop mode performance over the full
device in Normal Run, Wait and Stop modes. Table 37. I2S/SAI master mode timing Table continues on the next page...
Table 37. I2S/SAI master mode timing (continued) Figure 21. I2S/SAI timing — master modes Table 38. I2S/SAI slave mode timing
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 22. I2S/SAI timing — slave modes
6.8.6 VLPR, VLPW, and VLPS mode performance over the full
device in VLPR, VLPW, and VLPS modes. Table 39. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Figure 23. I2S/SAI timing — master modes Table 40. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 24. I2S/SAI timing — slave modes
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
8 Pinout
8.1 K12 Signal Multiplexing and Pin Assignments
for selecting which ALT functionality is available on each pin.
- The analog input signals ADC0_SE10, ADC0_SE11, ADC0_DP1, and ADC0_DM1 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices.
- The TRACE signals on PTE0, PTE1, PTE2, PTE3, and PTE4 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices.
- If the VBAT pin is not used, the VBAT pin should be left floating. Do not connect VBAT pin to VSS.
- The FTM_CLKIN signals on PTB16 and PTB17 are available only for K11, K12, K21, and K22 devices and is not present on K10 and K20 devices. For K22D devices this signal is on ALT4, and for K22F devices, this signal is on ALT7.
- The FTM0_CH2 signal on PTC5/LLWU_P9 is available only for K11, K12, K21, and K22 devices and is not present on K10 and K20 devices.
- The I2C0_SCL signal on PTD2/LLWU_P13 and I2C0_SDA signal on PTD3 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices. LQFP Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
1 ADC0_SE10ADC0_SE10PTE0 SPI1_PCS1UART1_TX TRACE_
I2C1_SDA RTC_CLKOUT
2 ADC0_SE11ADC0_SE11PTE1/
LLWU_P0 SPI1_SOUTUART1_RX TRACE_D3I2C1_SCL SPI1_SIN
3 ADC0_DP1ADC0_DP1PTE2/
LLWU_P1 SPI1_SCK UART1_CTS_b TRACE_D2
4 ADC0_DM1ADC0_DM1PTE3 SPI1_SIN UART1_RTS_b TRACE_D1 SPI1_SOUT
5 DISABLED PTE4/
LLWU_P2 SPI1_PCS0UART3_TX TRACE_D0
6 DISABLED PTE5 SPI1_PCS2UART3_RX
7 VDD VDD
8 VSS VSS
9 ADC0_SE4aADC0_SE4aPTE16 SPI0_PCS0UART2_TXFTM_CLKIN0 FTM0_FLT3
10 ADC0_SE5aADC0_SE5aPTE17 SPI0_SCK UART2_RXFTM_CLKIN1 LPTMR0_ALT3
11 ADC0_SE6aADC0_SE6aPTE18 SPI0_SOUTUART2_CTS_bI2C0_SDA
12 ADC0_SE7aADC0_SE7aPTE19 SPI0_SIN UART2_RTS_bI2C0_SCL
13 ADC0_DP0ADC0_DP0
Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 57 NXP Semiconductors
Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
14 ADC0_DM0ADC0_DM0
15 ADC0_DP3ADC0_DP3
16 ADC0_DM3ADC0_DM3
17 VDDA VDDA
18 VREFH VREFH
19 VREFL VREFL
20 VSSA VSSA
21 VREF_OUT/
CMP1_IN5/ CMP0_IN5 VREF_OUT/ CMP1_IN5/ CMP0_IN5
22 DAC0_OUT/
CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23
23 XTAL32 XTAL32
24 EXTAL32 EXTAL32
25 VBAT VBAT
26 JTAG_TCLK/
SWD_CLK/ EZP_CLK PTA0 UART0_CTS_ UART0_COL_b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK
27 JTAG_TDI/
EZP_DI PTA1 UART0_RXFTM0_CH6 JTAG_TDI EZP_DI
28 JTAG_TDO/
TRACE_SWO/ EZP_DO PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO
29 JTAG_TMS/
SWD_DIO PTA3 UART0_RTS_bFTM0_CH0 JTAG_TMS/ SWD_DIO
30 NMI_b/
EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b
31 DISABLED PTA5 FTM0_CH2 I2S0_TX_BCLKJTAG_TRST_b
32 DISABLED PTA12 FTM1_CH0 I2S0_TXD0FTM1_QD_
33 DISABLED PTA13/
LLWU_P4 FTM1_CH1 I2S0_TX_FSFTM1_QD_ PHB
34 DISABLED PTA14 SPI0_PCS0UART0_TX I2S0_RX_
I2S0_TXD1
35 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0
36 DISABLED PTA16 SPI0_SOUTUART0_CTS_
UART0_COL_b I2S0_RX_FSI2S0_RXD1
37 DISABLED PTA17 SPI0_SIN UART0_RTS_b I2S0_MCLK
38 VDD VDD
39 VSS VSS
40 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0
41 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ALT1
58 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
42 RESET_b RESET_b
43 ADC0_SE8ADC0_SE8PTB0/
LLWU_P5 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA
44 ADC0_SE9ADC0_SE9PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
45 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL UART0_RTS_b FTM0_FLT3
46 ADC0_SE13ADC0_SE13PTB3 I2C0_SDA UART0_CTS_
UART0_COL_b FTM0_FLT0
47 DISABLED PTB10 SPI1_PCS0UART3_RX FTM0_FLT1
48 DISABLED PTB11 SPI1_SCK UART3_TX FTM0_FLT2
49 DISABLED PTB12 UART3_RTS_bFTM1_CH0FTM0_CH4 FTM1_QD_
50 DISABLED PTB13 UART3_CTS_bFTM1_CH1FTM0_CH5 FTM1_QD_
51 DISABLED PTB16 SPI1_SOUTUART0_RX EWM_IN FTM_CLKIN0
52 DISABLED PTB17 SPI1_SIN UART0_TX EWM_OUT_bFTM_CLKIN1
53 DISABLED PTB18 FTM2_CH0I2S0_TX_BCLK
54 DISABLED PTB19 FTM2_CH1I2S0_TX_FS
55 ADC0_SE14ADC0_SE14PTC0 SPI0_PCS4PDB0_EXTRG I2S0_TXD1
56 ADC0_SE15ADC0_SE15PTC1/
LLWU_P6 SPI0_PCS3UART1_RTS_bFTM0_CH0 I2S0_TXD0
57 ADC0_SE4b/
CMP1_IN0 ADC0_SE4b/ CMP1_IN0 PTC2 SPI0_PCS2UART1_CTS_bFTM0_CH1 I2S0_TX_FS
58 CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_BCLK
59 VSS VSS
60 VDD VDD
61 DISABLED PTC4/
LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3 CMP1_OUT
62 DISABLED PTC5/
LLWU_P9 SPI0_SCK LPTMR0_ALT2I2S0_RXD0 CMP0_OUTFTM0_CH2
63 CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10 SPI0_SOUTPDB0_EXTRGI2S0_RX_ BCLK I2S0_MCLK
64 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN I2S0_RX_FS
65 CMP0_IN2 CMP0_IN2 PTC8 I2S0_MCLK
66 CMP0_IN3 CMP0_IN3 PTC9 I2S0_RX_
FTM2_FLT0
67 DISABLED PTC10 I2C1_SCL I2S0_RX_FS
68 DISABLED PTC11/
LLWU_P11 I2C1_SDA I2S0_RXD1
69 DISABLED PTC12
70 DISABLED PTC13
71 DISABLED PTC16 UART3_RX
Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 59 NXP Semiconductors
Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
72 DISABLED PTC17 UART3_TX
73 DISABLED PTD0/
LLWU_P12 SPI0_PCS0UART2_RTS_b
74 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK UART2_CTS_b
75 DISABLED PTD2/
LLWU_P13 SPI0_SOUTUART2_RXI2C0_SCL
76 DISABLED PTD3 SPI0_SIN UART2_TXI2C0_SDA
77 ADC0_SE21ADC0_SE21PTD4/
LLWU_P14 SPI0_PCS1UART0_RTS_bFTM0_CH4 EWM_IN
78 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_CTS_
UART0_COL_b FTM0_CH5 EWM_OUT_b
79 ADC0_SE7bADC0_SE7bPTD6/
LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6 FTM0_FLT0
80 ADC0_SE22ADC0_SE22PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1
8.2 K12 Pinouts
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout 60 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
ADC0_DM3 ADC0_DP3 ADC0_DM0 ADC0_DP0 PTE19 PTE18 PTE17 PTE16 VSS VDD PTE5 PTE4/LLWU_P2 PTE3 PTE2/LLWU_P1 PTE1/LLWU_P0 PTE0 PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC17 PTC16 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6 PTC0 PTB19 PTB18 PTB17 PTB16 PTB13 PTB12 PTB11 PTB10 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13/LLWU_P4 PTA12 PTA5 PTA4/LLWU_P3 PTA3 PTA2 PTA1 PTA0 VBAT EXTAL32 XTAL32 DAC0_OUT/CMP1_IN3/ADC0_SE23 VREF_OUT/CMP1_IN5/CMP0_IN5 Figure 25. K12 80 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Revision History
Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 61 NXP Semiconductors
Table 41. Revision History 1 6/2012 Alpha customer release. 2 7/2012 • Updated section "Power consumption operating behaviors".
- Updated section "Flash timing specifications — program and erase".
- Updated section "Flash timing specifications — commands".
- Removed the 32K ratio from "Write endurance" in section "Reliability specifications".
- Updated IDDstby maximum value in section "VREG electrical specifications".
- Added the charts in section "Diagram: Typical IDD_RUN operating behavior". 3 8/2012 • Updated section "Power consumption operating behaviors".
- Updated section "EMC radiated emissions operating behaviors".
- Updated section "MCG specifications".
- Added applicable notes in section "Signal Multiplexing and Pin Assignments". 4 12/2012 • Updated section "Power consumption operating behaviors"
- Updated section "MCG specifications"
- Updated section "16-bit ADC operating conditions"
- Added section "Small package marking" 5 10/2023 • Changed Freescale to NXP
- Updated CC values in section 2.3 Fields
- Updated Max value for VDIO, VAIO and VDDA in 4.4 Voltage and current operating ratings
- Added footnotes in Table 11 Thermal operating requirements
- Updated ADC frequencies at different modes in Table 24. 16-bit ADC operating conditions and footnotes
- Updated footnote in Table 27 12-bit DAC operating requirements
62 Kinetis K12D Sub-Family Data Sheet, Rev. 5, 10/2023 NXP Semiconductors
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