K10P64M50SF0_V01 NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 62
Technical content
– Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
- Performance – Up to 50 MHz Arm® Cortex®-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
- Memories and memory interfaces – Up to 128 KB program flash. – Up to 32 KB FlexNVM on FlexMemory devices – 2 KB FlexRAM on FlexMemory devices – Up to 16 KB RAM – Serial programming interface (EzPort)
- Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
- System peripherals – Multiple low-power modes to provide power optimization based on application requirements – 4-channel DMA controller, supporting up to 41 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
- Security and integrity modules Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip
- Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
- Analog modules – 16-bit SAR ADC – Two analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
- Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timer – Two-channel quadrature decoder/general purpose timer – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock
- Communication interfaces – SPI module – I2C module – Three UART modules – I2S module Document Number K10P64M50SF0NXP Semiconductors Data Sheet: Technical Data K10 Sub-Family Supports the following: MK10DN32VLH5, MK10DX32VLH5, MK10DN64VLH5, MK10DX64VLH5, MK10DN128VLH5, MK10DX128VLH5, MK10DN32VMP5, MK10DX32VMP5, MK10DN64VMP5, MK10DX64VMP5, MK10DN128VMP5, MK10DX128VMP5 Key features Rev. 5 10/2023 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
K10 Sub-Family, Rev. 5 10/2023
2 NXP Semiconductors
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: PK10 and MK10
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification K## Kinetis family • K10 A Key attribute • D = Cortex-M4 w/ DSP
- F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
- X = Program flash and FlexMemory FFF Program flash memory size • 32 = 32 KB
- 64 = 64 KB Table continues on the next page... Ordering parts K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 3
- 128 = 128 KB
- 256 = 256 KB
- 512 = 512 KB
- 1M0 = 1 MB
- 2M0 = 2 MB R Silicon revision • Z = Initial
- (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105
- C = –40 to 85
- FT = 48 QFN (7 mm x 7 mm)
- LF = 48 LQFP (7 mm x 7 mm)
- LH = 64 LQFP (10 mm x 10 mm)
- MP = 64 MAPBGA (5 mm x 5 mm)
- LK = 80 LQFP (12 mm x 12 mm)
- LL = 100 LQFP (14 mm x 14 mm)
- MC = 121 MAPBGA (8 mm x 8 mm)
- LQ = 144 LQFP (20 mm x 20 mm)
- MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
- 7 = 72 MHz
- 10 = 100 MHz
- 12 = 120 MHz
- 15 = 150 MHz
- 16 = 168 MHz
- 18 = 180 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
2.4 Example
This is an example part number: MK10DN128VLH5
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. Terminology and guidelines K10 Sub-Family, Rev. 5 10/2023
4 NXP Semiconductors
3.1.1 Example
This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V
3.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF Terminology and guidelines K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 5
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V
3.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines K10 Sub-Family, Rev. 5 10/2023
6 NXP Semiconductors
3.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 7
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines K10 Sub-Family, Rev. 5 10/2023
8 NXP Semiconductors
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 9
- Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Figure 1. Input signal measurement reference
- have C L=30pF loads,
- are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
- are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
- have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
10 NXP Semiconductors
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.71 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.71 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO I/O pin DC injection current — single pin
- V IN < VSS-0.3V (Negative current injection)
- V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
- Negative current injection
- Positive current injection -25 +25 mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
5.2.2 LVD and POR operating requirements
Table 2. V DD supply LVD and POR operating requirements Table continues on the next page...
Table 2. V DD supply LVD and POR operating requirements (continued)
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage.
Table 3. VBAT power operating requirements
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = - 9 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3 mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA Table continues on the next page... General K10 Sub-Family, Rev. 5 10/2023
12 NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 9 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3 mA 0.5 0.5 V V Output low voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin)
- @ full temperature range
- @ 25 °C 1.0 0.1 μA μA IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA IOZ Total Hi-Z (off-state) leakage current (all input pins) — 4 μA RPU Internal pullup resistors 22 50 kΩ 2 RPD Internal pulldown resistors 22 50 kΩ 3 1. Tested by ganged leakage method 2. Measured at Vinput = VSS 3. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
- CPU and system clocks = 50 MHz
- Bus clock = 50 MHz
- Flash clock = 25 MHz
- MCG mode: FEI
Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.
- VLLS0 → RUN — 130 μs
- VLLS1 → RUN — 130 μs — 70 μs Table continues on the next page... General K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 13
Table 5. Power mode transition operating behaviors (continued)
- VLLS2 → RUN
- VLLS3 → RUN — 70 μs
- LLS → RUN — 6 μs
- VLPS → RUN — 5.2 μs
- STOP → RUN — 5.2 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
- @ 1.8V
- @ 3.0V 13.7 13.9 15.1 15.3 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
- @ 1.8V
- @ 3.0V
- @ 25°C
- @ 125°C 16.1 16.3 16.7 18.2 17.7 18.4 mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 7.5 8.4 mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 5.6 6.4 mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 867 — μA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.1 — mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — 509 — μA 8 IDD_STOP Stop mode current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 310 384 629 426 458 1100 μA μA μA Table continues on the next page... General K10 Sub-Family, Rev. 5 10/2023
14 NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
- @ –40 to 25°C
- @ 70°C
- @ 105°C 3.5 20.7 22.6 52.9 220 μA μA μA IDD_LLS Low leakage stop mode current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 2.1 7.7 32.2 3.7 43.1 μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 1.5 4.8 2.9 22.5 37.8 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 1.4 4.1 17.3 2.8 19.2 32.4 μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 0.678 2.8 13.6 1.3 13.6 24.5 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled
- @ –40 to 25°C
- @ 70°C
- @ 105°C 0.367 2.4 13.2 1.0 13.3 24.1 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled
- @ –40 to 25°C
- @ 70°C
- @ 105°C 0.176 2.2 0.859 13.1 23.9 μA μA μA IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 0.19 0.49 2.2 0.22 0.64 3.2 μA μA μA Table continues on the next page... General K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 15
- @ 1.8V
- @ –40 to 25°C
- @ 70°C
- @ 105°C
- @ 3.0V
- @ –40 to 25°C
- @ 70°C
- @ 105°C 0.57 0.90 2.4 0.67 1.0 2.7 0.67 1.2 3.5 0.94 1.4 3.9 μA μA μA μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 4. Max values are measured with CPU executing DSP instructions 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG in FBE mode
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALLOFF curve, all peripheral clocks are disabled except FTFL General K10 Sub-Family, Rev. 5 10/2023
16 NXP Semiconductors
Figure 2. Run mode supply current vs. core frequency
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 64LQFP
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
18 NXP Semiconductors
measured orientations in each frequency range.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
5.2.7 Designing with radiated emissions in mind
- Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications Table continues on the next page...
Table 9. Device clock specifications (continued)
- The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
5.3.2 General switching specifications
- GPIO signaling
- Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
- Slew disabled
- 1.71 ≤ V DD ≤ 2.7V
- Slew enabled
- 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength)
- Slew disabled
- 1.71 ≤ V DD ≤ 2.7V
- Slew enabled
- 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. General K10 Sub-Family, Rev. 5 10/2023
20 NXP Semiconductors
- The greater synchronous and asynchronous timing must be met.
- This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
- Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
5.4.2 Thermal attributes
Table continues on the next page...
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
specification. For the MAPBGA, the board meets the JESD51-9 specification.
- Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions
—Forced Convection (Moving Air) with the board horizontal.
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
- Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
the top of the package and the cold plate.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 JTAG electricals
Table 12. JTAG limited voltage range electricals
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family, Rev. 5 10/2023
22 NXP Semiconductors
Table 12. JTAG limited voltage range electricals (continued)
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns
Table 13. JTAG full voltage range electricals
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
- Boundary Scan
- JTAG and CJTAG
- Serial Wire Debug 12.5 ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 23
Table 13. JTAG full voltage range electricals (continued) Figure 4. Test clock input timing Figure 5. Boundary scan (JTAG) timing
24 NXP Semiconductors
Figure 6. Test Access Port timing Figure 7. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 14. MCG specifications
- f DCO = 48 MHz
- f DCO = 98 MHz 180 150 ps Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family, Rev. 5 10/2023
26 NXP Semiconductors
Table 14. MCG specifications (continued)
- PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
- PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
- f vco = 48 MHz
- f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
- f vco = 48 MHz
- f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 9 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
6.3.2 Oscillator electrical specifications
6.3.2.1 Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high-gain mode (HGO=1)
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family, Rev. 5 10/2023
28 NXP Semiconductors
Table 15. Oscillator DC electrical specifications (continued)
- VDD=3.3 V, Temperature =25 °C
- See crystal or resonator manufacturer's recommendation.
- Cx and Cy can be provided by using either integrated capacitors or external components.
- When low-power mode is selected, RF is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
6.3.2.2 Oscillator frequency specifications
Table 16. Oscillator frequency specifications
- Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
- When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
Table 17. 32 kHz oscillator DC electrical specifications
- When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices. Table 18. 32 kHz oscillator frequency specifications
- Proper PC board layout procedures must be followed to achieve specifications.
- This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
- The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
active and do not include command overhead.
30 NXP Semiconductors
Table 19. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 20. Flash command timing specifications
- 32 KB data flash
- 128 KB program flash 0.5 1.7 ms ms trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersblk32k tersblk128k Erase Flash Block execution time
- 32 KB data flash
- 128 KB program flash 465 495 ms ms tersscr Erase Flash Sector execution time — 14 114 ms 2 tpgmsec512 tpgmsec1k Program Section execution time
- 512 bytes flash
- 1 KB flash 4.7 9.3 ms ms trd1all Read 1s All Blocks execution time — — 1.8 ms 1 trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 115 1000 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tpgmpart32k Program Partition for EEPROM execution time
- 32 KB FlexNVM ms tsetramff tsetram8k tsetram32k Set FlexRAM Function execution time:
- Control Code 0xFF
- 8 KB EEPROM backup
- 32 KB EEPROM backup 0.3 0.7 0.5 1.0 μs ms ms Byte-write to FlexRAM for EEPROM operation Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 31
Table 20. Flash command timing specifications (continued)
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 340 385 475 1700 1800 2000 μs μs μs Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 175 260 μs — teewr16b8k teewr16b16k teewr16b32k Word-write to FlexRAM execution time:
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 340 385 475 1700 1800 2000 μs μs μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 360 540 μs — teewr32b8k teewr32b16k teewr32b32k Longword-write to FlexRAM execution time:
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 545 630 810 1950 2050 2250 μs μs μs 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash high voltage current behaviors
Table 21. Flash high voltage current behaviors
6.4.1.4 Reliability specifications
Table 22. NVM reliability specifications Table continues on the next page...
32 NXP Semiconductors
Table 22. NVM reliability specifications (continued)
- EEPROM backup to FlexRAM ratio = 16
- EEPROM backup to FlexRAM ratio = 128
- EEPROM backup to FlexRAM ratio = 512
- EEPROM backup to FlexRAM ratio = 4096
- EEPROM backup to FlexRAM ratio = 8192 35 K 315 K 1.27 M 10 M 20 M 175 K 1.6 M 6.4 M 50 M 100 M writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C. 3. Write endurance represents the number of writes to each FlexRAM location at –40 °C ≤Tj ≤ 125 °C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum and typical values assume all byte-writes to FlexRAM.
6.4.1.5 Write endurance to FlexRAM for EEPROM
can be set to any of several non-zero values. larger EEPROM NVM storage space. shown below assume that only one configuration is ever used.
- Writes_FlexRAM — minimum number of writes to each FlexRAM location
- EEPROM — allocated FlexNVM based on DEPART; entered with the Program Partition command
- EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command
- Write_efficiency —
- 0.25 for 8-bit writes to FlexRAM
- 0.50 for 16-bit or 32-bit writes to FlexRAM
- n nvmcycd — data flash cycling endurance (the following graph assumes 10,000 cycles)
Figure 8. EEPROM backup writes to FlexRAM
34 NXP Semiconductors
6.4.2 EzPort switching specifications
Table 23. EzPort switching specifications Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
differential pins ADCx_DP0, ADCx_DM0. Table 24. 16-bit ADC operating conditions
1.13 VDDA VDDA V
- 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency <13-bit mode 1.0 — 4.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode — — 2.0 MHz 4 fADCK ADC conversion clock frequency <13-bit mode 1.0 — 8.0 MHz 5 fADCK ADC conversion clock frequency 16-bit mode 2 — 4.0 MHz 5 fADCK ADC conversion clock frequency <13-bit mode 1.0 — 16.0 MHz 6 fADCK ADC conversion clock frequency 16-bit mode 2 — 8.0 MHz 6 fADCK ADC conversion clock frequency <13-bit mode 1.0 — 18.0 MHz 7 fADCK ADC conversion clock frequency 16-bit mode 2 — 12.0 MHz 7 Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family, Rev. 5 10/2023
36 NXP Semiconductors
Table 24. 16-bit ADC operating conditions (continued)
- Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
- This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
time constant should be kept to < 1 ns.
- To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be clear and CFG1[ADLPC] must be set.
- To use the maximum ADC conversion clock frequency, both CFG2[ADHSC] and CFG1[ADLPC] must be set.
- To use the maximum ADC conversion clock frequency, both CFG2[ADHSC] and CFG1[ADLPC] must be cleared.
- To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
- For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Figure 10. ADC input impedance equivalency diagram
Table 25. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC = 1, ADHSC = 0
- ADLPC = 1, ADHSC = 1
- ADLPC = 0, ADHSC = 0
- ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
- 12-bit modes
- <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
- 12-bit modes
- <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non-linearity • 12-bit modes
- <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
- <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
- ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
- Avg = 32
- Avg = 4 16-bit single-ended mode
- Avg = 32
- Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
- Avg = 32 16-bit single-ended mode
- Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode 82 95 — dB 7 Table continues on the next page... Peripheral operating requirements and behaviors K10 Sub-Family, Rev. 5 10/2023
38 NXP Semiconductors
Table 25. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- Avg = 32 16-bit single-ended mode
- Avg = 32 78 90 — dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input ENOB ADC Clock Frequency (MHz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 12 11 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples
Figure 11. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Figure 12. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.2 CMP and 6-bit DAC electrical specifications
Table 26. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00
- CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. Peripheral operating requirements and behaviors K10 Sub-Family, Rev. 5 10/2023
40 NXP Semiconductors
- Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 Voltage reference electrical specifications
Table 27. VREF full-range operating requirements
- CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
- The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
Table 28. VREF full-range operating behaviors Table continues on the next page...
42 NXP Semiconductors
Table 28. VREF full-range operating behaviors (continued)
- current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 29. VREF limited-range operating requirements Table 30. VREF limited-range operating behaviors
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
6.8.1 DSPI switching specifications (limited voltage range)
for communicating with slower peripheral devices. Table 31. Master mode DSPI timing (limited voltage range)
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Figure 15. DSPI classic SPI timing — master mode Table 32. Slave mode DSPI timing (limited voltage range) Table continues on the next page...
44 NXP Semiconductors
Table 32. Slave mode DSPI timing (limited voltage range) (continued) Figure 16. DSPI classic SPI timing — slave mode
6.8.2 DSPI switching specifications (full voltage range)
used for communicating with slower peripheral devices. Table 33. Master mode DSPI timing (full voltage range) Table continues on the next page...
Table 33. Master mode DSPI timing (full voltage range) (continued)
- The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Figure 17. DSPI classic SPI timing — master mode Table 34. Slave mode DSPI timing (full voltage range)
46 NXP Semiconductors
Figure 18. DSPI classic SPI timing — slave mode
6.8.3 I2C switching specifications
See General switching specifications.
6.8.4 UART switching specifications
See General switching specifications.
6.8.5 I2S/SAI switching specifications
frame sync (FS) signal shown in the following figures.
6.8.5.1 Normal Run, Wait and Stop mode performance over the full
device in Normal Run, Wait and Stop modes. Table 35. I2S/SAI master mode timing Figure 19. I2S/SAI timing — master modes
48 NXP Semiconductors
Table 36. I2S/SAI slave mode timing
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 20. I2S/SAI timing — slave modes
6.8.5.2 VLPR, VLPW, and VLPS mode performance over the full operating
device in VLPR, VLPW, and VLPS modes. Table 37. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Table continues on the next page...
Figure 21. I2S/SAI timing — master modes Table 38. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Table continues on the next page...
50 NXP Semiconductors
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 22. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 39. TSI electrical specifications Table continues on the next page...
Table 39. TSI electrical specifications (continued)
- 2 μA setting (REFCHRG = 0)
- 32 μA setting (REFCHRG = 15) μA 2, 6 IELE Electrode oscillator current source base current
- 2 μA setting (EXTCHRG = 0)
- 32 μA setting (EXTCHRG = 15) μA 2, 7 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10 MaxSens Maximum sensitivity 0.008 1.46 — fF/count 11 Res Resolution — — 16 bits TCon20 Response time @ 20 pF 8 15 25 μs 12 ITSI_RUN Current added in run mode — 55 — μA ITSI_LP Low power mode current adder — 1.3 2.5 μA 13 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. VDD = 3.0 V. 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity depends on the configuration used. The documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN) The typical value is calculated with the following configuration: Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF The minimum value is calculated with the following configuration: Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 7. 13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
52 NXP Semiconductors
To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 64-pin LQFP 98ASS23234W 64-pin MAPBGA 98ASA00420D
8 Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. MAP BGA LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort A1 1 PTE0 DISABLED PTE0 UART1_TX RTC_ CLKOUT B1 2 PTE1/ LLWU_P0 DISABLED PTE1/ LLWU_P0 UART1_RX C5 3 VDD VDD VDD C4 4 VSS VSS VSS E1 5 PTE16 ADC0_SE4aADC0_SE4aPTE16 SPI0_PCS0UART2_TXFTM_CLKIN0 FTM0_FLT3 D1 6 PTE17 ADC0_SE5aADC0_SE5aPTE17 SPI0_SCKUART2_RXFTM_CLKIN1 LPTMR0_ ALT3 E2 7 PTE18 ADC0_SE6aADC0_SE6aPTE18 SPI0_SOUTUART2_ CTS_b I2C0_SDA D2 8 PTE19 ADC0_SE7aADC0_SE7aPTE19 SPI0_SIN UART2_ RTS_b I2C0_SCL G1 9 ADC0_DP0ADC0_DP0ADC0_DP0 F1 10 ADC0_DM0ADC0_DM0ADC0_DM0 G2 11 ADC0_DP3ADC0_DP3ADC0_DP3 F2 12 ADC0_DM3ADC0_DM3ADC0_DM3 F4 13 VDDA VDDA VDDA G4 14 VREFH VREFH VREFH G3 15 VREFL VREFL VREFL F3 16 VSSA VSSA VSSA H1 17 VREF_OUT/ CMP1_IN5/ CMP0_IN5 VREF_OUT/ CMP1_IN5/ CMP0_IN5 VREF_OUT/ CMP1_IN5/ CMP0_IN5 Pinout K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 53
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort H2 18 CMP1_IN3/ ADC0_SE23 CMP1_IN3/ ADC0_SE23 CMP1_IN3/ ADC0_SE23 H3 19 XTAL32 XTAL32 XTAL32 H4 20 EXTAL32 EXTAL32 EXTAL32 H5 21 VBAT VBAT VBAT D3 22 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1PTA0 UART0_ CTS_b/ UART0_ COL_b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK D4 23 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI E5 24 PTA2 JTAG_TDO/ TRACE_ SWO/ EZP_DO TSI0_CH3PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_ SWO EZP_DO D5 25 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4PTA3 UART0_ RTS_b FTM0_CH0 JTAG_TMS/ SWD_DIO G5 26 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b F5 27 PTA5 DISABLED PTA5 FTM0_CH2 I2S0_TX_ BCLK JTAG_TRST_ b H6 28 PTA12 DISABLED PTA12 FTM1_CH0 I2S0_TXD0FTM1_QD_ PHA G6 29 PTA13/ LLWU_P4 DISABLED PTA13/ LLWU_P4 FTM1_CH1 I2S0_TX_FSFTM1_QD_ PHB G7 30 VDD VDD VDD H7 31 VSS VSS VSS H8 32 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0 G8 33 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ ALT1 F8 34 RESET_b RESET_b RESET_b F7 35 PTB0/ LLWU_P5 ADC0_SE8/ TSI0_CH0 ADC0_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCLFTM1_CH0 FTM1_QD_ PHA F6 36 PTB1 ADC0_SE9/ TSI0_CH6 ADC0_SE9/ TSI0_CH6 PTB1 I2C0_SDAFTM1_CH1 FTM1_QD_ PHB E7 37 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCLUART0_ RTS_b FTM0_FLT3 E8 38 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDAUART0_ CTS_b/ UART0_ COL_b FTM0_FLT0 E6 39 PTB16 TSI0_CH9TSI0_CH9PTB16 UART0_RX EWM_IN D7 40 PTB17 TSI0_CH10TSI0_CH10PTB17 UART0_TX EWM_OUT_b D6 41 PTB18 TSI0_CH11TSI0_CH11PTB18 I2S0_TX_ BCLK C7 42 PTB19 TSI0_CH12TSI0_CH12PTB19 I2S0_TX_FS Pinout K10 Sub-Family, Rev. 5 10/2023
54 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort D8 43 PTC0 ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4PDB0_ EXTRG C6 44 PTC1/ LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3UART1_ RTS_b FTM0_CH0 I2S0_TXD0 B7 45 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_ CTS_b FTM0_CH1 I2S0_TX_FS C8 46 PTC3/ LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2 I2S0_TX_ BCLK E3 47 VSS VSS VSS E4 48 VDD VDD VDD B8 49 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3 CMP1_OUT A8 50 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0 CMP0_OUT A7 51 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_ EXTRG I2S0_RX_ BCLK I2S0_MCLK B6 52 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN I2S0_RX_FS A6 53 PTC8 CMP0_IN2CMP0_IN2PTC8 I2S0_MCLK B5 54 PTC9 CMP0_IN3CMP0_IN3PTC9 I2S0_RX_ BCLK B4 55 PTC10 DISABLED PTC10 I2S0_RX_FS A5 56 PTC11/ LLWU_P11 DISABLED PTC11/ LLWU_P11 C3 57 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_ RTS_b A4 58 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_ CTS_b C2 59 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RX B3 60 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX A3 61 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_ RTS_b FTM0_CH4 EWM_IN C1 62 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_ CTS_b/ UART0_ COL_b FTM0_CH5 EWM_OUT_b B2 63 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6 FTM0_FLT0 A2 64 PTD7 DISABLED PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1 Pinout K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 55
8.2 K10 pinouts
The figure below shows the pinout diagram for the devices supported by this document. used on which pin, see the previous section. Figure 23. K10 64 LQFP Pinout Diagram
56 NXP Semiconductors
LLWU_P0 C PTD5 D PTE17 E PTE16 F ADC0_DM0 G ADC0_DP0 H VREF_OUT/ CMP1_IN5/ CMP0_IN5 PTD7 PTD6/ LLWU_P15 PTD2/ LLWU_P13 PTE19 PTE18 ADC0_DM3 ADC0_DP3 CMP1_IN3/ ADC0_SE23 PTD4/ LLWU_P14 PTD3 PTD0/ LLWU_P12 PTA0 VSS VSSA VREFL XTAL32 PTD1 PTC10 VSS PTA1 VDD VDDA VREFH EXTAL32 PTC11/ LLWU_P11 PTC9 VDD PTA3 PTA2 PTA5 PTA4/ LLWU_P3 VBAT PTC8 PTC7 PTC1/ LLWU_P6 PTB18 PTB16 PTB1 PTA13/ LLWU_P4 PTA12 PTC6/ LLWU_P10 PTC2 PTB19 PTB17 PTB2 PTB0/ LLWU_P5 VDD VSS APTC5/ LLWU_P9 BPTC4/ LLWU_P8 CPTC3/ LLWU_P7 DPTC0 EPTB3 FRESET_b GPTA19 HPTA18 Figure 24. K10 64 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document. Table 40. Revision History 3 4/2012 • Replaced TBDs throughout.
- Updated "Power mode transition operating behaviors" table.
- Updated "Power consumption operating behaviors" table.
- For "Diagram: Typical IDD_RUN operating behavior" section, added "VLPR mode supply current vs. core frequency" figure.
- Updated "EMC radiated emissions operating behaviors" section.
- Updated "Thermal operating requirements" section.
- Updated "MCG specifications" table.
- Updated "VREF full-range operating behaviors" table.
- Updated "I2S/SAI Switching Specifications" section.
- Updated "TSI electrical specifications" table. 4 5/2012 • For the "32kHz oscillator frequency specifications", added specifications for an externally driven clock.
- Renamed section "Flash current and power specfications" to section "Flash high voltage current behaviors" and improved the specifications.
- For the "VREF full-range operating behaviors" table, removed the Ac (aging coefficient) specification. Table continues on the next page...
Revision History
K10 Sub-Family, Rev. 5 10/2023 NXP Semiconductors 57
Table 40. Revision History (continued)
- Corrected the following DSPI switching specifications: tightened DS5, DS6, and DS7; relaxed DS11 and DS13.
- Removed references to USB as non-applicable.
- For the "TSI electrical specifications", changed and clarified the example calculations for the MaxSens specification. 5 10/2023 • Added Human-machine interface in "Key features".
- Added new values for the Field "FFF" and "CC" in "Fields"
- Updated "Example" in "Defintion:Operating requirement" and "Definition:Operating behavior".
- Added a footnote in "ESD handling ratings.
- For "LVD and POR operating requiremnts" removed the sign +- from Typ. values of VHYSH and VHYSL and updated the footnote.
- Added a bullet in "Power mode transition operating behaviors".
- Updated "JTAG electricals".
- Updated table 16-bit ADC operating conditions" and footnote 6.
- Added a footnote below table "16-bit ADC characteristics..".
- Updated Min. Max value for Temperature in table "VREF full-range operating requirements".
K10 Sub-Family, Rev. 5 10/2023
58 NXP Semiconductors
Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. NXP Semiconductors Legal information
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. - NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. NXP Semiconductors Legal information
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. I2C-bus — logo is a trademark of NXP B.V. Kinetis — is a trademark of NXP B.V. NXP SECURE CONNECTIONS FOR A SMARTER WORLD — is a trademark of NXP B.V. NXP Semiconductors Legal information
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2012-2023. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10/2023 Document identifier: K10P64M50SF0