MIS2DH STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 49
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Block diagram
- 1.2 Pin description
- 2 Mechanical and electrical specifications
- 2.1 Mechanical characteristics
- 2.2 Temperature sensor characteristics
- 2.3 Electrical characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 I 2C - inter-IC control interface
- 2.5 Absolute maximum ratings
- 2.6 Terminology and functionality
- 2.6.1 Sensitivity
- 2.6.2 Zero-g level
- 2.6.3 High-resolution, normal mode, low-power mode
- 2.6.4 Self-test
- 2.7 Sensing element
- 2.8 IC interface
- 2.9 Factory calibration
- 2.10 FIFO
- 2.11 Temperature sensor
- 3 Application hints
- 3.1 Soldering information
- 4 Digital main blocks
- 4.1 FIFO
- 4.1.1 Bypass mode
Datasheet sections
- 7.20 INT1_SRC (31h)
- 7.21 INT1_THS (32h)
- 7.22 INT1_DURATION (33h)
- 7.23 INT2_CFG (34h)
- 7.24 INT2_SRC (35h)
- 7.25 INT2_THS (36h)
- 7.26 INT2_DURATION (37h)
- 7.27 CLICK_CFG (38h)
- 7.28 CLICK_SRC (39h)
- 7.29 CLICK_THS (3Ah)
- 7.30 TIME_LIMIT (3Bh)
- 7.31 TIME_LATENCY (3Ch)
- 7.32 TIME_WINDOW (3Dh)
- 7.33 Act_THS (3Eh)
- 7.34 Act_DUR (3Fh)
- 8 Package information
- 8.1 LGA package information
- 9 Revision history
Features
Wide supply voltage, 1.71 V to 3.6 V Independent IOs supply (1.8 V) and supply voltage compatible Ultra-low power consumption down to 2 μA 2g/±4g/8g/16g selectable full scales I2C/SPI digital output interface 3 operating modes: low-power, normal, high- resolution mode 2 independent programmable interrupt generators for free-fall and motion detection 6D/4D orientation detection Motion detection & free-fall detection “Sleep-to-wake” and “return-to-sleep” functions Embedded FIFO Embedded self-test Embedded temperature sensor ECOPACK®, RoHS and “Green” compliant
Applications
Activity monitoring and posture detection in medical and healthcare applications, including body-implantable products Remote patient monitoring and man-down alerts Diagnostic and treatment positioning equipment General motion-activated functions in the medical domain
Description
The MIS2DH is an ultra-low-power high- performance three-axis linear accelerometer with digital I 2C/SPI serial interface standard output. The MIS2DH has user-selectable full scales of 2g/±4g/8g/16g and is capable of measuring accelerations with output data rates from 1 Hz to 5.3 kHz. The MIS2DH is a device that has been conceived for medical and healthcare applications whenever the sensor itself is not used as a life-sustaining component. The device may be configured to generate interrupt signals by two independent inertial wake-up/free-fall events as well as by the position of the device itself. The self-test capability allows the user to check the functionality of the sensor in the final application. The MIS2DH is available in a small thin plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. LGA-12 (2.0x2.0x1 mm) Table 1. Device summary
Table 13. I
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connections
Table 2. Pin description
1 SCL
3 SDO
5 Res Connect to GND
6 GND 0 V supply
7 GND 0 V supply
8 GND 0 V supply
9 Vdd Power supply
10 Vdd_IO Power supply for I/O pins
11 INT2 Interrupt pin 2
12 INT1 Interrupt pin 1
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics
2.2 Temperature sensor characteristics
- Minimum and maximum values are based on characterization data and are not guaranteed
- Typical specifications are not guaranteed.
- Verified by wafer level test and measurement of initial offset and sensitivity.
- Typical zero-g level offset value after factory calibration test at socket level.
- The sign of “Self-test output change” is defined by the ST bit in CTRL_REG4 (23h), for all axes.
- After enabling the ST bit, correct data is obtained after two samples (low-power mode / normal mode) or after eight samples
Table 3. Mechanical characteristics (continued) Table 4. Temperature sensor characteristics
- Typical specifications are not guaranteed.
2.3 Electrical characteristics
Table 5. Electrical characteristics
- Typical specification are not guaranteed.
- It is possible to remove Vdd, maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 3. SPI slave timing diagram
- When no communication is ongoing, data on SDO is driven by internal pull-up resistors.
Table 6. SPI slave timing values
- Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
2.4.2 I 2C - inter-IC control interface
Subject to general operating conditions for Vdd and top. Figure 4. I2C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Table 7. I2C slave timing values
- Data based on standard I 2C protocol requirement, not tested in production.
2.5 Absolute maximum ratings
Table 8. Absolute maximum ratings permanent damage to the part. cause permanent damage to the part.
2.6 Terminology and functionality
2.6.1 Sensitivity
range of sensitivities of a large population of sensors.
2.6.2 Zero- g level
2.6.3 High-resolution, normal mode, low-power mode
The table below summarizes how to select the different operating modes. Table 9. Operating mode selection
The turn-on time to transition to another operating mode is given in Table 10.
2.6.4 Self-test
and the parameters of the interface chip are within the defined specifications. The MIS2DH includes 6D / 4D orientation detection. Table 10. Turn-on time for operating mode transition Table 11. Current consumption of operating modes
Mechanical and electrical specifications MIS2DH 6D / 4D orientation recognition In this configuration the interrupt is generated when the device is stable in a known direction. In 4D configuration, detection of the position of the Z-axis is disabled. 2.6.6 “Sleep-to-wake” and “Return-to-sleep” The MIS2DH can be programmed to automatically switch to low-power mode upon recognition of a determined event. Once the event condition is over, the device returns back to the preset normal or high- resolution mode. To enable this function the desired threshold value must be stored inside the Act_THS (3Eh) register while the duration value is written inside the Act_DUR (3Fh) register. When the acceleration falls below the threshold value, the device automatically switches to low-power mode (10Hz ODR). During this condition, the ODR[3:0] bits and the LPen bit inside CTRL_REG1 (20h) and the HR bit in CTRL_REG3 (22h) are not considered. As soon as the acceleration rises above threshold, the module restores the operating mode and ODRs as determined by the CTRL_REG1 (20h) and CTRL_REG3 (22h) settings.
2.7 Sensing element
A proprietary process is used to create a surface micromachined accelerometer. The technology processes suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation. When an acceleration is applied to the sensor, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.
2.8 IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalance of the MEMS sensor into an analog voltage that will be available to the user through an analog-to-digital converter. The acceleration data may be accessed through an I 2C/SPI interface, thus making the device particularly suitable for direct interfacing with a microcontroller. The MIS2DH features a data-ready signal (DRDY) which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device. The MIS2DH may also be configured to generate an inertial wake-up and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. Both free-fall and wake-up can be available simultaneously on two different pins.
MIS2DH Mechanical and electrical specifications
2.9 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and zero-g level (TyOff). The trim values are stored inside the device in non-volatile memory. Any time the device is turned on, these values are downloaded into the registers to be used during active operation. This allows using the device without further calibration.
2.10 FIFO
The MIS2DH contains a 10-bit, 32-level FIFO. Buffered output allows the following operation modes: FIFO, Stream, Stream-to-FIFO and FIFO bypass. When FIFO bypass mode is activated, FIFO is not operating and remains empty. In FIFO mode, measurement data from acceleration detection on the x, y, and z axes are stored in the FIFO buffer.
2.11 Temperature sensor
The MIS2DH is supplied with an internal temperature sensor. Temperature data can be enabled by setting the TEMP_EN[1:0] bits to ‘1’ in the TEMP_CFG_REG (1Fh) register. To retrieve the temperature sensor data the BDU bit in CTRL_REG4 (23h) must be set to ‘1’. Both the OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh) registers must be read. Temperature data is stored inside OUT_TEMP_H as two’s complement data in 8-bit format left-justified.
3 Application hints
Figure 5. MIS2DH electrical connections be placed as near as possible to pin 9 of the device (common design practice). 2C or SPI interfaces. When using the I2C, CS must be tied high. completely programmed by the user through the I2C/SPI interface.
3.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering.
MIS2DH Digital main blocks
4 Digital main blocks
4.1 FIFO
The MIS2DH embeds a 32-level FIFO for each of the three output channels, X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. In order to enable the FIFO buffer, the FIFO_EN bit in CTRL_REG5 (24h) must be set to ‘1’. This buffer can work according to the following different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each mode is selected by the FM [1:0] bits in FIFO_CTRL_REG (2Eh). Programmable FIFO watermark level, FIFO empty or FIFO overrun events can be enabled to generate dedicated interrupts on the INT1 pin (configuration through CTRL_REG3 (22h)). In the FIFO_SRC_REG (2Fh) register the EMPTY bit is equal to ‘1’ when all FIFO samples are ready and FIFO is empty. In the FIFO_SRC_REG (2Fh) register the WTM bit goes to ‘1’ if new data is written in the buffer and FIFO_SRC_REG (2Fh) (FSS [4:0]) is greater than or equal to FIFO_CTRL_REG (2Eh) (FTH [4:0]). FIFO_SRC_REG (2Fh) (WTM) goes to ‘0’ if reading an X, Y, Z data slot from FIFO and FIFO_SRC_REG (2Fh) (FSS [4:0]) is less than or equal to FIFO_CTRL_REG (2Eh) (FTH [4:0]). In the FIFO_SRC_REG (2Fh) register the OVRN_FIFO bit is equal to ‘1’ if the FIFO slot is overwritten.
4.1.1 Bypass mode
In Bypass mode the FIFO is not operational and for this reason it remains empty. For each channel only the first address is used. The remaining FIFO levels are empty. Bypass mode must be used in order to reset the FIFO buffer when a different mode is operating (i.e. FIFO mode).
4.1.2 FIFO mode
In FIFO mode, the buffer continues filling data from the X, Y and Z accelerometer channels until it is full (a set of 32 samples stored). When the FIFO is full, it stops collecting data from the input channels and the FIFO content remains unchanged. An overrun interrupt can be enabled, I1_OVERRUN = '1' in the CTRL_REG3 (22h) register, in order to be raised when the FIFO stops collecting data. When the overrun interrupt occurs, the first data has been overwritten and the FIFO stops collecting data from the input channels. After the last read it is necessary to exit Bypass mode in order to reset the FIFO content. After this reset command, it is possible to restart FIFO mode just by selecting the FIFO mode configuration (FM[1:0] bits) in register FIFO_CTRL_REG (2Eh).
Digital main blocks MIS2DH
4.1.3 Stream mode
In Stream mode the FIFO continues filling data from the X, Y, and Z accelerometer channels until the buffer is full (a set of 32 samples stored) at which point the FIFO buffer index restarts from the beginning and older data is replaced by the current data. The oldest values continue to be overwritten until a read operation frees the FIFO slots. An overrun interrupt can be enabled, I1_OVERRUN = '1' in the CTRL_REG3 (22h) register, in order to read the entire contents of the FIFO at once. If, in the application, it is mandatory not to lose data and it is not possible to read at least one sample for each axis within one ODR period, a watermark interrupt can be enabled in order to read partially the FIFO and leave memory slots free for incoming data. Setting the FTH [4:0] bit in the FIFO_CTRL_REG (2Eh) register to an N value, the number of X, Y and Z data samples that should be read at the rise of the watermark interrupt is up to (N+1).
4.1.4 Stream-to-FIFO mode
In Stream-to-FIFO mode, data from the X, Y and Z accelerometer channels are collected in a combination of Stream mode and FIFO mode. The FIFO buffer starts operating in Stream mode and switches to FIFO mode when the selected interrupt occurs. The FIFO operating mode changes according to the INT1 pin value if the TR bit is set to ‘0’ in the FIFO_CTRL_REG (2Eh) register or the INT2 pin value if the TR bit is set to‘1’ in the FIFO_CTRL_REG (2Eh) register. When the interrupt pin is selected and the interrupt event is configured on the corresponding pin, the FIFO operates in Stream mode if the pin value is equal to ‘0’ and it operates in FIFO mode if the pin value is equal to ‘1’. Switching modes is dynamically performed according to the pin value. Stream-to-FIFO can be used in order to analyze the sampling history that generates an interrupt. The standard operation is to read the contents of FIFO when the FIFO mode is triggered and the FIFO buffer is full and stopped.
4.1.5 Retrieving data from FIFO
FIFO data is read from OUT_X_L (28h), OUT_X_H (29h), OUT_Y_L (2Ah), OUT_Y_H (2Bh) and OUT_Z_L (2Ch), OUT_Z_H (2Dh). When the FIFO is in Stream, Stream-to-FIFO or FIFO mode, a read operation to the OUT_X_L (28h), OUT_X_H (29h), OUT_Y_L (2Ah), OUT_Y_H (2Bh) or OUT_Z_L (2Ch), OUT_Z_H (2Dh) registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X_L (28h), OUT_X_H (29h), OUT_Y_L (2Ah), OUT_Y_H (2Bh) and OUT_Z_L (2Ch), OUT_Z_H (2Dh) registers and both single read and read-burst operations can be used. The address to be read is automatically updated by the device and it rolls back to 0x28 when register 0x2D is reached. In order to read all FIFO levels in a multiple byte read, 192 bytes (6 output registers of 32 levels) have to be read.
5 Digital interfaces
CS line must be tied high (i.e. connected to Vdd_IO).
5.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. resistor. When the bus is free, both the lines are high. Table 12. Serial interface pin description Table 13. I2C terminology
5.1.1 I 2C operation
7 LSb represent the actual register address while the MSB enables address auto increment. allow multiple data read/writes. SAD+read/write bit pattern is composed, listing all the possible configurations. Table 14. SAD+read/write patterns Table 15. Transfer when master is writing one byte to slave
terminated by the generation of a STOP (SP) condition. address of the first register to be read. Table 16. Transfer when master is writing multiple bytes to slave Table 17. Transfer when master is receiving (reading) one byte of data from slave Table 18. Transfer when master is receiving (reading) multiple bytes of data from slave
5.2 SPI bus interface
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 6. Read and write protocol falling edge of SPC and should be captured at the rising edge of SPC. from the device is read. In the latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address is auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). the MS bit is ‘1’, the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1 SPI read
Figure 7. SPI read protocol performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. Figure 8. Multiple byte SPI read protocol (2-byte example)
5.2.2 SPI write
Figure 9. SPI write protocol is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 2 -7: address AD(5:0). This is the address field of the indexed register. Figure 10. Multiple byte SPI write protocol (2-byte example)
5.2.3 SPI read in 3-wire mode
Figure 11. SPI read protocol in 3-wire mode The SPI read command is performed with 16 clock pulses. bit 0: READ bit. The value is 1. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). The multiple read command is also available in 3-wire mode.
6 Register mapping
the corresponding addresses. Table 19. Register address map
to those registers may cause permanent damage to the device. The boot procedure is complete about 5 milliseconds after device power-up. Table 19. Register address map (continued)
7 Register description
7.1 STATUS_REG_AUX (07h)
7.2 OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh)
enable and read the temperature sensor output data.
7.3 INT_COUNTER_REG (0Eh)
7.4 WHO_AM_I (0Fh)
Device identification register.
7.5 TEMP_CFG_REG (1Fh)
Table 20. STATUS_REG_AUX register Table 21. STATUS_REG_AUX description Table 22. INT_COUNTER_REG register Table 23. WHO_AM_I register Table 24. TEMP_CFG_REG register Table 25. TEMP_CFG_REG description
7.6 CTRL_REG1 (20h)
the frequency of each combination of ODR[3:0]. Table 26. CTRL_REG1 register Table 27. CTRL_REG1 description Table 28. Data rate configuration
7.7 CTRL_REG2 (21h)
Table 29. CTRL_REG2 register Table 30. CTRL_REG2 description HPCF[2:1] High-pass filter cutoff frequency selection. Refer to Table 32. HPCLICK High-pass filter enable for CLICK function. HPIS2 High-pass filter enable for AOI function on Interrupt 2. HPIS1 High-pass filter enable for AOI function on Interrupt 1. Table 31. High-pass filter mode configuration Table 32. Low-power mode - high-pass filter cutoff frequency
7.8 CTRL_REG3 (22h)
7.9 CTRL_REG4 (23h)
Table 33. CTRL_REG3 register Table 34. CTRL_REG3 description I1_CLICK CLICK interrupt on INT1 pin. Default value 0. I1_AOI1 AOI1 interrupt on INT1 pin. Default value 0. I1_AOI2 AOI2 interrupt on INT1 pin. Default value 0. I1_DRDY1 DRDY1 interrupt on INT1 pin. Default value 0. I1_DRDY2 DRDY2 interrupt on INT1 pin. Default value 0. I1_WTM FIFO watermark interrupt on INT1 pin. Default value 0. I1_OVERRUN FIFO overrun interrupt on INT1 pin. Default value 0. Table 35. CTRL_REG4 register
- The BLE function can be activated only in high-resolution mode
Table 36. CTRL_REG4 description (0: 4-wire interface; 1: 3-wire interface).
7.10 CTRL_REG5 (24h)
7.11 CTRL_REG6 (25h)
Table 37. Self-test mode configuration Table 38. CTRL_REG5 register Table 39. CTRL_REG5 description by reading INT1_SRC (31h) itself. Default value: 0. cleared by reading INT2_SRC (35h) itself. Default value: 0. Table 40. CTRL_REG6 register Table 41. CTRL_REG6 description
7.12 REFERENCE/DATACAPTURE (26h)
7.13 STATUS_REG (27h)
P2_ACT Activity interrupt enable on INT2 pin. Default value: 0. H_LACTIVE Interrupt active. Default value: 0. Table 41. CTRL_REG6 description (continued) Table 42. REFERENCE/DATACAPTURE register Table 43. REFERENCE/DATACAPTURE description Table 44. STATUS_REG register Table 45. STATUS_REG description
7.14 OUT_X_L (28h), OUT_X_H (29h)
X-axis acceleration data. The value is expressed as two’s complement left-justified. Please refer to Section 2.6.3: High-resolution, normal mode, low-power mode.
7.15 OUT_Y_L (2Ah), OUT_Y_H (2Bh)
Y-axis acceleration data. The value is expressed as two’s complement left-justified. Please refer to Section 2.6.3: High-resolution, normal mode, low-power mode.
7.16 OUT_Z_L (2Ch), OUT_Z_H (2Dh)
Z-axis acceleration data. The value is expressed as two’s complement left-justified. Please refer to Section 2.6.3: High-resolution, normal mode, low-power mode.
7.17 FIFO_CTRL_REG (2Eh)
7.18 FIFO_SRC_REG (2Fh)
Table 46. FIFO_CTRL_REG register Table 47. FIFO_CTRL_REG description Table 48. FIFO mode configuration Table 49. FIFO_SRC_REG register
Table 50. FIFO_SRC_REG description
7.19 INT1_CFG (30h)
The content of this register is loaded at boot. A write operation to this address is possible only after system boot. WTM WTM bit is set high when FIFO content exceeds watermark level. EMPTY EMPTY flag is set high when all FIFO samples have been read and FIFO is empty. Table 51. INT1_CFG register Table 52. INT1_CFG description Table 53. Interrupt mode
The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. inside a known zone. The interrupt signal remains while the orientation is inside the zone.
7.20 INT1_SRC (31h)
Interrupt 1 source register. Read-only register.
7.21 INT1_THS (32h)
Table 54. INT1_SRC register
0 I A Z HZ LY HY LX HX L
Table 55. INT1_SRC description Table 56. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
7.22 INT1_DURATION (33h)
steps and maximum values depend on the ODR chosen. Duration time is measured in N/ODR, where N is the content of the duration register.
7.23 INT2_CFG (34h)
Table 57. INT1_THS description
1 LSb = 16 mg @ FS = 2 g
1 LSb = 32 mg @ FS = 4 g
1 LSb = 62 mg @ FS = 8 g
1 LSb = 186 mg @ FS = 16 g
Table 58. INT1_DURATION register
0 D 6D 5D 4D 3D 2D 1D 0
Table 59. INT1_DURATION description
1 LSb = 1/ODR
Table 60. INT2_CFG register Table 61. INT2_CFG description 6D 6-direction detection function enabled. Default value: 0. Refer to Table 62.
The content of this register is loaded at boot. A write operation to this address is possible only after system boot. The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. inside a known zone. The interrupt signal remains while the orientation is inside the zone.
7.24 INT2_SRC (35h)
Table 62. Interrupt mode Table 61. INT2_CFG description (continued) Table 63. INT2_SRC register Table 64. INT2_SRC description
Interrupt 2 source register. Read-only register.
7.25 INT2_THS (36h)
7.26 INT2_DURATION (37h)
time steps and maximum values depend on the ODR chosen.
7.27 CLICK_CFG (38h)
Table 64. INT2_SRC description (continued) Table 65. INT2_THS register Table 66. INT2_THS description Table 67. INT2_DURATION register Table 68. INT2_DURATION description
1 LSb = 1/ODR(1)
- Duration time is measured in N/ODR, where N is the content of the duration register.
Table 69. CLICK_CFG register
7.28 CLICK_SRC (39h)
Table 70. CLICK_CFG description Table 71. CLICK_SRC register Table 72. CLICK_SRC description
7.29 CLICK_THS (3Ah)
7.30 TIME_LIMIT (3Bh)
7.31 TIME_LATENCY (3Ch)
7.32 TIME_WINDOW (3Dh)
Table 73. CLICK_THS register Table 74. CLICK_SRC description Table 75. TIME_LIMIT register Table 76. TIME_LIMIT description Table 77. TIME_LATENCY register Table 78. TIME_LATENCY description Table 79. TIME_WINDOW register Table 80. TIME_WINDOW description
7.33 Act_THS (3Eh)
7.34 Act_DUR (3Fh)
Table 81. Act_THS register Table 82. Act_THS description Table 83. Act_DUR register Table 84. Act_DUR description
1 LSb = (8*1[LSb]+1)/ODR
8 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
8.1 LGA package information
Figure 12. LGA-12 package outline and mechanical data
9 Revision history
Table 85. Document revision history