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Technical content
- Introduction This document describes the functionality and electrical specification of the NFC Controller PN7150. Additional documents describing the product functionality further are available for design-in support. Refer to the references listed in this document to get access to the full for full documentation provided by NXP. 2. General description Best plug´n play and high-performance full NFC solution PN7150 is a full NFC controller solution with integrated firmware and NCI interface designed for contactless communication at 13.56 MHz. It is compatible with NFC forum requirements. PN7150 is designed based on learnings from previous NXP NFC device generation. It is the ideal solution for rapidly integrating NFC technology in any application, especially those running O/S environment like Linux and Android, reducing Bill of Material (BOM) size and cost, thanks to:
- Full NFC forum compliancy (see Ref. 1) with small form factor antenna
- Embedded NFC firmware providing all NFC protocols as pre-integrated feature
- Direct connection to the main host or microcontroller, by I2C-bus physical and NCI protocol
- Ultra-low power consumption in polling loop mode
- Highly efficient integrated power management unit (PMU) allowing direct supply from a battery PN7150 embeds a new generation RF contactless front-end supporting various transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693, MIFARE and FeliCa specifications. It embeds an ARM Cortex-M0 microcontroller core loaded with the integrated firmware supporting the NCI 1.0 host communication. It also allows to provide a higher output power by supplying the transmitter output stage from 3.0 V to 4.75 V. The contactless front-end design brings a major performance step-up with on one hand a higher sensitivity and on the other hand the capability to work in active load modulation communication enabling the support of small antenna form factor. Supported transmission modes are listed in Figure 1. For contactless card functionality, the PN7150 can act autonomously if previously configured by the host in such a manner. PN7150 High performance full NFC Forum-compliant controller with integrated firmware and NCI interface Rev. 3.3 — 4 July 2016 Product data sheet
Product data sheet Rev. 3.3 — 4 July 2016 2 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware PN7150 integrated firmware provides an easy integration and validation cycle as all the NFC real-time constraints, protocols and device discovery (polling loop) are being taken care internally. In few NCI commands, host SW can configure the PN7150 to notify for card or peer detection and start communicating with them. 3. Features and benefits Includes NXP ISO/IEC14443-A, Innovatron ISO/IEC14443-B and NXP MIFARE crypto1 intellectual property licensing rights ARM Cortex-M0 microcontroller core Highly integrated demodulator and decoder Buffered output drivers to connect an antenna with minimum number of external components Integrated RF level detector Integrated Polling Loop for automatic device discovery RF protocols supported NFCIP-1, NFCIP-2 protocol (see Ref. 8 and Ref. 11) ISO/IEC 14443A, ISO/IEC 14443B PICC, NFC Forum T4T modes via host interface (see Ref. 3) NFC Forum T3T via host interface ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital protocol T4T platform and ISO-DEP (see Ref. 1) FeliCa PCD mode MIFARE PCD encryption mechanism (MIFARE 1K/4K) NFC Forum tag 1 to 5 (MIFARE Ultralight, Jewel, Open FeliCa tag, DESFire) (see Ref. 1) ISO/IEC 15693/ICODE VCD mode (see Ref. 9) Supported host interfaces (1) According to ISO/IEC 18092 (Ecma 340) standard. Fig 1. PN7150 transmission modes aaa-023871 CARD (PICC) T4T - ISO/IEC 14443 A T4T - ISO/IEC 14443 B READER (PCD - VCD) ISO/IEC 14443 A ISO/IEC 14443 B ISO/IEC 15693 MIFARE 1K / 4K MIFARE DESFire Sony FeliCa(1) NFC FORUM NFC-IP MODES P2P ACTIVE
106 TO 424 kbps
Table 1. Quick reference data
1.8 V host supply;
[1] V SS represents VSS(PAD) and VSS(TX). another device must be taken into account). [3] External clock on NFC_CLK_XTAL1 must be LOW. [4] See Ref. 10 for computing the power consumption as it depends on several parameters. [1] xx = firmware code variant. Table 1. Quick reference data …continued Table 2. Ordering information Table 3. Marking codes
- diffusion center code: – Z: SSMC – S: Powerchip (PTCT)
- assembly center code: – S: APK
- RoHS compliancy indicator: – D: Dark Green; fully compliant RoHS and no halogen and antimony
- manufacturing year and week, 3 digits: – Y: year – WW: week code
- product life cycle status code: – X: means not qualified product – nothing means released product
Table 3. Marking codes …continued
Product data sheet Rev. 3.3 — 4 July 2016 6 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware 8. Block diagram Fig 3. PN7150 block diagram aaa-016737 RF DETECTRF DETECT CLESS INTERFACE UNIT SENSOR DEMOD ADC DRIVER TxCtrl PLL BG VMID MISCELLANEOUS TIMERS CRC COPROCESSOR RANDOM NUMBER GENERATOR CLOCK MANAGEMENT UNIT OSCILLATOR 380 kHz FRACN PLL OSCILLATOR
40 MHz
4.5 V TX-LDO 1.8 V DSLDO
9.1 Pinning
Table 4. Pin description
[1] P = power supply; G = ground; I = input, O = output; I/O = input/output. preserve energy supporting Power Off mode. Table 4. Pin description …continued
Product data sheet Rev. 3.3 — 4 July 2016 9 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware
- PN7150 User Manual (Ref. 5): User Manual describes the software interfaces (API) based on the NFC forum NCI standard. It does give full description of all the NXP NCI extensions coming in addition to NCI standard (Ref. 2).
- PN7150 Hardware Design Guide (Ref. 6): Hardware Design Guide provides an overview on the different hardware design options offered by the IC and provides guidelines on how to select the most appropriate ones for a given implementation. In particular, this document highlights the different chip power states and how to operate them in order to minimize the average NFC-related power consumption so to enhance the battery lifetime.
- PN7150 Antenna and Tuning Design Guide (Ref. 7): Antenna and Tuning Design Guide provides some guidelines regarding the way to design an NFC antenna for the PN7150 chip. It also explains how to determine the tuning/matching network to place between this antenna and the PN7150. Standalone antenna performances evaluation and final RF system validation (PN7150 + tuning/matching network + NFC antenna within its final environment) are also covered by this document.
- PN7150 Low-Power Mode Configuration (Ref. 10): Low-Power Mode Configuration documentation provides guidance on how PN7150 can be configured in order to reduce current consumption by using Low-power polling mode.
10.1 System modes
10.1.1 System power modes
PN7150 is designed in order to enable the different power modes from the system. Fig 5. PN7150 connection aaa-016739 NFCC host interface controlHOST CONTROLLER BATTERY/PMU ANTENNA MATCHING
2 power modes are specified: Full power mode and Power Off mode.
10.1.2 PN7150 power states
states include the logical status of the system thus extend the power modes. 4 power states are specified: Monitor, Hard Power Down (HPD), Standby, Active. Table 5. System power modes description Table 6. System power modes configuration Table 7. System power modes description
current consumption in here described states. to restrict parts of the PN7150 functionality.
10.1.2.1 Monitor state
level. Battery voltage monitor thresholds show hysteresis behavior as defined in Table 27.
10.1.2.2 Hard Power Down (HPD) state
entering or exiting this state.
10.1.2.3 Standby state
- I2C-bus interface wake-up event
- Antenna RF level detector
- Internal timer event when using polling loop (380 kHz Low-power oscillator is enabled)
Table 8. PN7150 power states system power mode is Power Off mode. the minimum power consumption. The system power mode is in Power Off. Host interface. The system power mode is Full power mode.
depends on software configuration and/or wake-up source.
10.1.2.4 Active state
different functional modes: Idle, Poller and Target. operational range (see Table 1). mode shall be used with 2.3 V < VBAT < 5.5 V and VEN voltage > 1.1 V.
10.1.2.5 Polling loop
The polling loop will sequentially set PN7150 in different power states (Active or Standby).
- Listening phase. The PN7150 can be in Standby power state or Listener mode
- Polling phase. The PN7150 is in Poller mode
Table 9. Functional modes in active state Listener the PN7150 is active and is config ured for listening to external device.
Product data sheet Rev. 3.3 — 4 July 2016 13 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware Listening phase uses Standby power state (when no RF field) and PN7150 goes to Listener mode when RF field is detected. When in Polling phase, PN7150 goes to Poller mode. To further decrease the power consumption when running the polling loop, PN7150 features a low-power RF polling. When PN7150 is in Polling phase instead of sending regularly RF command, PN7150 senses with a short RF field duration if there is any NFC Target or card/tag present. If yes, then it goes back to standard polling loop. With 500 ms (configurable duration, see Ref. 5) listening phase duration, the average power consumption is around 150 A. Fig 7. Polling loop: all phases enabled aaa-016741 Emulation Pause Type A Type B Type F @424 Type F @212ISO15693 Listening phase Polling phase
Product data sheet Rev. 3.3 — 4 July 2016 14 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware Detailed description of polling loop configuration options is given in Ref. 5.
10.2 Microcontroller
PN7150 is controlled via an embedded ARM Cortex-M0 microcontroller core. PN7150 features integrated in firmware are referenced in Ref. 5.
10.3 Host interface
PN7150 provides the support of an I2C-bus Slave Interface, up to 3.4 MBaud. The host interface is waken-up on I2C-bus address. To enable and ensure data flow control between PN7150 and host controller, additionally a dedicated interrupt line IRQ is provided which Active state is programmable. See Ref. 5 for more information. Fig 8. Polling loop: low-power RF polling aaa-016743 Listening phase Emulation Pause Polling phase
10.3.1 I 2C-bus interface
shift timing generation and slave address recognition. (3.4 MHz SCL) are supported.
- Support slave I2C-bus
- Standard, Fast and High-speed modes supported
- Wake-up of PN7150 on its address only
- Serial clock synchronization can be used by PN7150 as a handshake mechanism to suspend and resume serial transfer (clock stretching) The I2C-bus interface module meets the I2C-bus specification Ref. 4 except General call, 10-bit addressing and Fast mode Plus (Fm+).
10.3.1.1 I 2C-bus configuration
The I2C-bus interface shares four pins with I2C-bus interface also supported by PN7150. to one described in Table 10. lines connected to these pins.
10.4 PN7150 clock concept
- 27.12 MHz clock coming either/or from: – Internal oscillator for 27.12 MHz crystal connection
Table 10. Functionality for I 2C-bus interface Table 11. I 2C-bus interface addressing
- 13.56 MHz RF clock recovered from RF field
- Low-power oscillator 40 MHz
- Low-power oscillator 380 kHz 10.4.1 27.12 MHz quartz oscillator When enabled, the 27.12 MHz quartz oscillator applied to PN7150 is the time reference for the RF front end when PN7150 is behaving in Reader mode or NFCIP-1 initiator. Therefore stability of the clock frequency is an important factor for reliable operation. It is recommended to adopt the circuit shown in Figure 9. Table 12 describes the levels of accuracy and stability required on the crystal. [1] This requirement is according to FCC regulat ions requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then 14 kHz apply.
10.4.2 Integrated PLL to make use of external clock
configured in Active Communication mode. Table 12. Crystal requirements
27.12 MHz cc
38.4 MHz and 52 MHz:
Table 13. PLL input requirements
13 MHz, 26 MHz and
52 MHz
19.2 MHz, 24 MHz and
38.4 MHz
Product data sheet Rev. 3.3 — 4 July 2016 18 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware [1] This requirement is according to FCC regulat ions requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then 400 ppm limits apply. For detailed description of clock request mechanisms, refer to Ref. 5 and Ref. 6. 10.4.3 Low-power 40 MHz 2.5 % oscillator Low-power OSC generates a 40 MHz internal clock. This frequency is divided by two to make the system clock.
10.4.4 Low-power 380 kHz oscillator
A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) waking-up PN7150 from Standby state. This allows implementation of low-power reader polling loop at application level. Moreover, this 380 kHz is used as the reference clock for write access to EEPROM memory.
10.5 Power concept
10.5.1 PMU functional description
The Power Management Unit of PN7150 generates internal supplies required by PN7150 out of VBAT input supply voltage:
- VDD: internal supply voltage
- VDD(TX): output supply voltage for the RF transmitter The Figure 11 describes the main blocks available in PMU:
10.5.2 DSLDO: Dual Supply LDO
The input pin of the DSLDO is VBAT. The Low drop-out regulator provides VDD required in PN7150. Fig 11. PMU functional diagram aaa-016748 VBAT VDD NFCC BANDGAP DSLDO TXLDO VBAT1 and VBAT2 VDD(TX)
Product data sheet Rev. 3.3 — 4 July 2016 19 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware
10.5.3 TXLDO
Transmitter voltage can be generated by internal LDO (VDD(TX)) or come from an external supply source VDD(TX). The regulator has been designed to work in 2 configurations:
10.5.3.1 Configuration 1: supply connection in case the battery is used to generate RF field
The Low drop Out Regulator has been designed to generate a 3.0 V, 3.3 V or 3.6 V supply voltage to a transmitter with a current load up to 180 mA. The output is called VDD(TX). The input supply voltage of this regulator is a battery voltage connected to VBAT1 pin. VDD(TX) value shall be chosen according to the minimum targeted VBAT value for which reader mode shall work. If VBAT is above 3.0 V plus the regulator voltage dropout, then VDD(TX) = 3.0 V shall be chosen: If VBAT is above 3.3 V plus the regulator voltage dropout, then VDD(TX) = 3.3 V shall be chosen: If VBAT is above 3.6 V plus the regulator voltage dropout, then VDD(TX) = 3.6 V shall be chosen: Fig 12. V BAT1 = VBAT2 (between 2.3 V and 5.5 V) aaa-017002 VBAT1 NFCC VDD(TX) VDD(TX_IN) VBAT2 BATTERY 3.0VV BAT 2.3VV DD TX VBAT 1 load– = 3.3VV BAT 2.3VV DD TX VBAT 1 load– = 3.6VV BAT 2.3VV DD TX VBAT 1 load– =
Product data sheet Rev. 3.3 — 4 July 2016 20 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware Figure 13 shows VDD(TX) offset disabled behavior for both cases of VDD(TX) programmed for 3.0 V, 3.3 V or 3.6 V. In Standby state, whenever VDD(TX) is configured for 3.0 V, 3.3 V or 3.6 V, VDD(TX) is regulated at 2.5 V. Figure 14 shows the case where the PN7150 is in standby state.
10.5.3.2 Configuration 2: supply connection in case a 5 V supply is used to generate RF
field with the use of TXLDO TXLDO has also the possibility to generate 4.75 V or 4.5 V supply in case the supply of this regulator is an external 5 V supply. Fig 13. V DD(TX) offset behavior Fig 14. V DD(TX) behavior when PN7150 is in Standby state aaa-014174 5.0 V VBAT 2.8 V 3.6 V 3.3 V 3.0 V Drop = 1 Ω * load aaa-009463 VBAT 2.5 V 2.5 V
Product data sheet Rev. 3.3 — 4 July 2016 21 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware Figure 16 shows the behavior of VDD(TX) depending on VBAT1 value.
10.5.3.3 TXLDO limiter
The TXLDO includes a current limiter to avoid too high current within TX1, TX2 when in reader or initiator modes. The current limiter block compares an image of the TXLDO output current to a reference. Once the reference is reached, the output current gets limited which is equivalent to a typical output current of 220 mA whatever VBAT or VBAT1 value in the range of 2.3 V to 5.5 V.
10.5.4 Battery voltage monitor
The PN7150 features low-power VBAT voltage monitor which protects mobile device battery from being discharged below critical levels. When VBAT voltage goes below VBATcritical threshold, then the PN7150 goes in Monitor state. Refer to Figure 17 for principle schematic of the battery monitor. The battery voltage monitor is enabled via an EEPROM setting. At the first start-up, VBAT voltage monitor functionality is OFF and then enabled if properly configured in EEPROM. The PN7150 monitors battery voltage continuously. Fig 15. V BAT1 = 5 V, VBAT2 between 2.3 V and 5.5 V Fig 16. V DD(TX) behavior when PN7150 is supply using external supply on VBAT1 aaa-017003 NFCC EXTERNAL 5 V VBAT1 VBAT2 BATTERY VDD(TX) VDD(TX_IN) aaa-017004 VBAT1 Drop = 1 Ω * load 4.75 V 5.5 V 4.5 V VDD(TX)
Product data sheet Rev. 3.3 — 4 July 2016 22 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware The value of the critical level can be configured to 2.3 V or 2.75 V by an EEPROM setting. This value has a typical hysteresis around 150 mV.
10.6 Reset concept
10.6.1 Resetting PN7150
To enter reset, there are 2 ways:
- Pulling VEN voltage low (Hard Power Down state)
- if VBAT monitor is enabled: lowering VBAT below the monitor threshold (Monitor state, if VEN voltage is kept above 1.1 V) Reset means resetting the embedded FW execution and the registers values to their default values. Part of these default values is defined from EEPROM data loaded values, others are hardware defined. See Ref. 5 to know which ones are accessible to tune PN7150 to the application environment. To get out of reset:
- Pulling VEN voltage high with VBAT above VBAT monitor threshold if enabled Figure 18 shows reset done via VEN pin. Fig 17. Battery voltage monitor principle aaa-013868 SYSTEM MANAGEMENTlow power DVDD_CPU VDDD VDD power off VBAT MONITORREGISTERS enable threshold selection POWER SWITCHES POWER MANAGEMENT DIGITAL (memories, cpu, etc,...) VBAT EEPROM
Product data sheet Rev. 3.3 — 4 July 2016 23 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware See Section 14.2.2 for the timings values.
10.6.2 Power-up sequences
There are 2 different supplies for PN7150. PN7150 allows these supplies to be set up independently, therefore different power-up sequences have to be considered.
10.6.2.1 V BAT is set up before VDD(PAD)
This is at least the case when VBAT pin is directly connected to the battery and when PN7150 VBAT is always supplied as soon the system is supplied. As VEN pin is referred to VBAT pin, VEN voltage shall go high after VBAT has been set. See Section 14.2.3 for the timings values.
10.6.2.2 V DD(PAD) and VBAT are set up in the same time
It is at least the case when VBAT pin is connected to a PMU/regulator which also supply VDD(PAD). Fig 18. Resetting PN7150 via VEN pin aaa-015878 host communication possible tboottw(VEN)VEN VDD(PAD) VBAT Fig 19. V BAT is set up before VDD(PAD) aaa-015879 host communication possible tboottt(VDD(PAD)-VEN) VEN VDD(PAD) VBAT
Product data sheet Rev. 3.3 — 4 July 2016 24 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware See Section 14.2.3 for the timings values.
10.6.2.3 PN7150 has been enabled before V DD(PAD) is set up or before VDD(PAD) has been cut
This can be the case when VBAT pin is directly connected to the battery and when VDD(PAD) is generated from a PMU. When the battery voltage is too low, then the PMU might no more be able to generate VDD(PAD). When the device gets charged again, then VDD(PAD) is set up again. As the pins to select the interface are biased from VDD(PAD), when VDD(PAD) disappears the pins might not be correctly biased internally and the information might be lost. Therefore it is required to make the IC boot after VDD(PAD) is set up again. See Section 14.2.3 for the timings values. Fig 20. V DD(PAD) and VBAT are set up in the same time aaa-015881 host communication possible tboot tt(VBAT-VEN) VEN VDD(PAD) VBAT Fig 21. V DD(PAD) is set up or cut-off after PN7150 has been enabled tboot tW(VEN)VEN VDD(PAD) VBAT tt(VDD(PAD)-VEN) aaa-015884 host communication possible
Product data sheet Rev. 3.3 — 4 July 2016 25 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware
10.6.3 Power-down sequence
10.7 Contactless Interface Unit
PN7150 supports various communication modes at different transfer speeds and modulation schemes. The following chapters give more detailed overview of selected communication modes. Remark: all indicated modulation index and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance.
10.7.1 Reader/Writer communication modes
Generally 5 Reader/Writer communication modes are supported:
- PCD Reader/Writer for ISO/IEC 14443A/MIFARE
- PCD Reader/Writer for Jewel/Topaz tags
- PCD Reader/Writer for FeliCa cards
- PCD Reader/Writer for ISO/IEC 14443B
- VCD Reader/Writer for ISO/IEC 15693/ICODE
10.7.1.1 ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD communication mode
The ISO/IEC 14443A/MIFARE PCD communication mode is the general reader to card communication scheme according to the ISO/IEC 14443A specification. This modulation scheme is as well used for communications with Jewel/Topaz cards. Figure 23 describes the communication on a physical level, the communication table describes the physical parameters (the numbers take the antenna effect on modulation depth for higher data rates). Fig 22. PN7150 power-down sequence aaa-015886 tVBAT(L) t > 0 mst > 0 ms (nice to have) VBAT VEN VDD(PAD)
handle the application layer communication.
10.7.1.2 FeliCa PCD communication mode
a physical level, the communication overview describes the physical parameters. Table 14. Overview for ISO/IEC 14443A/MIF ARE Reader/Writer communication mode
The contactless coprocessor of PN7150 and the on-chip CPU handle the FeliCa protocol.
10.7.1.3 ISO/IEC 14443B PCD communication mode
Table 15. Overview for FeliCa Reader/Writer communication mode Table 16. Overview for ISO/IEC 14443B Reader/Writer communication mode
application layer communication.
10.7.1.4 R/W mode for NFC forum Type 5 Tag
Figure 26 and Table 17 show the communication schemes used. Table 17. Communication overview for NFC forum T5T R/W mode
Product data sheet Rev. 3.3 — 4 July 2016 29 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware
10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes
An NFCIP-1 communication takes place between 2 devices:
- NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
- NFC Target: responds to NFC Initiator command either in a load modulation scheme in Passive communication mode or using a self-generated and self-modulated RF field for Active communication mode. The NFCIP-1 communication differentiates between Active and Passive communication modes.
- Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to transmit data
- Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load modulation scheme. The NFC Initiator is active in terms of generating the RF field. PN7150 supports the Active Target, Active Initiator, Passive Target and Passive Initiator communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard. Nevertheless a dedicated external host has to handle the application layer communication.
10.7.2.1 ACTIVE communication mode
Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to transmit data. Fig 27. NFCIP-1 communication mode aaa-016755 NFCC BATTERY NFC Target: Passive or Active Communication modesNFC Initiator: Passive or Active Communication modes HOST NFCC BATTERY HOST
range as based on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see Ref. 7.
10.7.2.2 Passive communication mode
command in a load modulation scheme.
- NFC Initiator starts the communication at selected transfer speed
- NFC Target answers at the same transfer speed
Table 18. Overview for Active communication mode
range as based on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see Ref. 7.
10.7.2.3 NFCIP-1 framing and coding
defined in the NFCIP-1 standard: ISO/IEC 18092 or Ecma 340.
10.7.2.4 NFCIP-1 protocol support
explanation of the protocol, refer to the ISO/IEC 18092 or Ecma 340 NFCIP-1 standard.
- NFC Initiator starts the communication at selected transfer speed
- NFC Target answers using load modulation at the same transfer speed
Table 19. Overview for Passive communication mode
- Transaction includes initialization, anticollision methods and data transfer. This sequence must not be interrupted by another transaction
- PSL shall be used to change the speed between the target selection and the data transfer, but the speed should not be changed during a data transfer
10.7.3 Card communication modes
ISO/IEC 14443B and the Sony FeliCa interface description. , Table 21 and Table 22 describe the physical parameters.
10.7.3.1 NFC forum T4T, ISO/IEC 14443Acard mode
10.7.3.2 NC forum T4T, ISO/IEC 14443B card mode
Table 20. Overview for NFC forum T4T, ISO/IEC 14443A card mode Table 21. Overview for NFC forum T4T, ISO/IEC 14443B card mode
10.7.3.3 NFC forum T3T, Sony FeliCa card mode
10.7.4 Frequency interoperability
sensitive to some RF signals as it is looking from data in the field. antenna and design the board according to Ref. 6.
13.56 MHz 7 kHz, FCC regulation does not allow this wide spread and limits the
dispersion to 50 ppm, which is in line with PN7150 capability. Table 22. Overview for NFC forum T3T, Sony FeliCa card mode
dissipated from the field or generated by PN7150 does not exceed this value.
- Recommended operating conditions
Table 23. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 24. Operating conditions
3 V host supply;
[1] V SS represents VSS(PAD) and VSS(TX). another device must be taken into account). [3] External clock on NFC_CLK_XTAL1 must be LOW. [4] See Ref. 10 for computing the power consumption as it depends on several parameters. [5] The antenna shall be tuned not to exceed the maximum of I BAT.
14.1 Current consumption characteristics
Table 24. Operating conditions …continued Table 25. Thermal characteristics Table 26. Current consumption characteristics for operating ambient temperature range
[1] Refer to Section 10.1.2 for the description of the power modes. [2] This is the same value for V BAT = 2.3 V when the monitor threshold is set to 2.3 V.
14.2 Functional block elect rical characteristics
14.2.1 Battery voltage monitor characteristics
14.2.2 Reset via VEN
14.2.3 Power-up timings
14.2.4 Power-down timings
14.2.5 I 2C-bus timings
Here below are timings and frequency specifications. Table 27. Battery voltage monitor characteristics Table 28. Reset timing Table 29. Power-up timings Table 30. Power-down timings
Table 31. High-speed mode I 2C-bus timings specification Table 32. Fast mode I 2C-bus timings specification
14.3 Pin characteristics
14.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2 pins characteristics
14.3.2 VEN input pin characteristics
Table 33. Input clock characteristics on NFC_CLK_XTAL1 when using PLL Table 34. Pin characteristics for NFC_CLK_XTAL1 when PLL input Table 35. Pin characteristics for 27.12 MHz crystal oscillator Table 36. PLL accuracy
14.3.3 Pin characteristics for IRQ and CLK_REQ
[1] Activated in HPD and Monitor states.
14.3.4 Input pin characteristics for RXN and RXP
Table 38. pin characteristics for IRQ and CLK_REQ Table 39. Input pin characteristics for RXN and RXP
14.3.5 Output pin characteristics for TX1 and TX2
14.3.6 Input pin characteristics for I2CADR0 and I2CADR1
Table 39. Input pin characteristics for RXN and RXP …continued Table 40. Output pin characteristics for TX1 and TX2 Table 41. Output resistance for TX1 and TX2 Table 42. Input pin characteri stics for I2CADR0 and I2CADR1
14.3.7 Pin characteristics for I2CSDA and I2CSCL
[1] Only for pin I2CSDA as I2CSCL is only used as input.
14.3.8 V DD pin characteristic
Table 43. Pin characteristics for I2CSDA and I2CSCL Table 44. Electrical characteristic of V DD
Product data sheet Rev. 3.3 — 4 July 2016 42 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware 15. Package outline Fig 31. Package outline, HVQFN40, SOT618-1, MSL3 ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT618-1 MO-220 sot618-1_po 02-10-22 13-11-05 Unit mm max nom min 0.4 A(1) Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-1 A1 b 0.30 cD (1) Dh E(1) Eh 4.10 ee 1 e2 Lvw 0.05 y 0.05 0.1 e e 1/2 e 1/2 e y terminal 1 index area A A1 c L Eh Dh b 11 20 40 31 2110 D E terminal 1 index area 0 2.5 5 mm scale A C C Bv w Cy1 C X detail X B A
Product data sheet Rev. 3.3 — 4 July 2016 43 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
- Through-hole components
- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
- Board specifications, including the board finish, solder masks and vias
- Package footprints, including solder thieves and orientation
- The moisture sensitivity level of the packages
- Package placement
- Inspection and repair
- Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
- Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 32) than a SnPb process, thus reducing the process window
- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 45 and 46 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32.
Table 45. SnPb eutectic process (from J-STD-020D) Table 46. Lead-free process (from J-STD-020D)
Product data sheet Rev. 3.3 — 4 July 2016 45 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. MSL: Moisture Sensitivity Level Fig 32. Temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = MSL limit, damage level peak temperature
Table 47. Abbreviations
Table 47. Abbreviations …continued
Product data sheet Rev. 3.3 — 4 July 2016 48 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware 18. References [1] NFC Forum Device Requirements — V1.3 [2] NFC Controller Interface ( NCI) Technical Specification — V1.0 [3] ISO/IEC 14443 — parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001 COR 1 2006 (01/09/2006) and part 4: 2nd edition 2008 (15/07/2008) [4] I 2C Specification — I2C Specification, UM10204 rev4 (13/02/2012) [5] PN7150 User Manual — UM10936 PN7150 User Manual [6] PN7150 Hardware Design Guide — AN11756 PN7150 Hardware Design Guide [7] PN7150 Antenna design and matching guide — AN11755 PN7150 Antenna design and matching guide [8] ISO/IEC 18092 (NFCIP-1) — edition, 15/032013. This is similar to Ecma 340. [9] ISO/IEC15693 — part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001) [10] PN7150 Low-Power Mode Configuration — AN11757 PN7150 Low-Power Mode Configuration [11] ISO/IEC 21481 (NFCIP-2) — edition, 01/07/2012. This is similar to Ecma 352.
Table 48. Revision history Modifications: • Figure 1: updated.
- Section 10.7.1.4: updated.
- Section 10.7.3: updated. PN7150 v3.2 201600525 Product data sheet - PN7150 v3.1 PN7150 v3.1 20160511 Product data sheet - PN7150 v3.0 PN7150 v3.0 20151209 Product data sheet - PN7150 v2.1 PN7150 v2.1 20151127 Preliminary data sheet - PN7150 v2.0 PN7150 v2.0 20150701 Preliminary data sheet - PN7150 v1.2 PN7150 v1.2 20150625 Objective data sheet - PN7150 v1.1 PN7150 v1.1 20150212 Objective data sheet - PN7150 v1.0 PN7150 v1.0 20150129 Objective data sheet - - Modifications:
- Initial version
Product data sheet Rev. 3.3 — 4 July 2016 50 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware 20. Legal information
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[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
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Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Product data sheet Rev. 3.3 — 4 July 2016 51 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
20.4 Licenses
20.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. DESFire — is a trademark of NXP Semiconductors N.V. MIFARE — is a trademark of NXP B.V. MIFARE Classic — is a trademark of NXP B.V. MIFARE Ultralight — is a trademark of NXP B.V. ICODE and I-CODE — are trademarks of NXP B.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. RATP/Innovatron Technology Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP Semiconductors IC does not include a license to any NXP patent (or other IP right) covering combinations of those products with other products, whether hardware or software.
Table 10. Functionality for I Table 14. Overview for ISO/IEC 14443A/MIFARE Table 15. Overview for FeliCa Table 16. Overview for ISO/IEC 14443B Reader/Writer Table 17. Communication overview for NFC forum T5T Table 19. Overview for Passive communication mode . .31 Table 20. Overview for NFC forum T4T, ISO/IEC 14443A Table 21. Overview for NFC forum T4T, ISO/IEC 14443B Table 22. Overview for NFC forum T3T, Sony FeliCa card Table 26. Current consumption characteristics for operating Table 31. High-speed mode I Table 33. Input clock characteristics on NFC_CLK_XTAL1 Table 34. Pin characteristics for NFC_CLK_XTAL1 Table 35. Pin characteristics for 27.12 MHz crystal Table 38. pin characteristics for IRQ and CLK_REQ . . .39 Table 39. Input pin characteristics for RXN and RXP . . .39 Table 40. Output pin characteristics for TX1 and TX2 . . .40 Table 42. Input pin characteristics for I2CADR0 and Table 43. Pin characteristics for I2CSDA and I2CSCL. . .41 Table 44. Electrical characteristic of V Table 45. SnPb eutectic process (from J-STD-020D) . . . 44
Product data sheet Rev. 3.3 — 4 July 2016 53 of 55 NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware 23. Figures Fig 12. V Fig 14. V DD(TX) behavior when PN7150 is in Standby Fig 16. V DD(TX) behavior when PN7150 is supply using Fig 19. V Fig 20. V DD(PAD) and VBAT are set up in the same time . .24 Fig 21. V DD(PAD) is set up or cut-off after PN7150 has Fig 23. ISO/IEC 14443A/MIFARE Reader/Writer Fig 24. FeliCa Reader/Writ er communication mode Fig 25. ISO/IEC 14443B Reader/Writer communication Fig 26. R/W mode for NFC forum T5T communication Fig 30. I Fig 31. Package outline, HVQFN40, SOT618-1, MSL3. .42 Fig 32. Temperature profiles for large and small
Product data sheet Rev. 3.3 — 4 July 2016 54 of 55 continued >> NXP Semiconductors PN7150 Full NFC Forum-compliant controller with integrated firmware 24. Contents 10.3.1 I
10.4.2 Integrated PLL to make use of external clock 16
10.5.3.1 Configuration 1: su pply connection in case the
10.5.3.2 Configuration 2: supply connection in case
a 5 V supply is used to generate RF field 10.6.2.1 V
10.6.2.2 V DD(PAD) and VBAT are set up in the same time 23
10.6.2.3 PN7150 has been enabled before V DD(PAD) is set
10.7.1.1 ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD
10.7.1.3 ISO/IEC 14443B PC D communication mode. 27
10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1
10.7.3.1 NFC forum T4T, ISO/IEC 14443Acard mode. 32 10.7.3.2 NC forum T4T, ISO/IEC 14443B card mode . 32 14.2 Functional block electrical characteristics . . . 36 14.2.5 I
14.3.1 NFC_CLK_XTAL1 and NFC_CLK_XTAL2 pins
14.3.3 Pin characteristics for IRQ and CLK_REQ . 39 14.3.4 Input pin characteristics for RXN and RXP . . 39 14.3.5 Output pin characteristics for TX1 and TX2 . . 40
14.3.6 Input pin characteristics for I2CADR0 and
14.3.7 Pin characteristics for I2CSDA and I2CSCL . 41 14.3.8 V
Full NFC Forum-compliant controller with integrated firmware © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 July 2016 Document identifier: PN7150 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.