MIC9130BM

MIC9130_08 MICREL | Alldatasheet

Document overview

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• PDF pages: 19

Technical content

Features

• Input voltages up to 180V
• Internal oscillator capable of >2.5MHz operation
• Synchronisation capability to 4MHz
• Current sense delay of 34ns
• Minimum pulse width <25ns
• 90% ef fi ciency
• 1.3mA quiescent current
• 1 μA shutdown current
• Soft-start
• Resistor programmable current sense threshold
• Selectable soft-start retry
• 4 Ω sink, 12Ω source output driver
• Programmable under-voltage lockout
• Constant-frequency PWM current-mode control
• 16-pin SOIC and 16-pin QSOP

Applications

• Telecom power supplies
• Line cards
• ISDN network terminators
• Micro- and pico-cell base stations
• Low power (< 30W) dc-dc converters Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

MIC9130 Micrel, Inc. M9999-111108 2 November 2008 Pin Description Pin Number Pin Name Pin Function 1 LINE Line (Input): 180Vdc maximum supply input. May be fl oated if unused. 2 VCC Supply (Input): MIC9130 internal supply input. 3 RBIAS Bias Resistor (External Component): Connect 562K Ω to ground.

4 OSC Oscillator RC Network (External Components): Connect external resistor-

capacitor network to set oscillator frequency.

5 SYNC Synchronization (Input): External oscillator input for slave operation of

controller. See OSC. Do not fl oat.

6 COMP Compensation (External Components): Error ampli fi er output for external

compensation network connection. 7 FB Feedback (Input): Error ampli fi er inverting input.

8 CPWR Current Limit Selection (Input): When CPWR is high, an over-current

condition at the ISNS input will terminate the gate drive and reset the soft-start latch. If the CPWR pin is low, an over-current condition at the ISNS input will terminate the gate drive signal, but will not cause a reset of the soft-start circuit. 9 VBIAS Reference (Output): Internal 5V supply. Will source 5mA maximum.

10 EN Enable (Input): Logic level enable/shutdown input; logic high = enabled (on),

logic low = shutdown (off).

11 AGND Analog Ground (Return)

12 SS Soft-Start (External Components): Connect external capacitor to slowly ramp

up duty cycle during startup and over-current conditions.

13 UVLO Undervoltage Lockout (External Components): Connect to unbiased resistive

divider network to set controller’s minimum operating voltage. Connect to VBIAS if not needed.

14 ISNS Current Sense (Input): Connect between external switching MOSFET source

and switch current sense resistor.

15 PGND Power Ground (Return)

16 OUT Switch Drive Output (Output): Connect to gate of external switching

MOSFET. Pin Confi guration 2VCC 3RBIAS 4OSC 5SYNC 6COMP 7FB 1LINE 8CPWR OUT16 PGND15 ISNS14 UVLO13 SS12 AGND11

9 VBIAS

16-Pin SOP (M) 16-Pin QSOP (QS)

Ordering Information

Part Number Max. Duty Cycle Junction Temp. Range Package Standard Pb-Free MIC9130BM MIC9130YM 50% -40°C to +125°C 16-Pin SOP MIC9130BQS MIC9130YQS 50% -40°C to +125°C 16-Pin QSOP

November 2008 3 M9999-111108 MIC9130 Micrel, Inc. Absolute Maximum Ratings (Note 1) Power Dissipation (PD) ESD Rating, Note 3 Operating Ratings (Note 2) Package Thermal Resistance

Electrical Characteristics

TA = 25°C, VLINE = 48V, VCC = 10V, Rt = 9.47KΩ, Ct = 470pF, RBIAS = 562kΩ, VEN = 10V, VISNS = 0V, VUVLO = 2V, VSYNC = 0V, unless otherwise noted. Bold values indicate –40 °C ≤TJ ≤ +125°C. Parameter Condition Min Typ Max Units Bias Regulator Output Voltage I VBIAS = 0mA; VOSC = 0V (Oscillator OFF) 4.7 4.85 5.0 V 4.6 5.1 V Line Regulation 9V ≤ VCC ≤18V, IVBIAS = 0mA; VOSC = 0V 24 40 mV Load Regulation 0mA ≤ IVBIAS ≤ 5mA; VOSC = 0V 5 30 mV Oscillator Section Initial Accuracy (f OSC) R t = 9.47KΩ, Ct = 470pF 180 200 220 kHz Oscillator Output Frequency f OSC/2 kHz Maximum Duty Cycle 50 % Voltage Stability (Δf/f) 9V ≤ V CC ≤18V 2.5 % Temperature Stability –40°C ≤ TJ ≤ 125°C 100 ppm/°C Maximum Sync Frequency Note 5 4 MHz Sync Threshold Level 2.5 V Sync Hysteresis 0.7 V Sync Minimum Pulse Width 50 ns Error Amp Section FB Voltage V COMP = VFB 2.475 2.5 2.525 V 2.45 2.55 Open Loop Voltage Gain, AVOL 90 dB Unity Gain Bandwidth 4 MHz PSRR 9V ≤ V CC ≤ 18V 60 dB COMP Sink Current V FB = 2.7V; VCOMP = 5V 80 100 μA COMP Source Current V FB = 2.3V; VCOMP = 0V 1 2.5 mA VCOMP Low V FB = 2.7V; ICOMP = –50μA 115 300 mV VCOMP High V FB = 2.3V; ICOMP = +500μA 3.5 4 V Input Bias Current (IFB) V FB = VCOMP 160 nA Slew Rate SINK 1.5 V/ μs SOURCE 1.5 V/ μs

MIC9130 Micrel, Inc. M9999-111108 4 November 2008 Parameter Condition Min Typ Max Units Preregulator Input Leakage Current V LINE = 180V, VCC = 10V 0.1 10 μA VCC Gate Lockout (VGLO(ON)) V LINE = 48V 7.2 7.5 V VCC Gate Lockout Hysteresis V LINE = 48V 700 800 mV (ΔVGLO) VCC Pre-Regulator Off (VPR(OFF)) V LINE = 48V VGLO(ON) V 7.7 +0.5V VCC Pre-Regulator Hysteresis V LINE = 48V 500 700 mV (ΔVPR) Start-up Current V LINE = 48V, VCC = 7.5V, Note 4 9 12 mA Supply Supply Current, IVCC Pin 16 (OUT) = OPEN 1.3 1.5 mA Enable Input Current V EN = 0V ,10V; VLINE = 48V –10 0.1 10 μA Shutdown Supply Current V EN = 0V ; VCC = 18V 0.1 10 μA Protection and Control Current Limit Threshold Voltage 0.772 0.83 0.888 V Current Limit Delay to Output V ISNS = 0V to 5V 34 ns Current Limit Source Current V ISNS = 0V 30 40 50 μA Enable Input Threshold (Turn-on) 1 1.6 2.2 V Enable Input Hysteresis 150 mV CPWR Input Current V CPWR = 5V, 0V –1 +1 μA CPWR Threshold 1.6 V Soft-Start Current V SS = 0V 2.5 4 6 μA Line UVLO Threshold (Turn-on) 1.16 1.22 1.28 V Line UVLO Threshold Hysteresis 140 mV Thermal Shutdown 145 °C Thermal Shutdown Hysteresis 25 °C MOSFET Driver Output Minimum On-Time V ISNS = 5V 21 ns Output Driver Impedance SOURCE ; I SOURCE = 200mA 8 12 Ω SINK ; I SINK = 200mA 4 6 Ω Rise Time C OUT = 500pF 12 ns Fall Time C OUT = 500pF 8 ns Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Note 3. Devices are ESD sensitive. Handling precautions recommended. Note 4. If a substained DC voltage >150V is applied to the LINE pin, a current-limiting 1.8k Ωresistor should be used in series with the LINE pin. This condition does not apply for transient conditions over 150V. Note 5. For oscillator frequencies above 2.5MHz it may be necessary to power to VBIAS pin from an external power source due to the cur rent limita- tions of the internal 5V regulator. See Applications Information for details

November 2008 5 M9999-111108 MIC9130 Micrel, Inc. Typical Characteristics -2.0 -1.5 -1.0 -0.5 0.5 1.0 1.5 2.0 8 9 10 11 12 13 14 15 16 17 18 OSC FREQ. VARIATION (%) VCC (V) Oscillator Frequency vs. V CC Voltage FOSC( NOM)=200 kHz Rt=9.47K Ct=470pF -40 0 40 80 120 160 OSC FREQ. VARIATION (%) TEMPERATURE (°C) Oscillator Frequency vs. Temperature VCC =1 0 V RBI AS= 560 K Rt =9 . 4 7 K Ct = 470p F 2.499 2.500 2.501 2.502 8 9 10 11 12 13 14 15 16 17 18 REFERENCE VOLTAGE (V) VCC (V) Error Amp Reference Voltage vs. V CC Voltage RBI AS= 560 K 2.480 2.485 2.490 2.495 2.500 2.505 2.510 -40 -20 0 20 40 60 80 100120140 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Error Amp Reference Voltage vs. Temperature VCC =1 0 V RBI AS= 560 K 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 8 9 10 11 12 13 14 15 16 17 18 THRESHOLD (V) VCC (V) Line UVLO Threshold vs. VCC 1.18 1.19 1.2 1.21 1.22 1.23 1.24 -40 0 40 80 120 160 UVLO THRESHOLD (V) TEMPERATURE (°C) Line UVLO Threshold vs. Temperature VCC=10V RBIAS=560 K 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 8 1 01 21 41 61 8 QUIESCENT CURRENT (mA) VCC (V) Quiescent Current vs. VCC Voltage RBI AS= 560 K Rt =9 . 4 7 K Ct = 470pF 1.3 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.4 -40 -20 0 20 40 60 80 100120140 QUIESCENT CURRENT (mA) TEMPERATURE (°C) Quiescent Current vs. Temperature VCC =1 0 V RBIAS = 560 K Rt =9 . 4 7 K Ct = 470pF 0 200 400 600 800 1000 QUIESCENT CURRENT (mA) GATE DRIVE FREQUENCY (kHz) Quiescent Current vs. Frequency Ct = 120p F Ct = 470p F 1.5 2.5 3.5 0 200 400 600 800 1000 1200 QUIESCENT CURRENT (mA) RBIAS (kΩ) Quiescent Current vs. RBIAS VCC =1 0 V Rt =9 . 5 3 K Ct = 470pf fOSC = 200k Hz 0 200 400 600 800 1000 1200 DELAY (ns) RBIA S(kΩ) ISNS to Gate Output Delay vs. R BIAS 100 150 200 250 300 350 200 400 600 800 1000 1200 1400 1600 1800 2000 DELAY (ns) OVERDRIVE (mV) ISNS to Gate Output Delay vs. Overdrive RBI AS=160 K RBI AS=560 K RBI AS=360 K

MIC9130 Micrel, Inc. M9999-111108 6 November 2008 4.94 4.96 4.98 5.02 5.04 5.06 -40 -20 0 20 40 60 80 100120140 BIAS VOLTAGE (V) TEMPERATURE (°C) 5V VBIAS Voltage vs. Temperature VCC = 10V RBI AS= 560K Rt = 9.47K Ct = 470pF 4.94 4.95 4.96 4.97 4.98 4.99 BIAS VOLTAGE (V) IBIAS (mA) Bias Voltage Load Regulation VCC =1 0 V 12345 6.4 6.6 6.8 7.2 7.4 7.6 7.8 -40 -20 0 20 40 60 80 100120140 THRESHOLD (V) TEMPERATURE (°C) VCC Turn On/Off Thresholds vs. Temperature Vcc GLO On Vcc GLO Off VCC=10V RBI AS=560 K 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 8 9 10 11 12 13 14 15 16 17 18 SINK/SOURCE CURRENT (A) VCC (V) Gate Drive Current vs. VCC SINK SO UR CE -40 0 40 80 120 160SHORT CIRCUIT CURRENT (mA) TEMPERATURE (°C) Peak Short Circuit Depletion FET Current vs. Temperature 48VLine 180VLine VCC =0 V 0 40 80 120 160 200 SHORT CIRCUIT CURRENT (mA) VLINE (V) Peak Short Circuit Depletion FET Current vs. V LINE –40°C 25°C 125 °C VCC =0 V 818.0 818.5 819.0 819.5 820.0 820.5 821.0 821.5 822.0 8 9 10 11 12 13 14 15 16 17 18 THRESHOLD (mV) VCC (V) ISNS Current Limit Threshold vs. VCC Voltage RBI AS=560K 815 820 825 830 835 840 -40 0 40 80 120 160 THRESHOLD (mV) TEMPERATURE (°C) ISNS Current Limit Threshold vs. Temperature VCC= 10V RBI AS= 560K 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 8 9 10 11 12 13 14 15 16 17 18 THRESHOLD VOLTAGE (V) VCC (V) Enable Threshold vs. VCC 4.990 4.992 4.994 4.996 4.998 5.000 5.002 5.004 5.006 5.008 5.010 8 9 10 11 12 13 14 15 16 17 18 VBIAS (V) VCC (V) VBIAS vs. V CC RBIAS = 560 K 0 40 80 120 160 CURRENT (mA) VLINE (V) Depletion FET Current vs. VLINE –40°C25°C 125 °C VCC=7.5V 7 7.5 8 8.5 9 9.5 10 CURRENT (mA) VLINE (V) Depletion FET Current vs. Low V LINE Voltage –40°C 125°C 25°C

November 2008 7 M9999-111108 MIC9130 Micrel, Inc. -40 -20 0 20 40 60 80 100120140ISNS CURRENT (μA) TEMPERATURE (°C) ISNS Pin Source Current vs. Temperature RBI AS=560 K VCC=10V 38.5 39.5 40.5 41.5 8 1 01 21 41 61 8 ISNS CURRENT (μA) VCC (V) ISNS Pin Source Current vs. VCC RBI AS=560K

MIC9130 Micrel, Inc. M9999-111108 8 November 2008 Functional Block Diagram RBIAS 1.21V OUTR Q SR Latch 2Oscillator SYNCOSC 1.2V PWM COMP S Q Peak Current Limit Max. Duty Cycle 4μA FB VCC PGND ISNS SS 2.5V VBIAS EN VCC UNDERVOLT AGE LOCKOUT Thermal Shutdown UVLO AGND BIAS REG 0.82V MAXIMUM DUTY CYCLE VCC UVLO LINE UVLO LINE Error Amplifier 1-Shot CPWR Current Limit Selection 40μA 7 64 5 Figure 1 1000 10000 100000 1000000 10000 100000 1000000 10000000 RESISTOR VALUE (Ω) FREQUENCY (Hz) Oscillator Frequency vs. RC Values 47pF 100pF 220pF 470pF 680pF 1000pF 2200pF *See applications section for higher switching frequencies

November 2008 9 M9999-111108 MIC9130 Micrel, Inc. Functional Description Micrel’s MIC9130 is a high voltage, high speed current mode switching power supply controller. It uses a BiC/DMOS pro- cess to achieve a high voltage input, low quiescent current and very fast internal delay times. The MIC9130 is designed to drive an external low side N-channel MOSFET, which makes it suitable for controlling Boost, Flyback and Forward converter topologies. The high voltage startup pin eliminates the requirement for an external start up circuit. This makes it ideal for use with Telecom converters. A block diagram of the MIC9130 is shown in Figure 1. The de- scription of the controller is divided into 6 basic functions:

• Power and bias circuitry
• High voltage start-up circuit
• V CC and bias supplies
• Enable and undervoltage monitoring circuits
• V CC and VIN UVLO
• Enable
• Oscillator and sync circuitry
• Soft-start and soft-start reset circuits
• MOSFET gate drive circuits
• Control loop operation
• Current sensing & overcurrent protection
• Slope compensation
• Error ampli fi er High Voltage Start Up Circuit Many conventional Off-Line and Telecom power supplies use an external bias resistor and zener diode to supply the initial start-up voltage for the control IC. The control IC gets its supply voltage from a bias winding once the power sup- ply is running. This method has the disadvantages of extra components (diode and power resistor), continuous power dissipation in the resistor and a large bias capacitor, used to supply the IC until the bias winding takes over. The MIC9130 eliminates these problems by using an internal depletion mode MOSFET as a pre-regulator to provide the start-up bias voltage from the high voltage input of the power supply. This approach eliminates the need for external start up components and reduces the size of the controller’s bias supply capacitor. The MOSFET is turned off once the external bias winding takes over, which eliminates power dissipation in the start-up circuit. In some cases, the MIC9130 may be run directly from the input voltage rail, eliminating the need for an external bias winding. Transformer Bias Winding VIN 180V DEPLETION FET Internal Circuitry MIC9130 VCC Line THERMAL SHUTDOWN 1.21V VCC UVLO ∆VPR VPR(OFF) Depletion FET Pre-Regultor turn-off threshold Depletion FET turn-on threshold ∆VGLO VCC Gate Lockout Hysteresis VCC voltage when powered from VLINE VGLO(ON) VCC gate lockout turn on threshold Figure 2

MIC9130 Micrel, Inc. M9999-111108 10 November 2008 Start-up circuit operation is illustrated in Figure 2. VIN is ap- plied and the depletion FET, which is normally enabled allows current from V IN to charge the VCC bias capacitor. Once the VCC voltage reaches the VCC enable threshold, VGLO(ON) , the gate drive is enabled and the MIC9130 starts switching. V CC continues to increase until the Pre-Regulator turn-off threshold, (VPR(OFF)), is reached and the depletion FET is turned off. The VCC voltage decreases as energy from the bias capacitor is used to supply the controller. The deple- tion FET is turned back on when the pre-regulator turn-on threshold is reached. A bias winding derived supply voltage, set higher than the FET turn-off threshold, V PR(OFF), raises the VCC voltage over the threshold and prevents the FET from turning on. In certain designs the MIC9130 may be powered directly from the Line voltage, eliminating the need for an extra transformer bias winding. When operating in this fashion the designer must insure the power dissipation in the IC does not cause the die temperature to exceed the 125°C maximum. Power dissipation is calculated by: PV V IDISS IN CC VCC= −() × Where : VIN is the line input voltage V CC is the average VCC voltage (typically 8.5V) I VCC is the total current drawn by the IC IVCC is the sum of the operating current of the MIC9130 at a given frequency and the average current required to drive the external switching MOSFET. A plot of typical operating current vs. frequency is given in Figure 3. The average MOS- FET gate drive current is calculated in the “MOSFET GATE DRIVE” section of this specifi cation. 0 200 400 600 800 1000 QUIESCENT CURRENT (mA) GATE DRIVE FREQUENCY (kHz) Quiescent Current vs. Frequency Ct = 120p F Ct = 470p F Figure 3 The die junction temperature is calculated by TTPJA DISS JA=+ × θ Where: TJ is the die junction temperature T A is the ambient temperature of the circuit θ JA is the junction to ambient thermal resistance of the MIC9130 (listed in the operating ratings section of the specifi cation. When powered directly from the Line voltage, the V CC volt- age will vary between the upper and lower pre-regulator thresholds. The amplitude of the output gate drive voltage will vary with the V CC voltage. This should not be a problem for most topologies since the variation is small (equal to the ΔVPR hysteresis). The bias regulator in the MIC9130 buffers the internal circuits from VCC variations. The pre-regulator FET is protected by a thermal shutdown circuit, which turns the MOSFET off if its temperature exceeds approximately 150 degrees C. When operating at input voltages greater than 150V, a fast input voltage risetime during turn-on (which may occur during a hot plug operation) may cause a high peak current to fl ow through the depletion FET, damaging the MIC9130. A 1.8kΩ resistor in series between the input voltage and the line pin (pin 1) is recommended when operating at input voltages greater than 150V. This resistor limits the maximum peak current to 100mA (at 180V IN) and protects the part. The depletion mode MOSFET contains an internal parasitic diode. The V IN pin voltage must be greater than the V CC voltage or the VCC voltage will be clamped to a diode drop greater than the VIN voltage. Excessive power dissipation in the parasitic diode will destroy the IC. VCC and Bias Supplies The power for the controller and gate drive circuitry is sup- plied through the VCC pin. The gate drive current is returned to ground through the power ground pin (PGND). The rest of the supply current is returned to ground through the analog ground pin (AGND). The two ground pins must be connected together through the PCB ground plane. High frequency decoupling is provided at the V CC pin to sup- ply the gate drive’s peak current requirements. Turn-on of the external MOSFET causes a voltage glitch on the V CC pin. If the glitch is excessive, this disruption can appear as noise or jitter in the oscillator circuit or the gate drive waveform. The decoupling capacitor must be able to supply the MOSFET gate with the charge required to turn it on. A 0.1μF ceramic capacitor is usually suf fi cient for most MOSFETs. Larger FETs, with a higher gate charge requirement may require a 0.22μF ceramic capacitor or a ceramic capacitor paralleled with a 2.2 μF tantalum or 4.7uF aluminum electrolytic. It is recommend that if V LINE is greater than 150V DC than the maximum capacitor recommended on VCC is 2.2μF.The ca- pacitor must be located next to the VCC pin of the MIC9130. The ground end of the capacitor should be connected to the ground plane, making a low impedance connection to the power ground pin (pin 15). The internal bias regulator block provides several internal and external bias voltages. Referring to Figure 1, a 2.5V refer- ence is used for the internal error ampli fi er, a 0.82V bias is used by the current limit comparator and a 1.21V reference is used by the Line UVLO circuit. An external 5V bias volt- age (V BIAS) powers the oscillator circuit and may be used as a reference voltage for other external components. The V BIAS pin requires a minimum 0.1μf capacitor to ground for decoupling. Enable and Undervoltage Monitoring circuits The two undervoltage lockout circuits in the MIC9130 are shown in Figure 4. One monitors the V CC voltage and the other monitors the input line voltage. These signals are OR’d together and either one can disable the gate drive pin and discharge the voltage on the soft start capacitor.

November 2008 11 M9999-111108 MIC9130 Micrel, Inc. VCC Undervoltage Lockout The VCC voltage is internally divided down and compared to a 1.21V internal bandgap reference. As VCC rises above the turn-on threshold, it disables the Vcc undervoltage lockout circuit. Once above the turn-on threshold, hysteresis prevents the lockout circuit from disabling the IC until the V CC voltage falls below the lower threshold. Line Undervoltage Circuit (UVLO) The line voltage is monitored by an external resistor divider and fed into the negative input of the line UVLO comparator. As the comparator trip point is exceeded, the line UVLO circuit is disabled. Hysteresis built into the comparator prevents the circuit from toggling on an off in the presence of noise or a high input line impedance. The line voltage turn-on trip point is: VV R2 R1 R2 LINE_ON THRESHOLD=× + where: V THRESHOLD is the voltage level of the internal comparator reference, typically 1.21V. The line hysteresis is equal to: VV R1 R2 R2HYSTERESIS HYST=× + where: V HYST is the internal hysteresis level, typically 75mV. V HYSTERESIS is the hysteresis of the line input voltage The MIC9130 will be disabled when the line voltage drops back down to: VV V VV R2 R1 R2 LINE_OFF LINE_ON HYTERESIS THRESHOLD HYST = − = −() × + Enable A low level on the enable pin turns off all the functions of the MIC9130 and places it in a low quiescent current state. The output driver is in a low state. When the enable pin is pulled high, the MIC9130 goes through its normal start up sequence including undervoltage lock out and soft start. When not used, the pin should be connected to V CC. Oscillator Block An external resistor and capacitor set the oscillator frequency. The MIC9130 contains an internal divide-by-two circuit that limits the maximum duty cycle at the gate drive to 50%. The oscillator frequency for the MIC9130 is twice the output switching frequency. Oscillator Pin The operation of the oscillator is shown in Figure 5. The volt- age waveform at the OSC pin is a sawtooth whose amplitude increases as capacitor Cosc is charged up through R OSC from the 5V bias. When the OSC pin voltage reaches the internal comparator upper threshold, C OSC is quickly discharged to zero volts by an internal MOSFET. After a brief delay, typi- cally 75ns, the internal MOSFET is turned off and the C OSC charges, repeating the cycle. Figure 5 show the relationship between the oscillator and gate drive waveforms. The delays in the IC force the duty cycle of the gate drive signal to be slightly less than 50% duty cycle (typically 48%). For V BIAS = 5V and a peak oscillator waveform voltage of 3V, the design equations simplify to: Charging tCHARGE ttRC=× ×09 2. Discharging tCDISCHARGE t≈ ×40 MIC9130 S SET RESET R Q LINE UVLO VCC UVLO VCC AGND VIN UVLO UVLO 1.21V PGND OUT SS 4μA Figure 4: UVLO and Soft Start Circuits

November 2008 15 M9999-111108 MIC9130 Micrel, Inc. series resistance is 10K, for a 500kHz switcher, the maximum series resistance is 2K. Sensing Current with a Resistor The fast transition times of the current signal prohibit the use of inductive resistors. Standard wire wound power resistors will not work. Carbon composition or metal fi lm resistors or low inductance power resistors may be used. The overcurrent range of the power supply and component tolerances must be considered when selecting the current sense resistor value. The power supply specifi cation may call for an overcurrent limit, which must be accounted for when selecting the cur- rent sense resistor value. The relationship between the peak primary current and the current sense resistor is: VI R I RISNS P ISENSE ISNS f=× + × where: Ip is the current in the sense resistor R ISENSE is the current sense resistance I ISNS is the current sourced from the ISNS pin (40μA) R f is the series resistor between the ISNS pin and the current sense resistor. The current sense resistor must not be too small or the cur- rent sense signal will be susceptible to noise. If noise is a problem, the current signal level should be increased. An example is illustrated below. The maximum peak current, I PMAX= 1A at 120% overcurrent and minimum input voltage The maximum rms current, IRMS=0.65A The desired current sense signal amplitude is 500mV at 1A output current. The current sense resistor value and power dissipation is: R V I 0.5 1 0.5SENSE SENSE SENSE == = Ω PIR WDISS RMS SENSE=× = × =2 206 5 05 02 1.. . A 0.5Ω, non inductive resistor with at least a 1/2W rating should be selected. The series resistor is calculated to allow the 500mV-peak signal to reach 0.82V. R VI R IA kf ISNS P ISENSE ISNS − ×() = − ×() μ = Ω08 2 1 05 40 10 25.. . The next lower value of 10kΩ is selected. The bandwidth of the 10K resistor and the 25pF input capaci- tance is calculated. The resistor value must be lowered if the bandwidth is too low for the switching frequency. BW kp F kHz= ×× × =1 21 0 2 5 630ππ The maximum switching frequency of this power supply should be approximately six times less than the BW to pre- vent current waveform distortion and excessive delays in the current loop. This limits the switching frequency to the range of 100kHz. Sensing Current with a Current Sense Transformer At higher power levels, the power dissipation in a current sense resistor is excessive. A current sense transformer can be used to sense the current while minimizing power dissipation. See Figure 11. The schematic shows the circuitry necessary when using a current sense transformer. The resistor, R1, provides a path to reset the current sense transformer. The resistor, R2, converts the scaled down current to a voltage, which is sent to the ISNS pin. OUT (pin 16) ISNS (pin 14) MIC9130 R2 R1 Rf IPRI VIN Current Sense Transformer Figure 11 The voltage at the ISNS pin is calculated by: V I N RI RISNS P ISNS f=× + × 2 where: I P is the current in the primary of the current sense transformer R2 is the current sense resistance at the secondary of the current sense transformer N is the turns ratio of the current sense transformer (N=Nsec/Npri) I ISNS is the current sourced from the ISNS pin (40μA) R f is the series resistor between the ISNS pin and the current sense resistor. Current Transformer example: The maximum peak current, I PMAX = 5A at 120% overcur- rent and minimum input voltage The maximum rms current, IRMS = 3.25A The full 0.82V peak signal a the ISNS input can be used since very little power is dissipation in the secondary side sense resistor. The maximum peak to peak volt- age at the sense pin (pin 14) is 0.82V at the 5A maximum output current. The current sense resistor value and power dissipation is: R VN I SENSE P 2 0 82 100 P I N Rm WDISS PRMS= ⎛ ⎝⎜ ⎞ ⎠⎟ ×= ⎛ ⎝⎜ ⎞ ⎠⎟ ×= 2 2 2 32 5 100 16 4 17 4. ..

MIC9130 Micrel, Inc. M9999-111108 16 November 2008 A 16.2 ohm, 1%, non inductive resistor with at least a 50mW rating should be selected. A good choice would be an 0805 size metal fi lm or a 1/8 watt leaded metal fi lm resistor. A series resistor between the current sense transformer and the Isns input is not necessary unless it is used for low pass fi ltering. If the current sense transformer were not used, the sense resistor would dissipate 1.7 watts. R V ISENSE SENSE SENSE == = Ω08 2 5 0 164. . PIR WDISS RMS SENSE=× = × =2 232 5 01 6 4 17... Slope Compensation Power supplies using peak current mode control techniques require slope compensation when they are operating in continuous mode and have a duty cycle greater than 50%. Without slope compensation, the duty cycle of the power sup- ply will alternate wide and narrow pulses commonly referred to as subharmonic oscillations. Even though the MIC9130 operates below a 50% duty cycle, slope compensation adds the bene fi ts of improved transient response and greater noise immunity in the current sense loop (especially when the current ramp is shallow). Slope compensation can be implemented by adding an optimum 1/2 of the inductor cur- rent downslope, refl ected back to the current sense input. In real world applications, 2/3 of the inductor current downslope is used to allow for component tolerances. Slope compensation at the ISNS input may be implemented by using a resistor and capacitor as shown in Figure 12. The rectangular waveshape of the gate drive output is integrated by the resistor/capacitor fi lter, which results in a ramp used for the slope compensation signal. When the gate drive and the current signal at the sense resistor goes low, the capaci- tor is discharged to 0V. Gate Drive (pin 16) ISNS (pin 14) MIC9130 R2 C1 RSENSE Figure 12 The procedure outlined below demonstrates how to calculate the component values. Compute the inductor current downslope as seen at the cur- rent sense input. For a fl yback, buck or forward mode topology the inductor downslope is equal to: M di dt VV L O D2= = + where : V O is the output voltage V D is the forward voltage drop of the rectifi er diode L is the inductance of the output inductor (or the secondary windin g inductance for the fl yback topology) M2 is the inductor current downslope For a boost topology, the inductor downslope is: M di dt VV V L OUT IN D2= = − + In a transformer isolated topology, the downslope must be refl ected back to the primary by the turns ratio of the trans- former. The refl ected downslope is: MM Ns NpREFLECTED22 =× where : Ns/Np is the turns ratio of the secondary winding to the primary winding. M2 REFLECTED is the inductor curent downslope refl ected to the secondary side of the current sense transformer. The refl ected downslope is multiplied by the current sense resistor to obtain the downslope at the current sense input pin (ISNS). IM RSNS SLOPE REFLECTED S_ =× 2 where Rs is the value of the current sense resistor. The required downslope of the compensation ramp at the ISNS input is: MI SNS SLOPE30 6 7=× _ . R1 is know if a value for the resistor between the current sense resistor and the Isns pin, has already been selected. If not chose a value of 1k, which will minimize any offset and signal degradation at the ISNS pin. Select a value of C1 to minimize signal degradation from the cutoff frequency of R1/C1. The bandwidth should be at least six times the switching frequency. C fRS 1 1 21= ×××ππ where: f S is the switching frequency of the power supply (not the oscillator frequency) The slope of the generated compensation ramp is: MV R1 R2 R1 R2 C1GATE_DRIVE3= × + × × Solving for R2 and assuming R2 is much greater than R1. R VR MC GATE DRIVE2 1 31= × where: VGATE_DRIVE is the amplitude of the gate drive waveform

November 2008 17 M9999-111108 MIC9130 Micrel, Inc. Error Amplifi er The error amplifi er is part of the voltage control loop of the power supply. The FB pin is the inverting input to the error amplifi er. The non-inverting input is internally connected to a 2.5V reference. The output of the error ampli fi er, COMP, is connected to the PWM comparator. The error ampli fi er provides the reference to limit and control the peak current of the power supply. There is a 1.2V level shift between the output of the error amplifi er and the PWM comparator. This allows the output of the error amplifi er to operate in a linear region and prevents loading on the COMP pin from interfering with proper control of the current signal.

MIC9130 Micrel, Inc. M9999-111108 18 November 2008

Package Information

16-Lead SOIC (M) 16-Lead QSOP (QS)

November 2008 19 M9999-111108 MIC9130 Micrel, Inc. MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifi cations at any time without notifi cation to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signifi cant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2001 Micrel Incorporated