MIC5010 MICREL | Alldatasheet

Document overview

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Technical content

Features

  • 7V to 32V operation
  • Less than 1µA standby current in the “OFF” state
  • Internal charge pump to drive the gate of an N-channel power FET above supply
  • Available in small outline SOIC packages
  • Internal zener clamp for gate protection
  • 2 5µs typical turn-on time to 50% gate overdrive
  • Programmable over-current sensing
  • Dynamic current threshold for high in-rush loads
  • Fault output pin indicates current faults
  • Implements high- or low-side switches

Applications

  • Lamp drivers
  • Relay and solenoid drivers
  • Heater switching
  • Power bus switching
  • Motion control
  • Half or full H-bridge drivers Typical Application Protected under one or more of the following Micrel patents: patent #4,951,101; patent #4,914,546 Note: The MIC5010 is ESD sensitive.

Pin Description (Refer to Figures 1 and 2) Pin Number Pin Name Pin Function 1 Inhibit Inhibits current sense function when connected to supply. Normally grounded.

3 Input Resets current sense latch and turns on power MOSFET when taken above

threshold (3.5V typical). Pin 3 requires <1µA to switch.

4 Threshold Sets current sense trip voltage according to:

R +1000TRIPV= TH where RTH to ground is 3.3k to 20kΩ . Adding capacitor CTH increases the trip voltage at turn-on to 2V. Use CTH =10µF for a 10mS turn-on time constant.

5 Sense The sense pin causes the current sense to trip when V SENSE is VTRIP above

VSOURCE . Pin 5 is used in conjunction with a current shunt in the source of a 3 lead FET or a resistor RS in the sense lead of a current sensing FET.

6 Source Reference for the current sense voltage on pin 5 and return for the gate

clamp zener. Connect to the load side of current shunt or kelvin lead of current sensing FET. Pins 5 and 6 can safely swing to –10V when turning off inductive loads.

7 Ground

8 Gate Drives and clamps the gate of the power FET. Pin 8 will be clamped to approximately –0.7V by an internal diode when turning off inductive loads. 9, 10, 11 C2, Com, C1 Optional 1nF capacitors reduce gate turn-on time; C2 has dominant effect.

13 V + Supply pin; must be decoupled to isolate from large transients caused by

the power FET drain. 10µF is recommended close to pins 13 and 7. 14 Fault Outputs status of protection circuit when pin 3 is high. Fault low indicates normal operation; fault high indicates current sense tripped. Absolute Maximum Ratings (Note 1, 2) Inhibit Voltage, Pin 1 –1V to V+ Input Voltage, Pin 3 –10V to V+ Threshold Voltage, Pin 4 – 0.5 to +5V Sense Voltage, Pin 5 –10V to V+ Source Voltage, Pin 6 –10V to V+ Current into Pin 6 50 mA Gate Voltage, Pin 8 –1V to 50V Supply Voltage (V +), Pin 13 –0.5V to 36V Fault Output Current, Pin 14 –1mA to +1mA Junction Temperature 150 °C Operating Ratings (Notes 1, 2) Power Dissipation 1.56W θJA (Plastic DIP) 80 °C/W θJA (SOIC) 115 °C/W Ambient Temperature: B version –40 °C to +85°C Storage Temperature –65 °C to +150°C Lead Temperature 260 °C (Soldering, 10 seconds) Supply Voltage (V +), Pin 13 7V to 32V high side 7V to 15V low side Pin Configuration Inhibit Input Thresh Sense Source Gnd Fault Com Gate 7 8 MIC5010 NC NC

Electrical Characteristics (Note 3) Test circuit. TA = –55°C to +125°C, V+ = 15V, V1 = 0 V, I4 = I5 = I14 = 0, all switches open, unless otherwise specified. Parameter Conditions Min Typical Max Units Supply Current, I13 V+ = 32V V IN = 0V, S4 closed 0.1 10 µA VIN = VS = 32V, I4 = 200µA8 2 0 m A Logic Input Voltage, VIN V+ = 4.75V Adjust V IN for VGATE low 2 V Adjust VIN for VGATE high 4.5 V V+ = 15V Adjust V IN for VGATE high 5.0 V Logic Input Current, I3 V+ = 32V V IN = 0V –1 µA VIN = 32V 1 µA Input Capacitance Pin 3 5 pF Gate Drive, VGATE S1, S2 closed, V + = 7V, I8 = 0 13 15 V VS = V+, VIN = 5V V + = 15V, I8 = 100 µA2 4 2 7 V Zener Clamp, S2 closed, V IN = 5V V+ = 15V, V S = 15V 11 12.5 15 V VGATE – VSOURCE V+ = 32V, VS = 32V 11 13 16 V Gate Turn-on Time, tON VIN switched from 0 to 5V; measure time 25 50 µs (Note 4) for V GATE to reach 20V Gate Turn-off Time, tOFF VIN switched from 5 to 0V; measure time 4 10 µs for VGATE to reach 1V Threshold Bias Voltage, V4 I4 = 200 µA 1.7 2 2.2 V Current Sense Trip Voltage, S2 closed, VIN = 5V, V + = 7V, S4 closed 75 105 135 mV VSENSE – VSOURCE Increase I5 I4 = 100 µAV S = 4.9V 70 100 130 mV V+ = 15V S4 closed 150 210 270 mV I4 = 200 µAV S = 11.8V 140 200 260 mV V+ = 32V V S = 0V 360 520 680 mV I4 = 500 µAV S = 25.5V 350 500 650 mV Peak Current Trip Voltage, S3, S4 closed, 1.6 2.1 V VSENSE – VSOURCE V+ = 15V, VIN = 5V Fault Output Voltage, V14 VIN = 0V, I14 = –100 µA 0.4 1 V VIN = 5V, I14 = 100 µA, current sense tripped 14 14.6 V Current Sense Inhibit, V1 V1 above which current sense is disabled 7.5 13 V Minimum possible V1 1V Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device beyond its specified Operating Ratings. Note 2 The MIC5010 is ESD sensitive. Note 3 Minimum and maximum Electrical Characteristics are 100% tested at TA = 25°C and TA = 85°C, and 100% guaranteed over the entire range. Typicals are characterized at 25°C and represent the most likely parametric norm. Note 4 Test conditions reflect worst case high-side driver performance. Low-side and bootstrapped topologies are significantly faster—see Applications Information.

3.5k VS 1nF 1nF 1nF I14 Inhibit Input Thresh Sense Source Gnd Fault Com Gate 7 8 MIC5010 S3 I4 + 1mF 500W NC NC Test Circuit 0 5 10 15 20 25 30 35 Supply Current SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA) 0 3 6 9 12 15 SUPPLY VOLTAGE (V) VGATE – V+ (V) DC Gate Voltage above Supply Typical Characteristics

TURN-ON TIME (mS) SUPPLY VOLTAGE (V) High-side Turn-on Time* GATEC =1 nF 0369 1 2 1 50 100 120 140 TURN-ON TIME (mS) SUPPLY VOLTAGE (V) C2=1 nF High-side Turn-on Time* GATEC =1 nF 0369 1 2 1 5 TURN-ON TIME (mS) SUPPLY VOLTAGE (V) High-side Turn-on Time* GATEC =10 nF 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0369 1 2 1 5 TURN-ON TIME (mS) SUPPLY VOLTAGE (V) C2=1 nF High-side Turn-on Time* GATEC =10 nF 0.2 0.4 0.6 0.8 1.0 1.2 1.4 CHARGE-PUMP CURRENT ( mA) 100 150 200 250 0 5 10 15 20 25 30 SUPPLY VOLTAGE (V) Charge Pump Output Current V =VGATE + V =V +5VGATE + VS=V –5V+ CHARGE-PUMP CURRENT (mA) 0 5 10 15 20 25 30 SUPPLY VOLTAGE (V) Charge Pump Output Current V =VGATE + 0.2 0.4 0.6 0.8 1.0 V =V +5VGATE + VS=V –5V+ C2=1 nF Typical Characteristics (Continued) * Time for gate to reach V+ + 5V in test circuit with VS = V+ – 5V (prevents gate clamp from interfering with measurement).

SUPPLY VOLTAGE (V) GATEC =10 nF TURN-OFF TIME (mS) GATEC =1 nF Turn-off Time 0.5 0.75 1.0 1.25 1.5 1.75 2.0 –25 0 25 50 75 100 125 DIE TEMPERATURE ( °C) NORMALIZED TURN-ON TIME Turn-on Time 0369 1 2 1 5 SUPPLY VOLTAGE (V) GATEC =10 nF 100 300 1000TURN-ON TIME (mS) GATEC =1 nF Low-side Turn-on Time for Gate = 5V 0369 1 2 1 5 SUPPLY VOLTAGE (V) C2=1 nF GATEC =10 nF 100 300 1000TURN-ON TIME (mS) GATEC =1 nF Low-side Turn-on Time for Gate = 5V 0369 1 2 1 5 SUPPLY VOLTAGE (V) GATEC =10 nF TURN-ON TIME (mS) GATEC =1 nF Low-side Turn-on Time for Gate = 10V 100 300 1000 3000 0369 1 2 1 5 SUPPLY VOLTAGE (V) GATEC =10 nF TURN-ON TIME (mS) GATEC =1 nF Low-side Turn-on Time for Gate = 10V 100 300 1000 3000 C2=1 nF Typical Characteristics (Continued)

Functional Description (Refer to Block Diagram) The various MIC5010 functions are controlled via a logic block connected to the input pin 3. When the input is low all functions are turned off for low standby current, and the gate of the power MOSFET is also held low through 500Ω to an N-channel switch. When the input is taken above the turn- on threshold (3.5V typical), the N-channel switch turns off and the charge pump is turned on to charge the gate of the power FET. A bandgap type voltage regulator is also turned on which biases the current sense circuitry. The charge pump incorporates a 100kHz oscillator and on- chip pump capacitors capable of charging 1 nF to 5V above supply in 60µS typical. With the addition of 1nF capacitors at C1 and C2, the turn-on time is reduced to 25µS typical. The charge pump is capable of pumping thegate up to over twice the supply voltage. For this reason a zener clamp (12.5V typical) is provided between the gate pin 8 and the source pin 6 to prevent exceeding the V GS rating of the MOSFET at high supplies. The current sense operates by comparing the sense volt- age at pin 5 to an offset version of the source voltage at pin 6. Current I4 flowing in threshold pin 4 is mirrored and returned to the source via a 1kΩ resistor to set the offset or trip voltage. When (V SENSE – VSOURCE ) exceeds VTRIP , the current sense trips and sets the current sense latch to turn off the power FET. An integrating comparator is used to reduce sensitivity to spikes on pin 5. The latch is reset to turn the FET back on by “recycling” the input pin 3 low and then high again. A resistor R TH from pin 4 to ground sets I4, and hence VTRIP. An additional capacitor CTH from pin 4 to ground creates a higher trip voltage at turn-on, which is necessary to prevent high in-rush current loads such as lamps or capacitors from false-tripping the current sense. When the current sense has tripped, the fault pin 14 will be high as long as the input pin 3 remains high. However, when the input is low the fault pin will also be low. Construction Hints High current pulse circuits demand equipment and assem- bly techniques that are more stringent than normal, low current lab practices. The following are the sources of common pitfalls encountered while prototyping:Supplies: many bench power supplies have poor transient response. Circuits that are being pulse tested, or those that operate by pulse-width modulation will produce strange results when used with a supply that has poor ripple rejection, or a peaked transient response. Monitor the power supply volt- age that appears at the drain of a high-side driver (or the supply side of the load in a low-side driver) with an oscillo- scope. It is not uncommon to find bench power supplies in the 1kW class that overshoot or undershoot by as much as 50% when pulse loaded. Not only will the load current and voltage measurements be affected, but it is possible to over-stress various components—especially electrolytic capacitors—with possibly catastrophic results. A 10µF sup- ply bypass capacitor at the chip is recommended. CHARGE PUMP TEMP SENSE V. REG R S Q LOGIC MIC5010 71 4 9101113 500W C1 Com C2V+ Gate Sense Source Ground Inhibit Threshold Input Fault CURRENT SENSE LATCH VTRIP 12.5V Block Diagram

load current that just trips the over-current comparator. VTRIP. RTH is selected to produce the desired trip voltage. S, to eliminate the effects of ground resistance. a large current will be forced through the gate clamp zener. 10V enhancement in 10µs or less on a 12 to 15V supply. as the voltage drop across R1 (and therefore R2) is zero. Figure 2. Low-Side Driver with

and it dissipates the energy stored in the load inductance. reduce power dissipation in the MOSFET. potentials of 200mV thermocouple effects are insignificant. shunt service drift less than 100ppm/°C. Figure 3. High-Side Driver

Figure 11. Half-Bridge

Figure 14. Gate Control and is clamped by the zener diode. and Q4 back on, and Q1 and Q3 off. be limited to 15V in low-side applications.