MIC4120_05 MICREL | Alldatasheet

Document overview

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Technical content

Features

  • CMOS Construction
  • Latch-Up Protected: Will Withstand >200mA Reverse Output Current
  • Logic Input Withstands Negative Swing of Up to 5V 25ns
  • Logic High Input for Any Voltage From 2.4V to V S
  • Output Voltage Swing Within 25mV of Ground or V S
  • Exposed backside pad packaging reduces heat - ePAD SOIC-8L ( θJA = 58°C/W) - 3mm x 3mm MFL™-8L (θJA = 60°C/W)

Applications

  • Switch Mode Power Supplies
  • Motor Controls
  • Pulse Transformer Driver
  • Class-D Switching Amplifiers Functional Diagram IN OUT MIC4129 INVERTING MIC4120 NONINVERTING 0.1mA 0.4mA 2kΩ VS GND Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

MIC4120/4129 Micrel, Inc. M9999-081105 2 August 2005 Pin Configurations V S OU T OU T GND V S IN NC GND EPAD SOIC-8 (ME) MLF-8 (ML)

Ordering Information

Part Number Package Configuration Lead Finish MIC4120YME EPAD 8-Pin SOIC Non-Inverting Pb-Free MIC4120YML 8-Pin MLF Non-Inverting Pb-Free MIC4129YME EPAD 8-Pin SOIC Inverting Pb-Free MIC4129YML 8-Pin MLF Inverting Pb-Free Pin Description Pin Number Pin Name Pin Function

2 IN Control Input

4, 5 GND Ground: Duplicate pins must be externally connected together 1, 8 VS Supply Input: Duplicate pins must be externally connected together 6, 7 OUT Output: Duplicate pins must be externally connected together

3 NC Not connected

EP GND Ground: Backside

MIC4120/4129 Micrel, Inc. August 2005 3 M9999-081105 Electrical Characteristics: (TA = 25°C with 4.5V ≤ VS ≤ 20V unless otherwise specified. Note 3.) Input Voltage slew rate >1V/µs Symbol Parameter Conditions Min Typ Max Units INPUT VIH Logic 1 Input Voltage 2.4 1.9 V VIL Logic 0 Input Voltage 1.5 0.8 V VIN Input Voltage Range –5 V S + 0.3 V IIN Input Current 0 V ≤ VIN ≤ VS –10 10 µA OUTPUT VOH High Output Voltage See Figure 1 VS–0.025 V VOL Low Output Voltage See Figure 1 0.025 V RO Output Resistance, IOUT = 10 mA, VS = 20 V 1.4 5 Ω Output Low RO Output Resistance, IOUT = 10 mA, VS = 20 V 1.5 5 Ω Output High IPK Peak Output Current VS = 20 V (See Figure 6) 6 A IR Latch-Up Protection 200 mA Withstand Reverse Current SWITCHING TIME tR Rise Time Test Figure 1, CL = 2200 pF 12 30 ns 35 ns tF Fall Time Test Figure 1, CL = 2200 pF 13 30 ns 35 ns tD1 Delay Time Test Figure 1 45 75 ns 100 ns tD2 Delay Time Test Figure 1 50 75 ns 100 ns POWER SUPPLY IS Power Supply Current V IN = 3 V 0.45 3 mA VIN = 0 V 60 400 µA VS Operating Input Voltage 4.5 20 V Notes: 1. Functional operation above the absolute maximum stress ratings is not implied. 2. Static-sensitive device. Store only in conductive containers. Handling personnel and equipment should be grounded to prevent damage from static discharge. 3. Specification for packaged product only. Absolute Maximum Ratings (Notes 1, 2 and 3) ESD Rating, Note 4 Operating Ratings Package Thermal Resistance

MIC4120/4129 Micrel, Inc. August 2005 5 M9999-081105 Typical Characteristics 5 1 0 1 5 2 0 RISE TIME (ns) INPUT VOLTAGE (V) R is eT ime 4700p F 10000 pF 2200p F 5 1 0 1 5 2 0 FALL TIME (ns) INPUT VOLTAGE (V) F all T ime 4700p F 10000 pF 2200p F 5 1 0 1 5 2 0 DELAY TIME (ns) INPUT VOLTAGE (V) De la y T ime vs . Input V oltag e td1 td2 0.5 1.0 1.5 2.0 2.5 3.0 5 1 0 1 5 2 0 RESISTANCE (Ω) SUPPLY VOLTAGE (V) Ou tput R es is tan c e vs . S upply V oltag e Output Low Output Hi gh

MIC4120/4129 Micrel, Inc. M9999-081105 6 August 2005 Applications Information Supply Bypassing Charging and discharging large capacitive loads quickly requires large currents. For example, charging a 2500pF load to 18V in 25ns requires a 1.8 A current from the device power supply. The MIC4120/4129 has double bonding on the supply pins, the ground pins and output pins This reduces parasitic lead inductance. Low inductance enables large currents to be switched rapidly. It also reduces internal ringing that can cause voltage breakdown when the driver is operated at or near the maximum rated voltage. Internal ringing can also cause output oscillation due to feedback. This feedback is added to the input signal since it is referenced to the same ground. To guarantee low supply impedance over a wide frequency range, a parallel capacitor combination is recommended for supply bypassing. Low inductance ceramic capacitors should be used. A 1µF low ESR film capacitor in parallel with two 0.1 µF low ESR ceramic capacitors provide adequate bypassing. Connect one ceramic capacitor directly between pins 1 and 4. Connect the second ceramic capacitor directly between pins 8 and 5. Grounding The high current capability of the MIC4120/4129 demands careful PC board layout for best performance. Since the MIC4129 is an inverting driver, any ground lead impedance will appear as negative feedback which can degrade switch ing speed. Feedback is especially noticeable with slow-rise time inputs. Figure 3 shows the feedback effect in detail. As the MIC4129 input begins to go positive, the output goes negative and several amperes of current flow in the ground lead. As little as 0.05Ω of PC trace resistance can produce hundreds of millivolts at the MIC4129 ground pins. If the driving logic is referenced to power ground, the effective logic input level is reduced and oscillation may result. To insure optimum performance, separate ground traces should be provided for the logic and power connections. Con- necting the logic ground directly to the MIC4129 GND pins will ensure full logic drive to the input and ensure fast output switching. Both of the MIC4129 GND pins should, however, still be connected to power ground. The E-Pad and MLF packages have an exposed pad under the package. It's important for good thermal performance that this pad is connected to a ground plane.

level signals reduce quiescent current to 55µA maximum. The MIC4120/4129 input is designed to provide hysteresis. improve performance and reliability. will occur to MIC4120/4129 however, and it will not latch. loads and/or operating at high frequency. be obtained by summing the three dissipation sources.

  • Load Power Dissipation (PL)
  • Quiescent power dissipation (PQ)
  • Transition power dissipation (PT) Calculation of load power dissipation differs depending upon whether the load is capacitive, resistive or inductive. Resistive Load Power Dissipation Dissipation caused by a resistive load can be calculated as: PL = I2 RO D where: I = the current drawn by the load R O = the output resistance of the driver when the output is high, at the power supply voltage used. (See data sheet) D = fraction of time the load is conducting (duty cycle)

Figure 3. Switching Time Degradation Due to

6 AMPS

MIC4120/4129 Micrel, Inc. M9999-081105 8 August 2005 Transition Power Dissipation Transition power is dissipated in the driver each time its out- put changes state, because during the transition, for a very brief interval, both the N- and P-channel MOSFETs in the output totem-pole are ON simultaneously, and a current is conducted through them from V S to ground. The transition power dissipation is approximately: P T = 2 f VS (A•s) where (A•s) is a time-current factor derived from the typical characteristic curves. Total power (P D) then, as previously described is: P D = PL + PQ +PT Definitions CL = Load Capacitance in Farads. D = Duty Cycle expressed as the fraction of time the input to the driver is high. f = Operating Frequency of the driver in Hertz. I H = Power supply current drawn by a driver when both inputs are high and neither output is loaded. I L = Power supply current drawn by a driver when both inputs are low and neither output is loaded. I D = Output current from a driver in Amps. P D = Total power dissipated in a driver in Watts. P L = Power dissipated in the driver due to the driver’s load in Watts. P Q = Power dissipated in a quiescent driver in Watts. P T = Power dissipated in a driver when the output changes states (“shoot-through current”) in Watts. NOTE: The “shoot-through” current from a dual transition (once up, once down) for both drivers is shown by the "Typical Characteristic Curve": Crossover Area vs. Supply Voltage and is in am pere-seconds. This figure must be multiplied by the number of repetitions per second (frequency) to find Watts. R O = Output resistance of a driver in Ohms. V S = Power supply voltage to the IC in Volts. Capacitive Load Power Dissipation Dissipation caused by a capacitive load is simply the energy placed in, or removed from, the load capacitance by the driver. The energy stored in a capacitor is described by the equation: E = 1/2 C V 2 As this energy is lost in the driver each time the load is charged or discharged, for power dissipation calculations the 1/2 is removed. This equation also shows that it is good practice not to place more voltage on the capacitor than is necessary, as dissipation increases as the square of the voltage applied to the capacitor. For a driver with a capacitive load: P L = f C (VS)2 where: f = Operating Frequency C = Load Capacitance V S = Driver Supply Voltage Inductive Load Power Dissipation For inductive loads the situation is more complicated. For the part of the cycle in which the driver is actively forcing current into the inductor, the situation is the same as it is in the resistive case: P L1 = I2 RO D However, in this instance the R O required may be either the on resistance of the driver when its output is in the high state, or its on resistance when the driver is in the low state, depending on how the inductor is connected, and this is still only half the story. For the part of the cycle when the induc tor is forcing current through the driver, dissipation is best described as P L2 = I VD (1-D) where VD is the forward drop of the clamp diode in the driver (generally around 0.7V). The two parts of the load dissipation must be summed in to produce PL P L = PL1 + PL2 Quiescent Power Dissipation Quiescent power dissipation (P Q, as described in the input section) depends on whether the input is high or low. A low input will result in a maximum current drain (per driver) of ≤0.2mA; a logic high will result in a current drain of ≤2.0mA. Quiescent power can therefore be found from: P Q = VS [D IH + (1-D) IL] where: I H = quiescent current with input high I L = quiescent current with input low D = fraction of time input is high (duty cycle) V S = power supply voltage

Figure 4. Peak Output Current Test Circuit

MIC4120/4129 Micrel, Inc. M9999-081105 10 August 2005

Package Information

8-Pin 3x3 MLF (ML) 8-Pin Exposed Pad SOIC (ME) MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2004 Micrel Incorporated