MIC4126 MICROCHIP | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 22

Technical content

Features

  • Dual 1.5A-Peak Drivers
  • 4.5V to 20V Operating Range
  • Exposed Backside Pad Packaging Reduces Heat - ePAD SOIC-8L ( JA = 58°C/W) - ePAD MSOP-8L ( JA = 60°C/W) - VDFN ML™-8L ( JA = 60°C/W)
  • Bipolar/CMOS/DMOS Construction - 25mV maximum output offset from supply or ground
  • Latch-Up Protection to >200mA Reverse Current
  • Switches 1000pF in 25ns
  • Logic-Input Threshold Independent of Supply Voltage
  • Logic-Input Protection to –5V
  • 6pF Typical Equivalent Input Capacitance
  • Dual Inverting, Dual Noninverting, and Complementary Configurations - -40°C to +125°C operating junction tempera- ture range General Description The MIC4126, MIC4127, and MIC4128 family are highly-reliable dual 1.5A low-side MOSFET drivers fabricated on Microchi p’s BiCMOS/DMOS process. The devices feature low power consumption and high efficiency. The MIC4126/27/28 translate TTL or CMOS input logic levels to output voltage levels that swing within 25mV of the positiv e supply or ground whereas comparable bipolar devices are capable of swinging only to within 1V of the supply. The MIC4126/7/8 is available in three configurations: dual inverting, dual noninverting, and complimentary output. The MIC4126/27/28 offer pin-compatible as well as smaller footprint replacements for the MIC4426/27/28 with improved packaging and electrical performance. The MIC4126/27/28 are available in exposed pad, EPAD, SOIC-8L and MSOP-8L options as well as a small-size VDFN ML™-8L option. The devices have an input operating range of 4.5V to 20V. Primarily intended for driving power MOSFETs, MIC4426/7/8 drivers are suitable for driving other loads (capacitive, resistive, or inductive) which require low-impedance, high peak current, and fast switching time. The devices can withstand up to 500mA of reverse current (either polarity) without latching and up to 5V noise spikes (either polarity) on ground pins. Data sheets and support documentation can be found on Microchip’s website at www.microchip.com.

Applications

  • DC/DC Converters
  • Motor Drivers
  • Clock Line Driver Package Types MIC4126 ePad SOIC-8L (ME) ePad MSOP-8L (MME) VDFN-8 (ML) (Top View) MIC4127 ePad SOIC-8L (ME) ePad MSOP-8L (MME) VDFN-8 (ML) (Top View) MIC4128 ePad SOIC-8L (ME) ePad MSOP-8L (MME) VDFN-8 (ML) (Top View) Dual 1.5A-Peak Low-Side MOSFET Drivers in Advanced Packaging

 2019 Microchip Technology Inc. DS20006084A-page 2 MIC4126/27/28 Functional Block Diagram The function block diagram contains only four resistors, four capacitors, and 52 transistors. Be sure to ground any unused inputs. INA OUTA INVERTING NONINVERTING 0.1mA 0.6mA 2k: INB OUTB INVERTING NONINVERTING 0.1mA 0.6mA 2k: VS GND

 2019 Microchip Technology Inc. DS20006084A-page 3 MIC4126/27/28

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † Operating Ratings †† † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this s pecification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. †† Notice: The device is not guaranteed to function outside its operating ratings. Note 1: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 k in series with 100 pF.

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: 4.5V  VS  20V; TA = +25°C, bold values indicate full specified temperature range; unless noted. Input voltage slew rate >1V/µs; COUT = 1000pF. Note 1 Parameter Sym. Min. Typ. Max. Units Conditions Input Logic 1 Input Voltage VIH 2.4 1.4 — V — 2.4 1.6 —V — Logic 0 Input Voltage VIL —1 . 1 0 . 8 V — — 1.3 0.8 V— Input Current I IN –1 — 1 µA 0V  VIN  VS Output High Output Voltage V OH VS – 0.025 —— V — Low Output Voltage V OL —— 0.025 V— Output Resistance R O —6 1 0  IOUT = 10 mA, VS = 20V — 81 2 Peak Output Current I PK — 1.5 —A — Latch-Up Protection I >200 — — mA Withstand Reverse Current Switching Time Rise Time t R —1 3 3 0 ns Test Figure 1-1 — 20 40 Fall Time t F —1 5 2 5 ns Test Figure 1-1 — 18 40 Delay Time t D1 —3 7 5 0 ns Test Figure 1-1 — 43 60 Delay Time t D2 —4 0 6 0 ns Test Figure 1-1 — 45 70 Note 1: Specification for packaged product only.

 2019 Microchip Technology Inc. DS20006084A-page 4 MIC4126/27/28 Power Supply Power Supply Current I S —1 . 4 4 . 5 mA V INA = VINB 3.0V — 1.5 8 Power Supply Current I S — 0.18 0.4 mA V INA = VINb 0.0V — 0.19 0.6 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: 4.5V  VS  20V; TA = +25°C, bold values indicate full specified temperature range; unless noted. Input voltage slew rate >1V/µs; COUT = 1000pF. Note 1 Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Specification for packaged product only.

 2019 Microchip Technology Inc. DS20006084A-page 5 MIC4126/27/28 TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Maximum Junction Temperature T J — — +150 °C — Storage Temperature Range T S –65 — +150 °C — Lead Temperature — — — +300 °C 10 sec. Junction Operating Temperature Range TJ –40 — +125 °C — Package Thermal Resistances Thermal Resistance, 3x3 VDFN 8-Ld JA —6 0 — ° C / W — Thermal Resistance, EP MSOP 8-Ld JA —6 0 — ° C / W — Thermal Resistance, EP SOIC 8-Ld JA —5 8 — ° C / W — Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.

 2019 Microchip Technology Inc. DS20006084A-page 7 MIC4126/27/28

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: Rise and Fall Time. FIGURE 2-2: MIC4127 Supply Current vs. Capacitive Load. FIGURE 2-3: Supply Current vs. Frequency. FIGURE 2-4: MIC4126 Output Resistance. FIGURE 2-5: Turn On and Turn Off Delay. FIGURE 2-6: Rise and Fall Time vs. Capacitive Load. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or t ables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

 2019 Microchip Technology Inc. DS20006084A-page 9 MIC4126/27/28

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Number Pin Name Description 1, 8 NC Not internally connected

2 INA Control Input A: TTL/CMOS compatible logic input

3 GND Ground

4 INB Control Input B: TTL/CMOS compatible logic input

5 OUTB Output B: CMOS totem-pole output

S Supply Input: +4.5V to +20V

7 OUTA Output A: CMOS totem-pole output

EP GND Ground, backside pad

 2019 Microchip Technology Inc. DS20006084A-page 10 MIC4126/27/28

4.0 APPLICATION INFORMATION

Large currents are required to charge and discharge large capacitive loads quickly. For example, changing a 1000pF load by 16V in 25ns requires 0.8A from the supply input. To ensure low supply impedance over a wide frequency range, parallel capacitors are recommended for power supply bypassing. Low-inductance ceramic MLC capacitors with short lead lengths (< 0.5") should be used. A 1.0µF film capacitor in parallel with one or two 0.1µF ceramic MLC capacitors normally provides adequate bypassing. Grounding When using the inverting drivers in the MIC4126 or MIC4128, individual ground returns for the input and output circuits or a ground plane are recommended for optimum switching speed. The voltage drop that occurs between the driver’s ground and the input signal ground, during normal high-current switching, will behave as negative feedback and degrade switching speed. The E-pad and ML packages have an exposed pad under the package. It is important for good thermal performance that this pad is connected to a ground plane. Control Input Unused driver inputs must be connected to logic high (which can be V S) or ground. For the lowest quiescent current (< 500µA), connect unused inputs-to-ground. A logic-high signal will cause the driver to draw up to 9mA. The control input voltage threshold is approximately 1.5V. The control input recognizes 1.5V up to V S as a logic high and draws less than 1µA within this range. Power Dissipation Power dissipation should be calculated to make sure that the driver is not ope rated beyond its thermal ratings. Quiescent power dissipation is negligible. A practical value for total power dissipation is the sum of the dissipation caused by the load and the transition power dissipation (P L + PT). Load Dissipation Power dissipation caused by continuous load current (when driving a resistive load) through the driver’s output resistance is: P L = IL2 RO For capacitive loads, the dissipation in the driver is: PL = f CL VS2 Transition Dissipation In applications switching at a high frequency, transition power dissipation can be significant. This occurs during switching transitions when the P-channel and N-channel output FETs are both conducting for the brief moment when one is turning on and the other is turning off. P T = 2 f VS Q Charge (Q) is read from the following graph: Crossover Energy Loss per Transition

 2019 Microchip Technology Inc. DS20006084A-page 11 MIC4126/27/28

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Example8-Lead SOIC* XXX XXXXXXX WNNN MIC 4123YME 8790 Example8-Lead VDFN* XXXXXXX WNNN 4125YML 2943 8-Lead MSOP Example XXXXXX 0NNN 4126YM 0NNN Legend: XX...X Product code or cust omer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.

  • , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (⎯) symbol may not be to scale.

 2019 Microchip Technology Inc. DS20006084A-page 12 MIC4126/27/28 8-Lead SOICN ePad Package Outline and Recommended Land Pattern © 2018 Microchip Technology Incorporated CSEATING PLANE END VIEW BOTTOM VIEW 0.10 C Microchip Technology Drawing C04-1136 Rev A Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Small Outline Integrated Circuit Package (EQA) - 3.90 mm (1.50 In) Body [SOIC] With 3.10x2.41 mm Exposed Pad A D E e B A E 0.10 C SIDE VIEW TOP VIEW 0.18 C

0.09 C D

0.09 C A-B

D h h SEE DETAIL A

 2019 Microchip Technology Inc. DS20006084A-page 13 MIC4126/27/28 © 2018 Microchip Technology Incorporated Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Lead Thickness Pitch Standoff Units Dimension Limits A b c e L E N

1.27 BSC

0.20 0.41 0.35 1.43 0.00 0.41 0.64 2.41 1.55 0.05

6.02 BSC

0.89 0.49 1.68 0.10 MAX L1 1.04 REFTerminal-to-Exposed-Pad For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Overall Length Exposed Pad Length D

4.89 BSC

3.10 REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M ڧ C L (L1) Molded Package Thickness A2 1.25 - - Foot Angle Terminal Length Lead Bend Radius R1 0.07 0° 5° -5° 15°Mold Draft Angle ڧ Mold Draft Angle - 5° 15° -0.07 0.250.19 Molded Package Width E1 3.90 BSC Microchip Technology Drawing C04-1136 Rev A Sheet 2 of 2 8-Lead Small Outline Integrated Circuit Package (EQA) - 3.90 mm (1.50 In) Body [SOIC] With 3.10x2.41 mm Exposed Pad C SEATING PLANE DETAIL A

 2019 Microchip Technology Inc. DS20006084A-page 14 MIC4126/27/28 © 2018 Microchip Technology Incorporated RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Optional Center Pad Length Contact Pitch 2.45 3.15 MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) 1.60 0.60 NOM CContact Pad Spacing 5.40 Contact Pad to Center Pad (X8) G1 0.68 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Microchip Technology Drawing C04-1136 Rev A 8-Lead Small Outline Integrated Circuit Package (EQA) - 3.90 mm (1.50 In) Body [SOIC] With 3.10x2.41 mm Exposed Pad E EV EVC ØV Contact Pad to Contact Pad (X6) G2 0.67 SILK SCREEN

 2019 Microchip Technology Inc. DS20006084A-page 15 MIC4126/27/28 8-Lead MSOP ePad Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

 2019 Microchip Technology Inc. DS20006084A-page 16 MIC4126/27/28 BA 0.05 C 0.05 C

0.10 C A B

0.05 C (DATUM A) C SEATING PLANE TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing C04-1021 A Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Very Thin Plastic Dual Flat, No Lead Package (JMA) - 3x3x0.9 mm Body [VDFN] Micrel Legacy Package DFN33-8LD-PL-1 D E e L 8X b K (A3) A N (DATUM B)

 2019 Microchip Technology Inc. DS20006084A-page 17 MIC4126/27/28 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.65 BSC

0.203 REF

1.50 0.35 0.20 0.80 0.00 0.25 0.40 1.55 0.85 0.02

3.00 BSC

1.60 0.45 0.30 0.90 0.05 MAX K- 0.20 -Terminal-to-Exposed-Pad Overall Length Exposed Pad Length D D2 2.25 2.30 2.35 Microchip Technology Drawing C04-1021 A Sheet 1 of 2 8-Lead Very Thin Plastic Dual Flat, No Lead Package (JMA) - 3x3x0.9 mm Body [VDFN] Micrel Legacy Package DFN33-8LD-PL-1

 2019 Microchip Technology Inc. DS20006084A-page 18 MIC4126/27/28 RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Optional Center Pad Length Contact Pitch 1.60 2.35 MILLIMETERS E MAX Contact Pad Length (X8) Contact Pad Width (X8) 0.85 0.30 NOM CContact Pad Spacing 2.90 Contact Pad to Contact Pad (X6) G2 0.35 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Contact Pad to Center Pad (X8) G1 0.23 C EV EV ØV SILK SCREEN E Microchip Technology Drawing C04-3021 Rev A 8-Lead Very Thin Plastic Dual Flat, No Lead Package (JMA) - 3x3x0.9 mm Body [VDFN] Micrel Legacy Package DFN33-8LD-PL-1

 2019 Microchip Technology Inc. DS20006084A-page 19 MIC4126/27/28 APPENDIX A: REVISION HISTORY Revision A (06/2019)

  • Converted Micrel document MIC4126/27/28 (M9999-072605) to Microchip data sheet template DS20006084A.
  • Minor grammatical text changes throughout.
  • Updated Packaging Information to MCHP standard versions.

 2019 Microchip Technology Inc. DS20006084A-page 20 MIC4126/27/28 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: a) MIC4126:1.5A-Peak, Dual Inverting, Low-Side MOSFET Driver in Advanced Packaging, Extended Temperature Range, –40°C to +125°C, RoHS Compliant. MIC4126YME 8-Lead ePad SOIC Package 95/Tube MIC4126YME-TR 8-Lead ePad SOIC Package 2500/Reagingel MIC4126YMME 8-Lead ePad MSOP Package 100/Tube MIC4126YMME-TR8-Lead ePad MSOP Package 2500/Reel MIC4126YML-TR 8-Lead VDFN Package 5000/Reel b) MIC4127:1.5A-Peak, Dual Noninverting, Low-Side MOSFET Driver in Advanced Packaging, Extended Temperature Range, –40°C to +125°C, RoHS Compliant. MIC4127YME 8-Lead ePad SOIC Package 95/Tube MIC4127YME-TR 8-Lead ePad SOIC Package 2500/Reagingel MIC4127YMME 8-Lead ePad MSOP Package 100/Tube MIC4127YMME-TR8-Lead ePad MSOP Package 2500/Reel MIC4127YML-TR 8-Lead VDFN Package 5000/Reel c) MIC4128:1.5A-Peak, Inverting and Noninverting, Low-Side MOSFET Driver in Advanced Packaging, Extended Temperature Range, – 40°C to +125°C, RoHS Compliant. MIC4128YME 8-Lead ePad SOIC Package 95/Tube MIC4128YME-TR 8-Lead ePad SOIC Package 2500/Reagingel MIC4128YMME 8-Lead ePad MSOP Package 100/Tube MIC4128YMME-TR 8-Lead ePad MSOP Package 2500/Reel MIC4128YML-TR 8-Lead VDFN Package 5000/Reel Device: Dual 1.5A-Peak Low-Side MOSFET Driver in Advance Packaging Bipolar/CMOS/DMOS Process MIC4126: Dual Inverting MIC4127: Dual Noninverting MIC4128: Inverting and Noninverting Junction Temperature Range: Y = –40°C to +125°C, RoHS Compliant Package: ME = 8-Lead ePad SOIC MME= 8-Lead ePad MSOP ML = 8-Lead VDFN Media Type: <blank>= 95/Tube (ME, ePad SOIC) <blank>= 100/Tube (MME, ePad MSOP) TR = 2,500/Reel (ME & MME, ePad SOIC) TR = 5,000/Reel (ML, VDFN) Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Device X XX -XX Part No. Junction Temp. Range Package Media Type

 2019 Microchip Technology Inc. DS20006084A-page 21 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-4600-2 Note the following details of the code protection feature on Microchip devices:

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  • There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
  • Microchip is willing to work with the customer who is concerned about the integrity of their code.
  • Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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