MIC4102

MIC4102_11 MIC | Alldatasheet

Document overview

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• PDF pages: 17

Technical content

Features

• Drives high- and low-side N-Channel MOSFETs with single input
• Adaptive anti-shoot-through protection
• Low side drive disable pin
• Bootstrap supply voltage to 118V DC
• Supply voltage up to 16V
• TTL input thresholds
• On-chip bootstrap diode
• Fast 30ns propagation times
• Drives 1000pF load with 10ns rise and 6ns fall times
• Low power consumption
• Supply under-voltage protection
• 2.5 Ω pull up , 1.5Ω pull down output resistance
• Space saving SOIC-8L package
• –40 °C to +125°C junction temperature range

Applications

• High voltage buck converters
• Networking / Telecom power supplies
• Automotive power supplies
• Current Fed Push-Pull Topologies
• U ltrasonic drivers
• Avionic power supplies Typical Application 100V Buck Regulator Solution

Micrel, Inc. MIC4102 November 2006 2 M9999-112806

Ordering Information

Input Junction Temp. Range Package MIC4102BM MIC4102YM TTL –40° to +125°C SOIC-8L Pin Configuration 1VDD HB HO HS 8L O VSS LS PWM SOIC-8L (M) Pin Description Pin Number Pin Name Pin Function 1 VDD Positive Supply to lower gate drivers. Decouple this pin to VSS (Pin 7). Bootstrap diode connected to HB (pin 2). 2 HB High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. 3 HO High-Side Output. Connect to gate of High-Side power MOSFET. 4 HS High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 5 PWM Control Input. PWM high signal makes high-side HO output high, and low-side LO output low. PWM low signal makes high-side HO output low, and low-side LO output high. 6 LS Low-Side Disable. When pulled low, this control signal immediately terminates the low-side LO output drive. The low-side LO output drive will remain low until this signal is removed. HS drive is not affected by the LS signal. Here is the logic table: LS PWM LO HO 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 7 VSS Chip negative supply, generally will be grounded. 8 LO Low-Side Output. Connect to gate of Low-Side power MOSFET.

Micrel, Inc. MIC4102 November 2006 3 M9999-112806 Absolute Maximum Ratings(1) Operating Ratings(2) Junction Thermal Resistance Electrical Characteristics(4) VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = 25°C; unless noted. Bold values indicate –40°C< TJ < +125°C. Symbol Parameter Condition Min Typ Max Units Supply Current IDD VDD Quiescent Current PWM = 0V 150 450 600 µA IDDO VDD Operating Current f = 500kHz 3 3.5 4.0 mA IHB Total HB Quiescent Current PWM = 0V 25 150 200 µA IHBO Total HB Operating Current f = 500kHz 1.5 2.5 3 mA IHBS HB to VSS Current, Quiescent VHS = VHB = 110V 0.05 1 30 µA Input Pins (TTL) VIL Low Level Input Voltage Threshold 0.8 1.5 V VIH High Level Input Voltage Threshold 1.5 2.2 V RI Input Pull-down Resistance 100 200 500 kΩ Under Voltage Protection VDDR VDD Rising Threshold 6.5 7.3 8.0 V VDDH VDD Threshold Hysteresis 0.5 V VHBR HB Rising Threshold 6.0 7.0 8.0 V VHBH HB Threshold Hysteresis 0.4 V Boost Strap Diode VDL Low-Current Forward Voltage IVDD-HB = 100µA 0.4 0.55 0.70 V VDH Low-Current Forward Voltage IVDD-HB = 100mA 0.7 0.8 1.0 V RD Dynamic Resistance IVDD-HB = 100mA 1.0 1.5 2.0 Ω

Micrel, Inc. MIC4102 November 2006 4 M9999-112806

Electrical Characteristics

Symbol Parameter Condition Min Typ Max Units LO Gate Driver VOLL Low Level Output Voltage ILO = 160mA 0.18 0.3 0.4 V VOHL High Level Output Voltage ILO = -100mA, VOHL = VDD - VLO 0.25 0.3 0.45 V IOHL Peak Sink Current VLO = 0V 3 A IOLL Peak Source Current VLO = 12V 2 A HO Gate Driver VOLH Low Level Output Voltage IHO = 160mA 0.22 0.3 0.4 V VOHH High Level Output Voltage IHO = -100mA, VOHH = VHB – VHO 0.25 0.3 0.45 V IOHH Peak Sink Current VHO = 0V 3 A IOLH Peak Source Current VHO = 12V 2 A Switching Specifications (Anti-Shoot-Through Circuitry) tLOOFF Delay between PWM going high to LO going low 30 45 60 ns VLOOFF Voltage threshold for LO MOSFET to be considered OFF 1.7 V tHOON Delay between LO OFF to HO going High 30 50 60 ns tHOOFF Delay between PWM going Low to HO going low 45 65 70 ns VSWth Switch Node Voltage Threshold when HO turns off 1 2.5 4 V tLOON Delay between HO MOSFET being considered off to LO turning ON 30 60 70 ns tLSOFF Delay between LS going low and LO turning OFF CL = 1000pF 36 45 70 ns tSWTO Forced LO ON, if VLOTH is not detected 120 250 450 ns Switching Specifications tR Either Output Rise Time (3V to 9V) CL = 1000pF 10 ns tF Either Output Fall Time (3V to 9V) CL = 1000pF 6 ns tR Either Output Rise Time (3V to 9V) CL = 0.1µF 0.33 0.6 0.8 µs tF Either Output Fall Time (3V to 9V) CL = 0.1µF 0.2 0.3 0.4 µs

Micrel, Inc. MIC4102 November 2006 5 M9999-112806 Electrical Characteristics (cont.) Symbol Parameter Condition Min Typ Max Units Switching Specifications (cont.) tPW Minimum Input Pulse Width that changes the output with LS=5V CL=0 Note 6 40 60 ns tPW Minimum Output Pulse Width on HO with min pulse width on PWM with LS=5V CL=0 Note 6 15 ns tPW Minimum Input Pulse Width that changes the output with LS=0V CL=0 Note 6 13 20 ns Minimum Output Pulse Width on HO with min pulse width on PWM with LS=0V CL=0 Note 6 tBS Bootstrap Diode Turn-On or Turn-Off Time 10 ns Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 4. Specification for packaged product only. 5. All voltages relative to pin7, VSS unless otherwise specified. 6. Guaranteed by design. Not production tested.

Micrel, Inc. MIC4102 November 2006 6 M9999-112806 Typical Characteristics

Micrel, Inc. MIC4102 November 2006 7 M9999-112806 Typical Characteristics (cont.)

Micrel, Inc. MIC4102 November 2006 8 M9999-112806 Timing Diagrams tLOOFF 30ns 60ns PWM LS Switch node (HS Pin) LO HO 2 3. VLOOFF <1.7V 7. VSWth <(VDD-2.5V) tHOON 30ns 60ns tHOOFF 45ns 70ns tLOON 30ns 70ns tLSOFF 36ns 70ns Time Point Action 1-2 PWM signal goe s hi gh. This initiate s the LO signal to go low. The delay between PWM high to (VLO –10%) is typically 30ns (tLOOFF) 2-4 LO goes low. When LO reaches 1.7V (VLOOFF) the low side MOSFET is deemed to be off. The high side output HO th en goes hig h. The d elay between 3 and 4 i s typically 30n s (T HOON); this allows for large turn off delay times of MOSFETs. 5-7 PWM g oes l ow; HO goes lo w, typica lly within 45ns, t HOOFF. The switch node (HS pin) is then monitored; when the switch no de i s VDD-2.5V (VSWTH) the h igh side MO SFET is dee med to be off and the LO output goes hig h within typically 30ns (tLOON ). This is controlled by a one shot and remains high until PWM goe s hig h. This i s because it is po ssible to have the SW nod e oscillate, and coul d easily bounce through 10V level. If the L O high tra nsition has n ot happened within 250ns, it is forced to happen, unless the LS input is low. 8-10 If at any tim e after 7 ha s occu rred a nd LS pin goes low, the LO output will turn off within 36ns (VLSOFF). HO will remain off. The LS pi n overrides all shoot through control logic. If LS is low at the start of the next cycle wh en PWM signal goe s high then HO shall switch transitio n 1-4 as normal. I.e. PWM signal equals HO output, LO = 0V.

Figure 1. MIC4102 Functional Block Diagram MIC4102 is shown in Figure 1. voltage for the high-side output. from causing chatter during turn-on. always be a diode drop less than VDD. MOSFETs from a low voltage PWM IC.

1. The lo w-side drive r i s de signed to drive a g round

output ensures a low Rdson from the external MOSFET. Pulling the LS pin low disables the LO pin.

• Internal diode dissipation in the bootstrap circuit
• Internal driver dissipation
• Quiescent current di ssipation u sed t o su pply the internal logic and control functions. Bootstrap Circuit Power Dissipation Power dissi pation of the internal bootstra p diode primarily comes from the average charging current of the CB capacitor times the forward voltage drop of the diode. Secondary source s of di ode po wer di ssipation a re t he reverse leakage current and reverse recovery effects of the diode. The average current drawn by repeated charging of the high-side MOSFET is calculated by: frequency switching drive gate Vat ChargeGateTotalQ:where HBgate S SgateAVEF f fQI The avera ge powe r dissi pated by the forwa rd voltage drop of the diode equals: drop voltage forward DiodeV:where F ×= FAVEFfwd VIPdiode The value of V F should b e take n at t he pe ak current through th e diode, however, this cur rent is difficul t to calculate because of differ ences in source impedances. The peak current can either be measured or the value of VF at the average current can be used and will yiel d a good approximation of diode power dissipation. The reverse lea kage cur rent of th e i nternal bo otstrap diode is typically 11uA at a reverse voltage of 100V and 125C. Power dissip ation due to re verse le akage is typically much less than 1mW and can be ignored. Reverse recovery time is the time required for the injected min ority car riers to be swept away f rom the depletion reg ion duri ng turn- off of the diode. Powe r dissipation due to reverse recovery can be calculated by computing th e ave rage r everse current due to reverse recovery charge times th e r everse vo ltage a cross the diode. Th e avera ge reverse current and power dissipation due to reverse recovery can be estimated by: TimeRecovery Reverset CurrentRecovery Reverse PeakI:where rr RRM ×××= REVAVERRRR SrrRRMAVERR VIPdiode ftII The total diode power dissipation is: RRfwdtotal PdiodePdiodePdiode += An optional external bo otstrap diode may be used instead of th e inter nal di ode (Figure 5). An exte rnal diode may b e useful if hi gh gate cha rge MOSFETs are being drive n and the p ower di ssipation of th e int ernal diode is contributing to excessive die temperatures. The voltage drop of the external diode must be less than the internal di ode for this o ption to wor k. The rev erse voltage across the diode w ill be equal to the input voltage minus the Vdd supply voltage. A 100V S chottky diode will work for most 72V input tel ecom applications. The above e quations can be used to cal culate power dissipation in the external d iode, however, if the external diode has significant reverse leakage current, the power dissipated in that diode du e to rever se leakage can be calculated as: supply power the offrequency switching fs /t CycleDuty D VoltageReverse Diode V T and Vatflow current ReverseI:where )1( ON REV JREVR −××= S REVRREV f DVIPdiode The o n-time is the ti me the hi gh-side switch is conducting. In most po wer supply topologies, the dio de is reverse biased during the switching cycle off-time. CB Vin external diode HS HB HO Vdd LO Level shift PWM Vss Q FF Q

Figure 5. Optional Bootstrap Diode and gate to drain capacitance of the external MOSFET.

voltage ringing generate conducted and radiated EMI. variations in the MOSFET and MOSFET driver. external damping resistor is used. Figure 8. Gate Drive Circuit with Parasitics the same time a nd to minimize shoot-through cu rrent. monitoring circuit and is not recommended.

Micrel, Inc. MIC4102 November 2006 14 M9999-112806 the voltage on the switchi ng node (HS pin) must h ave dropped to 2.5V below the Vdd voltage. Monitori ng the switch voltage instead of t he HO pin v oltage eliminates timing variati ons a nd excessive delay s due to the high side MOSFE T turn-off. The LO driver turns on aft er a short delay (TLOON). O nce the LO driver is turn on, it is latched o n until the P WM signal goes hi gh. This prevents any ringing or oscillations on the switch node or HS pi n fro m turning off th e LO d river. If the P WM pin goes low and the voltage on the HS pi n does not cross the VSWth threshold, the LO pin will be forced high after a short delay (TSWTO), insuring proper operation. Fast propa gation delay between the input and o utput drive wavefo rm is de sirable. It im proves overcurrent protection by decreasing the response time between the control signal and the MOSFET gate drive. Mini mizing propagation delay also minimizes pha se shift errors in power supplies with wide bandwidth control loops. Care must be taken to insure the input signal pulse width is greater than the minimu m specified pulse width. An input signal t hat is le ss th an the minim um p ulse width may result in no output pu lse or a n output pulse wh ose width is significantly less than the input. The maximu m duty cycle (ratio of high side on -time to switching period) is determined by the time requi red for the CB capacitor to charge during the off-time. Adequate time must be allowed for the CB capacitor to charge up before the high-side driver is turned back on. The a nti-shoot-through ci rcuit in the M IC4102 p revents the driver fro m turning bot h MOSFETs on at the sa me time, howeve r, other facto rs outside of the anti-sh oot- through circuit’s control can cause shoot-through. Some of these are ringi ng o n the gate drive n ode an d capacitive coupling of the switching node voltage on the gate of the low-side MOSFET. Decoupling and Bootstrap Capacitor Selection Decoupling capacitors are required for both the low side (Vdd) and high side (HB) supply pins. These capacitors supply the cha rge n ecessary to dri ve the exte rnal MOSFETs a s well a s minimize the v oltage rip ple on these pins. The capa citor from HB to HS serves double duty by providing decoupling for the high-side circuitry as well as providing current to the high-side circuit while the high-side external MOSFET is on. C eramic cap acitors are recommended because of their low impedan ce and small si ze. Z5U type cer amic capacitor diele ctrics are not recomm ended due to the la rge chan ge in capacitance over temperature and voltage. A minimum value of 0.1uf is req uired for each of the capa citors, regardless o f the MOSFETs bein g driven. Large r MOSFETs m ay require la rger cap acitance value s for proper op eration. Th e vo ltage rating of the capa citors depends on the supply v oltage, am bient tempe rature and the voltage derating used fo r reliability. 25V rated X5R o r X7 R ce ramic cap acitors are recommended for most ap plications. The minimum capacitance value should be i ncreased if lo w voltag e capacitors a re use since even g ood quality diele ctric capacitors, su ch as X5R, will lose 40% to 70% of their capacitance val ue at the rated voltage. Placement of the de coupling capacitors is critical. T he bypass capacitor for Vd d should be pl aced as close as possible b etween the Vd d an d V ss pi ns. The byp ass capacitor (CB) for th e HB supply pin m ust be located as close a s po ssible b etween the HB an d HS pin s. The etch conne ctions mu st be short, wide and direct. The use of a ground pla ne to minim ize conn ection impedance is re commended. Refe r to the sectio n on layout and component placement for more information. The voltage on the bootstrap capacitor drops each time it delivers ch arge to turn on the MOSF ET. The voltage drop de pends o n the g ate cha rge required by the MOSFET. Most MOSF ET spe cifications specify gate charge vs. Vgs voltage. Based on this information and a recommended ∆VHB of less tha n 0.1 V, the mini mum value of bootstrap capacitance is calculated as: pin HB the at drop Voltage ∆ VatChargeGateTotalQ:where HB HBgate HB gate B V Q C The d ecoupling capacitor for the Vd d input may be calculated in with the same form ula, however, the two capacitors are usually equal in value. Grounding, Component Placement and Circuit Layout Nanosecond switching speeds and ampere p eak currents in and a round the MIC41 02 drive r re quire proper placement an d tra ce routing of all compo nents. Improper pl acement m ay cau se degraded n oise immunity, false swit ching, excessive ri nging or circuit latch-up. Figure 9 shows the critical current paths when the driver outputs go high and tu rn on the extern al MOSFETs. It also shown the need for a low impedance ground plane. Charge n eeded to turn-o n the MOSFET gates co mes from the decoupling capacitors CVDD and CB. Current in the lo w-side gate driver flows from CVDD through the internal d river, into the MOSFET g ate and out the Source. The return conn ection back t o the de coupling capacitor is made throug h the gro und plane. Any inductance o r re sistance in the g round return path causes a vo ltage spi ke or rin ging to appea r on the source of the MOSFET. This voltage works against the gate voltage and can eith er sl ow down or tu rn off the MOSFET during the period where it should be turned on.

Micrel, Inc. MIC4102 November 2006 17 M9999-112806

Package Information

8-Pin SOIC (M) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical impla into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. can nt © 2006 Micrel, Incorporated.