MIC3002GML

Micrel Semiconductor

FOM Management IC with Internal Calibr ation

Manufacturer: Micrel Semiconductor

Document: 65 Pages / 1Mb

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MIC3002 MICREL | Alldatasheet

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PDF pages: 65

Technical content

Datasheet sections

Features

Extensive temperature range
Alarms and Warnings interrupt and TXFAULT masks
Capability to support up to four chips on the serial interface
LUT to compensate for chip-FOM case temperature difference
APC or constant-current laser bias
Turbo mode for APC loop start-up and shorter laser turn on time
Supports multiple laser types and bias circuit topologies
Integrated digital temperature sensor
Temperature compensation of modulation, bias, and fault levels via NVRAM look-up tables
NVRAM to support GBIC/SFP serial ID function
User writable EEPROM scratchpad
Diagnostic monitoring interface per SFF-8472 – Monitors and reports critical parameters: temperature, bias current, TX and RX optical power, and supply voltage – S/W control and monitoring of TXFAULT, RXLOS, RATESELECT, and TXDISABLE – Internal or external calibration – EEPOT for adjusting RX power measurement
Power-on hour meter
Interrupt capability
Extensive test and calibration features
2-wire SMBus-compatible serial interface
SFP/SFP+ MSA and SFF-8472 compliant
3.0V to 3.6V power supply range
5V-tolerant I/O
Available in (4mm x 4mm) 24-pin MLF ® package

Applications

SFP/SFP+ optical transceivers
SONET/SDH transceivers and transponders
Fibre Channel transceivers
10Gbps transceivers
Free space optical communications
Proprietary optical links

Micrel, Inc. MIC3002 July 2007 2 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690

Ordering Information

Part Number Package Type Junction Temp. Range Package Marking Lead Finish MIC3002BML 24-pin MLF ® –45°C to +105°C 3002 Sn-Pb MIC3002BMLTR(1) 24-pin MLF ® –45°C to +105°C 3002 Sn-Pb MIC3002GML 24-pin MLF ® –45°C to +105°C 3002 with Pb-Free bar-line indicator Pb-Free NiPdAu MIC3002GMLTR(1) 24-pin MLF ® –45°C to +105°C 3002 with Pb-Free bar-line indicator Pb-Free NiPdAu 1. Note: 2. Tape and Reel.

Micrel, Inc. MIC3002 July 2007 4 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690

Micrel, Inc. MIC3002 July 2007 7 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Pin Configuration 24-Pin MLF® (MLF-24) Pin Description Pin Number Pin Name Pin Function 1 FB Analog Input. Feedback voltage for the APC loop op-amp. Polarity and scale are programmable via the APC configuration bits. Connect to VBIAS if APC is not used. 2 VMPD Analog Input. Multiplexed A/D converter input for monitoring transmitted optical power via a monitor photodiode. In most applications, VMPD will be connected directly to FB. The input range is 0 - VREF or 0 - VREF/4 depending on the setting of the APC configuration bits 3 GNDA Ground return for analog functions. 4 VDDA Power supply input for analog functions. 5 VILD– Analog Input. Reference terminal for the multiplexed pseudo-differential A/D converter inputs for monitoring laser bias current via a sense resistor (VILD+ is the sensing input). Tie to VDD or GND to reference the voltage sensed on VILD+ to VDD or GND, respectively. Limited common-mode voltage range, see “Applications Information” section for more details. 6 VILD+ Analog Input. Multiplexed A/D input for monitoring laser bias current via a sense resistor (signal input); accommodates inputs referenced to VDD or GND (see pin 5 description). Limited common- mode voltage range, see “Applications Information” section for more details. 7 SHDN/TXFIN Digital output/Input; programmable polarity. When used as shutdown output (SHDN), OEMCFG3-2 set to 0, SHDN is asserted at the detection of a fault condition if OEMCFG4-7 is set to 0. If the latter bit is set to 1, a fault condition will not assert SHDN. When programmed as TXFIN, it is an input for external fault signals to be ORed with the internal fault sources to drive TXFAULT. 8 VRX Analog Input. Multiplexed A/D converter input for monitoring received optical power. The input range is 0 to VREF. A 5-bit programmable EEPOT on this pin provides for coarse calibration and ranging of the RX power measurement. 9 XPN Analog Input/Output. Optional connection to an external PN junction for sensing temperature at a remote location. The Zone bit in OEMCFG1 determines whether temperature is measured using the on-chip sensor or the remote PN junction. 10 TXFAULT Digital Output; Open-Drain, programmable polarity. If OEMCFG5-4 is set to 0, a high level indicates a hardware fault impeding transmitter operation. The state of this pin is always reflected in the TXFLT bit.

Micrel, Inc. MIC3002 July 2007 8 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Pin Description Pin Number Pin Name Pin Function 11 TXDISABLE Digital Input; Active High. The transmitter is disabled when this line is high or the STXDIS bit is set. The state of this input is always reflected in the TXDIS bit. 12 DATA Digital I/O; Open-drain. Bi-directional serial data input/output. 13 CLK Digital Input; Serial clock input. 14 VIN/INT If bit 4 (IE) in USRCTL register is set to 0 (default), this pin is configured as analog input. If IE bit is set to 1, this pin is configured as open-drain output. Analog Input: Multiplexed A/D input for monitoring supply voltage. 0V to 5.5V input range. Open-drain output: outputs the internally generated interrupt signal /INT. 15 RSIN Digital Input; Rate Select Input; ORed with rate select bit to determine the state of the RSOUT pin. The state of this pin is always reflected in the RSEL bit. 16 GNDD Ground return for digital functions. 17 NC No connection. This pin is used for test purposes and must be left unconnected. 18 VDDD Power supply input for digital functions. 19 RXLOS Digital Output; programmable polarity Open-Drain. Indicates the loss of the received signal as indicated by a level of received optical power below the programmed RXLOS comparator threshold; may be wire-ORed with external signals. Normal operation is indicated by a Low level when OEMCFG6-3 is set to 0 and a high level when OEMCFG6-3 is set to 1. RXLOS is de- asserted when VRX > LOSFLTn. The LOS bit reflects the state of RXLOS whether driven by the MIC3002 or an external circuit. 20 RS0/GPO Digital Output. Open-Drain or push-pull. When used as rate select output, it represents the receiver rate select as per SFF. This output is controlled by the SRSEL bit ORed with RSIN input and is open drain only. When used as a general-purpose, non-volatile output, it is controlled by the GPO configuration bits in OEMCFG3. 21 COMP Analog Output, compensation terminal. Connect a capacitor between this pin and GNDA or VDDA with appropriate value to tune the APC loop time constant to a desirable value. 22 VBIAS Analog Output. Buffered DAC output capable of sourcing or sinking up to 10mA under control of the APC function to drive an external transistor for laser diode D.C. bias. The output and feedback polarity are programmable to accommodate either a NPN or a PNP transistor to drive a common-anode or common-cathode laser diode. 23 VMOD– Analog Input. Inverting terminal of VMOD buffer op-amp. Connect to VMOD+ (gain = 1) or feedback resistors network to set a different gain 24 VMOD+ Analog Output. Buffered DAC output to set the modulation current on the laser driver IC. Operates with either a 0– VREF or a (VDD–VREF) – VDD output swing so as to generate either a ground- referenced or a VDD referenced programmed voltage. A simple external circuit can be used to generate a programmable current for those drivers that require a current rather than a voltage input. See “Applications Information” section for more details.

Micrel, Inc. MIC3002 July 2007 9 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Absolute Maximum Ratings(1) Voltage on CLK, DATA, TXFAULT, VIN, RXLOS, ESD Ratings(3) Operating Ratings(2) Ambient Temperature Range (TA) ... –40°C to +105°C Package Thermal Resistance

Electrical Characteristics

For typical values, TA = 25°C, VDDA = VDDD = +3.3V, unless otherwise noted. Bold values are guaranteed for +3.0V ≤ (VDDA = VDDD) ≤ 3.6V, T(min) ≤ TA ≤ T(max)(8) Symbol Parameter Condition Min Typ Max Units Power Supply CLK = DATA = VDDD = VDDA; TXDISABLE low; all DACs at full- scale; all A/D inputs at full-scale; all other pins open. 2.3 3.5 mA IDD Supply Current CLK = DATA = VDDD = VDDA; TXDISABLE high; FLTDAC at full- scale; all A/D inputs at full-scale; all other pins open. 2.3 3.5 mA VPOR Power-on Reset Voltage All registers reset to default values; A/D conversions initiated. 2.9 2.98 V VUVLO Under-Voltage Lockout Threshold Note 5 2.5 2.73 V VHYST Power-on Reset Hysteresis Voltage 170 mV tPOR Power-on Reset Time VDD > VPOR(4) 50 µs VREF Reference Voltage 1.210 1.225 1.240 V ∆VREF/∆VDDA Voltage Reference Line Regulation 1.7 mV/V Temperature-to-Digital Converter Characteristics Local Temperature Measurement Error Remote Temperature Measurement Error tCONV Conversion Time Note 4 60 ms tSAMPLE Sample Period 100 ms Remote Temperature Input, XPN XPN at high level, clamped to 0.6V. 192 400 µA IF Current to External Diode(4) XPN at low level, clamped to 0.6V. 7 12 µA

Micrel, Inc. MIC3002 July 2007 10 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Voltage-to-Digital Converter Characteristics (VRX, VAUX, VBIAS, VMPD, VILD±) Symbol Parameter Condition Min Typ Max Units Voltage Measurement Error –40°C ≤ TA ≤ +105°C(6) ±1 ±2.0 %fs tCONV Conversion Time Note 4 10 ms tSAMPLE Sample Period Note 4 100 ms Voltage Input, VIN (Pin 14 used as an ADC Input) VIN Input Voltage Range –0.3 ≤ VDD ≤ 3.6V GNDA 5.5 V ILEAK Input Current V IN = VDD or GND; VAUX = VIN 55 µA CIN nput Capacitance 10 pF Digital-to-Voltage Converter Characteristics (VMOD, VBIAS) Accuracy –40°C ≤ TA ≤ +105°C(6) ±1 2.0 %fs tCONV Conversion Time Note 4 20 ms DNL Differential Non-linearity Error Note 4 ±0.5 ±1 LSB Bias Current Sense Inputs, VILD+, VILD– VILD Differential Input Signal Range, | VILD+ – VILD– |

0 V REF/4 mV

IIN+ VILD+ input current ±1 µA VILD– referred to VDDA +150 µA IIN– VILD– input current | VILD+ – VILD– | = 0.3V VILD– referred to GND -150 µA CIN Input Capacitance 10 pF APC Op Amp, FB, VBIAS, COMP GBW Gain Bandwidth Product C COMP = 20pF; Gain = 1 1 MHz TCVOS Input Offset Voltage Temperature Coefficient(4) 1 µV/°C IOUT = 10mA, SRCE bit = 1 GNDA 1.25 V VOUT Output Voltage Swing IOUT = -10mA, SRCE bit = 0 V DDA -1.25 V DDA V ISC Output Short-Circuit Current 55 mA tSC Short Circuit Withstand Time TJ ≤ 150°C(4) sec CCOMP = 20pF; Gain = 1, to GND 55 dB PSRR Power Supply Rejection Ratio CCOMP = 20pF; Gain = 1, to VDD 40 AMIN Minimum Stable Gain C COMP = 20pF, Note 4 1 V/V ∆V/∆t Slew Rate C COMP = 20pF; Gain = 1 3 V/µs ∆RFB Internal Feedback Resistor Tolerance ±20 % ∆RFB/∆t Internal Feedback Resistor Temperature Coefficient 25 ppm/C START = 01h 0.375 mA START = 02h 0.750 mA START = 04h 1.500 mA ISTART Laser Start-up Current Magnitude START = 08h 3.000 mA CIN Pin Capacitance 10 pF

Micrel, Inc. MIC3002 July 2007 11 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Symbol Parameter Condition Min Typ Max Units VMOD Buffer Op-Amp, VMOD+, VMOD– GBW Gain Bandwidth C COMP = 20pF; Gain = 1 1 MHz TCVOS Input Offset Voltage Temperature Coefficient 1 µV/°C IBIAS V MOD– Input Current ±0.1 ±1 µA VOUT Output Voltage Swing I OUT = ±1mA GNDA+75 V DDA-75 mV ISC Output Short-Circuit Current 35 mA tSC Short Circuit Withstand Time TJ ≤ 150°C(4) sec PSRR Power Supply Rejection Ratio C COMP = 20pF; Gain = 1, to GND 65 dB C COMP = 20pF; Gain = 1, to VDD 44 dB AMIN Minimum Stable Gain C COMP = 20pF 1 V/V ∆V/∆T Slew Rate C COMP = 20pF; Gain = 1 1 V/µs CIN Pin Capacitance 10 pF Control and Status I/O, TXDISABLE, TXFAULT, RSIN, RSOUT(GPO), SHDN(TXFIN), RXLOS, /INT VIL Low Input Voltage 0.8 V VIH High Input Voltage 2.0 V VOL Low Output Voltage I OL ≤ 3mA 0.3 V VOH High Output Voltage (applies to SHDN only) IOH ≤ 3mA V DDD–0.3 V ILEAK Input Current ±1 µA CIN Input Capacitance 10 pF Transmit Optical Power Input, VMPD VIN Input Voltage Range Note 4 GNDA V DDA V VRX Input Signal Range BIASREF=0 V REF V BIASREF=1 V DDA–VREF V DDA V CIN Input Capacitance Note 4 10 pF ILEAK Input Current ±1 µA Received Optical Power Input, VRX, RXPOT Input Voltage Range Note 4 GNDA V DDA V VRX Valid Input Signal Range (ADC Input Range)

0 V REF V

RRXPOT(32) End-to-End Resistance RXPOT = 1F h 32 K Ω ∆RXPOT Resistor Tolerance ±20 % ∆RXPOT/∆T Resistor Temperature Coefficient 25 ppm/C ∆VRX/VRXPOT Divider Ratio Accuracy 00 ≤ RXPOT ≤ 1Fh -5 +5 % ILEAK Input Current RXPOT = 0 (disconnected) ±1 µA CIN Input Capacitance Note 4 10 pF ILEAK Input Current ±1 µA

Micrel, Inc. MIC3002 July 2007 12 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Symbol Parameter Condition Min Typ Max Units Control and Status I/O Timing, TXFAULT, TXDISABLE, RSIN, RSOUT, and RXLOS tOFF TXDISABLE Assert Time From input asserted to optical output at 10% of nominal, CCOMP = 10nF. 10 µs tON TXDISABLE De-assert Time From input de-asserted to optical output at 90% of nominal, CCOMP = 10nF. 1 ms tINIT Initialization Time From power on or transmitter enabled to optical output at 90% of nominal and TX_FAULT de-asserted.(4) 300 ms tINIT2 Power-on Initialization Time From power on to APC loop-enabled. 200 ms tFAULT TXFAULT Assert Time From fault condition to TXFAULT assertion.(4) 95 µs tRESET Fault Reset Time Length of time TXDISABLE must be asserted to reset fault condition. 10 µs tLOSS_ON RXLOS Assert Time From loss of signal to RXLOS asserted. 95 µs tLOSS_OFF RXLOS De-assert Time From signal acquisition to LOS de- asserted. 100 µs tDATA Analog Parameter Data Ready From power on to valid analog parameter data available.(4) 400 ms tPROP_IN TXFAULT, TXDISABLE, RXLOS, RSIN Input Propagation Time Time from input change to corresponding internal register bit set or cleared.(4) 1 µs tPROP_OUT TXFAULT, RSOUT, /INT Output Propagation Time From an internal register bit set or cleared to corresponding output change.(4) 1 µs Fault Comparators φFLTTMR Fault Suppression Timer Clock Period Note 4 0.475 0.5 0.525 ms Accuracy -3 +3 %/F.S. tREJECT Glitch Rejection Maximum length pulse that will not cause output to change state.(4) 4.5 µs High level 95 %VDDA VSAT Saturation Detection Threshold Low level 5 %VDDA Power-On Hour Meter Timebase Accuracy 0°C ≤ TA ≤ +70°C(4) +5 -5 % Resolution Note 4 10 hours Non-Volatile (FLASH) Memory tWR Write Cycle Time(7) From STOP of a one to four-byte write transaction.(4) 13 ms Data Retention 100 years Endurance Minimum Permitted Number Write Cycles 10,000 cycles

Micrel, Inc. MIC3002 July 2007 13 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Serial Data I/O Pin, Data Symbol Parameter Condition Min Typ Max Units IOL = 3mA 0.4 V VOL Low Output Voltage IOL = 6mA 0.6 V VIL Low Input Voltage 0.8 V VIH High Input Voltage 2.1 V ILEAK Input Current ±1 µA CIN Input Capacitance Note 4 10 pF Serial Clock Input, CLK VIL Low Input Voltage 2.7V ≤ VDD ≤ 3.6V 0.8 V VIH High Input Voltage 2.7V ≤ VDD ≤ 3.6V 2.1 V ILEAK Input Current ±1 µA CIN Input Capacitance Note 4 10 pF Serial Interface Timing(4) t1 CLK (clock) Period 2.5 µs t2 Data In Setup Time to CLK High 100 ns t3 Data Out Stable After CLK Low 300 ns t4 Data Low Setup Time to CLK Low Start Condition 100 ns t5 Data High Hold Time After CLK High Stop Condition 100 ns tDATA Data Ready Time From power on to completion of one set of ADC conversions; analog data available via serial interface. 400 ms Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. 4. Guaranteed by designing and/or testing of related parameters. Not 100% tested in production. 5. The MIC3000 will attempt to enter its shutdown state when V DD falls below VUVLO. This operation requires time to complete. If the supply voltage falls too rapidly, the operation may not be completed. 6. Does not include quantization error. 7. The MIC3002 will not respond to serial bus transactions during an EEPROM write-cycle. The host will receive a NACK during tWR. 8. Final test on outgoing product is performed at T A = +25°C.

Micrel, Inc. MIC3002 July 2007 14 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Timing Diagram Serial Interface Timing

0 –95 96 Serial ID defined by SEP MSA G-P NVRAM; R/W under valid OEM password. Table 1. MIC3002 Address Map, Serial Address = A0h 28-37 40-55 16 Reserved Reserved – do not write; reads undefined. 5C-5E 92-94 3 Reserved Reserved – do not write; reads undefined. 5F 95 1 Checksum G-P NVRAM; writeable using OEM p/w; ready only otherwise. 60-69 96-105 10 Analog Data Real time analog parameter data. 6A-6D 106-109 4 Reserved Reserved – do not write; reads undefined. 6E 110 1 Control/Status Bits Control and status bits. 6F 111 1 Reserved Reserved – do not write; reads undefined. 70-71 112-113 2 Alarm Flags Alarm status bits; read only. 72-73 114-115 2 Reserved Reserved – do not write; reads undefined. 74-75 116-117 2 Warning Flags Warning status bits; read only. 76-77 118-119 2 Reserved Reserved – do not write; reads undefined. 7F 127 1 Vendor Specific Vendor specific . Reserved – do not write; reads undefined. 80-DD 128-221 94 User Scratchpad User writeable EEPROM . G-P NVRAM; R/W using any valid password. select this location. Can be used as a scratch pad if not selected. DF-F5 223-245 23 User Scratchpad Us er writeable EEPROM. G-P NVRAM; R/W using any valid password. F6 246 1 USRPWSET User password setting; read/wr ite using any p/w; returns zero otherwise. FC-FE 252-254 3 Reserved Reserved – do not write; reads undefined. used as a scratch pad if not selected. Table 2. MIC3002 Address Map, Serial Address = A2h

entries are located in A6: 90-9B. 12 entries are located in A6: A0-AB. entries. Additional 12 entries are located in A6: B0-BB. 64 entries. Additional 12 entries are located in A6: C0-CB. Table 3. Temperature Compensation Tables, Serial Address = A4h 1C-1D 28-29 2 SCRATCH Reserved – do not write; reads undefined.

temperature to be used by parameters compensation LUT. 87-8F 135-143 9 SCRATCH OEM scratchpad area. 90-9B 144-155 12 BIASLUT2 Bias temperature compensation L.U.T. additional 12 entries. A0-AB 160-171 12 MODLUT2 Modulation temperatur e compensation L.U.T. additional 12 entries. AC-AF 172-175 14 SCRATCH OEM scratchpad area. C0-CB 192-203 12 HATLUT2 Bias current high alarm threshold temperature compensation L.U.T. have its own slope and offset. Table 4. OEM Configuration Registers, Serial Address = A6h

Table 5. A/D Input Signal Ranges and Resolutions

Assumes typical VREF value of 1.22V.

Table 6. VAUX Input Signal Ranges and Resolutions

Assumes typical VREF value of 1.22V.

case temperature over the operating temperature range. the value to be entered should be 2x5=10.

0 A6: 96 (60h) t ≤ -45 ºC

1 A6: 97 (61h) -44 ºC ≤ t ≤ -41 ºC

2 A6: 98 (62h) -40 ºC ≤ t ≤ -37 ºC

36 A6: 97 (61h) 96 ºC ≤ t ≤ 99 ºC

37 A6: 97 (61h) 100 ≤ t ≤ 103 ºC

38 A6: 134 (86h) t ≥ 104 ºC

Table 7. L.U.T. for Temperature Reading Compensation alarm or warning is masked, it will not set the Interrupt.

5 Reserved

4 Reserved

3 Reserved

2 Reserved

1 Reserved

0 Reserved

Table 8. Alarms Interrupt Sources Masking Bits

Table 9. Warnings Interrupt Sources Masking Bits individually in the same way shown in Tables 7 and 8. or toggling TXDISABLE will clear the flag. parts have new different address.

Micrel, Inc. MIC3002 July 2007 22 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Calibration Modes The default mode of calibration in the MIC3002 is external calibration, for which INTCAL bit (bit 0 in OEMCF3 register) is set to 0. The internal calibration mode is selected by setting INTCAL bit to 1. A/ External Calibration The voltage and temperature values returned by the MIC3002’s A/D converter are internally calibrated. The binary values of TEMPh:TEMPl and VOLTh:VOLTl are in the format called for by SFF-8472 under Internal Calibration. SFF-8472 calls for a set of calibration constants to be stored by the transceiver OEM at specific non-volatile memory locations; refer to SFF-8472 specifications for memory map of calibration coefficient. The MIC3002 provides the non-volatile memory required for the storage of these constants. The Digital Diagnostic Monitoring Interface specification should be consulted for full details. Slopes and offsets are stored for use with voltage, temperature, bias current, and transmitted power measurements. Coeffi cients for a fourth-order polynomial are provided for use with received power measurements. The host sy stem can retrieve these constants and use them to process the measured data. Voltage The voltage values returned by the MIC3002’s A/D converter are internally calibrated. The binary values of VOLTh:VOLTl are in the format called for by SFF-8472 under Internal Calibration. Since VINh:VINl requires no processing, the corresponding slope should be set to one and the offset to zero. Temperature The temperature values returned by the MIC3002’s A/D converter are internally calibrated. The binary values of TEMPh:TEMPl are in the format called for by SFF-8472 under Internal Calibration. Bias Current Bias current is sensed via an external sense resistor as a voltage appearing between VILD+ and VILD-. The value returned by the A/D is therefore a voltage analogous to bias current. Bias current, IBIAS, is simply V VILD/RSENSE. The binary value in IBIASh (IBIASl is always zero) is related to bias current by: (1) The value of the least significant bit (LSB) of IBIASh is given by: (2) Per SFF-8472, the value of the bias current LSB is 2µA. The conversion factor, “slope”, needed is therefore: The tolerance of the sense re sistor directly impacts the accuracy of the bias current measurement. It is recommended that the sense resistor chosen be 1% accurate or better. The offset correction, if needed, can be determined by shutting down the laser, i.e., asserting TXDISABLE, and measuring the bias current. Any non- zero result gives the offset required. The offset will be equal and opposite to the result of the “zero current” measurement. TX Power Transmit power is sensed via a resistor carrying the monitor photodiode current. In most applications, the signal at VMPD will be feedback voltage on FB. The VMPD voltage may be measured relative to GND or V DDA depending on the setting of the BIASREF bit in OEMCFG1. The value returned by the A/D is therefore a voltage analogous to transmit power. The binary value in TXOPh (TXOPl is always zero) is related to transmit power by: (3) For a given implementation, the value of R SENSE is known. It is either the value of the external resistor or the chosen value of RFB used in the application. The constant, K, will likely have to be determined through experimentation or closed-loop calibration, as it depends on the monitoring photodiode responsivity and coupling efficiency. It should be noted that the APC circuit acts to hold the transmitted power constant. The value of transmit power reported by the circuit s hould only vary by a small amount as long as APC is functioning correctly.

memory at the lower numerical address. voltage, bias current, transmit power, and receive power. the lower numerical address. intervals corresponding to the RX power level. Table 10. LSB Values of Offset Coefficients

48-49 72-73 2 RESERVED Reserved. (There is no slope for temperature.) Do not write; reads undefined. 4A-4B 74-75 2 RESERVED Reserved. (There is no offset for temperature.) Do not write; reads undefined. 4C-4D 76-77 2 VSLPh:VSLPl Voltage slope; unsigned fixed-point; MSB is at lower physical address. 4E-4F 78-79 2 VOFFh:VOFFl Voltage offset; signed fixed point; MSB is at lower physical address. 50-51 80-81 2 ISLPh:ISLPl Bias current slope; unsign ed fixed-point; MSB is at lower physical address. 52-53 82-83 2 IOFFh:IOFFl Bias cu rrent offset; signed fixed point; MSB is at lower physical address. TX power slope; unsigned fixed-point; MSB is at lower physical address. TX power offset; signed fixed point; MSB is at lower physical address. Table 11. Internal Calibration Coefficient Memory Map – Part I RX power slope 0; unsigned fixed-point; MSB is at lower physical address. RX power offset 0; signed twos-complement; MSB is at lower physical address. RX power slope 1; unsigned fixed-point; MSB is at lower physical address. RX power offset 1; signed twos-complement; MSB is at lower physical address. RX power slope 2; unsigned fixed-point; MSB is at lower physical address. RX power offset 2; signed twos-complement; MSB is at lower physical address. RX power slope 3; unsigned fixed-point; MSB is at lower physical address. RX power offset 3; signed twos-complement; MSB is at lower physical address. RX power slope 4; unsigned fixed-point; MSB is at lower physical address. RX power offset 4; signed twos-complement; MSB is at lower physical address. RX power slope 5; unsigned fixed-point; MSB is at lower physical address. RX power offset 5; signed twos-complement; MSB is at lower physical address. RX power slope 6; unsigned fixed-point; MSB is at lower physical address. RX power offset 6; signed twos-complement; MSB is at lower physical address. RX power slope 7; signed twos-complement; MSB is at lower physical address. RX power offset 7; signed fixed-point; MSB is at lower physical address. Table 12. Internal Calibration Coefficient Memory Map – Part II

Figure 8. VMOD Configured as Voltage Output set of analog data will be available t CONV after t POR.

0 Don’t Care Hi-Z

Table 13. Shutdown State of SHDN vs.

0 Don’t Care Don’t Care Hi-Z

1 Don’t Care 0 ≈GND

1 Don’t Care 1 ≈VDD

Table 14. Shutdown State of VBIAS vs. Table 15. Shutdown State of VMOD vs. conversions will begin, but the laser will remain off.

the hysteresis is much larger than ±1⁄2 LSB. Table 16. Temperature Compensation Look-up Tables

Table 17. APC Temperature Compensation

82 A0 64

102 AA 74

Table 18. VMOD Temperature Compensation

82 B0 64

102 BA 74

Table 19. IBIAS Comparator Temperature Compensation

82 C0 64

Table 20. BIAS Current High Alarm Temperature

Micrel, Inc. MIC3002 July 2007 32 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 The internal state machine calculates a new table index each time a new average temperature value becomes available. This table index is derived from the average temperature value. The table index is then converted into a table address for each of the four look-up tables. These operations can be expressed as: (12) where TAVG(n) is the current average temperature; and TABLE_ADDRESS=INDEX+BASE_ADDRES where BASE_ADDRESS is the phy sical base address of each table, i.e., 00h, 40h, 80h, or C0h (tables reside in the I2CADR+4h and I2CADR+6h pages of memory). At any given time, the current table index can be read in the LUTINDX register. Alarms and Warning Flags There are 20 different conditions that will cause the MIC3002 to set one of the bits in the WARNx or ALARMx registers. These conditions are listed in Table 22. The less critical of these even ts generate warning flags by setting a bit in WARN0 or WARN1. The more critical events cause bits to be set in ALARM0 or ALARM1. An event occurs when any alarm or warning condition becomes true. Each event causes its corresponding status bit in ALARM0, ALAR M1, WARN0, or WARN1 to be set. This action cannot be masked by the host. The status bit will remain se t until the host reads that particular status register, a power on-off cycle occurs, or the host toggles TXDISABLE. If TXDISABLE is asserted at any time during normal operation, A/D conver sions continue. The A/D results for all parameters will continue to be reported. All events will be reported in the normal wa y. If they have not already been individually cleared by read operations, when TXDISABLE is de-asserted, a ll status registers will be cleared. Control and Status I/O The logic for the transceiver control and status I/O is shown schematically in Figure 13. Note that the internal drivers on RXLOS, RATE_SELECT, and TXFAULT are all open-drain. These signals may be driven either by the internal logic or external drivers connected to the corresponding MIC3002 pins. In any case, the signal level appearing at the pins of the MIC3002 will be re ported in the contro l register status bits. Note that the control bits for TX_DISABLE and RATE_SELECT and the status bits for TXFAULT and RXLOS do not meet the timing requirements as specified in the SFP MSA or the GBIC Spec ification, revision 5.5 (SFF- 8053) for the hardware signals. The speed of the serial interface limits the rate at which these functions can be manipulated and/or reported. Th e response time for the control and status bits is given in the “Electrical Characteristics” subsection.

Table 22. MIC3002 Events Figure 13. Control and Status I/O Logic

Table 24. Test and Diagnostic Features

Figure 24. Four-Byte Page White Protocol periodically checking for an acknowledgement. h (or 7Eh) at serial address A2 h. warm reset is performed using the RST bit in OEMCFG0. cases, OEMPW must be written LSB first through MSB last. OEMPW field. This is the factory default security setting. access and write protection for the user areas. address A2 h is used for setting the USER password. new password to be verified before it takes effect. password is in place, the user password will have no effect.

Micrel, Inc. MIC3002 July 2007 40 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Detailed Register Descriptions Note: Serial bus addresses shown assume that I2CADR = Axh. Alarm Threshold Registers Temperature High Alarm Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0°C) Serial Address A2 h Byte Address MSB (TXMAHh): 00 = 00 h LSB (TXMAHl): 00 = 01h Each LSB of TMAXh represents one degree centigrade. This register is to be used in conjunction with TMAXl to yield a sixteen- bit temperature value. The value in this register is uncalibrated. The nine MSbits of threshold value (TMAXh;TMAXl) are compared bit to bit to the nine MSbits value of the temperature reading (TEMPh;TEMPl).. Alarm bit Ax is set if Reading > Threshold. Temperature Low Alarm Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0°C) Serial Address A2 h Byte Address MSB (TMINh): 02 = 02 h LSB (TMINl): 02 = 02h Each LSB of TMINh represents one degree centigrade. TMINh is to be used in conjunction with TMINl to yield a sixteen-bit temperature value. The value in this register is uncalibrated. The nine MSbits of threshold value (TMINh;TMINl) are compared, bit to bit, to The nine MSbits value of the temperature reading (TEMPh;TEMPl). Alarm bit Ax is set if Reading < Threshold. Voltage High Alarm Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0V) Serial Address A2 h Bytes Address MSB (VMAXh): 08 = 08 h LSB (VMAXl): 09 = 09h Each LSB of VMAXh represents 25.6mV and each LSB of VMAXl represents 0.1mV. The sixteen bits threshold value (VMAXh;VMAXl) is compared bit to bit to the sixteen bits value of the voltage reading (VINh;VINl). Alarm bit Ax is set if Reading > Threshold.

Micrel, Inc. MIC3002 July 2007 41 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Voltage Low Alarm Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0V) Serial Address A2 h Bytes Address MSB (VMINh): 10 = 0A h LSB (VMINl): 11 = 0Bh Each LSB of VMINh represents 25.6mV and each LSB of VMINl represents 0.1mV. The sixteen bits threshold value (VMINh;VMINl) is compared bit to bit to the sixteen bits value of the voltage reading (VINh;VINl). Alarm bit Ax is set if Reading < Threshold. Bias Current High Alarm Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mA) Serial Address A2 h Bytes Address MSB (IMAXh): 16 = 10 h LSB (IMAXl): 17 = 11h Each LSB of IMAXh represents 512µA and each LSB of IMAXl represents 2µA. The sixteen bits threshold value (IMAXh;IMAXl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ILDh:ILDl). Alarm bit Ax is set if Reading > Threshold. Bias Current Low Alarm Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mA) Serial Address A2 h Byte Address MSB (IMINh): 18 = 12 h LSB (IMINl): 19 = 13h Each LSB of IMINh represents 512µA and each LSB of IMINl represents 2µA. The sixteen bits threshold value (IMINh;IMINl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ILDh:ILDl). Alarm bit Ax is set if Reading < Threshold. TX Optical Power High Alarm D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mW) Serial Address A2 h Byte Address MSB (TXMAXh): 24 = 18 h LSB (TXMAXl): 25 = 19h 24 = 18h Each LSB of TXMAXh represents 25.6µW. This register is to be used in conjunction with TXMAXl to yield a sixteen-bit value. The values in TXMAXh:TXMAXl are in an unsigned binary format. The value in this register is uncalibrated. The sixteen bits threshold value (TXMAXh;TXMAXl) is compared, bit to bit, to the sixteen bits value of the TX power reading (TXOPh:TXOPl). Alarm bit Ax is set if Reading > Threshold.

Micrel, Inc. MIC3002 July 2007 42 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 TX Optical Power Low Alarm D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mW) Serial Address A2 h Byte Address MSB (TXMAXh): 24 = 18 h LSB (TXMAXl): 25 = 19h Each LSB of TXMINh represents 25.6µW. This register is to be used in conjunction with TXMINl to yield a sixteen-bit value. The values in TXMINh:TMINl are in an unsigned binary format. The value in this register is uncalibrated. The sixteen bits threshold value (TXMINh;TXMINl) is compared, bit to bit, to the sixteen bits value of the RTX power reading (TXOPh:TXOPl). Alarm bit Ax is set if Reading < Threshold. RX Optical Power High Alarm Threshold MSB (RXMAXh) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mW) Serial Address A2 h Bytes Address MSB (RXMAXh): 32 = 20 h LSB (RXMAXl): 33 = 21h Each LSB of RXMAXh represents 25.6µW. This register is to be used in conjunction with RXMAXl to yield a sixteen-bit value. The value in this register is uncalibrated. The sixteen bits threshold value (RXMAXh;RXMAXl) is compared, bit to bit, to the sixteen bits value of the RX power reading (RXOPh:RXOPl). Alarm bit Ax is set if Reading > Threshold. RX Optical Power Low Alarm Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mW) Serial Address A2 h Byte Address MSB (RXMINh): 34 = 22 h LSB (RXMINl): 35 = 23h Each LSB of RXMINh represents 25.6µW. This register is to be used in conjunction with RXMINl to yield a sixteen-bit value. The value in this register is uncalibrated. The sixteen bits threshold value (RXMINh;RXMINl) is compared, bit to bit, to the sixteen bits value of the RX power reading (RXOPh:RXOPl). Alarm bit Ax is set if Reading < Threshold.

Micrel, Inc. MIC3002 July 2007 43 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Warning Threshold Registers Temperature High Warning Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0°C) Serial Address A2 h Bytes Address MSB (THIGHh): 04 = 04 h LSB (THIGHl): 05 = 05h Each LSB of THIGHh represents one degree centigrade. This register is to be used in conjunction with THIGHl to yield a sixteen-bit temperature value. The value in this register is uncalibrated. The nine MSbits of threshold value (THIGHh;THIGHl) are compared, bit to bit, to the nine MSbits value of the temperature reading (TEMPh;TEMPl).. Warning bit Wx is set if Reading > Threshold. Temperature Low Warning Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0°C) Serial Address A2 h Bytes Address MSB (TLOWh): 06 = 06 h LSB (TLOWl): 06 = 06h Each LSB of TLOWh represents one degree centigrade. This register is to be used in conjunction with TLOWl to yield a sixteen-bit temperature value. The value in this register is uncalibrated. The threshold value (THIGHh;THIGHl) is compared, bit to bit, to the value of the temperature reading (TEMPh;TEMPl). Warning bit Wx is set if Reading < Threshold, Voltage High Warning Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0V) Serial Address A2 h Bytes Address MSB (VHIGHh): 12 = 0C h LSB (VHIGHl): 13 = 0Dh 12 = 0Ch Each LSB of VHIGHh represents 25.6mV. This register is to be used in conjunction with VHIGHl to yield a sixteen-bit value. The value in this register is uncalibrated. The threshold value (VHIGHh;VHIGHl) is compared. bit to bit. to the value of the voltage reading (VINh;VINl). Warning bit Wx is set if Reading > Threshold. Voltage Low Warning Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0V) Serial Address A2 h Byte Address MSB (VLOWh): 14 = 0E h LSB (VLOWl): 15 = 0Fh Each LSB of VLOWh represents 25.6mV. This register is to be used in conjunction with VLOWl to yield a sixteen-bit value. The value in this register is uncalibrated. The threshold value (VLOWh;VLOWl) is compared. bit to bit, to the value of the voltage reading (VINh;VINl). Warning bit Wx is set if Reading < Threshold.

Micrel, Inc. MIC3002 July 2007 44 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Bias Current High Warning Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mA) Serial Address A2 h Bytes Address MSB (IHIGHh): 20 = 14 h LSB (IHIGHl): 21 = 15h Each LSB of IHIGHh represents 512µA and each LSB of IHIGHl represents 2µA. The sixteen bits threshold value (IHIGHh;IHIGHl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ILDh:ILDl). Warning bit Wx is set if Reading > Threshold. Bias Current Low Warning Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mA) Serial Address A2 h Bytes Address MSB (ILOWh): 22 = 16 h LSB (ILOWl): 23 = 17h Each LSB of ILOWh represents 512µA and each LSB of ILOWl represents 2µA. The sixteen bits threshold value (ILOWh;ILOWl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ILDh:ILDl). Warning bit Wx is set if Reading < Threshold. TX Optical Power High Warning MSB (TXHIGHh) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mW) Serial Address A2 h Bytes Address MSB (TXHIGHh): 28 = 1C h LSB (TXHIGHl): 29 = 1Dh Each LSB of TXHIGHh represents 25.6µW. This register is to be used in conjunction with TXHIGHl to yield a sixteen-bit value. The values in TXHIGHh:TXHIGHl are in an unsigned binary format. The value in this register is uncalibrated. The sixteen bits threshold value (TXHIGHh;TXHIGHl) is compared, bit to bit, to the sixteen bits value of the TX power reading (TXOPh:TXOPl). Warning bit Wx is set if Reading > Threshold. TX Optical Power Low Warning D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mW) Serial Address A2 h Byte Address MSB (TXLOWh): 30 = 1E h LSB (TXLOWl): 31 = 1Fh Each LSB of TXLOWh represents 25.6µW. This register is to be used in conjunction with TXLOWl to yield a sixteen-bit value. The values in TXLOWh:TLOWl are in an unsigned binary format. The value in this register is uncalibrated. The sixteen bits threshold value (TXLOWh;TXLOWl) is compared, bit to bit, to the sixteen bits value of the TX power reading (TXOPh:TXOPl). Warning bit Wx is set if Reading < Threshold.

Micrel, Inc. MIC3002 July 2007 45 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 RX Optical Power High Warning Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mW) Serial Address A2 h Byte Address MSB (RXHIGHh): 36 = 24 h LSB (RXHIGHl): 37 = 25h Each LSB of RXHIGHh represents 25.6µW and each ach LSB of RXHIGHl represents 0.1µW.. The value in this register is uncalibrated. The sixteen bits threshold value (RXHIGHh;RXHIGHl) is compared, bit to bit, to the sixteen bits value of the RX power reading (RXOPh:RXOPl). Warning bit Wx is set if Reading > Threshold. RX Optical Power Low Warning Threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0mW) Serial Address A2 h Byte Address 38 = 26 h Each LSB of RXLOWh represents 25.6µW and each eah LSB of RXLOWl represents 0.1µW. The value in this register is uncalibrated. The sixteen bits threshold value (RXlOWh;RXLOWl) is compared, bit to bit, to the sixteen bits value of the RX power reading (RXOPh:RXOPl). Warning bit Wx is set if Reading > Threshold. Checksum (CHKSUM) Checksum of bytes 0 - 94 at serial address A2h D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (0°C) Serial Address A2 h Byte Address 95 = 5F h This register is provided for compliance with SFF-8472. It is implemented as general-purpose non-volatile memory. Read/write access is possible whenever a valid OEM password has been entered. CHKSUM is read-only in USER mode. ADC Result Registers Temperature Result D[7] read-only D[6] read-only D[5] read-only D[4] read-only D[3] read-only D[2] read-only D[1] read-only D[0] read-only Default Value 0000 0000b = 00h (0°C)(1) Serial Address A2 h Byte Address MSB (TEMPh): 96 = 60 h LSB (TEMPl): 97 = 61h Each LSB of TEMPh represents one degree centigrade. The TEMPh register is to be used in conjunction with TEMPl to yield a sixteen-bit temperature value. If OEMCFG6 bit 1 is a zero, temperature is read to 1°C resolution in TEMPh only, and TEMPl is zero. If OEMCFG6 bit 1 is a one, then temperature is read to 0.5°C resolution as a nine-bit value consisting of TEMPh and the MS bit of TEMPl. The lower seven bits of TEMPl are zero.

Micrel, Inc. MIC3002 July 2007 46 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Voltage D[7] read-only D[6] read-only D[5] read-only D[4] read-only D[3] read-only D[2] read-only D[1] read-only D[0] read-only Default Value 0000 0000b = 00h (0V)(2) Serial Address A2 h Byte Address MSB (VINh): 98 = 62 h LSB (VINl): 99 = 63h Each LSB of VINh represents 25.6mV. VINh register is to be used in conjunction with VINl to yield a sixteen-bit value. The values in VINh:VlNl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. In the MIC3002, VINl will always return zero. It is provided for compliance with SFF-8472. Notes: 1. TEMPh will contain measured temperature dat a after the completion of one conversion. 2. VINh will contain measured data after one A/D conversion cycle. Laser Diode Bias Current D[7] read-only D[6] read-only D[5] read-only D[4] read-only D[3] read-only D[2] read-only D[1] read-only D[0] read-only Default Value 0000 0000b = 00h (0mA)(3) Serial Address A2 h Byte Address MSB (ILDh):100 = 64 h LSB (ILDl):100 = 65h ILDh is to be used in conjunction with ILDl to yield a sixteen-bit value. The values in ILDh:ILDl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration sections. In the MIC3002, ILDl will always return zero. It is provided for compliance with SFF-8472. Transmitted Optical Power D[7] read-only D[6] read-only D[5] read-only D[4] read-only D[3] read-only D[2] read-only D[1] read-only D[0] read-only Default Value 0000 0000b = 00h (0mW)(5) Serial Address A2 h Byte Address MSB (TXOPh): 102 = 66 h LSB (TXOPl): 103 = 67h Each LSB of TXOPh represents 25.6µW. THOPh is to be used in conjunction with TXOPl to yield a sixteen-bit value. The values in TXOPh:TXOPl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. In the MIC3002, this TXOPl will always return zero. It is provided for compliance with SFF-8472. Notes: 3. ILDh will contain measured data after one A/D conversion cycle. 4. The scale factor corresponding to the sense resist or used must be set in the configuration register. 5. TXOPh will contain measured data after one A/D conversion cycle.

Micrel, Inc. MIC3002 July 2007 47 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Received Optical Power D[7] read-only D[6] read-only D[5] read-only D[4] read-only D[3] read-only D[2] read-only D[1] read-only D[0] read-only Default Value 0000 0000b = 00h (0mW)(6) Serial Address A2 h Byte Address MSB (RXOPh): 104 = 68 h LSB (RXOPl): 105 = 69h Each LSB of RXOPl represents 25.6µW and each LSB of RXOPl represents 0.1µW. RXOPh is to be used in conjunction with RXOPl to yield a sixteen-bit value. The values in RXOPh:RXOPl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration section. Control and Status (CNTRL) D[7] TXDIS read-only D[6] STXDIS read/write D[5] reserved D[4] RSEL read/write D[3] SRSEL read/write D[2] XFLT read-only D[1] LOS read-only D[0] POR read-only Default Value 0000 0000 b = 00h Serial Address A2 h Byte Address 110 = 6E h Bit(s) Function Operation D[7] TXDIS Reflects the stat e of the TXDISABLE pin 1 = disabled, 0 = enabled, read only. D[6] STXDIS Soft transmit disable 1 = disabled; 0 = enabled. D[5] D[5] Reserved Reserved - always write as zero. D[4] RSEL Reflects the state of the RSEL pin 1 = high; 0 = low. D[3] SREL Soft rate select 1 = high (2Gbps); 0 = low (1Gbps). D[2] TXFLT Reflects the stat e of the TXFAULT pin 1 = high (fault); 0 = low (no fault). D[1] LOS Loss of signal. Reflects the state of the LOS pin 1 = high (loss of signal); 0 = low (no loss of signal). D[0] POR MIC3002 power-on status 0 = POR complete, analog data ready; 1 = POR in progress. Notes: 6. RXOPh will contain measured data after one A/D conversion cycle.

Micrel, Inc. MIC3002 July 2007 48 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Alarm Flags Alarm Status Register 0 (ALARM0) D[7] read-only D[6] read-only D[5] read-only D[4] read-only D[3] read-only D[2] read-only D[1] read-only D[0] read-only Default Value 0000 0000 b = 00h (no events pending) Serial Address A2 h Byte Address 112 = 70 h The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending upon the results. Bit(s) Function Operation D[7] A7 High temperature alarm, TEMP > TMAXh 1 = condition exists, 0 = normal/OK. D[6] A6 Low temperature alarm, TEMPh< TMIN 1 = condition exists, 0 = normal/OK. D[5] A5 High voltage alarm, VIN > VM AX 1 = condition exists, 0 = normal/OK. D[4] A4 Low voltage alarm, VIN < VM IN 1 = condition exists, 0 = normal/OK. D[3] A3 High laser diode bias alarm, IBI AS > IMAX 1 = condition exists, 0 = normal/OK. D[2] A2 Low laser diode bias alarm, IBI AS < IMIN 1 = condition exists, 0 = normal/OK. D[1] A1 High transmit optical power alarm, TXOP > TXMAX 1 = condition exists, 0 = normal/OK. D[0] A0 Low transmit optical power alarm, TXOP < TXMIN 1 = condition exists, 0 = normal/OK. Alarm Status Register 1 (ALARM1) D[7] A15 read-only D[6] A14 read-only D[5] reserved D[4] reserved D[3] reserved D[2] reserved D[1] reserved D[0] reserved Default Value 0000 0000 b = 00h (no events pending) Serial Address A2 h Byte Address 113 = 71 h The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending upon the results. Bit(s) Function Operation D[7] A15 High received power (overload) alarm, RXOP > RXMAX 1 = condition exists, 0 = normal/OK. D[6] A14 Low received power (LOS) alarm, RXOP < RXMIN 1 = condition exists, 0 = normal/OK. D[5:0] Reserved Reserved - always write as zero.

Micrel, Inc. MIC3002 July 2007 49 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Warning Flags Warning Status Register 0 (WARN0) D[7] read-only D[6] read-only D[5] read-only D[4] read-only D[3] read-only D[2] read-only D[1] read-only D[0] read-only Default Value 0000 0000b = 00h (no events pending) Serial Address A2h Byte Address 116 = 74h The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending upon the results. Bit(s) Function Operation D[7] W7 High temperature warning, TEMP > THIGH 1 = condition exists, 0 = normal/OK. D[6] W6 Low temperature warning, TEMP < TLOW 1 = condition exists, 0 = normal/OK. D[5] W5 High voltage warning, VIN > VH IGH 1 = condition exists, 0 = normal/OK. D[4] W4 Low voltage warning, VIN < VL OW 1 = condition exists, 0 = normal/OK. D[3] W3 High laser diode bias warning, IBI AS > IHIGH 1 = condition exists, 0 = normal/OK. D[2] W2 Low laser diode bias warning, IBI AS < ILOW 1 = condition exists, 0 = normal/OK. D[1] W1 High transmit optical power warning, TXOP > TXHIGH 1 = condition exists, 0 = normal/OK. D[0] W0 Low transmit optical power warning, TXOP < TXLOW 1 = condition exists, 0 = normal/OK. Warning Status Register 1 (WARN1) D[7] W15 read-only D[6] W14 read-only D[5] read-only D[4] read-only D[3] read-only D[2] read-only D[1] read-only D[0] read-only Default Value 0000 0000 b = 00h (no events pending) Serial Address A2 h Byte Address 117 = 75 h The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending upon the results. Bit(s) Function Operation D[7] W15 Received power high warning, RXOP > RXHIGH 1 = condition exists, 0 = normal/OK. D[6] W14 Received power low warning, RXOP < RXMIN 1 = condition exists, 0 = normal/OK. D[5:0] Reserved Reserved - always write as zero.

Micrel, Inc. MIC3002 July 2007 50 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 OEM Password Entry (OEMPW) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h (reset to zero at power-on) Serial Address A2 h Byte Address If OEMCFG5-2 = 0: 120 – 123 = 78h - 7Bh (MSB is 7Bh If OEMCFG5-2 = 1: 123– 126 = 7Bh – 7Eh (MSB is 7Eh) This four-byte field is for entry of the password required to access the OEM area of the MIC3002’s memory and registers. A valid OEM password will also permit access to the user areas of memory. The byte at address 123 (7Bh), 126 (7Eh) if OMGFG5 bit2 =1, is the most significant byte. This field is compared to the four-byte OEMPWSET field at serial address A6h, bytes 12 to 15. If the two fields match, access is allowed to the OEM areas of the MIC3002 non-volatile memory at serial addresses A4h and A6h. The OEM password is set by writing the new value into OEMPWSET. The password comparison is performed following the write to the MSB, address 7Bh (7Eh if OEMCFG5-2 = 1). This byte must be written last! A four-byte burst-write sequence to address 78h(7Bh if OEMCFG5-2 = 1) may be used as this will result in the MSB being written last. The new password will not take effect until after a power-on reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. This field is reset to all zeros at power on. Any values written to these locations will be readable by the host regardless of the locked/unlocked status of the device. If OEMPWSET is set to zero (00000000h), the MIC3002 will remain unlocked regardless of the contents of the OEMPW field. This is the factory default security setting. Byte Weight 3 OEM Password Entry, Most Significant Byte (Address = 7Bh resp. 7Eh) 2 OEM Password Entry, 2nd Most Significant Byte (Address = 7Ah resp. 7Dh) 1 OEM Password Entry, 2nd Least Significant Byte (Address = 79h resp. 7Ch) 0 OEM Password Entry, Least Significant Byte (Address = 78h resp. 7Bh) USER Password Setting (USRPWSET) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A2 h Byte Address 246 = F6 h This register is for setting the password required to access the USER area of the MIC3002’s memory and registers. This field is compared to the USRPW field at serial address A2h, byte 247(F7h). If the two fields match, access is allowed to the USER areas of the MIC3002 non-volatile memory at serial addresses A0h and A2h. If a valid USER password has not been entered, writes to the serial ID fields, USRCTRL, and the user scratchpad areas of A0h and A2h will not be allowed, and USRPWSET will be unreadable (returns all zeroes). A USER password is set by writing the new value into USRPWSET. The new password will not take effect until after a power- on reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. This register is non-volatile and will be maintained through power and reset cycles. A valid USER or OEM password is required for access to this register. Otherwise, this register will read as 00h. Note: a valid OEM password overrides the USER password setting. If a valid OEM password is currently in place, the user password will have no effect.

Micrel, Inc. MIC3002 July 2007 51 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 USER Password (USRPW) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A2 h Byte Address 247 = F7 h USER passwords are entered in this field. This field is compared to the USRPWSET field at serial address A2h, byte 246 (F6h). If the two fields match, access is allowed to the USER areas of the MIC3002 non-volatile memory at serial addresses A0h and A2h. If a valid USER password has not been entered, writes to the serial ID fields and user scratchpad areas of A0h and A2h will not be allowed and USRPWSET will be unreadable (returns all zeroes). Power-On Hours D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Bytes Address MSB (POHh): 251 = FB h LSB (POHl): 252 = FCh The lower seven bits of POHh register contain the most-significant bits of the 15-bit power-on hours measurement. POHFLT is an error flag. The value in POHh should be combined with the Power-on Hours, Low Byte, POHl, to yield the complete result. If POHFLT is set, the power-on hour meter data has been corrupted and should be ignored. It is recommended that a two-byte (or more) sequential read operation be performed on POHh and POHl to insure coherency between the two registers. This register is non-volatile and will be maintained through power and reset cycle. POHh Bit(s) Function Operation D[7] Power-on hours fault flag 1 = fault; 0 = no fault. D[6:0] Power-on hours, high byte Non-volatile. Data Ready Flags (DATARDY) D[7] TRDY read/write D[6] VRDY read/write D[5] IRDY read/write D[4] TXRDY read/write D[3] RXDY read/write D[2] reserved D[1] reserved D[0] reserved Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 253 = FD h When the A/D conversion for a given parameter is completed and the results available to the host, the corresponding data ready flag will be set. The flag will be cleared when the host reads the corresponding result register. Bit(s) Function Operation D[7] TRDY Temperature data ready fl ag 0 = old data; 1 = new data ready D[6] VRDY Voltage dat a ready flag 0 = old data; 1 = new data ready D[5] IRDY Bias current data ready flag 0 = old data; 1 = new data ready D[4] TXRDY Transmit power data ready f lag 0 = old data; 1 = new data ready D[3] RXRDY Receive power data ready f lag 0 = old data; 1 = new data ready D[2:0] Reserved Reserved

Micrel, Inc. MIC3002 July 2007 52 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 USER Control Register (USRCTL) D[7] read/write D[6] PORM read/write D[5] PORS read/write D[4] IE read/write D[3] APCSEL[1] read/write D[2] APCSEL[0] read/write D[1] MODSEL[1] read/write D[0] MODSEL[0] read/write Default Value 0010 0000 b = 20h Serial Address A2 h Byte Address 255 = FF h if OMCFG6 bit 2 = 0 222 = DEh if OMCFG6 bit 2 = 1 This register provides for control of the nominal APC setpoint and management of interrupts by the end-user. APCSEL[1:0] select which of the APC setpoint registers, APCSET0, APCSET1, or APCSET2 are used as the nominal automatic power control setpoint. IE must be set for any interrupts to occur. If PORM is set, the power-on event will generate an interrupt and warm resets using RST will not generate a POR interrupt. When a power-on interrupt occurs, assuming PORM=1, PORS will be set. PORS will be cleared and the interrupt output de-asserted when USRCTL is read by the host. If IE is set while /INT is asserted, /INT will be de-asserted. The host must still clear the various status flags by reading them. If PORM is set following the setting of PORS, PORS will remain set, and /INT will not be de-asserted, until USRCTL is read by the host. PORM, IE, and APCSEL are non-volatile and will be maintained through power and reset cycles. A valid USER password is required for access to this register. Bit Function Operation D[7] Reserved Always write as zero; reads undefined. D[6] PORM Power-on interrupt mask 1 = POR interrupts enabled; 0 = disabled; read/write; non-volatile. D[5] PORS Power-on interrupt flag 1 = POR interrupt occurred; 0 = no POR interrupt; read-only. D[4] IE Global interrupt enable 1 = enabled; 0 = disabled; read/write; non-volatile. D[3:2] APCSEL Selects APC setpoint register 00 = APCSET0, 01 = APCSET1, 10 = APCSET2; 11 = reserved; read/write; non-volatile. D[1:0] MODSEL Selects Modulation setpoint register 00 = MODSET0, 01 = MODSET1, 10 = MODSET2, 11 = reserved; read/write; non volatile. OEM Configuration Register 0 (OEMCFG0) D[7] RST write only D[6] ZONE read/write D[5] DFLT read only D[4] OE reserved D[3] MODREF reserved D[2] VAUX[2] read/write D[1] VAUX[1] read/write D[0] VAUX[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 00 = 00 h A write to OEMCFG0 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a new conversion sequence once the write operation is complete. All bits in OEMCFG0 are non-volatile except DFLT and RST. A valid OEM password is required for access to this register. Bit(s) Function Operation D[7] RST 0 = no action; 1 = reset; write-only. D[6] ZONE Selects temperature zone. 0 = internal; 1 = external; non-volatile. D[5] DFLT Diode fault flag. 1 = diode fault; 0 = OK. D[4] OE Output enable for SHDN, VMOD, 1 = enabled; 0 = hi-Z; non-volatile.

Micrel, Inc. MIC3002 July 2007 53 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 and VBIAS. D[3] MODREF Selects whether VMOD is referenced to ground or VDD. 1 = VDD; 0 = GND; non-volatile. D[2:0] VAUX[2:0] Selects the voltage reported in VINh:VINl. 000 = VIN; 001 = VDDA; 010 = VBIAS; 011 = VMOD; 100 = APCDAC; 101 = MODDAC; 110 = FLTDAC; non- volatile OEM Configuration Register 1 (OEMCFG1) D[7] INV read/write D[6] GAIN read/write D[5] BIASREF read/write D[4] RFB[2] read/write D[3] RFB[1] read/write D[2] RFB[0] read/write D[1] SRCE read/write D[0] SPOL read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 1 = 01 h A write to OEMCFG1 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a new conversion sequence once the write operation is complete. All bits in OEMCFG1 are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register. Bit(s) Function Operation D[7] INV Inverts the APC op-amp inputs. When set to “0” the BIAS DAC output is connected to the “+”input and FB is connected to the “–” input of the op amp. Set to “0” to use the ADC feedback loop. 0 = emitter follower (no inversion); 1 = common emitter (inverted); read/write; non-volatile. D[6] GAIN Sets the feedback voltage range by changing the APCDAC output swing; 0-VREF for optical feedback, 0-VREF/4 for electrical feedback. 1 = VREF/4 full scale; 0 = VREF full scale; read/write; non-volatile. D[5] BIASREF Selects whether FB and VMPD are referenced to ground or VDD and selects feedback resistor termination voltage (VDDA or GNDA). 1 = VDD; 0 = GND; read/write; non-volatile. D[4:2] RFB[2:0] Selects internal feedback resistance. (Resistors will be terminated to VDDA or GNDA according to BIASREF.) 000 = ∞; 001 = 800Ω, 010 = 1.6kΩ, 011 = 3.2kΩ, 100 = 6.4kΩ, 101 = 12.8kΩ, 110 = 25.6kΩ, 111 = 51.2kΩ; read/write; non-volatile. D[1] SRCE VBIAS source vs. sink drive. 1 = source (NPN), 0 = sink (PNP); read/write; non-volatile. D[0] SPOL Polarity of shutdown output, SHDN, when active. 1 = high; 0 = low; read/write; non-volatile.

Micrel, Inc. MIC3002 July 2007 54 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 OEM Configuration Register 2 (OEMCFG2) D[7] I2CADR[3] read/write D[6] I2CADR[2] read/write D[5] I2CADR[1] read/write D[4] I2CADR[0] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 1010 xxxx b = xxh (slave address = 1010xxxb) Serial Address A6 h Byte Address 2 = 02 h CAUTION: Changes to I2CADR take effect immediately! Any accesses following a write to I2CADR must be to the newly programmed serial bus address. A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. Bit(s) Function Operation D[7:4] I2CADR[3:0] Upper four MSBs of the serial bus slave address; writes take effect immediately. Read/write; non-volatile. D[3:0] Reserved Read/write; non-volatile. APC Setpoint x (APCSETx) Automatic power control setpoint (unsigned binary) used when APCSEL[1:0] = 00 D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Bytes Address APCSET0: 3 = 03 h APCSET1: 4 = 04h APCSET2: 5 = 05h VBIAS DAC, bypassing the look-up table entirely. In either case, the VBIAS DAC setting is reported in the VBIAS register. The APCCFG bits determine the DAC’s response to higher or lower numeric values. A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. Modulation Setpoint x (MODSETx) Nominal VMOD setpoint D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address MODSET0: 6 = 06 h MODSET1: 30 = 1Eh MODSET2: 31 = 1Fh When A.P.C. is on, the value corresponding to the current temperature is taken from the MODLUT look-up table, added to MODSET and loaded into the VMOD DAC. This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register.

Micrel, Inc. MIC3002 July 2007 55 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 IBIAS Fault Threshold (IBFLT) Bias current fault threshold D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 7 = 07 h A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. A fault is generated if the bias current is higher than IBFLT value set in this register. Transmit Power Fault Threshold (TXFLT) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 8 = 08 h A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. A fault is generated if the Transmit power is higher than TXFLT value set in this register. Loss-Of-Signal Threshold (LOSFLT) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 9 = 09 h A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. A fault is generated if the received power is lower than LOSFLT value set in this register. Byte Function Operation D[7:4] Receive loss-of-signal thre shold Read/write; non-volatile. Fault Suppression Timer (FLTTMR) Fault suppression interval in increments of 0.5ms D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 10 = 0A h Saturation faults are suppressed for a time, tFLTTMR, following laser turn-on. This avoids nuisance tripping while the APC loop starts up. The length of this interval is (FLTTMRx 0.5ms), typical. A value of zero will result in no fault suppression. A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles.

Micrel, Inc. MIC3002 July 2007 56 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Fault Mask (FLTMSK) D[7] OEMIM read/write D[6] POHE read/write D[5] reserved D[4] reserved D[3] SATMSK read/write D[2] TXMSK read/write D[1] IAMSK read/write D[0] DFMSK read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 11 = 0B h A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles. Bit Function Operation D[7] OEMIM OEM interrupt mask bit 1 = masked; 0 = enabled; Read/write; non-volatile. D[6] POHE OEM Power-on Hour Meter enable bit 1 = enabled; 0 = disabled; Read/write; non-volatile. D[5:4] D[5:4] Reserved Always write as zero; reads undefined. D[3] SATMSK APC saturation fault mask bit 1 = masked; 0 = enabled; Read/write; non-volatile. D[2] TXMSK High TX optical power fault mask bit 1 = masked; 0 = enabled; Read/write; non-volatile. D[1] IAMSK Bias current high alarm mask bit 1 = masked; 0 = enabled; Read/write; non-volatile. D[0] DFMSK Diode fault mask bit 1 = masked; 0 = enabled; Read/write; non-volatile. OEM Password Setting (OEMPWSET) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 12 - 15 = 0C h - 0Fh; 0Ch = MSB This four-byte field is the password required for access to the OEM area of the MIC3002’s memory and registers. The byte at address 12 (0Ch) is the most significant byte. This field is compared to the four-byte OEMPW field at serial address A2h, byte 120 to 123 if OMCFG6-2 = 0, or byte 123 to 126 if OEMCFG6-2 = 1. If the two fields match, access is allowed to the OEM areas of the MIC3002 non-volatile memory at serial addresses A4h and A6h. The OEM password may be set by writing the new value into OEMPWSET. The new password will not take effect until after a power-on reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register. Byte Weight

3 OEM Password, Most Significant Byte

2 OEM Password, 2nd Most Significant Byte

1 OEM Password, 2nd Least Significant Byte

0 OEM Password, Least Significant Byte

Micrel, Inc. MIC3002 July 2007 57 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 OEM Calibration 0 (OEMCAL0) D[7] reserved D[6] FLTDIS read/write D[5] FSPIN read/write D[4] WRINH read/write D[3] APCCAL read/write D[2] FRCINT read/write D[1] FRCTXF read/write D[0] FRCLOS read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 16 = 10 h A valid OEM password is required for access to this register. Bit Function Operation D[7] Reserved Always write as zero; reads undefined. D[6] FLTDIS Fault comparator disable; inhibits output of fault comparators when set. 0 = faults enabled; 1 = disabled; Read/write. D[5] FSPIN Fault comparator “spin-on-channel” mode select; do not enable ADC and FC spin- on-channel modes simultaneously. 0 = normal operation; 1 = spin on channel; Read/write. D[4] WRINH Inhibit NVRAM write cycles. 0 = nor mal operation; 1 = inhibit writes; Read/write. D[3] APCCAL Selects APC calibration mode - DACs may be controlled directly. 0 = normal mode; 1 = calibration mode; Read/write. D[2] FRCINT Forces the assertion of /INT 0 = normal operation; 1 = asserted; Read/write. D[1] FRCTXF Forces the assertion of TXFAULT 0 = normal operation; 1 = asserted; Read/write. D[0] FDCLOS Forces the assertion of RXLOS 0 = normal operation; 1 = asserted; Read/write. OEM Calibration 1 (OEMCAL1) D[7] reserved D[6] ADSTP read/write D[5] ADIDL read/write D[4] 1SHOT read/write D[3] ADSPIN read/write D[2] SPIN[2] read/write D[1] SPIN[1] read/write D[0] SPIN[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 17 = 11 h A valid OEM password is required for access to this register. Bit Function Operation D[7] Reserved Always write as zero; reads undefined. D[6] ADSTP Stop ADC Halts the analog to digital converter 0 = normal operation; 1 = stopped; Read/write. D[5] ADIDL ADC idle flag 0 = busy; 1 = idle; Read/write. D[4] 1SHOT Triggers one-shot A/D conversion cycle 0 = normal operation; 1 = one-shot; Read/write. D[3] ADSPIN Selects ADC spin-on-channel mode; do not enable ADC and FC spin-on-channel modes simultaneously 0 = normal operation; 1 = spin-on-channel; Read/write. D[2], D[1], D[0] SPIN[2:0] ADC and fault comparator (FC) channel select for spin-on-channel mode; do not enable ADC and FC spin-on-channel modes simultaneously ADC: 000 = temperature; 001 = voltage; 010 = VILD; 011 = VMPD; 100 = VRX; FC: 001 = VILD; 001 = VMPD; 010 = VRX; Read/write.

Micrel, Inc. MIC3002 July 2007 58 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 OEM Calibration 1 (LUT Index) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 18 = 12h The look-up table index is derived from the current temperature measurement as follows: INDEX = TAVG / 2 where TAVG(n) is the current average temperature. This register allows the current table index to be read by the host. The table base address must be added to LUTINDX to form a complete table index in physical memory. A valid OEM password is required for access to this register. Otherwise, reads are undefined. OEM Configuration 3 (OEMCFG3) D[7] LUTSEL read/write D[6] TXFPOL read/write D[5] GPOD read/write D[4] GPOM read/write D[3] GPOC read/write D[2] TXFIN read/write D[1] LOSDIS read/write D[0] INTCAL read/write Default Value 0000 1000 b = 08h Serial Address A6 h Byte Address 19 = 13 h This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this register. GPOD and GPOC are ignored when GPOM = 0. TXFPOL is ignored if TXFIN = 0. Bit Function Operation D[7] LUTSEL RX power look-up table input selection bit 1 = RX power; 0 = temperature; read/write; ignored if INTCAL = 0. D[6] TXFPOL TXFIN active polarity select; a fault is indicated when TXFIN = TXFPOL 0 = active-low; 1 = active-high; read/write; ignored if TXFIN = 0. D[5] GPOD GPO output drive 0 = open drain; 1 = push-pull; read/write; ignored if GPOM = 0. D[4] GPOM GPO/RSOUT mode select 0 = RSOUT; 1 = GPO; read/write. D[3] GPOC GPO output control 0 = low; 1 = high; read/write; ignored if GPOM = 0. D[2] TXFIN TXFIN mode select 0 = SHDN; 1 = TXFIN; read/write. D[1] LOSDIS RXLOS comparator disable 0 = enabled; 1 = disabled; read/write. D[0] INTCAL Calibration mode select 0 = external calibration; 1 = internal calibration; read/write. BIAS DAC Setting (APCDAC) Current VBIAS Setting D[7] read only D[6] read only D[5] read only D[4] read only D[3] read only D[2] read only D[1] read only D[0] read only Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 20 = 14 h This register reflects (reads back) the value set in the APC register (APCSET0, APCSET1, or APCSET2 whichever is selected). A valid OEM password is required for access to this register.

Micrel, Inc. MIC3002 July 2007 59 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Modulation DAC Setting (MODDAC) Current VMOD Setting D[7] read only D[6] read only D[5] read only D[4] read only D[3] read only D[2] read only D[1] read only D[0] read only Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 21 = 15 h This register reflects (reads back) the value set in the MODSET register. A valid OEM password is required for access to this register. OEM Readback Register (OEMRD) D[7] reserved D[6] reserved D[5] reserved D[4] INT read only D[3] APCSAT read only D[2] IBFLT read only D[1] TXFLT read only D[0] RSOUT read only Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 22 = 16 h This register reflects (reads back) the status of the bits corresponding to the parameters defined below. A valid OEM password is required for access to this register. Otherwise, reads are undefined and writes are ignored. Bit Function Operation D[7:5] Reserved Always write as zero; reads undefined. D[4] INT Mirrors state of /INT but active-high; not state of physical pin! 1 = interrupt; 0 = no interrupt. D[3] APCSAT APC saturation fault comparator output state 1 = fault; 0 = normal operation. D[2] IBFLT State of IBIAS over-current fault comparator output 1 = fault; 0 = normal operation; read-only. D[1] TXFLT State of transmit power fault comparator output 1 = fault; 0 = normal operation; read-only. D[0] RSOUT State of the rate select output pin, RSOUT 1 = high; 0 = low; Read-only. Signal Detect Threshold (LOSFLTn) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 23 = 17 h This register works in conjunction with the LOSFLT register to control the operation of the loss of signal comparator. The comparator’s output, RXLOS, is asserted when the input on VRX falls below the level in LOSFLT. The output will then be de- asserted when the VRX signal rises above LOSFLTn. The input signal is subject to scaling by the RXPOT. If the LOS comparator is disabled, i.e., LOSDIS = 1, this register is ignored. A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power and reset cycles.

Micrel, Inc. MIC3002 July 2007 60 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 RX EEPOT Tap Selection (RXPOT) D[7] reserved D[6] reserved D[5] reserved D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 24 = 18 h This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers. Bit(s) Function Operation D[7:5] Reserved Reserved. Always write as zero; reads undefined. D[4:0] RXPOT tap selection: 00000 = No divider action; POT disconnected 00001 = 31/32 00010 = 30/32 11110 = 2/32 11111 = 1/32 Read/write; non-volatile. OEM Configuration 4 (OEMCFG4) D[7] reserved D[6] reserved D[5] reserved D[4] reserved D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 25 = 19 h This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers. Bit(s) Function Operation D[7] Allows Warnings to assert TXFAULT 0: Warnings do not assert TXFAULT 1: Warnings assert TXFAULT The RXPWR low warning flag does not assert TXFAULT D[6] Allows Alarms to assert TXFAULT 0: Alarms do not assert TXFAULT 1: Alarms assert TXFAULT The RXPWR low alarm flag does not assert TXFAULT D[5] Warning Latch 0: Warnings flags are latched. They are cleared by reading the register or toggling TXDISABLE. 1: Warnings flags are not latched., i.e. they are set and reset with alarm condition. The flags are also cleared by reading the register or toggling TXDISABLE. D[4] Alarm Latch 0: Alarms flags are latched. They are cleared by reading the register or toggling TXDISABLE. 1: Alarms flags are not latched., i.e. they are set and reset with alarm condition. The flags are also cleared by reading the register or toggling TXDISABLE.

Micrel, Inc. MIC3002 July 2007 61 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 ISTART[3:0] I START current level selection: 0000 = No ISTART current 0001 - 1111 = 0.375mA x ISTART[3:0] ISTART is used to speed up the laser start-up after a fault occurs. The charging current of the compensation cap starts from ISTART instead of ramping up from 0. Read/write; non-volatile. OEM Configuration 5 (OEMCFG5) D[7] reserved D[6] reserved D[5] reserved D[4] reserved D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 26 = 1A h This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers. Bit(s) Function Operation D[7] SHDN output enable / disable 0: SHDN is enabled. TXFAULT will trigger SHDN output 1: SHDN is disabled. TXFAULT has no effect on SHDN output This applies when pin 7 is set as SHDN output. D[6] Temperature-compensation of the temperature used to access the L.U.T.s. 0: The temperature used to index into the LUTs is not compensated (sensed temperature used) 1: The temperature used to index the LUTs is temperature-compensated (module case temperature used) D[5] Temperature-compensation of the temperature result in the temperature register. 0: The temperature result in the temperature register is not compensated (sensed temperature sed) 1: The temperature result in the temperature register is compensated (module case temperature used) D[4] Polarity of TXFAULT 0: TXFAULT is active high 1: TXFAULT is active low D[3] SMBUS multipart support 0: Multipart mode off 1: Multipart mode on D[2] OEM password location 0: A6h 120-123 (78h-7Bh) 1: A6h 123-126 (7Bh-7Eh) D[1] SMBUS timeout enable / disable 0: SMBUS timeout enabled 1: SMBUS timeout disabled D[0] DACs reset 0: Clear DACs when the laser is off 1: Do not clear the DACs when laser is off

Micrel, Inc. MIC3002 July 2007 62 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 OEM Configuration 6 (OEMCFG6) D[7] reserved D[6] reserved D[5] reserved D[4] reserved D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 27 = 1B h This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers. Bit(s) Function Operation D[5-7] Reserved D[4] TXDISABLE debounce enable / disable 0: TXDISABLE is not debounced 1: TXDISABLE is debounced. Glitches less than 5 ms are rejected. Set the bit to 1 is a mechanical switch is used for TXDISABLE. Set to 0 for normal operation to assure compliance to the SFP MSA. D[3] RXLOS Polarity 0: RXLOS low for normal operation and high with a loss of signal condition. 1: RXLOS high for normal operation (signal detected) and low with a loss of signal (no signal detected) condition. D[2] USRCTRL register location 0: A2 255 (FFh) 1: A2 222 (DEh) D[1] Temperature resolution 0: Temperature is measured to a resolution of 1ºC 1: Temperature is measured to a resolution of 0.5ºC D[0] TXFAULT clear mode 0: TXFAULT remains set until TXDISABLE is toggled 1: TXFAULT is in continuous mode and follows the state of the faults. Power-On Hour Meter Data (POHDATA) D[7] read/write D[6] read/write D[5] read/write D[4] read/write D[3] read/write D[2] read/write D[1] read/write D[0] read/write Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 32-39 = 20 h - 27h These registers are used for backing up the POH result during power cycles. At power-up, the POH meter selects the larger of the two values as the initial count. Incremental results are stored in alternate register pairs. The power-on hour meter may be reset or preset by writing to these registers. These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers. Byte Weight

3 POHA, high-byte

2 POHA, low-byte

1 POHB, high-byte

0 POHB, low-byte

Micrel, Inc. MIC3002 July 2007 63 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 OEM Scratchpad Registers (SCRATCHn) Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 135-143 (87-8Fh) 156-159 (9C-9Fh) 172-175 (AC-AFh) 188-191 (BC-BFh) 204-207 (CC-CFh) 222-250 (DE-FAh) The scratchpad registers are general-purpose non-volatile memory locations. They can be freely read from and written to any time the MIC3002 is in OEM mode. RX Power Look-up Table (RXLUTn) Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 40-71 = 28 h - 47h These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers. Bytes Definition RXSLP0h RX Slope 0, High Byte. RXSLP0l RX Slope 0, Low Byte. RXOFF0h RX Offset 0, High Byte. RXOFF0l RX Offset 0, Low Byte. RXSLP1h RX Slope 1, High Byte. RXSLP1l RX Slope 1, Low Byte. RXOFF1h RX Offset 1, High Byte. RXOFF1l RX Offset 1, Low Byte.

•
•
• RXSLP7h RX Slope 7, High Byte. RXSLP7l RX Slope 7, Low Byte. RXOFF7h RX Offset 7, High Byte. RXOFF7l RX Offset 7, Low Byte. Calibration Constants (CALn) Default Value 0000 0000 b = 00h Serial Address A6 h Byte Address 74 - 87 = 4A h - 57h These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to these registers.

Micrel, Inc. MIC3002 July 2007 64 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690 Bytes Definition VSLP0h Voltage Slope, High Byte. VSLP0l Voltage Slope, Low Byte. VOFFh Voltage Offset, High Byte. VOFF0l Voltage Offset, Low Byte. ISLP0h Bias Current Slope, High Byte. ISLP0l Bias Current Slope, Low Byte. IOFFh Bias Current Offset, High Byte. IOFF0l Bias Current Offset, Low Byte. TXSLPh TX Power Slope, High Byte. TXSLPl TX Power Slope, Low Byte. TXOFFh TX Power Offset, High Byte. TXOFFl TX Power Offset, Low Byte. Manufacturer ID Register (MFG_ID) Identifies Micrel as the manufacturer of the device. Always returns 2Ah D[7] read only D[6] read only D[5] read only D[4] read only D[3] read only D[2] read only D[1] read only D[0] read only Default Value 0010 1010 b = 2Ah Serial Address A6 h Byte Address 254 = FE h The value in this register, in combination with the DEV_ID register, serve to identify the MIC3002 and its revision number to software. This register is read-only. Bit(s) Function Operation D[7:0] Identifies Micrel as the manufacturer of the device. Always returns 2Ah. Read only. Always returns Ah Device ID Register (DEV_ID) D[7] read only D[6] read only D[5] read only D[4] read only D[3] read only D[2] read only D[1] read only D[0] read only MIC3002 DEVICE ID always reads 0 at D[5-7] and 1 at D[4] DIE REVISION Default Value 0001 xxxx b = 1xh Serial Address A6 h Byte Address 255 = FF h The value in this register, in combination with the MFG_ID regi ster, serve to identify the MIC3002 and its revision number to software. This register is read-only.

Micrel, Inc. MIC3002 July 2007 65 M9999-073107-B hbwhelp@micrel.com or (408) 955-1690

Package Information

24-Pin MLF® (MLF-24) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2007 Micrel, Incorporated.

Product Information

MIC3002GML specifications and overview.

Summary

FOM Management IC with Internal Calibr ation

Description

FOM Management IC with Internal Calibr ation

Source title MIC3002GML Datasheet(PDF) - Micrel Semiconductor

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