MG82F6D17

MG82F6D17 MEGAWIN | Alldatasheet

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Technical content

This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice.  Megawin Technology Co., Ltd. 2021 All rights reserved. 2021/04 version 1.00 MG82F6D17 Datasheet Version: 1.00

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Features

 1-T 80C51 Central Processing Unit  MG82F6D17 with 16K Bytes flash ROM ━ ISP memory zone could be optioned as 0.5KB/1.0KB~7.5KB ━ Flexible IAP size by software configured ━ Code protection for flash memory access ━ Flash write/erase cycle: 20,000 ━ Flash data retention: 100 years at 25°C  Default MG82F6D17 Flash space mapping  AP Flash default mapping (13.5KB, 0000h~35FFh)  IAP Flash default mapping (1.0KB, 3600h~39FFh)  ISP Flash default mapping (1.5KB, 3A00h~3FFFh), ISP Boot code  Data RAM: 1K Bytes ━ On-chip 256 bytes scratch-pad RAM ━ 768 bytes expanded RAM (XRAM) for MG82F6D17 ━ Support page select on XRAM access in MG82F6D17  Dual data pointer  Provide one channel DMA engine ━ P 2 P, M 2 P, P 2 M ━ Memory target: XRAM ━ Peripheral target: UART0, UART1, SPI, TWI0/I2C0, ADC12 & CRC16 ━ Timer 5 and Timer 6 are used for DMA, but it also can be traded as independent timer when DMA not in use  Interrupt controller ━ 16 sources, four-level-priority interrupt capability ━ Three external interrupt inputs, nINT0, nINT1 and nINT2 with glitch filter ━ All external interrupts support High/Low level or Rising/Falling edge trigger  Total 9/11 timers in MG82F6D17 ━ RTC Timer and WDT Timer ━ Timer 0, Timer 1, Timer 2 and Timer 3 ━ PCA0, Program Counter Array 0 ━ S0 BRG and S1 BRG ━ If Timer 2/3 in split mode, total 11 timers  Four 16-bit timer/counters, Timer 0, Timer 1, Timer 2 and Timer 3 ━ X12 mode and timer clock output function ━ Synchronous Run-Enable on all timer (same function on Stop and Reload) ━ New 5 operating modes in Timer 2/3 with 8 clock sources and 8 capture sources ━ Timer 2/3 can be split to two 8-bit timers ━ Clock Count Output (CCO) on T2CKO and T3CKO ━ All timers support PWM mode  One Programmable 16-bit counter/timer Arrays (PCA0) with 8 Compare/PWM modules ━ PCA0 has 6 CCP (Capture/Compare/PWM) modules and 2 CP (Compare/PWM) modules ━ Reloadable 16-bit base counter to support variable length PWM ━ Up to 144 MHz clock source from on-chip CKM ━ Capture mode, 16-bit software timer mode and High speed output mode ━ Buffered capture mode to monitor narrow pulse input ━ Variable 8/10/12/16-bit PWM mode, the PCA can be configured to:  Up to 8 channels un-buffered 10/12/16-bit PWM, or

megawin Version: 1.00 4  Up to 8 channels buffered 2~8-bit PWM, or  Up to 4 channels buffered 9~16-bit PWM ━ PCA0 PWM module 0~5 with dead-time control, break control and central-aligned option  8 Inputs Keypad Interrupt  12-Bit Single-ended ADC ━ Programmable throughput up to 800K sps ━ 8 channel external inputs and one channel internal input (IVR/1.4V) ━ Support window detect function on ADC result ━ Support channel scan mode  Enhanced UART (S0) ━ Framing Error Detection ━ Automatic Address Recognition ━ Max. UART baud rate up to 3.6864MHz/ 6MHz ━ Support SPI Master in Mode 4, up to 12MHz on SPICLK ━ Built-in baud rate generator (S0BRG) to support TX or RX on different baud rate ━ Support LIN bus protocol with auto baud rate detection in mode 5 ━ S0BRG in timer mode cascaded with Timer 0/1 to be a 16/24-bit timer/counter  Secondary UART (S1) ━ Dedicated Baud Rate Generator (S1BRG) shares to S0 or set as an 8-bit timer ━ Max. UART baud rate up to 1.8432/3.0MHz ━ Support SPI Master in Mode 4, up to 12MHz on SPICLK ━ S1BRG in timer mode cascaded with Timer 0/1 to be a 16/24-bit timer/counter  One Master/Slave SPI serial interface ━ Max. 24MHz SPICLK on SPI master ━ Max 12MHz on SPI slave ━ 8 bits data transfer ━ Up to 3 SPI masters including S0/S1 in mode 4 ━ Support daisy-chain function in SPI slave mode  Two Master/Slave two wire serial interfaces: TWI0/ I2C0 and STWI (SI2C) ━ One Master/Slave hardware engine: TWI0/ I2C0 ━ Max. 1MHz on TWI0/ I2C0 master mode and Max. 400KHz on TWI0 slave mode ━ One software TWI/ I2C, STWI/ SI2C, Start/Stop serial interface detection (SID)  Programmable Watchdog Timer (WDT), clock sourced from ILRCO or SYSCLK/12 ━ One time enabled by CPU or power-on ━ Interrupt CPU or Reset CPU on WDT overflow ━ Support WDT function in power down mode (watch mode) for auto-wakeup function  Real-Time-Clock (RTC) module, clock sourced from ILRCO, WDTPS, WDTOF, SYSCLK or SYSCLK/12 ━ Programmable interrupt period from mini-second wakeup to minute wakeup ━ 21-bit length system timer  Beeper function  General purpose logic (GPL/CRC) ━ Bit order reversed function ━ 16-bit CRC engine (CCITT-16 polynomial) ━ Support automatic CRC of flash content ━ Programmable initial seed function of CRC  On-Chip-Debug interface (OCD) ━ MG82F6D17AS8 SOP8 not support OCD  Maximum 17 GPIOs in 20-pin package ━ P3 can be configured to quasi-bidirectional, push-pull output, open-drain output and input only ━ P0, P1, P2, P4 and P6 can be configured to open-drain output or push-pull output

megawin Version: 1.00 5 ━ P4.7 shared with RST ━ Programmable GPIO driving strength and driving speed ━ On chip pull-up enabled on each pin  Clock Sources ━ Internal 12MHz/11.059MHz oscillator (IHRCO): factory calibrated to ±1%, typical ━ Internal Low power 32KHz RC Oscillator (ILRCO) ━ External clock input (ECKI) on P6.0, up to 25MHz ━ Internal RC Oscillator output on P6.0 ━ On-chip Clock Multiplier (CKM) to provide high speed clock source (144 MHz)  Two Brown-Out Detectors ━ BOD0: detect 1.7V ━ BOD1: selected detection level on 4.2V/3.7V/2.4V/2.0V ━ Interrupt CPU or reset CPU ━ Wake up CPU in Power-Down mode (BOD1)  Multiple power control modes: idle mode, power-down mode, slow mode, sub-clock mode, RTC mode, watch mode and monitor mode. ━ All interrupts can wake up IDLE mode ━ 12(13) sources with 16 pins to wake up Power-Down mode ━ Slow mode and sub-clock mode support low speed MCU operation ━ RTC mode supports RTC to resume CPU in power down ━ Watch mode supports WDT to resume CPU in power down ━ Monitor mode supports BOD1 to resume CPU in power down  Operating voltage range: 1.8V – 5.5V ━ Minimum 1.8V requirement in flash write operation (ISP/IAP/ICP)  Operation frequency range: 32 (max) ━ External clock input mode, 0 – 12MHz @ 2.0V – 5.5V, 0 – 25MHz @ 2.4V – 5.5V ━ CPU up to 12MHz @ 1.8V – 5.5V, and up to 25MHz @ 2.2V – 5.5V ━ CPU up to 36MHz @ 2.7V -5.5V with on-chip CKM  16-Bytes Unique ID code  Operating Temperature: ━ Industrial (-40°C to +105°C)*  Package Types: ━ SOP8 (150 mil): MG82F6D17AS8 (16K) ━ SSOP20 (150 mil): MG82F6D17AL20 (16K) ━ TSSOP20 (173 mil): MG82F6D17AT20 (16K) ━ QFN20 (3 x 3 x 0.55 mm): MG82F6D17AZ20 (16K) *: Tested by sampling.

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megawin Version: 1.00 17 List of Tables

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megawin Version: 1.00 19 1. General Description The MG82F6D17 is a single -chip microcontroller based on a high performance 1- T architecture 80C51 CPU that executes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device), and has an 8051 compatible instruction set. Therefore at the same performance as the standard 8051, the MG82F6D17 can operate at a much lower speed and thereby greatly reduce the power consumption. The MG82F6D17 has 16K bytes of embedded Flash memory for code and data. The Flash memory can be programmed either in serial writer mode (via ICP , In-Circuit Programming) or in In-System Programming mode. And, it also provides the In- Application Programming (IAP) capability. ICP and ISP allow the user to download new code without removing the microcontroller from the actual end product; IAP means that the device can write non-volatile data in the Flash memory while the application program is running. There needs no external high voltage for programming due to its built-in charge-pumping circuitry. The MG82F6D17 retains all features of the standard 80C52 with 256 bytes of scratch-pad RAM, two external interrupts, a multi-source 4-level interrupt controller, a serial port (UART0) and three timer/counters. In addition, the MG82F6D17 has17 I/O port pins, one XRAM of 768 bytes, one extra external interrupts with High/low trigger option, 800KHz 12-bit ADC, one 16-bit timer, one 8-channel PCA with dead-time controlled PWM, one 8-bit SPI, two TWI/ I2C (TWI0/ I2C0 and STWI/ SI2C), secondary serial port (UART1), keypad interrupt, Watchdog Timer, Real-Time-Clock module, two Brown-out Detectors, an ECKI external clock input (P6.0), an internal high precision oscillator (IHRCO), an on-chip clock multiplier (CKM) to generate high speed clock source, an internal low speed RC oscillator (ILRCO) and an enhanced serial function in UART0 that facilitates multiprocessor communication, LIN bus mode and a speed improvement mechanism (X2/X4 mode). Support 3 different DMA transfer types, M2P (XRAM to Peripheral), P2M (Peripheral to XRAM) and P2P (Peripheral to Peripheral) to enhance transfer performance and reduce CPU loading. The MG82F6D17 has multiple operating modes to reduce the power consumption: idle mode, power down mode, slow mode, sub- clock mode, RTC mode, watch mode and monitor mode. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the Power -Down mode the RAM and SFRs’ value are saved and all other functions are inoperative; most importantly, in the Power-down mode the device can be waked up by many interrupt or reset sources. In slow mode, the user can further reduce the power consumption by using the 8 -bit system clock pre- scaler to slow down the operating speed. Or select sub -clock mode which clock source is derived from internal low speed oscillator (ILRCO) for CPU to perform an ultra -low speed operation. The RTC module supports Real-Time-Clock function in all operating modes. In watch mode, it keeps WDT running in power -down or idle mode and resumes CPU as an auto- wakeup timer when WDT overflows. Monitor mode provides the Brown- Out detection in power down mode and resumes CPU when chip VDD reaches the specific detection level. Additionally, the MG82F6D17 is equipped with the Megawin proprietary On-Chip Debug (OCD) interface for In-Circuit Emulator (ICE). The OCD interface provides on-chip and in-system non-intrusive debugging without any target resource occupied. Several operations necessary for an ICE are supported such as Reset, Run, Stop, Step, Run to Cursor and Breakpoint Setting. The user has no need to prepare any development board during firmware developing or the socket adapter used in the traditional ICE probe head. All the thing the user needs to do is to prepare a connector for the dedicated OCD interface. This powerful feature makes the developing very easy for any user.

megawin Version: 1.00 20 2. Block Diagram Figure 2–1. Block Diagram

8051 CPU (1T)

256 X 8

768 X 8

(LIN) Timer 0 Timer 1 Timer 2 PCA0 Timer Port 1 Port 2 Port 3 Port 4 Ext. INT (P4.5) nINT0 (P3.3) nINT1 (P4.4) nINT2 (P3.4) T0/T0CKO (P3.5) T1/T1CKO (P1.0) T2/T2CKO (P3.0) RXD0 (P3.1) TXD0 P1.0~P1.1 P1.5~P1.7 P2.2, P2.4 P3.0~P3.1 P3.3~P3.5 P4.4,P4.5 P4.7 (P6.0) ICKO/ECKI (P1.1) T2EX (P4.4) ECI ISP/IAP 12-bit ADC 800K sps CEX0~CEX7 AIN0~AIN7 Keypad Int. KBI0~KBI7 OCD_SCL (P4.4) OCD_SDA (P4.5) OCD/ICP Interface SPI (P3.3) nSS (P1.5) MOSI (P1.6) MISO (P1.7) SPICLK TWI0 (P3.1) TWI0_SCL (P3.0) TWI0_SDA IHRCO 12MHz/ 11.059M ILRCO 32KHz Port 6 P6.0~P6.1 STWI (SID) (nINT1) STWI_SCL (S0MI) STWI_SDA BOD0 BOD1 VDD WDT RST (P4.7) RTC (P1.6) S0MI IVR 1.4V Timer 3 UART1 DMA GPL/CRC16 (P3.3) T3/T3CKO (P3.4) T3EX (P1.0) RXD1 (P1.1) TXD1 (P6.1) S1MI Timer 5 Timer 6 T5 (P3.4) T6 (P3.5)

megawin Version: 1.00 21 3. Special Function Register 3.1. SFR Map (Page 0~F) *: User needs to set SFRPI as SFRPI=0x00 ~ 0x0F for SFR page access. （MCU will not keep SFRPI value in interrupt. User need to keep SFRPI value in software flow.） F8 0 P6 CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H CCAP5H 1 CCAP6H CCAP7H F0 0 B PAOE PCAPWM0 PCAPWM1 PCAPWM2 PCAPWM3 PCAPWM4 PCAPWM5 1 PCAPWM6 PCAPWM7 E8 0 P4 CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L CCAP5L 1 CCAP6L CCAP7L E0 0

1 ACC WDTCR IFD IFADRH IFADRL IFMT SCMD ISPCR

D8 0 CCON CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 CCAPM5 1 CCAPM6 CCAPM7 D0 0

1 PSW SIADR SIDAT SISTA SICON KBPATN KBCON KBMASK

0 T2CON T2MOD RCAP2L RCAP2H TL2 TH2

CLRL CHRL 1 T3CON T3MOD RCAP3L RCAP3H TL3 TH3

3 T5CON -- TLR5 THR5 TL5 TH5

4 T6CON -- TLR6 THR6 TL6 TH6

1 XICFG1 ADCFG1

3 ADCFG3

4 ADCFG4

5 ADCFG5

S0CR1 -- -- PWMCR CRC0DA RTCCR -- 1 PDTCRA P3 P3M0 P3M1 P4M0 -- -- RTCTM IP0H 1 -- -- P6M0 2 -- PDRVC0 -- 3 -- PDRVC1 -- A8 0

1 IE SADDR -- -- SFRPI EIE1 EIP1L EIP1H

1 AUXR4

2 AUXR5

3 AUXR6

4 AUXR7

5 AUXR8

6 AUXR9

7 AUXR10

8 AUXR11

98 0 S0CON S0BUF S0BRT S0BRC S0CFG S0CFG1

1 S1CON S1BUF S1BRT S1BRC S1CFG

1 P2M1 T2MOD1 DMACR0 TREN0

2 P4M1 T3MOD1 DMACR0 TRLC0

3 P6M1 -- DMACR0 TSPC0

7 P3FDC -- DMACR0 --

8 P1FDC -- DMACG0 --

9 P2FDC -- DMADS0 --

1 TCON TMOD TL0 TL1 TH0 TH1 SFIE XRPS

1 -- SP DPL DPH SPSTAT SPCON SPDAT PCON0

megawin Version: 1.00 22 SFRPI: SFR Page Index Register SFR Page = 0~F SFR Address = 0xAC RESET = xxxx-0000 7 6 5 4 3 2 1 0 -- -- -- -- IDX3 IDX2 IDX1 IDX0 W W W W R/W R/W R/W R/W Bit 7~4: Reserved. Software must write “0” on these bits when SFRPI is written. Bit 3~0: SFR Page Index. PIDX[3:0] Selected Page

0000 Page 0

0001 Page 1

0010 Page 2

0011 Page 3

…… …… …… …… …… ……

1111 Page F

megawin Version: 1.00 23 3.2. SFR Bit Assignment (Page 0~F) Table 3–1. SFR Bit Assignment (Page 0~F) SYMBOL DESCRIPTION ADDR (HEX) PAGE (HEX) BIT ADDRESS AND SYMBOL RESET VALUE Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 SPSTAT SPI Status Register 84 0-F SPIF WCOL THRF SPIBSY MODF -- -- SPR2 00000xx0 SPCON SPI Control Register 85 0-F SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 00000100 PCON0 Power Control 0 87 0-F SMOD1 SMOD0 GF POF0 GF1 GF0 PD IDL 00010000 TCON Timer Control 88 0-F TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 TMOD Timer Mode 89 0-F T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00000000 SFIE System Flag INT En. 8E 0-F SIDFIE -- -- RTCFIE -- BOF1IE BOF0IE WDTFIE 0000x000 XRPS XRAM Page Select 8F 0-F -- -- -- -- -- -- .1 .0 xxxxx000 P2M1 P2 Mode Register 1 92 1 -- -- -- P2M1.4 -- P2M1.2 -- -- 11111111 P4M1 P4 Mode Register 1 92 2 P4M1.7 -- P4M1.5 P4M1.4 -- -- -- -- 11111111 P6M1 P6 Mode Register 1 92 3 -- -- -- -- -- -- P6M1.1 P6M1.0 11111111 P2FDC P2 Fast Drv. Ctrl. 92 9 -- -- -- .4 -- .2 -- -- 00000000 T2MOD1 Timer2 mode 1 Reg. 93 1 TL2CS TF2IG TL2IS T2CKS T2MS1 CP2S2 CP2S1 CP2S0 00000000 T3MOD1 Timer3 mode 1 Reg. 93 2 TL3CS TF3IG -- T3CKS T3MS1 CP3S2 CP3S1 CP3S0 00x00000 DMACR0 DMA Control Reg. 0 94 0-7 -- -- -- -- DMAE0 DMAS0 DIE0 DCF0 xxx00000 DMACG0 DMA Configured Reg. 0 94 8 PDMAH PDMAL CRCW0 0 EXTS10 EXTS00 FAEN0 LOOP0 00000000 DMADS0 DMA Data path Selection 0 94 9 DSS30 DSS20 DSS10 DSS00 DDS30 DDS20 DDS10 DDS00 00000000 P2M0 P2 Mode Register 0 95 0 -- -- -- P2M0.4 -- P2M0.2 -- -- 00000000 TREN0 Timer Run Enable Register 0 95 1 -- TR3LE TR2LE -- TR3E TR2E TR1E TR0E x00x0000 TRLC0 Timer Reload Control Register 0 95 2 -- TL3RLC TL2RLC -- T3RLC T2RLC T1RLC T0RLC x00x0000 TSPC0 Timer Stop Control Register 0 95 3 -- TL3SC TL2SC -- T3SC T2SC T1SC T0SC x00x0000 PCON1 Power Control 1 97 0-F SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF 0000x000 S0CON Serial 0 Control 98 0 SM00 /FE SM10 SM20 REN0 TB80 RB80 TI0 RI0 00000000 S1CON Serial 1 Control 98 1 SM01 SM11 SM21 REN1 TB81 RB81 TI1 RI1 00000000 S0CFG S0 Configuration 9C 0 URTS SMOD2 URM0X3 SM30 S0DOR BTI UTIE SMOD3 00001000 S1CFG S1 Configuration 9C 1 SM31 S1M0X3 S1DOR S1TR S1MOD1 S1TX12 S1CKOE S1TME 00100000 S0CFG1 S0 Configuration 1 (LINCFG) 9D 0 SBF0 TXER0 S0SB16 ATBR0 TXRX0 SYNC0 -- -- 000000xx AUXR0 Auxiliary Register 0 A1 0-F P60OC1 P60OC0 P60FD PBKF -- -- INT1H INT0H 00000000 AUXR1 Auxiliary Register 1 A2 0-F -- -- CRCDS1 CRCDS0 -- -- -- DPS 00000000 AUXR2 Auxiliary Register 2 A3 0-F STAF STOF -- -- T1X12 T0X12 T1CKOE T0CKOE 00000000 AUXR3 Auxiliary Register 3 A4 0 T0PS1 T0PS0 BPOC1 BPOC0 S0PS0 TWIPS1 TWIPS0 T0XL 00000000 AUXR4 Auxiliary Register 4 A4 1 T2PS1 T2PS0 T1PS1 T1PS0 -- -- -- -- 00000000 AUXR5 Auxiliary Register 5 A4 2 C0IC4S0 C0IC2S0 C0PPS1 C0PPS0 -- C0PS0 ECIPS0 C0COPS 00000000 AUXR6 Auxiliary Register 6 A4 3 KBI4PS1 KBI4PS0 KBI6PS0 KBI2PS0 T3FCS T2FCS SnMIPS S0COPS 00000000 AUXR7 Auxiliary Register 7 A4 4 POE5 POE4 C0CKOE SPI0M0 -- -- -- -- 11000000 AUXR8 Auxiliary Register 8 A4 5 POE7 POE6 C0PPS2 -- KBI0PS0 S1COPS -- -- 11000000 AUXR9 Auxiliary Register 9 A4 6 -- -- T1G1 T0G1 C0FDC1 C0FDC0 S1PS1 S1PS0 00000000 AUXR10 Aux. Register 10 A4 7 -- -- -- SPIPS0 S0PS1 -- TWICF PAA 00000000 AUXR11 Aux. Register 11 A4 8 P30AM -- -- -- -- -- C0M0 C0OFS 00000000 EIE2 Extended INT Enable 2 A5 0-F -- -- -- -- -- -- -- ET3 xxxxxxx0

megawin Version: 1.00 24 SYMBOL DESCRIPTION ADDR (HEX) PAGE (HEX) BIT ADDRESS AND SYMBOL RESET VALUE Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 EIP2L Ext. INT Priority 2 Low A6 0-F -- -- -- -- -- -- -- PT3L xxxxxxx0 EIP2H Ext. INT Priority 2 High A7 0-F -- -- -- -- -- -- -- PT3H xxxxxxx0 IE Interrupt Enable A8 0-F EA EDMA ET2 ES0 ET1 EX1 ET0 EX0 00000000 SFRPI SFR Page Index AC 0-F -- -- -- -- IDX3 IDX2 IDX1 IDX0 xxx00000 EIE1 Extended INT Enable 1 AD 0-F -- ETWI0 EKB ES1 ESF EPCA EADC ESPI 00000000 EIP1L Ext. INT Priority 1 Low AE 0-F -- PTWI0L PKBL PS1L PSFL PPCAL PADCL PSPIL 00000000 EIP1H Ext. INT Priority 1 High AF 0-F -- PTWI0H PKBH PS1H PSFH PPCAH PADCH PSPIH 00000000 P4M0 P4 Mode Register 0 B3 0 P4M0.7 -- P4M0.5 P4M0.4 -- -- -- -- 10110000 PDRVC0 Port Driving Control 0 B4 2 P3DC1 P3DC0 P2DC1 P2DC0 P1DC1 P1DC0 -- -- 00000000 PDRVC1 Port Driving Control 1 B4 3 -- -- -- -- -- -- P4DC1 -- xxx0xx00 P6M0 P6 Mode Register 0 B5 1 -- -- -- -- -- -- P6M0.1 P6M0.0 00000000 RTCTM RTC Timer Register B6 0-F RTCCS1 RTCCS0 RTCCT5 RTCCT4 RTCCT3 RTCCT2 RTCCT1 RTCCT0 01111111 IP0H Interrupt Priority 0 High B7 0-F -- PX2H PT2H PSH PT1H PX1H PT0H PX0H 00000000 IP0L Interrupt Priority Low B8 0-F -- PX2L PT2L PSL PT1L PX1L PT0L PX0L 00000000 S0CR1 S0 Control 1 B9 0-F S0TR S0TX12 S0TCK S0RCK S0CKOE ARTE -- -- 00000000 PDTCRA PWM Dead-Time RTCCR RTC Control Reg. BE 0-F RTCE RTCO RTCRL5 RTCRL4 RTCRL3 RTCRL2 RTCRL1 RTCRL0 00111111 XICON External INT Control C0 0-F -- -- -- -- INT2H EX2 IE2 IT2 xxxx0000 XICFG Ext. INT. Configured C1 0 INT1IS1 INT1IS0 INT0IS1 INT0IS0 -- X2FLT X1FLT X0FLT 00000000 XICFG1 Ext. INT. Configured 1 C1 1 INT1IS2 INT0IS2 INT2IS1 INT2IS0 -- X2FLT1 X1FLT1 X0FLT1 00000000 ADCFG0 ADC Configuration 0 C3 0 ADCKS2 ADCKS1 ADCKS0 ADRJ ACHS SMPF ADTM1 ADTM0 00000000 ADCFG1 ADC Configuration 1 C3 1 IGADCI EADCWI SMPFIE SIGN AOS.3 AOS.2 AOS.1 AOS.0 00000000 ADCFG3 ADC Configuration 3 C3 3 ADPS1 ADPS0 -- -- ARES1 ARES0 ADES0 -- 010000xx ADCFG4 ADC Configuration 4 C3 4 -- ADWM0 ADTM3 ADTM2 -- -- DBSD -- 0000xx00 ADCFG11 ADC Configuration 11 C3 B WHB.3 WHB.2 WHB.1 WHB.0 1 1 1 1 11111111 ADCFG13 ADC Configuration 13 C3 D WLB.3 WLB.2 WLB.1 WLB.0 0 0 0 0 00000000 ADCON0 ADC Control 0 C4 0-F ADCEN ADCWI -- ADCI ADCS CHS2 CHS1 CHS0 0x000000 ADCDL ADC Data Low C5 0-F ADCV.3 ADCV.2 ADCV.1 ADCV.0 -- -- -- -- 0000xxxx CKCON0 Clock Control 0 C7 0-F AFS ENCKM CKMIS1 CKMIS0 CCKS SCKS2 SCKS1 SCKS0 00010000 T2CON Timer 2 Control Reg. C8 0 TF2 EXF2 RCLK/ TF2L TCLK/ TL2IE EXEN2 TR2 C/T2 CP/RL2 00000000 T3CON Timer 3 Control Reg. C8 1 TF3 EXF3 TF3L TL3IE EXEN3 TR3 C/T3 CP/RL3 00000000 T5CON Timer 5 Control Reg. C8 3 TF5 -- T5CKS1 T5CKS0 T5IE TR5 T5GAT1 T5GAT0 00000000 T6CON Timer 6 Control Reg. C8 4 TF6 -- T6CKS1 T6CKS0 T6IE TR6 T6GAT1 T6GAT0 00000000 T2MOD Timer 2 mode Reg. C9 0 T2SPL TL2X12 T2EXH T2X12 TR2L TR2LC T2OE T2MS0 00000000 T3MOD Timer 3 mode Reg. C9 1 T3SPL TL3X12 T3EXH T3X12 TR3L TR3LC T3OE T3MS0 00000000 PSW Program Status Word D0 0-F CY AC F0 RS1 RS0 OV F1 P 00000000

megawin Version: 1.00 25 SYMBOL DESCRIPTION ADDR (HEX) PAGE (HEX) BIT ADDRESS AND SYMBOL RESET VALUE Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 SICON TWI0 Control Reg. D4 0-F CR2 ENSI STA STO SI AA CR1 CR0 00000000 KBCON Keypad Control D6 0-F KBCS1 KBCS0 KBES -- -- -- PATN_ SEL KBIF 00000001 CCON PCA Control Reg. D8 0-F CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 00000000 CMOD PCA Mode Reg. D9 0-F CIDL BME4 BME2 BME0 CPS2 CPS1 CPS0 ECF 00000000 CCAPM0 PCA Module0 Mode DA 0 DTE0 ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 00000000 CCAPM6 PCA Module6 Mode DA 1 BME6 ECOM6 -- CAPN6 MAT6 TOG6 PWM6 ECCF6 00xx0000 CCAPM1 PCA Module1 Mode DB 0 -- ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x0000000 CCAPM7 PCA Module7 Mode DB 1 -- ECOM7 -- CAPN7 MAT7 TOG7 PWM7 ECCF7 x0xx0000 CCAPM2 PCA Module2 Mode DC 0-F DTE2 ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 00000000 CCAPM3 PCA Module3 Mode DD 0-F -- ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 x0000000 CCAPM4 PCA Module4 Mode DE 0-F DTE4 ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 00000000 CCAPM5 PCA Module5 Mode DF 0-F -- ECOM5 CAPP5 CAPN5 MAT5 TOG5 PWM5 ECCF5 x0000000 WDTCR WDT Control register E1 0-F WREN NSW ENW CLRW WIDL PS2 PS1 PS0 00000000 ISPCR ISP Control Register E7 0-F ISPEN SWBS SRST CFAIL -- -- -- -- 00000xxx PAOE PWM Additional Output Enable F1 0-F POE3 POE2B POE2A POE2 POE1 POE0B POE0A POE0 10011001 PCAPWM0 PCA PWM0 Mode F2 0 P0RS1 P0RS0 -- -- -- P0INV ECAP0H ECAP0L 00xxx000 PCAPWM6 PCA PWM6 Mode F2 1 P6RS1 P6RS0 -- -- CCF6 P6INV ECAP6H ECAP6L 00xx0000 PCAPWM1 PCA PWM1 Mode F3 0 P1RS1 P1RS0 -- -- -- P1INV ECAP1H ECAP1L 00xxx000 PCAPWM7 PCA PWM7 Mode F3 1 P7RS1 P7RS0 -- -- CCF7 P7INV ECAP7H ECAP7L 00xx0000 PCAPWM2 PCA PWM2 Mode F4 0-F P2RS1 P2RS0 -- -- -- P2INV ECAP2H ECAP2L 00xxx000 PCAPWM3 PCA PWM3 Mode F5 0-F P3RS1 P3RS0 -- -- -- P3INV ECAP3H ECAP3L 00xxx000 PCAPWM4 PCA PWM4 Mode F6 0-F P4RS1 P4RS0 -- -- -- P4INV ECAP4H ECAP4L 00xxx000 PCAPWM5 PCA PWM5 Mode F7 0-F P5RS1 P5RS0 -- -- -- P5INV ECAP5H ECAP5L 00xxx000 CCAP0H PCA Module0 capture CCAP6H PCA Module6 capture CCAP1H PCA Module1 capture CCAP7H PCA Module7 capture CCAP2H PCA Module2 capture CCAP3H PCA Module3 capture CCAP4H PCA Module4 capture CCAP5H PCA Module5 capture

megawin Version: 1.00 26 3.3. Auxiliary SFR Map (Page P) MG82F6D17 has an auxiliary SFR page which is indexed by page P and the SFRs’ write is a different way from standard 8051 SFR page. The registers in auxiliary SFR map are addressed by IFMT and SCMD like ISP/IAP access flow. Page P has 256 bytes space that can target to 11 physical bytes and 6 logical bytes. IAPLB, CKCON2, CKCON3, CKCON4, CKCON5, PCON2, PCON3, SPCON0, DCON0, RTCTM and RTCCR. The 6 logical bytes include PCON0, PCON1, CKCON0, WDTCR, P4 and P6. Access on the 6 logical bytes gets the coherence content with the same SFR in Page 0~F. Please refer Section “29 Page P SFR Access” for more detail information. Table 3–2. Auxiliary SFR Map (Page P) 50 -- -- -- -- RTCCR RTCTM -- --

48 SPCON0 -- -- -- DCON0 -- -- --

40 CKCON2 CKCON3 CKCON4 CKCON5 PCON2 PCON3 -- --

megawin Version: 1.00 27 3.4. Auxiliary SFR Bit Assignment (Page P) Table 3–3. Auxiliary SFR Bit Assignment (Page P) SYMBOL DESCRIPTION ADDR BIT ADDRESS AND SYMBOL RESET VALUE Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Physical Bytes IAPLB IAP Low Boundary 03H IAPLB6 IAPLB5 IAPLB4 IAPLB3 IAPLB2 IAPLB1 IAPLB0 0 CKCON2 Clock Control 2 40H -- -- -- IHRCOE MCKS1 MCKS0 OSCS1 OSCS0 0001-0000 CKCON3 Clock Control 3 41H WDTCS1 WDTCS0 FWKP WDTFS MCKD1 MCKD0 -- -- 00000000 CKCON4 Clock Control 4 42H RCSS2 RCSS1 RCSS0 RPSC2 RPSC1 RPSC0 RTCCS3 RTCCS2 00000000 CKCON5 Clock Control 5 43H -- -- -- -- -- -- -- CKMS0 00000000 PCON2 Power Control 2 44H AWBOD1 0 BO1S1 BO1S0 BO1RE EBOD1 BO0RE 1 0000x1x1 PCON3 Power Control 3 45H IVREN 0 0 0 0 0 0 0 00000000 SPCON0 SFR Page Control 0 48H -- P6CTL P4CTL WRCTL -- CKCTL0 PWCTL1 PWCTL0 00000000 DCON0 Device Control 0 4CH HSE IAPO HSE1 -- -- IORCTL RSTIO OCDE 100xx011 RTCCR RTC Control Reg. 54H RTCE RTCO RTCRL5 RTCRL4 RTCRL3 RTCRL2 RTCRL1 RTCRL0 00111111 RTCTM RTC Timer Register 55H RTCCS1 RTCCS0 RTCCT5 RTCCT4 RTCCT3 RTCCT2 RTCCT1 RTCCT0 01111111 Logical Bytes PCON0 Power Control 0 87H SMOD1 SMOD0 GF POF0 GF1 GF0 PD IDL 00010000 PCON1 Power Control 1 97H SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF 0000x000 CKCON0 Clock Control 0 C7H AFS ENCKM CKMIS1 CKMIS0 CCKS SCKS2 SCKS1 SCKS0 00010000 WDTCR Watch-dog-timer Control register E1H WREN NSW ENW CLRW WIDL PS2 PS1 PS0 00000000 P4 Port 4 E8H P4.7 -- P4.5 P4.4 -- -- -- -- 1x11xx11 P6 Port 6 F8H -- -- -- -- -- -- P6.1 P6.0 xxxxxx11 Sample Code of Page-P SFR write： IFADRH = 0x00; ISPCR = ISPEN; //enable IAP/ISP IFMT = MS2; // Page-P write，IFMT =0x04 IFADRL = SPCON0; //Set Page-P SFR address IFD |= CKCTL0; // set CKCTL0 SCMD = 0x46; // SCMD = 0xB9; // IFMT = Flash_Standby; // IAP/ISP standby，IFMT =0x00 ISPCR &= ~ISPEN;

megawin Version: 1.00 29 4.2. Pin Description Table 4–1. Pin Description MNEMONIC PIN NUMBER I/O TYPE DESCRIPTION 20-Pin SSOP 20-Pin TSSOP 20-Pin QFN 8-Pin SOP P1.0 (AIN0) (KBI0) (T2) (T2CKO) (RXD1) 6 6 4 I/O * Port 1.0. * AIN0: ADC channel-0 analog input. * KBI0: keypad input 0. * T2: Timer/Counter 2 external clock input. * T2CKO: Timer 2 programmable clock output. * RXD1: UART1 serial input port. P1.1 (AIN1) (KBI1) (T2EX) (TXD1) 7 7 5 I/O * Port 1.1. * AIN1: ADC channel-1 analog input. * KBI1: keypad input 1. * T2EX: Timer/Counter 2 external control input. * TXD1: UART1 serial output port. P1.5 (AIN5) (KBI5) (MOSI) 8 8 6 I/O * Port 1.5. * AIN5: ADC channel-5 analog input. * KBI5: keypad input 5. * MOSI: SPI master out & slave in. P1.6 (AIN6) (KBI6) (MISO) (S0MI) (PWM0A) 9 9 7 I/O * Port 1.6. * AIN6: ADC channel-6 analog input. * KBI6: keypad input 6. * MISO: SPI master in & slave out. * S0MI: Serial Port 0 SPI Master mode data Input. * PWM0A: PCA PWM0 output sub-channel A. P1.7 (AIN7) (KBI7) (SPICLK) (CEX4) (PWM0B) 10 10 8 I/O * Port 1.7. * AIN7: ADC channel-7 analog input. * KBI7: keypad input 7. * SPICLK: SPI clock, output for master and input for slave. * CEX4: PCA0 module-4 external I/O. * PWM0B: PCA0 PWM0 output sub-channel B. P2.2 (AIN2) (CEX0) 11 11 9 I/O * Port 2.2. * AIN2: ADC channel-2 analog input. * CEX0: PCA0 module-0 external I/O. P2.4 (AIN3) (CEX2) 12 12 10 I/O * Port 2.4. * AIN3: ADC channel-3 analog input. * CEX2: PCA0 module-2 external I/O. P3.0 (AIN4) (RXD0) (KBI2) (TWI0_SDA) 13 13 11 4 I/O * Port 3.0. * AIN4: ADC channel-4 analog input. * RXD0 : UART0 serial input port. * KBI2: keypad input 2. * TWI0_SDA: serial data of TWI0/ I2C0. P3.1 (TXD0) (KBI3) (TWI0_SCL) 14 14 12 5 I/O * Port 3.1. * TXD0 : UART0 serial output port. * KBI3: keypad input 3. * TWI0_SCL: serial clock of TWI0/ I2C0. P3.3 (nINT1) (KBI4) (CEX1) (nSS) (T3) (T3CKO) 15 15 13 6 I/O * Port 3.3. * nINT1: external interrupt 1 input. * KBI4: keypad input 4. * CEX1: PCA0 module-1 external I/O. * nSS: SPI Slave select. * T3: Timer/Counter 3 external clock input. * T3CKO: Timer 3 programmable clock output. P3.4 (T0) (T0CKO) (CEX3) (T3EX) (T5) 16 16 14 I/O * Port 3.4. * T0: Timer/Counter 0 external input. * T0CKO: Timer 0 programmable clock output. * CEX3: PCA0 module-3 external I/O. * T3EX: Timer/Counter 3 external control input. * T5: Timer/Counter 5 external clock input.

megawin Version: 1.00 30 MNEMONIC PIN NUMBER I/O TYPE DESCRIPTION 20-Pin SSOP 20-Pin TSSOP 20-Pin QFN 8-Pin SOP P3.5 (T1) (T1CKO) (CEX5) (T6) 17 17 15 I/O * Port 3.5. * T1: Timer/Counter 1 external input. * T1CKO: Timer 1 programmable clock output. * CEX5: PCA0 module-5 external I/O. * T6: Timer/Counter 6 external clock input. P4.4 (OCD_SCL) (nINT2) (BEEP) (ECI) 19 19 17 7 I/O * Port 4.4. * OCD_SCL: OCD interface, serial clock. (Need to disable by firmware of MG82F6D17AS8 SOP8) * nINT2: external interrupt 2 input. * BEEP: Beeper output. * ECI: PCA external clock input. P4.5 (OCD_SDA) (nINT0) (RTCKO) 20 20 18 8 I/O * Port 4.5. * OCD_SDA: OCD interface, serial data. (Need to disable by firmware of MG82F6D17AS8 SOP8) * nINT0: external interrupt 0 input. * RTCKO: RTC programmable clock output. P6.0 (ECKI) (ICKO) (PWM6) (PWM2A) 2 2 20 I/O I O * Port 6.0. * ECKI: In external clock input mode, this is clock input pin. * ICKO: Internal Clock (MCK) Output. * PWM6: PCA0 module-6 PWM6 output. * PWM2A: PCA0 PWM2 output sub-channel A. P6.1 (S1MI) (PWM7) (PWM2B) 1 1 19 I/O * Port 6.1. * S1MI: Serial Port 1 SPI Master mode data Input. * PWM7: PCA0 module-7 PWM7 output. * PWM2B: PCA0 PWM2 output sub-channel B. RST (P4.7) (C0CKO) (S0CKO) (S1CKO) 18 18 16 I I/O * RST: External RESET input, high active. * Port 4.7. * C0CKO: Programmable clock output of PCA base counter. * S0CKO: S0BRT programmable clock output. * S1CKO: S1BRG programmable clock output. VDD 5 5 3 3 P Power supply input. VSS 3 3 1 1 G Ground, 0 V reference.

megawin Version: 1.00 31 4.3. Alternate Function Redirection Many I/O pins, in addition to their normal I/O function, also serve the alternate function for internal peripherals. For the digital peripherals, all GPIOs serve the alternate function in the default state. However, the user may set the corresponding control bits in AXUR0~AUXR3 to serve their alternate function on the relocated ports. AUXR0: Auxiliary Register 0 SFR Page = 0~F SFR Address = 0xA1 RESET = 0000-0000 7 6 5 4 3 2 1 0 P60OC1 P60OC0 P60FD PBKF -- -- INT1H INT0H R/W R/W R/W R/W W W R/W R/W Bit 7~6: P6.0 function configured control bit 1 and 0. The two bits only act when internal RC oscillator (IHRCO or ILRCO) is selected for system clock source. In external clock input mode, P6.0 is the dedicated clock input pin. In internal oscillator condition, P6.0 provides the following selections for GPIO or clock source generator. When P60OC[1:0] index to non-P6.0 GPIO function, P6.0 will drive the on-chip RC oscillator output to provide the clock source for other devices. P60OC[1:0] P60 function I/O mode 00 P60 By P6M0.0 01 MCK By P6M0.0 10 MCK/2 By P6M0.0 11 MCK/4 By P6M0.0 Please refer Section “9 System Clock” to get the more detailed clock information. For clock-out on P6.0 function, it is recommended to set P6M0.0 to “1” which selects P6.0 as push-push output mode. Bit 5: P60FD, P6.0 Fast Driving. 0: P6.0 output with default driving. 1: P6.0 output with fast driving enabled. If P6.0 is configured to clock output, enable this bit when P6.0 output frequency is more than 12MHz at 5V application or more than 6MHz at 3V application. AUXR3: Auxiliary Register 3 SFR Page = 0 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T0PS1 T0PS0 BPOC1 BPOC0 S0PS0 TWIPS1 TWIPS0 T0XL R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: T0PS1~0, Timer 0 Port pin Selection [1:0]. T0PS1~0 T0/T0CKO 00 P3.4 01 P4.4 10 P2.2 11 P1.7 Bit 3: S0PS0, Serial Port 0 pin Selection 0. (Add new S0PS1 at AUXR10.3) S0PS1~0 RXD0 TXD0 00 P3.0 P3.1 01 P4.4 P4.5 10 P3.1 P3.0 11 P1.7 P2.2 Bit 2~1: TWIPS1~0, TWI0/I2C0 Port pin Selection [1:0]. TWIPS1~0 TWI0_SCL TWI0_SDA 00 P3.1 P3.0 01 P6.0 P6.1 10 P3.0 P3.1 11 P2.2 P2.4

megawin Version: 1.00 32 AUXR4: Auxiliary Register 4 SFR Page = 1 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T2PS1 T2PS0 T1PS1 T1PS0 -- -- -- -- R/W R/W R/W R/W W W W W Bit 7~6: T2PS1~0, Timer 2 Port pin Selection [1:0]. T2PS1~0 T2/T2CKO T2EX 00 P1.0 P1.1 01 P3.0 P3.1 10 P6.0 P3.5 11 P4.5 P4.4 Bit 5~4: T1PS1~0, Timer 1 Port pin Selection [1:0]. T1PS1~0 T1/T1CKO 00 P3.5 01 P4.5 10 P1.7 11 P3.3 AUXR5: Auxiliary Register 5 SFR Page = 2 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 C0IC4S0 C0IC2S0 C0PPS1 C0PPS0 -- C0PS0 ECIPS0 C0COPS R/W R/W R/W R/W W R/W R/W R/W Bit 7: C0IC4S0, PCA0 Input Channel 4 input port pin Selection. C0IC4S0 CEX4 input

0 CEX4 Port Pin

1 T2EXI

Bit 6: C0IC2S0, PCA0 Input Channel 2 input port pin Selection. C1IC2S0 CEX2 input

0 CEX2 Port Pin

1 T3EXI

Bit 5: C0PPS1, {PWM2A, PWM2B} Port pin Selection 1. C0PPS1 PWM2A PWM2B 0 P6.0 P6.1 1 P3.4 P3.5 Bit 4: C0PPS0, {PWM0A, PWM0B} Port pin Selection 0. C0PPS0 PWM0A PWM0B 0 P1.6 P1.7 1 P6.0 P6.1 Bit 3: Reserved. Bit 2: C0PS0, PCA0 Port pin Selection 0. C0PS0 CEX0 CEX2 CEX4 0 P2.2 P2.4 P1.7 1 P3.0 P2.4 P3.1 Bit 1: ECIPS0, PCA0 ECI Port pin Selection0. ECIPS0 ECI 0 P4.4 1 P1.6

megawin Version: 1.00 33 Bit 0: C0COPS, PCA0 Clock Output (C0CKO) port pin Selection. C0COPS C0CKO 0 P4.7 1 P3.3 AUXR6: Auxiliary Register 6 SFR Page = 3 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 KBI4PS1 KBI4PS0 KBI6PS0 KBI2PS0 T3FCS T2FCS SnMIPS S0COPS R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: KBI4PS1~0, KBI4~5 Port pin Selection [1:0]. KBI4PS1~0 KBI4 KBI5 00 P3.3 P1.5 01 P3.4 P3.5 10 P6.0 P6.1 11 P1.5 P3.3 Bit 5: KBI6PS0, KBI6~7 Port pin Selection 0. KBI6PS0 KBI6 KBI7 0 P1.6 P1.7 1 P3.0 P3.1 Bit 4: KBI2PS0, KBI2~3 Port pin Selection 0. KBI2PS0 KBI2 KBI3 0 P3.0 P3.1 1 P2.2 P2.4 Bit 3: T3FCS, Reserved for chip test. Bit 2: T2FCS, Reserved for chip test. Bit 1: SnMIPS, S0MI & S1MI Port pin Selection. SnMIPS S0MI S1MI 0 P1.6 P6.1 1 P3.3 P4.7 Bit 0: S0COPS, S0BRG Clock Output (S0CKO) port pin Selection. S0COPS S0CKO 0 P4.7 1 P3.3 AUXR7: Auxiliary Register 7 SFR Page = 4 only SFR Address = 0xA4 RESET = 1100-0000 7 6 5 4 3 2 1 0 POE5 POE4 C0CKOE SPI0M0 -- -- -- -- R/W R/W R/W R/W W W W W Bit 7: POE5, PCA0 PWM5 main channel (PWM5O) output control. 0: Disable PWM5O output on port pin. 1: Enable PWM5O output on port pin. Default is enabled.

megawin Version: 1.00 34 Bit 6: POE4, PCA0 PWM4 main channel (PWM4O) output control. 0: Disable PWM4O output on port pin. 1: Enable PWM4O output on port pin. Default is enabled. Bit 5: C0CKOE, PCA0 clock output (C0CKO) enable. 0: Disable PCA0 clock output. 1: Enable PCA0 clock output with PCA0 base timer overflow rate/2. AUXR8: Auxiliary Register 8 SFR Page = 5 only SFR Address = 0xA4 RESET = 1100-0000 7 6 5 4 3 2 1 0 POE7 POE6 C0PPS2 -- KBI0PS0 S1COPS -- -- R/W R/W R/W W R/W R/W W W Bit 7: POE7, PCA0 PWM7 main channel (PWM7O) output control. 0: Disable PWM7O output on port pin. 1: Enable PWM7O output on port pin. Default is enabled. Bit 6: POE6, PCA0 PWM6 main channel (PWM6O) output control. 0: Disable PWM6O output on port pin. 1: Enable PWM6O output on port pin. Default is enabled. Bit 5: C0PPS2, {PWM6, PWM7} Port pin Selection 2. C0PPS2 PWM6 PWM7 0 P6.0 P6.1 1 P3.0 P3.1 Bit 3: KBI0PS0, KBI0~1 Port pin Selection 0. KBI0PS KBI0 KBI1 0 P1.0 P1.1 1 P4.7 P3.3 Bit 2: S1COPS, S1BRG Clock Output (S1CKO) port pin Selection. S1COPS S1CKO 0 P4.7 1 P6.1 AUXR9: Auxiliary Register 9 SFR Page = 6 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- T1G1 T0G1 C0FDC1 C0FDC0 S1PS1 S1PS0 W W R/W R/W R/W R/W R/W R/W Bit 1~0: S1PS1~0, Serial Port 1 pin Selection [1:0]. S1PS1~0 RXD1 TXD1 00 P1.0 P1.1 01 P6.0 P6.1 10 P4.4 P4.5 11 P3.4 P3.5

megawin Version: 1.00 35 AUXR10: Auxiliary Register 10 SFR Page = 7 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- -- SPIPS0 S0PS1 -- TWICF PAA W W W R/W R/W W R/W R/W Bit 4: SPIPS0, SPI Port pin Selection 0. SPIPS0 nSS MOSI MISO SPICLK 0 P3.3 P1.5 P1.6 P1.7 1 P1.7 P3.5 P3.4 P3.3 XICFG: External Interrupt Configured Register SFR Page = 0 only SFR Address = 0xC1 RESET = 0000-0000 7 6 5 4 3 2 1 0 INT1IS.1 INT1IS.0 INT0IS.1 INT0IS.0 -- X2FLT X1FLT X0FLT R/W R/W R/W R/W W R/W R/W R/W Bit 7~6: INT1IS.1~0, nINT1 input port pin selection bits which function is defined with INT1IS.2 as following table. INT1IS.2~0 Selected Port Pin of nINT1 000 P3.3 001 P3.1 010 P3.5 011 P1.0 100 P6.1 101 P3.4 110 P1.5 111 P2.4 Bit 5~4: INT0IS.1~0, nINT0 input port pin selection bits which function is defined with INT0IS.2 as following table. INT0IS.2~0 Selected Port Pin of nINT0 000 P4.5 001 P3.0 010 P3.4 011 P4.7 100 P6.0 101 P1.1 110 P1.7 111 P2.2 XICFG1: External Interrupt Configured 1 Register SFR Page = 1 only SFR Address = 0xC1 RESET = 0000-0000 7 6 5 4 3 2 1 0 INT1IS.2 INT0IS.2 INT2IS.1 INT2IS.0 -- X2FLT1 X1FLT1 X0FLT1 R/W R/W R/W R/W W R/W R/W R/W Bit 7: INT1IS2, nINT1 input port pin selection bit which function is defined with INT1IS.1~0. Bit 6: INT0IS2, nINT0 input port pin selection bit which function is defined with INT0IS.1~0. Bit 5~4: INT2IS1~0, nINT2 input port pin selection bits which function is defined as following table. INT2IS.1~0 Selected Port Pin of nINT2 00 P4.4 01 P3.0 10 P1.1 11 P1.6

megawin Version: 1.00 36 5. 8051 CPU Function Description 5.1. CPU Register PSW: Program Status Word SFR Page = 0~F SFR Address = 0xD0 RESET = 0000-0000 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P R/W R/W R/W R/W R/W R/W R/W R/W CY: Carry bit. AC: Auxiliary carry bit. F0: General purpose flag 0. RS1: Register bank select bit 1. RS0: Register bank select bit 0. OV: Overflow flag. F1: General purpose flag 1. P: Parity bit. The program status word (PSW) contains several status bits that reflect the current state of the CPU. The PSW, shown above, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags. The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the “Accumulator” for a number of Boolean operations. The bits RS0 and RS1 are used to select one of the four register banks shown in Section “6.2 On-Chip Data RAM”. A number of instructions refer to these RAM locations as R0 through R7. The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s and otherwise P=0. SP: Stack Pointer SFR Page = 0~F SFR Address = 0x81 RESET = 0000-0111 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. DPL: Data Pointer Low SFR Page = 0~F SFR Address = 0x82 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory.

megawin Version: 1.00 37 DPH: Data Pointer High SFR Page = 0~F SFR Address = 0x83 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. ACC: Accumulator SFR Page = 0~F SFR Address = 0xE0 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W This register is the accumulator for arithmetic operations. B: B Register SFR Page = 0~F SFR Address = 0xF0 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W This register serves as a second accumulator for certain arithmetic operations. 5.2. CPU Timing The MG82F6D17 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that has an 8051 compatible instruction set, and executes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device). It employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. The instruction timing is different than that of the standard 8051. In many 8051 implementations, a distinction is made between machine cycles and clock c ycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the 1T-80C51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. For more detailed information about the 1T-80C51 instructions, please refer section “34 Instruction Set” which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.

megawin Version: 1.00 38 5.3. CPU Addressing Mode Direct Addressing (DIR) In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal data RAM and SFRs can be direct addressed. Indirect Addressing (IND) In indirect addressing the instruction specified a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit data pointer register – DPTR. Register Instruction (REG) The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3- bit register specification within the op-code of the instruction. Instructions that access the registers this way are code efficient because this mode eliminates the need of an extra address byte. When such instruction is executed, one of the eight registers in the selected bank is accessed. Register-Specific Instruction Some instructions are specific to a certain register. For example, some instructions always operate on the accumulator or data pointer, etc. No address byte is needed for such instructions. The op-code itself does it. Immediate Constant (IMM) The value of a constant can follow the op-code in the program memory. Index Addressing Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode is intended for reading look-up tables in program memory. A 16-bit base register (either DPTR or PC) points to the base of the table, and the accumulator is set up with the table entry number. Another type of indexed addressing is used in the conditional jump instruction. In conditional jump, the destination address is computed as the sum of the base pointer and the accumulator.

megawin Version: 1.00 39 6. Memory Organization Like all 80C51 devices, the MG82F6D17 has separate address spaces for program and data memory. The logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be quickly stored and manipulated by the 8-bit CPU. Program memory (ROM) can only be read, not written to. There can be up to 16K bytes of program memory. In the MG82F6D17, all the program memory are on-chip Flash memory, and without the capability of accessing external program memory because of no External Access Enable (/EA) and Program Store Enable (/PSEN) signals designed. Data memory occupies a separate address space from program memory. In the MG82F6D17, there are 256 bytes of internal scratch-pad RAM and 768 bytes of on-chip expanded RAM (XRAM). 6.1. On-Chip Program Flash Program memory is the memory which stores the program codes for the CPU to execute, as shown in Figure 6–1. After reset, the CPU begins execution from location 0000H, where should be the starting of the user’s application code. To service the interrupts, the interrupt service locations (called interrupt vectors) should be located in the program memory. Each interrupt is assigned a fixed location in the program memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service routine must begin at location 0003H. If the interrupt is not going to be used, its service location is available as general purpose program memory. The interrupt service locations are spaced at an interval of 8 bytes: 0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. Figure 6–1. Program Memory 0000H 0003H 0013H 001BHInterrupt Locations Reset 000BH 8 bytes Program Memory16.0K: 3FFFH

megawin Version: 1.00 40 6.2. On-Chip Data RAM Figure 6–2 shows the internal and external data memory spaces available to the MG82F6D17 user. Internal data memory can be divided into three blocks, which are generally referred to as the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 bytes of SFR space. Internal data memory addresses are always 8- bit wide, which implies an address space of only 256 bytes. Direct addresses higher than 7FH access the SFR space; and indirect addresses higher than 7FH access the upper 128 bytes of RAM. Thus the SFR space and the upper 128 bytes of RAM occupy the same block of addresses, 80H through FFH, although they are physically separate entities. The lower 128 bytes of RAM are present in all 80C51 devices as mapped in Figure 6–3. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word (PSW) select which register bank is in use. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes above the register banks form a block of bit-addressable memory space. The 80C51 instruction set includes a wide selection of single- bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00H through 7FH. All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing while the Upper 128 can only be accessed by indirect addressing. Figure 6–4 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers, peripheral controls, etc. These registers can only be accessed by direct addressing. Sixteen addresses in SFR space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in 0H or 8H. Figure 6–2. Data Memory Upper 128 Bytes Internal 256 Bytes SRAM Addressable by Indirect Addressing Only Addressable by Direct and Indirect Addressing Lower 128 Bytes Addressable by Direct Addressing (SFRs) SFRs 00H 7FH 80H FFH FFH 80H Addressable by Indirect External Addressing On-chip XRAM

768 Bytes

megawin Version: 1.00 42 6.3. On-chip expanded RAM (XRAM) To access the on-chip expanded RAM (XRAM), refer to Figure 6–2, the 768 bytes of XRAM (0000H to 02FFH) are indirectly accessed by move external instruction, “MOVX @Ri” and “MOVX @DPTR”. For C51 compiler, to assign the variables to be located at XRAM, the “pdata” or “xdata” definition should be used. After being compiled, the variables declared by “pdata” and “xdata” will become the memories accessed by “MOVX @Ri” and “MOVX @DPTR”, respectively. Thus the MG82F6D17 hardware can access them correctly. 6.4. Off-Chip External Data Memory access The off-chip external data memory access function is not supported in MG82F6D17. 6.5. Declaration Identifiers in a C51-Compiler The declaration identifiers in a C51-compiler for the various MG82F6D17 memory spaces are as follows: data 128 bytes of internal data memory space (00h~7Fh); accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. idata Indirect data; 256 bytes of internal data memory space (00h~FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the data area and the 128 bytes immediately above it. sfr Special Function Registers; CPU registers and peripheral control/status registers, accessible only via direct addressing. xdata External data or on-chip eXpanded RAM (XRAM); duplicates the classic 80C51 64KB memory space addressed via the “MOVX @DPTR” instruction. The MG82F6D17 has 768 bytes of on-chip xdata memory. pdata Paged (256 bytes) external data or on-chip eXpanded RAM; duplicates the classic 80C51 256 bytes memory space addressed via the “MOVX @Ri” instruction. The MG82F6D17 has 256 bytes of on-chip pdata memory which is shared with on-chip xdata memory. code 16K bytes of program memory space; accessed as part of program execution and via the “MOVC @A+DTPR” instruction. The MG82F6D17 has 16K bytes of on-chip code memory.

megawin Version: 1.00 43 7. XRAM Access The MG82F6D17 MCUs include 768 bytes of on-chip RAM mapped into the external data memory space (XRAM). The external memory space may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the XRAM Page Select Register (XRPS). The internal XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms, both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit register which contains the effective address of the XRAM location to be read or written. The second method uses R0 or R1 in combination with the XRPS register to generate the effective XRAM address. 7.1. MOVX on 16-bit Address with dual DPTR The dual DPTR structure as shown in Figure 7–1 is a way by which the chip can specify the address of an external data memory location. There are two 16- bit DPTR registers that address the external memory, and a single bit called DPS (AUXR1.0) that allows the program code to switch between them. Figure 7–1. Dual DPTR Structure DPTR Instructions The six instructions that refer to DPTR currently selected using the DPS bit are as follows: INC DPTR ; Increments the data pointer by 1 MOV DPTR,#data16 ; Loads the DPTR with a 16-bit constant MOV A,@A+DPTR ; Move code byte relative to DPTR to ACC MOVX A,@DPTR ; Move external RAM (16-bit address) to ACC MOVX @DPTR,A ; Move ACC to external RAM (16-bit address) JMP @A+DPTR ; Jump indirect relative to DPTR DPTR1 DPTR0 AUXR1.0 External Data Memory (83h) (82h) DPLDPH DPLDPH DPS DPS=0 DPS=1 MOVX @DPTR0 or DPTR1

megawin Version: 1.00 44 AUXR1: Auxiliary Control Register 1 SFR Page = 0~F SFR Address = 0xA2 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- CRCDS1 CRCDS0 -- -- -- DPS W W R/W R/W W W W R/W Bit 0: DPS, DPTR select bit. Use to switch between DPTR0 and DPTR1. 0: Select DPTR0. 1: Select DPTR1. DPS Selected DPTR

0 DPTR0

1 DPTR1

DPL: Data Pointer Low SFR Page = 0~F SFR Address = 0x82 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. DPH: Data Pointer High SFR Page = 0~F SFR Address = 0x83 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory.

megawin Version: 1.00 45 7.2. MOVX on 8-bit Address with XRPS The 8-bit form of the MOVX instruction uses the contents of the XRPS SFR to determine the upper 8-bits of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8- bits of the effective address to be accessed. Figure 7–2. XRPS Structure XRPS: XRAM Page Select Register SFR Page = 0~F SFR Address = 0x8F RESET = XXXX-XX00 7 6 5 4 3 2 1 0 -- -- -- -- -- -- XRPS.1 XRPS.0 W W W W W W R/W R/W Bit 7~2: Reserved. Software must write “0” on these bits when XRPS is written. Bit 1~0: XRPS, XRAM Page Select. The XRPS register provides the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. Since the upper (reserved) bits of the register are always zero, the XRPS determines which page of XRAM is accessed. In MG82F6D17, XRPS indexes the three pages 256-byte RAM. For Example: If XRPS = 0x01, addresses 0x0100 through 0x01FF in XRAM will be accessed. 256B RAM 256B RAM 256B RAM 256B RAM 256B RAM 256B RAM XRAM Space XRPS = 0 XRPS[7:0] XRPS = 2XRPS = 1 CPU MOVX @Ri A[15:8]= 2; A[15:8]= 1; A[15:8]= 0; A[7:0] = Ri; A[7:0] = Ri; A[7:0] = Ri; 256B RAM 256B RAM A[15:8]= 3; A[7:0] = Ri; 256B RAM 256B RAM MOVX @Ri with XRPS on XRAM

megawin Version: 1.00 46 8. Direct Memory Access Controller (DMA) The direct memory access (DMA) controller transfers data from data source to data destination, without CPU intervention, across the entire XRAM address range and the entire SFR address range. For example, the DMA controller can move data from the ADC12 conversion result register to 8051 XRAM. This keeps CPU resources free for other operations. Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system power consumption by allowing the CPU to remain in a low-power mode without having to awaken to move data to or from a peripheral. The DMA controller features include:

• Easy use one channel DMA
• Transfer type: Memory to peripheral (M2P), peripheral to memory (P2M), peripheral to peripheral (P2P)
• Configurable transfer trigger selections: CPU software or external hardware
• Support block transfer mode, transfer sizes up to 65536 transactions
• Capability to copy data to CRC engine during DMA transfer
• Auto-initialization for circular buffer management (loop mode)
• Capability to suspend and resume a DMA transfer.
• Capability to operate in low power modes (idle mode for interrupt)
• Option interrupt on End of DMA transfer The DMA access diagram is shown in Figure 8–1. Figure 8–1. DMA Access Diagram

8051 CPU

Memory to Peripheral (M2P) Peripheral to Memory (P2M) Peripheral to Peripheral (P2P)

megawin Version: 1.00 47 8.1. DMA Structure In MG82F6D17, the DMA controller provides one channel DMA to support 3 transfer types: transfer the data from XRAM to peripheral, from peripheral to XRAM and from peripheral to peripheral. DMADS0 register in DMA channel 0 defines the DMA transfer type to configure DMA controller behavior and defines the data path to generate the SFR address on peripheral access. Timer 5 and Timer 6 are embedded in DMA module. The DMA controller supports the block mode transfer by one DMA trigger, on CPU software trigger or external hardware trigger. The transfer size is programmable from 1 to 65536 and this function is implemented on Timer 5 for DMA transfer count. If DMA needs to access XRAM, the Timer 6 implements the XRAM address pointer. When DMA finishes one data transaction, DMA_CLK will trigger Timer 5 to increase the DMA transfer count and increase Timer 6 to point next XRAM address. Both of Timer 5 and Timer 6 only support up-count operation. When DMA function is not in used, the Timer 5 and Timer 6 can be traded as a general Timer 0 with 16-bit counter. DMACR0 and DMACG0 are the SFRs for DMA operation mode control. It includes DMA start, suspend, interrupt enabled….etc. In DMA Operation section, will introduce the function in detailed. The DMA controller block diagram is shown in Figure 8–2. Figure 8–2. DMA Structure SFR Address DecoderDMADS0 DSS10 DSS00 DDS30 DDS20 DDS10 DDS00 DSS20DSS10 DMA SFR Address (A7~A0) Base Address {THR6 + TLR6} DMA XRAM Address (A15~A0) Base Transfer Count {THR5 + TLR5} DMA CH0 Complete InterruptDCF0 DMA Control Logic CPU Halt DMA XRAM RD/WR DMA SFR RD/WR CPU software trigger External hardware trigger DIE0 16-bit Up Counter 16-bit Up Counter (1~65536 bytes) DMA Complete Flage DMA Complete Interrupt Enable XRAM_Data.7~0 SFR_Data.7~0 DMA CLK reload overflowCurrent Transfer Count {TH5 + TL5} Current Address {TH6 + TL6} reload

megawin Version: 1.00 48 8.2. DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 8.2.1. DMA Transfer Types The DMA controller in MG82F6D17 supports 3 type data transfer as following list:

• M2P: XRAM to Peripheral
• P2M: Peripheral to XRAM
• P2P: Peripheral to Peripheral The DMA controller does not support the data transfer for XRAM to XRAM (M2M). It also cannot access the internal data RAM area and flash ROM area. The DMA transfer type is defined by DMADS0 when software configures the DMA data path of source and destination. Otherwise, if a peripheral is configured for DMA access, software must not access the data register of the peripheral. For example 1: The source data is selected on ADC12 and the destination data is selected on XRAM. Then, DMA controller will move data from the ADC12 conversion result register ADCDH and ADCDL to 8051 XRAM. The DMA transfer type is peripheral to XRAM. And software must avoid the read operation on ADCDH and ADCDL. For example 2: The source data is selected on ADC12 and the destination data is selected on S0 TX. Then, DMA controller will move data from the ADC12 conversion result register ADCDH and ADCDL to S0BUF. The DMA transfer type is peripheral to peripheral. Software must avoid to read ADCDH, ADCDL and to write data to S0BUF. The configuration of DMA data path selection is listed in below Table 8–1. Table 8–1. DMA Data Path Selection DSS30~00 (DMADS0[7:4]) Source Selection DDS30~00 (DMADS0[3:0]) Destination Selection 0 0 0 0 Disabled 0 0 0 0 Disabled 0 0 0 1 S0 RX 0 0 0 1 S0 TX 0 0 1 0 S1 RX 0 0 1 0 S1 TX 0 1 0 1 TWI0 RX 0 1 0 1 TWI0 TX 0 1 1 1 SPI0 RX 0 1 1 1 SPI0 TX 1 0 0 1 ADC0 1 0 0 1 Reserved 1 1 0 1 Reserved 1 1 0 1 CRC 1 1 1 1 XRAM 1 1 1 1 XRAM 8.2.2. DMA Transfer Mode The DMA controller in MG82F6D17 only supports block transfer mode. After DMA trigger active, DMA controller start to move data until the overflow event happened on DMA Current Transfer Count. That is one trigger input to activate a block data transfer by DMA controller. The block data transfer size is defined in {TH5+TL5} as DMA Current Transfer Count. It supp orts the transfer size from 1 DMA transaction to 65536 DMA transactions. In MG82F6D17, one DMA transaction move one byte data from source to destination.

megawin Version: 1.00 49 8.2.3. Transfer Count & Address Pointer DMA transfer count control and memory address pointer are implemented on Timer 5 and Timer 6 in DMA module. The action of Timer 5 and Timer 6 likes general Timer 0 with 16-bit counter (TH5 + TL5, TH6 + TL6) and 16-bit reload register (THR5 + TLR5, THR6 + TLR6). If DMA enabled, Timer 5 controls the DMA transfer count and Timer 6 points to memory address. Both of Timer 5 and Timer 6 is always 16-bit up-count counter. The Current Transfer Count implemented on {TH5 + TL5} register determines the number of transactions to be performed. The Base Transfer Count is implemented on {THR5 + TLR5}. It supports the maximum transfer count is up to 65536. The actual transfer count is equal to the value of (65536 – {TH5 + TL5}). The Current Transfer Count is increment after each DMA transaction. When the value in the register goes from FFFFH to 0000H, an event at “End of DMA transfer” is generated to stop the DMA transfer by clear DMAS0 and set DMA Complete Flag (DCF0). The event also reloads {THR5 + TLR5} to {TH5 + TL5} to initialize the new Current Transfer Count for next DMA transfer. For examples on transfer count initial, a. If DMA transfer size is 65536, the {TH5 + TL5} will be programmed to 0000H. b. If DMA transfer size is 1, the {TH5 + TL5} will be written by FFFFH. The Current Address implemented on {TH6 + TL6} register points the memory address for DMA access on XRAM. Based on {TH6 + TL6} up counting function, the addresses generated will be increased. There is a Base Address located on {THR6 + TLR6}. Each event on “End of DMA transfer” will reload the {THR6+ TLR6} to {TH6 + TL6} to initialize the new Current Address for next DMA transfer. The Current Address covers the entire XRAM memory space. 8.2.4. Start a DMA Transfer It is an easy handling DMA controller in MG82F6D17.To starting a DMA transfer, software must issue the following sequence to construct a DMA operation: 1) Configure DMADS0 to determine the DMA transfer type and DMA data path on source and destination. 2) Configure DMA interrupt and its interrupt priority. 3) Configure the Current Transfer Count and Base Transfer Count 4) Configure the Current Address and Base Address if XRAM accessed by DMA is necessary 5) Configure the peripheral to ready state 6) Set DMAE0 to enable DMA FSM 7) Configure DMA trigger source and trigger DMA to start operation -- If select software trigger, software sets DMAS0 to start DMA -- If select external trigger, wait external active signal to start DMA 8) Software waits DMA Complete Flag (DCF0) that indicates the DMA transfer finished 9) Write 0 on DMAE0 to end DMA operation and configure DMADS0 to disable state. In DMA external trigger operation, the external active signal will set DMAS0 automatically. Both of internal and external trigger, the DMAS0 will be cleared automatically when DMA transfer is finished, End of DMA transfer. 8.2.5. Suspend or Stop DMA Transfer A DMA transaction can be suspended during the transfer (after DMAS0 set) by writing 0 on DMAS0. If the channel is suspended when a DMA data transaction is ongoing, the channel is effectively disabled only once the current data transaction is completed. Re-enabling the DMAS0 resumes the DMA transfer. Software can write “0” on DMAE0 to stop current DMA transfer at any time or to end the DMA transfer after End of DMA transfer. It is recommended software must also configure data path (DMADS0) to disable state and clear DMAS0.

megawin Version: 1.00 50 8.2.6. DMA Interrupt DCF0 is set in any transfer mode or transfer type, when the corresponding Current Transfer Count register {TH5 + TL5} counts to overflow. If the corresponding DIE0 and EDMA (IE.6) are set, a DMA interrupt request is generated. If the DMA function is disabled, the Timer 5 and Timer 6 of DMA module can be a general 16- bit timer. Each timer has its own timer flag, TF5 and TF6 with corresponding interrupt enable bit. They share the DMA interrupt with DAM complete flag. The following diagram shows the DMA interrupt architecture. If software enables DMA transfer function, the interrupt enables of Timer 5 and Timer 6 must be disabled. Figure 8–3. DMA Interrupt 8.2.7. DMA Loop Mode Loop mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the LOOP bit in the DMACG0 register. When loop mode is activated, the Current Transfer Count is automatically reloaded with the Base Transfer Count, the Current Address is automatically reloaded with the Base Address, and the DMA requests continue to be served without setting DMAS0. 8.2.8. Error Handling in DMA There is no any error handling function in the DMA controller, software will take care on: a. Current Address cannot over the XRAM boundary. In MG82F6D17, XRAM boundary is 768 bytes (02FFH). b. Cannot support the even/odd parity check and generation on S0 and S1. c. Cannot handle the Not ACK status on TWI0/I2C0. 8.2.9. Data Copied to CRC16 If DMA destination is not CRC16 module, enabled CRCW0 will copy the data content to CRC16 module on each DMA transaction. For example, moving data from S0 RX to SPI0 TX will fed the data to CRC16 simultaneously. This function is supported in any transfer type. DMA Interrupt TF5 TF6 T6IE DCF0 DIE0 T5IE EDMA (IE.6)

megawin Version: 1.00 52 8.3. DMA Register DMACR0: DMA Control Register 0 SFR Page = 0~7 SFR Address = 0x94 RESET = xxx0-0000 7 6 5 4 3 2 1 0 -- -- -- -- DMAE0 DMAS0 DIE0 DCF0 W W W W R/W R/W R/W R/W Bit 7~4: Reserved. Software must write “0” on these bits when DMACR0 is written. Bit 3: DMAE0, DMA Enable 0. 0: Clear to disable DMA operation. 1: Set to enable DMA operation. Bit 2: DMAS0. DMA transfer Start 0. 0: Cleared by H/W when DMA end-of-transfer. If Cleared by S/W will suspend DMA transfer. 1: Setting this bit by software starts or resume the DMA transfer. Bit 1: DIE0, DCF0 Interrupt Enable. 0: Disable DCF0 interrupt. 1: Enable DCF0 interrupt to share the DMA interrupt vector. Bit 0: DCF0, DMA Complete Flag 0. 0: DCF0 must be cleared by software writing 0. 1: DCF0 is set by DMA end-of-transfer. DMACG0: DMA ConfiGuration Register 0 SFR Page = 8 only SFR Address = 0x94 RESET = 0000-0000 7 6 5 4 3 2 1 0 PDMAH PDMAL CRCW0 0 EXTS10 EXTS00 FAEN0 LOOP0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: PDMAH/L, DMA interrupt priority control bits. Bit 5: CRCW0, CRC16 Write (copied) enable. 0: Disable the DMA data is copied to CRC16 concurrently. 1: Enable the DMA data is copied to CRC16 concurrently. Bit 4: Reserved. Software must write “0” on these bits when DMACG0 is written. Bit 3~2: EXTS10~00. DMA external trigger source selection. EXTS10, EXTS00 Selected Signal 0 0 Disabled, software trigger 0 1 INT2ET 1 0 Reserved 1 1 KBIET Bit1: Reserved. Bit 0: LOOP0. 0: Disable DMA loop operation. 1: Enable DMA loop operation.

megawin Version: 1.00 53 DMADS0: DMA Data path Selection Register 0 SFR Page = 9 only SFR Address = 0x94 RESET = 0000-0000 7 6 5 4 3 2 1 0 DSS30 DSS20 DSS10 DSS00 DDS30 DDS20 DDS10 DDS00 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~4: DMA data Source Selection. Bit 3~0: DMA data Destination Selection. DSS30~00 (DMADS0[7:4]) Source Selection DDS30~00 (DMADS0[3:0]) Destination Selection 0 0 0 0 Disabled 0 0 0 0 Disabled 0 0 0 1 S0 RX 0 0 0 1 S0 TX 0 0 1 0 S1 RX 0 0 1 0 S1 TX 0 1 0 1 TWI0 RX 0 1 0 1 TWI0 TX 0 1 1 1 SPI0 RX 0 1 1 1 SPI0 TX 1 0 0 1 ADC0 1 0 0 1 Reserved 1 1 0 1 Reserved 1 1 0 1 CRC 1 1 1 1 XRAM 1 1 1 1 XRAM Note 1: When use DMA to transfer ADC data, please watch out the Data Bit setting. Please reference

26.2.8 Transfer ADC Data by DMA

8.4. Timer5 Register T5CON: Timer 5 Control Register SFR Page = 3 Only SFR Address = 0xC8 RESET = 0000-0000 7 6 5 4 3 2 1 0 TF5 -- T5CKS1 T5CKS0 T5IE TR5 T5GAT1 T5GAT0 R/W W R/W R/W R/W R/W R/W R/W Bit 7: TF5, Timer 5 overflow flag. 0: TF5 must be cleared by software. 1: TF5 is set by a Timer 5 overflow happened. Bit 6: --. Bit 5~4: T5CKS.1~0, Timer 5 clock source selector. T5CKS.1~0 T5 Clock Selection

00 SYSCLK/12

01 T5 Pin

10 SYSCLK

11 T2EXI input selection

T5 Pin: P3.4 Bit 3: T5IE, TF5 interrupt enable. 0: Disable TF5 interrupt. 1: Enable TF5 interrupt to share the DMA interrupt vector. Bit 2: TR5, Timer 5 Run control bit. 0: Disabled to stop the Timer/Counter 5. Before starting the DMA process, software must be disabled TR5. 1: Enabled to start the Timer/Counter 5. Bit 1~0: T5GAT.1~0, Gating source selection of Timer 5. T5GAT.1~0 T5 Gate source

00 Disable

01 INT0ET

10 INT2ET

11 KBIET

megawin Version: 1.00 54 TL5: Timer 5 Low byte Register SFR Page = 3 Only SFR Address = 0xCC RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TH5: Timer 5 High byte Register SFR Page = 3 Only SFR Address = 0xCD RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TLR5: Timer 5 Low byte Reload Register SFR Page = 3 Only SFR Address = 0xCA RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W THR5: Timer 5 High byte Reload Register SFR Page = 3 Only SFR Address = 0xCB RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 8.5. Timer 6 Register T6CON: Timer 6 Control Register SFR Page = 4 Only SFR Address = 0xC8 RESET = 0000-0000 7 6 5 4 3 2 1 0 TF6 -- T6CKS1 T6CKS0 T6IE TR6 T6GAT1 T6GAT0 R/W W R/W R/W R/W R/W R/W R/W Bit 7: TF6, Timer 6 overflow flag. 0: TF6 must be cleared by software. 1: TF6 is set by a Timer 6 overflow happened. Bit 6: --. Bit 5~4: T6CKS.1~0, Timer 6 clock source selector. T6CKS.1~0 T6 Clock Selection

01 T6 Pin

11 T3EXI input selection

T6 Pin: P3.5 Bit 3: T6IE, TF6 interrupt enable. 0: Disable TF6 interrupt. 1: Enable TF6 interrupt to share the DMA interrupt vector.

megawin Version: 1.00 55 Bit 2: TR6, Timer 6 Run control bit. 0: Disabled to stop the Timer/Counter 6. Before starting the DMA process, software must be disabled TR6. 1: Enabled to start the Timer/Counter 6. Bit 1~0: T6GAT.1~0, Gating source selection of Timer 5. T6GAT.1~0 T6 Gate source

01 INT1ET

TL6: Timer 6 Low byte Register SFR Page = 4 Only SFR Address = 0xCC RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TH6: Timer 6 High byte Register SFR Page = 4 Only SFR Address = 0xCD RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TLR6: Timer 6 Low byte Reload Register SFR Page = 4 Only SFR Address = 0xCA RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W THR6: Timer 6 High byte Reload Register SFR Page = 4 Only SFR Address = 0xCB RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W

megawin Version: 1.00 56 9. System Clock There are three clock sources for the system clock: Internal High-frequency RC Oscillator (IHRCO), Internal Low-frequency RC Oscillator (ILRCO) and External Clock Input. Figure 9–1 shows the structure of the system clock in MG82F6D17. The MG82F6D17 always boots from IHRCO on 12MHz. Software can select the OSCin input on one of the three clock sources application required and switches them on the fly. But software needs to settle the clock source stably before clock switching. In external clock input mode (ECKI), the clock source comes from P6.0 input . The built-in IHRCO provides two kinds of frequency for software selected. Another frequency is 11.059MHz by software setting AFS on CKCON0.7. Both of 12MHz and 11.059 MHz in IHRCO provide high precision frequency for system clock source. To find the detailed IHRCO performance, please refer Section “33.3 IHRCO Characteristics”). In IHRCO or ILRCO mode, P6.0 can be configured to internal MCK output or MCK/2 and MCK/4 for system application. The built-in ILRCO provides the low power and low speed frequency about 32KHz to WDT and system clock source. MCU can selects the ILRCO to system clock source by software for low power operation. To find the detailed IHRCO performance, please refer Section “33.4 ILRCO Characteristics”). In ILRCO mode, P6.0 can be configured to internal MCK output or MCK/2 and MCK/4 for system application. The MG82F6D17 device includes a Clock Multiplier (CKM) to generate the high speed clock for system clock source. CKM applied in MG82F6D17 is shown in Figure 9–1 and its typical input frequency is around 6MHz. Before enable CKM, software must configure the CKMIS1~0 (CKCON.5~4) to get the reasonable CKMI frequency for CKM input source. CKM can generate 4/5.33/8 times frequency of CKMI and setting MCKS1~0 (CKCON2.3~2) selects different CKM outputs to provide the high speed operation on MCU without high-frequency clock source. To find the detailed CKM performance, please refer Section “33.5 CKM Characteristics”). The system clock, SYSCLK, is obtained from one of these four clock sources through the clock divider, as shown in Figure 9–1. The user can program the divider control bits SCKS2~SCKS0 (in CKCON0 register) to get the desired system clock.

megawin Version: 1.00 58 9.2. Clock Source Switching There are three clock sources for the system clock: Internal High-frequency RC Oscillator (IHRCO), Internal Low-frequency RC Oscillator (ILRCO) and External Clock Input. Figure 9–1 shows the structure of the system clock in MG82F6D17. The MG82F6D17 always boots from IHRCO on 12MHz. OSCS[1:0] are used to select the clock source by software setting, but the software need to wait until the clock be settle before switch the clock source. 9.3. On-chip CKM (PLL) The MG82F6D17 includes a Clock Multiplier (CKM) to generate the high speed clock for system clock source. It is shown in Figure 9–1 and its typical input frequency is around 6MHz. Before enable CKM, software must configure the CKMIS1~0 (CKCON.5~4) to get the suitable CKMI frequency for CKM input source. CKM can generate 4/5.33/8 times frequency of CKMI and setting MCKS1~0 (CKCON2.3~2) selects different CKM outputs on MCK to provide the high speed operation on MCU without high-frequency clock source. To find the detailed CKM performance, please refer Section “33.5 CKM Characteristics”). 9.4. Wake-up clock from CKM When enable CKM circuit, it needs 100us to output stable frequency, within this uncertain frequency period, the input of the MCK needs to keep MCKS on OSCin to guarantee system’s satiability. Please reference the following procedure: How to Program to Support wake-up with clock from CKM

• Program MCKS[1:0] (CKCON2.3~2) to “00” to select non-CKM output as clock source
• MCU enters power down
• MCU wakes up
• delay 100us to wait CKM working stable.
• Modify MCKS[1:0] (CKCON2.3~2) to select CKM output as clock source
• Continue program execution………

megawin Version: 1.00 59 9.5. Clock Register CKCON0: Clock Control Register 0 SFR Page = 0~F & P SFR Address = 0xC7 RESET = 0001-0000 7 6 5 4 3 2 1 0 AFS ENCKM CKMIS1 CKMIS0 CCKS SCKS2 SCKS1 SCKS0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: AFS, Alternated Frequency Selection. 0: Select IHRCO on 12MHz. 1: Select IHRCO on 11.059MHz. Bit 6: ENCKM, Enable clock multiplier (X8/X12) 0: Disable the X8/X12 clock multiplier. 1: Enable the X8/X12 clock multiplier. Bit 5~4: CKMIS1 ~ CKMIS0, Clock Multiplier Input Selection. CKMIS[1:0] Clock Multiplier Input Selection 0 0 OSCin/1 (when OSCin = 5 ~ 7MHz) 0 1 OSCin/2 (when OSCin = 10 ~ 14MHz) 1 0 OSCin/4 (when OSCin = 20 ~ 28MHz) 1 1 Reserved Bit 3: CCKS, CPU Clock Select. 0: Select CPU Clock as SYSCLK. 1: Select CPU Clock as SYSCLK/2. Bit 2~0: SCKS2 ~ SCKS0, programmable System Clock Selection. SCKS[2:0] System Clock (SYSCLK) 0 0 0 MCKDO/1 0 0 1 MCKDO/2 0 1 0 MCKDO/4 0 1 1 MCKDO/8 1 0 0 MCKDO/16 1 0 1 MCKDO/32 1 1 0 MCKDO/64 1 1 1 MCKDO/128 CKCON2: Clock Control Register 2 SFR Page = P Only SFR Address = 0x40 RESET = 0001-0000 7 6 5 4 3 2 1 0 -- -- -- IHRCOE MCKS1 MCKS0 OSCS1 OSCS0 W W W R/W R/W R/W R/W R/W Bit 4: IHRCOE, Internal High frequency RC Oscillator Enable. 0: Disable internal high frequency RC oscillator. 1: Enable internal high frequency RC oscillator. If this bit is set by CPU software, it needs 32 us to have stable output after IHRCOE is enabled.

megawin Version: 1.00 60 Bit 3~2: MCKS[1:0], MCK Source Selection. MCKS[1:0] MCK Source Selection OSCin =12MHz CKMIS = [01] OSCin =11.059MHz CKMIS = [01] CKMS0 = 0 CKMS0 = 1 CKMS0 = 0 CKMS0 = 1 0 0 OSCin 12MHz 11.059MHz 0 1 CKMI x4 / x6 24MHz 36MHz 22.118MHz 33.177MHz 1 0 CKMI x5.33 / x8 32MHz 48MHz 29.491MHz 44.236MHz 1 1 CKMI x8 / x12 48MHz 72MHz 44.236MHz 66.354MHz Note: It needs to set ENCKM = 1 to enable CKM. Note: Needs to be careful of the limitation of CPUCLK and SYSCLK. Needs to use SCKS[2:0] and CCKS to choose proper range of CPUCLK and SYSCLK to not exceed the limitation. CPUCLK ≤ 36MHz, SYSCLK ≤ 50MHz. Bit 1~0: OSCS[1:0], OSCin Source selection. OSCS[1:0] OSCin source Selection 0 0 IHRCO 0 1 ECKI 1 0 ILRCO 1 1 Reserved CKCON3: Clock Control Register 3 SFR Page = P only SFR Address = 0x41 RESET = 0000-0000 7 6 5 4 3 2 1 0 WDTCS1 WDTCS0 FWKP WDTFS MCKD1 MCKD0 -- -- R/W R/W R/W R/W R/W R/W W W Bit 5: FWKP, MCU Fast wake up control. 0: Select MCU for normal wakeup time about 120us from power-down mode. 1: Select MCU for fast wakeup time about 30us from power-down mode. Bit 4: WDTFS. WDT overflow source selection. 0: Select WDT bit-8 overflow as WDT event source. 1: Select WDT bit-0 overflow as WDT event source. Bit 3~2: MCKD[1:0], MCK Divider Output selection. MCKD[1:0] MCKDO Frequency if MCK = 12MHz if MCK = 48MHz 0 0 MCKDO = MCK MCKDO = 12MHz MCKDO = 48MHz 0 1 MCKDO = MCK/2 MCKDO = 6MHz MCKDO = 24MHz 1 0 MCKDO = MCK/4 MCKDO = 3MHz MCKDO = 12MHz 1 1 MCKDO = MCK/8 MCKDO = 1.5MHz MCKDO = 6MHz CKCON5: Clock Control Register 5 SFR Page = P only SFR Address = 0x43 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W W W W W W R/W Bit 7~1: Reserved. Software must write “0” on these bits when CKCON5 is written. Bit 0: CKMS0, CKM mode selection 0. 0: Select CKM operating for 8X mode. (96MHz) 1: Select CKM operating for 12X mode. (144MHz)

megawin Version: 1.00 61 AUXR0: Auxiliary Register 0 SFR Page = 0~F SFR Address = 0xA1 RESET = 0000-0000 7 6 5 4 3 2 1 0 P60OC1 P60OC0 P60FD PBKF -- -- INT1H INT0H R/W R/W R/W R/W W W R/W R/W Bit 7~6: P6.0 function configured control bit 1 and 0. The two bits only act when internal RC oscillator (IHRCO or ILRCO) is selected for system clock source. In external clock input mode, P6.0 is the dedicated clock input pin. In internal oscillator condition, P6.0 provides the following selections for GPIO or clock source generator. When P60OC[1:0] index to non-P6.0 GPIO function, P6.0 will drive the on-chip RC oscillator output to provide the clock source for other devices. P60OC[1:0] P60 function I/O mode 00 P60 By P6M0.0 01 MCK By P6M0.0 10 MCK/2 By P6M0.0 11 MCK/4 By P6M0.0 For clock-out on P6.0 function, it is recommended to set P6M0.0 to “1” which selects P6.0 as push-push output mode. Bit 5: P60FD, P6.0 Fast Driving. 0: P6.0 output with default driving. 1: P6.0 output with fast driving enabled. If P6.0 is configured to clock output, enable this bit when P6.0 output frequency is more than 12MHz at 5V application or more than 6MHz at 3V application. DCON0: Device Control Register 0 SFR Page = P Only SFR Address = 0x4C POR = 100x-x011 7 6 5 4 3 2 1 0 HSE IAPO HSE1 -- -- IORCTL RSTIO OCDE R/W R/W R/W W W R/W R/W R/W Bit 7: HSE, High Speed operation Enable. 0: Select CPU running in lower speed mode (FCPUCLK ≤ 6MHz) which is slow down internal circuit to reduce power consumption. 1: Enable CPU full speed operation if FCPUCLK > 6MHz. Before select high frequency clock (> 6MHz) on CPUCLK, software must set HSE to switch internal circuit for high speed operation. Bit 5: HSE1, High Speed operation Enable 1. 0: No function. 1: Enable MCU for ultra-high speed operation. (FCPUCLK > 25MHz). It also needs to set HSE when use HSE1 = 1.

megawin Version: 1.00 63 10.4. WDT Register WDTCR: Watch-Dog-Timer Control Register SFR Page = 0~F & P SFR Address = 0xE1 POR = XXX0-XXXX (0000-0111) 7 6 5 4 3 2 1 0 WREN NSW ENW CLRW WIDL PS2 PS1 PS0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: WREN, WDT Reset Enable. The initial value can be changed by hardware option, WRENO. 0: The overflow of WDT does not set the WDT reset. The WDT overflow flag, WDTF, may be polled by software or trigger an interrupt. 1: The overflow of WDT will cause a system reset. Once WREN has been set, it can not be cleared by software in page 0~F. In page P , software can modify it to “0” or “1”. Bit 6: NSW. Non-Stopped WDT. The initial value can be changed by hardware option, NSWDT. 0: WDT stop counting while the MCU is in power-down mode. 1: WDT always keeps counting while the MCU is in power-down mode (Watch Mode) or idle mode. Once NSW has been set, it can not be cleared by software in page 0~F. In page P , software can modify it to “0” or “1”. Bit 5: ENW. Enable WDT. 0: Disable WDT running. This bit is only cleared by POR. 1: Enable WDT while it is set. Once ENW has been set, it can not be cleared by software in page 0~F. In Page P, software can modify it as “0” or “1”. Bit 4: CLRW. WDT clear bit. 0: Writing “0” to this bit is no operation in WDT. 1: Writing “1” to this bit will clear the 8-bit WDT counter to 00H. Note this bit has no need to be cleared by writing “0”.Clear WDT to recount while it is set. Bit 3: WIDL. WDT idle control. 0: WDT stops counting while the MCU is in idle mode. 1: WDT keeps counting while the MCU is in idle mode. Bit 2~0: PS2 ~ PS0, select prescaler output for WDT time base input. When WDTFS (CKCON3.4) = 0, WDT clock source= ILRCO or SYSCLK/12 PS[2:0] Prescaler Value WDT Period (WDT clock = ILRCO) WDT Period (WDT clock = SYSCLK/12) (SYSCLK = IHRCO, 12MHz) 0 0 0 2 16 ms 0.512 ms 0 0 1 4 32 ms 1.024 ms 0 1 0 8 64 ms 2.048 ms 0 1 1 16 128 ms 4.096 ms 1 0 0 32 256 ms 8.192 ms 1 0 1 64 512 ms 16.384 ms 1 1 0 128 1024 ms 32.768 ms 1 1 1 256 2048 ms 65.536 ms When WDTFS (CKCON3.4) = 1, WDT clock source= ILRCO PS[2:0] Prescaler Value WDT Period Note (clock source = ILRCO) 0 0 0 2 245 us= 125+120 0 0 1 4 370 us= 250+120 0 1 0 8 620 us= 500+120 0 1 1 16 1.12 ms= 1ms+120 1 0 0 32 2.12 ms= 2ms+120 1 0 1 64 4.12 ms= 4ms +120 1 1 0 128 8.12 ms= 8ms +120 1 1 1 256 16.12ms= 16ms+120 Note: When WDT clock source is ILRCO, the WDT internal logic latency is around 120us. Under this condition we suggest to add 120us of WDT period it shorter than 12ms.

megawin Version: 1.00 64 CKCON3: Clock Control Register 3 SFR Page = P only SFR Address = 0x41 RESET = 0000-0000 7 6 5 4 3 2 1 0 WDTCS1 WDTCS0 FWKP WDTFS MCKD1 MCKD0 -- -- R/W R/W R/W R/W R/W R/W W W Bit 7~6: WDTCS1~0, WDT Clock Source selection [1:0]. WDTCS1~0 WDT Clock Source

00 ILRCO

01 ECKI

10 SYSCLK/12

11 S0TOF

Bit 4: WDTFS. WDT overflow source selection. 0: Select WDT bit-8 overflow as WDT event source. 1: Select WDT bit-0 overflow as WDT event source. PCON1: Power Control Register 1 SFR Page = 0~F & P SFR Address = 0x97 POR = 0000-x000 7 6 5 4 3 2 1 0 SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF R/W R/W W R/W W R/W R/W R/W Bit 1: WDTF, WDT overflow flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware when WDT overflows. Writing “1” on this bit will clear WDTF. SFIE: System Flag Interrupt Enable Register SFR Page = 0~F SFR Address = 0x8E POR = 0000-x000 7 6 5 4 3 2 1 0 SIDFIE -- -- RTCFIE -- BOF1IE BOF0IE WDTFIE R/W W W R/W W R/W R/W R/W Bit 0: WDTFIE, Enable WDTF (PCON1.0) Interrupt. 0: Disable WDTF interrupt. 1: Enable WDTF interrupt.

megawin Version: 1.00 65 10.5. WDT Hardware Option In addition to being initialized by software, the WDTCR register can also be automatically initialized at power -up by the hardware options WRENO, NSWDT, HWENW, HWWIDL and HWPS[2:0], which should be programmed by a universal Writer or Programmer, as described below. If HWENW is programmed to “enabled”, then hardware will automatically do the following initialization for the WDTCR register at power-up: (1) set ENW bit, (2) load WRENO into WREN bit, (3) load NSWDT into NSW bit, (4) load HWWIDL into WIDL bit, and (5) load HWPS[2:0] into PS[2:0] bits. If both of HWENW and WDSFWP are programmed to “enabled”, hardware still initializes the WDTCR register content by WDT hardware option at power-up. Then, any CPU writing on WDTCR bits will be inhibited except writing “1” on WDTCR.4 (CLRW), clear WDT, even though access through Page-P SFR mechanism. WRENO: : Enabled. Set WDTCR.WREN to enable a system reset function by WDTF. : Disabled. Clear WDTCR.WREN to disable the system reset function by WDTF. NSWDT: Non-Stopped WDT : Enabled. Set WDTCR.NSW to enable the WDT running in power down mode (watch mode). : Disabled. Clear WDTCR.NSW to disable the WDT running in power down mode (disable Watch mode). HWENW: Hardware loaded for “ENW” of WDTCR. : Enabled. Enable WDT and load the content of WRENO, NSWDT, HWWIDL and HWPS2~0 to WDTCR after power-on. : Disabled. WDT is not enabled automatically after power-on. HWWIDL, HWPS2, HWPS1, HWPS0: When HWENW is enabled, the content on these four fused bits will be loaded to WDTCR SFR after power-on. WDSFWP: : Enabled. The WDT SFRs, WREN, NSW, WIDL, PS2, PS1 and PS0 in WDTCR, will be write-protected. : Disabled. The WDT SFRs, WREN, NSW, WIDL, PS2, PS1 and PS0 in WDTCR, are free for writing of software.

megawin Version: 1.00 66 11. Real-Time-Clock (RTC)/System-Timer The MG82F6D17 has a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a maximum 21-bit up counter comprised of a 0~15-bit prescaler and a 6-bit loadable up counter. When it overflows, the 6-bit counter will be reloaded again and the RTCF flag will be set. The clock source for this prescaler has 6 selections, and needs to set RCSS[2:0] to select one of source before enable WDT . Figure 11–1 shows the RTC structure in MG82F6D17. To input 32.768 KHz from ECKI for the RTC module input will provide a programmable overflow period for 0.5S to 64S. The counter also provides a timer function with the clock derived from SYSCLK for a system timer function. The maximum overflow period for the system timer function is SYSCLK/2^21. The ILRCO provides the internal clock source for RTC module. The WDTPS and WDTOF come from WDT prescaler and WD T overflow to provide the extended prescaler source for more long wake-up time requirement. The RCT clock source must be configured before RTCE enabled. RTCO enables the RTC overflow output on port pin. Only power-on reset will reset the Real-Time clock and its associated SFRs to the default state. Figure 11–1. Real-Time-Clock Counter RTCTM Register RTCCT[5:0] RPSC[2:0] SFIE.RTCFIE EIE1.ESF RTC Interrupt SYSCLK RTCCT[5:0] RTCRL[5:0] Overflow Reload RTCF PCON1.4 RTCPS[13] ( /2^15) RTCPS[14] RTCCS[3:0] RTCCR Register RTCORTCE RTCRL[5:0] 6-bit Counter RTCKO SFR P4.5 Toggle Q (0,0,0,0) (0,0,0,1) (0,0,1,0) (0,0,1,1) (0,1,0,0) RCSS[2:0] ILRCO WDTPS WDTOF CKCON4 Register RTCCS[3:2]RCSS[2:0] RTCCS[1:0] RTCPS[0:4] RTCPS[5:8] RTCPS[9:12] RTCPS[13:14] RTC Prescaler RTCPS[12] RTCPS[11] RTCPS[10] (1,1,0,1)RTCPS[1] (1,1,1,0)RTCPS[0] (1,1,1,1)RTCPSI RPCS[2]RPCS[1]RPCS[0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) D SYSCLK/12 (1,0,1) ECKI (P6.0)

megawin Version: 1.00 67 11.1. RTC Register RTCCR: Real-Time-Clock Control Register SFR Page = 0~7 & P SFR Address = 0xBE/0x54 POR = 0011-1111 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: RTCE, RTC Enable. 0: Stop RTC Counter, RTCCT. 1: Enable RTC Counter and set RTCF when RTCCT overflows. When RTCE is set, CPU can not access RTCTM. RTCTM must be accessed in RTCE cleared. Bit 6: RTCO, RTC Output enabled. The frequency of RTCKO is (RTC overflow rate)/2. 0: Disable the RTCKO output. 1: Enable the RTCKO output on P4.5. Bit 5~0: RTCRL[5:0], RTC counter reload value register. This register is accessed by CPU and the content in the register is reloaded to RTCCT when RTCCT overflows. RTCTM: Real-Time-Clock Timer Register SFR Page = 0~7 & P SFR Address = 0xB6/0x55 POR = 0111-1111 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: RTCCS.1~0, RTC Clock Selection. Default is “01”. RTCCS.3~0 Clock Source RTC Interrupt Duration Min. Step 0 0 0 0 RTCPS[14] (/2^15) 1S ~ 64S when P6.0 = 32768Hz 1S 0 0 0 1 RTCPS[13] (/2^14) 0.5S ~ 32S when P6.0 = 32768Hz 0.5S (default) 0 0 1 0 RTCPS[13] (/2^13) 0.25S ~ 16S when P6.0 = 32768Hz 0.25S 1 0 1 0 RTCPS[4] (/2^5) 976us ~ 62.46ms when P6.0 = 32768Hz 976 us 1 0 1 1 RTCPS[3] (/2^4) 488 us 1 1 0 0 RTCPS[2] (/2^3) 244 us 1 1 0 1 RTCPS[1] (/2^2) 122us ~ 3.9ms when P6.0 = 32768Hz 122 us 1 1 1 0 RTCPS[0] (/2^1) 61us ~ 1.952ms when P6.0 = 32768Hz 61 us 1 1 1 1 RTCPSI (/2^0) 30.5us ~ 976us when P6.0 = 32768Hz 30.5 us Bit 5~0: RTCCT[5:0], RTC counter register. It is a counter for RTC function or System Timer function by different clock source selection on RTCCS[1:0]. When the counter overflows, it sets the RTCF flag which shares the system flag interrupt when RTCFIE is enabled. The maximum RTC overflow period is 64 seconds.

megawin Version: 1.00 68 CKCON4: Clock Control Register 4 SFR Page = P only SFR Address = 0x42 RESET = 0000-0000 7 6 5 4 3 2 1 0 RCSS2 RCSS1 RCSS0 RPCS2 RPCS1 RPCS0 RTCCS3 RTCCS2 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~5: RTC Clock Source selection [2:0] RCSS2, RCSS1, RCSS0 RTC Clock Selection 0 0 0 ECKI (P6.0) 0 0 1 ILRCO 0 1 0 WDTPS 0 1 1 WDTOF 1 0 0 SYSCLK 1 0 1 SYSCLK / 12 1 1 0 Reserved 1 1 1 Reserved PCON1: Power Control Register 1 SFR Page = 0~F & P SFR Address = 0x97 POR = 0000-x000 7 6 5 4 3 2 1 0 SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF R/W R/W W R/W W R/W R/W R/W Bit 4: RTCF, RTC overflow flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware when RTCCT overflows. Writing “1” on this bit will clear RTCF. SFIE: System Flag Interrupt Enable Register SFR Page = 0~F SFR Address = 0x8E POR = 0000-x000 7 6 5 4 3 2 1 0 SIDFIE -- -- RTCFIE -- BOF1IE BOF0IE WDTFIE R/W W W R/W W R/W R/W R/W Bit 4: RTCFIE, Enable RTCF (PCON1.4) Interrupt. 0: Disable RTCF interrupt. 1: Enable RTCF interrupt. If enabled, RTCF will wake up CPU in Idle mode or power-down mode.

megawin Version: 1.00 70 12.3. External Reset A reset is accomplished by holding the RESET pin HIGH for at least 24 oscillator periods while the oscillator is running. To ensure a reliable power-up reset, the hardware reset from RST pin is necessary. PCON1: Power Control Register 1 SFR Page = 0~F & P SFR Address = 0x97 POR = 0000-x000 7 6 5 4 3 2 1 0 SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF R/W R/W W R/W W R/W R/W R/W Bit 6: EXRF, External Reset Flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware if an External Reset occurs. Writing “1” on this bit will clear EXRF. 12.4. Software Reset Software can trigger the CPU to restart by software reset, writing “1” on SWRST (ISPCR.5), and set the SWRF flag (PCON1.7). SWBS decides the CPU is boot from ISP or AP region after the reset action ISPCR: ISP Control Register SFR Page = 0~F SFR Address = 0xE7 POR = 0000-XXXX 7 6 5 4 3 2 1 0 ISPEN SWBS SWRST CFAIL -- -- -- -- R/W R/W R/W R/W W W W W Bit 6: SWBS, software boot selection control. 0: Boot from AP-memory after reset. 1: Boot from ISP memory after reset. Bit 5: SWRST, software reset trigger control. 0: Write “0” is no operation 1: Write “1” to generate software system reset. It will be cleared by hardware automatically. PCON1: Power Control Register 1 SFR Page = 0~F & P SFR Address = 0x97 POR = 0000-x000 7 6 5 4 3 2 1 0 SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF R/W R/W W R/W W R/W R/W R/W Bit 7: SWRF, Software Reset Flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware if a Software Reset occurs. Writing “1” on this bit will clear SWRF.

megawin Version: 1.00 71 12.5. Brown-Out Reset In MG82F6D17, there are two Brown-Out Detectors (BOD0 & BOD1) to monitor VDD power. BOD0 services the fixed drops below BOD0 or BOD1 monitor level. Associated flag, BOF0 and BOF1, is set. If BO0RE (PCON2.1) is enabled, BOF0 indicates a BOD0 Reset occurred. If BO1RE (PCON2.3) is enabled, BOF1 indicates a BOD1 Reset occurred. PCON1: Power Control Register 1 SFR Page = 0~F & P SFR Address = 0x97 POR = 0000-x000 7 6 5 4 3 2 1 0 SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF R/W R/W W R/W W R/W R/W R/W Bit 2: BOF1, BOF1 (Reset) Flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware when VDD meets BOD1 monitored level. Writing “1” on this bit will clear BOF1. If BO1RE (PCON2.3) is enabled, BOF1 indicates a BOD1 Reset occurred. Bit 1: BOF0, BOF0 (Reset) Flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware when VDD meets BOD0 monitored level. Writing “1” on this bit will clear BOF0. If BO0RE (PCON2.1) is enabled, BOF0 indicates a BOD0 Reset occurred. 12.6. WDT Reset When WDT is enabled to start the counter, WDTF will be set by WDT overflow. If WREN (WDTCR.7) is enabled, the WDT overflow will trigger a system reset that causes CPU to restart. Software can read the WDTF to recognize the WDT reset occurred. PCON1: Power Control Register 1 SFR Page = 0~F & P SFR Address = 0x97 POR = 0000-x000 7 6 5 4 3 2 1 0 SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF R/W R/W W R/W W R/W R/W R/W Bit 0: WDTF, WDT Overflow/Reset Flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware when WDT overflows. Writing “1” on this bit will clear WDTF. If WREN (WDTCR.7) is set, WDTF indicates a WDT Reset occurred. 12.7. Illegal Address Reset In MG82F6D17, if software program runs to illegal address such as over program ROM limitation, it triggers a RESET to CPU.

megawin Version: 1.00 72 13. Power Management The MG82F6D17 supports two power monitor modules, Brown-Out Detector 0 (BOD0) and Brown-Out Detector 1 (BOD1), and 7 power-reducing modes: Idle mode, Power-down mode, Slow mode, Sub-Clock mode, RTC mode, Watch mode and Monitor mode. BOD0 and BOD1 report the chip power status on the flags, BOF0 and BOF1, which provide the capability to interrupt CPU or to reset CPU by software configured. The seven power-reducing modes provide the different power-saving scheme for chip application. These modes are accessed through the CKCON0, CKCON2, CKCON3, CKCON4, CKCON5, PCON0, PCON1, PCON2, PCON3, RTCCR and WDTCR register. 13.1. Brown-Out Detector In MG82F6D17, there are two Brown-Out Detectors (BOD0 & BOD1) to monitor VDD power. Figure 13–1 shows the functional diagram of BOD0 and BOD1. BOD0 services the fixed detection level at VDD=1.7V and BOD1 detects the the detection level. If both of ESF (EIE1.3) and BOF0IE (SFIE.1) are enabled, a set BOF0 will generate a system flag interrupt. It can interrupt CPU either CPU in normal mode or idle mode. The BOD1 has the same flag function, BOF1, and same interrupt function. The BOD1 interrupt also wakes up CPU in power down mode if AWBOD1 (PCON2.7) is enabled. If BO0RE (PCON2.1) is enabled, the BOD0 event will trigger a system reset and set BOF0 to indicate a BOD0 Reset occurred. The BOD0 reset restart the CPU either CPU in normal mode or idle mode. BOD1 also h as the same reset capability with associated control bit, BO1RE (PCON2.3). The BOD1 reset also restart CPU in power down mode if AWBOD1 (PCON2.7) is enabled in BOD1 reset operation. To reduce power consumption, software may clear EBOD1 (PCON2.2) to disable BOD1 if the BOD1 is not applied in user application. Figure 13–1. Brown-Out Detector 0/1 1.7V VDD Voltage Comparator “1” Load BOF0 BOD0 Interrupt BOD0 Reset PCON0.PD Enable (PCON1.1) BOF0IE (SFIE.1) ESF (EIE1.3) BO0RE (PCON2.1) VDD Voltage Comparator “1” Load BOF1 BOD1 Interrupt BOD1 Reset PCON0.PD Enable (PCON1.2) BOF1IE (SFIE.2) ESF (EIE1.3) BO1RE (PCON2.3) AWBOD1 (PCON2.7) 34.2V 3.7V 2.4V 2.0V 00: 2.0V 01: 2.4V 10: 3.7V 11: 4.2V BO1S1,0 (PCON2.5~4)

megawin Version: 1.00 73 13.2. Power Saving Mode 13.2.1. Slow Mode The alternative to save the operating power is to slow the MCU’s operating speed by programming SCKS2~SCKS0 bits (in CKCON0 register, see Section “9 System Clock”) to a non-0/0/0 value. The user should examine which program segments are suitable for lower operating speed. In principle, the lower operating speed should not affect the system’s normal function. Then, restore its normal speed in the other program segments. 13.2.2. Sub-Clock Mode The alternative to slow down the MCU’s operating speed by programming OSCS1~0 can select the ILRCO for system clock. The 32KHz ILRCO provides the MCU to operates in an ultra-low speed and low power operation. Additional programming SCKS2~SCKS0 bits (in CKCON0 register, see Section “9 System Clock”), the user could put the MCU speed down to 250Hz slowest. 13.2.3. RTC Mode The MG82F6D17 has a simple RTC module that allows a user to continue running an accurate timer while the rest of the device is powered-down. In RTC mode, the RTC module behaves a “Clock” function and can be a wake-up source from chip power down by RTC overflow rate. Please refer Section “11 Real-Time-Clock (RTC)/System-Timer” for more detail information. 13.2.4. Watch Mode If Watch-Dog-Timer is enabled and NSW is set, Watch-Dog-Timer will keep running in power down mode to support an auto-wakeup function, which named Watch Mode in MG82F6D17. When WDT overflows, set WDTF and wakeup CPU from interrupt or system reset by software configured. The maximum wakeup period is about 2 seconds that is defined by WDT pre-scaler. Please refer Section “10 Watch Dog Timer (WDT)” and Section “15 Interrupt” for more detail information. 13.2.5. Monitor Mode If AWBOD1 (PCON2.3) is set, BOD1 will keep VDD monitor in power down mode. It is the Monitor Mode in MG82F6D17. When BOD1 meets the detection level, set BOF1 and wakeup CPU from interrupt or system reset by software configured. Please refer Section “13.1 Brown-Out Detector” and Section “15 Interrupt” for more detail information. 13.2.6. Idle Mode Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator. The Port pins hold the logical states they had at the time that Idle was activated. Idle mode leaves the peripherals running in order to allow them to wake up the CPU when an interrupt is generated. Timer 0, Timer 1, Timer 2, Timer 3, DMA, SPI, KBI, ADC, S0, S1, TWI0/I2C0, RTC, MCD, BOD0 and BOD1 will continue to function during Idle mode. PCA Timer and WDT are conditional enabled during Idle mode to wake up CPU. Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI, the next instruction to be executed will be the one following the instruction that put the device into Idle. The ADC or analog comparator input channels must be set to “Analog Input Only” when MCU is in idle mode or power-down mode to reduce power consumption. 13.2.7. Power-down Mode Setting the PD bit in PCON0 enters Power-down mode. Power-down mode stops the oscillator and powers down the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to draw power during Power-down. During Power-down the power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be retained; however, the SFR contents are not guaranteed once VDD has been reduced. Power-down may be exited by external reset, power-on reset, enabled external interrupts, enabled KBI, enabled RTC (RTC mode), enabled BOD1 (monitor mode) or enabled Non-Stop WDT (watch mode). The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 μs until after one of the following conditions has occurred: Start of code execution (after any type of reset), or Exit from power -down mode. To ensure minimum power consumption in power down mode, software must confirm all I/O not in floating state

megawin Version: 1.00 75 13.2.8. Interrupt Recovery from Power-down Four external interrupts may be configured to terminate Power-down mode. External interrupts nINT0, nINT1, nINT2 and nINT3 may be used to exit Power-down. To wake up by external interrupt nINT0, nINT1, nINT2 or nINT3, the interrupt must be enabled and configured for level-sensitive operation. If the enabled external interrupts are configured to edge-sensitive operation (Falling or Rising), they will be forced to level-sensitive operation (Low level or High level) by hardware in power-down mode. When terminating Power-down by an interrupt, the wake up period is internally timed. At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be allowed to propagate and the CPU will not resume execution until after the timer has reached internal counter full. After the timeout period, the interrupt service routine will begin. To prevent the interrupt from re-triggering, the ISR should disable the interrupt before returning. The interrupt pin should be held low until the device has timed out and begun executing. 13.2.9. Reset Recovery from Power-down Wakeup from Power-down through an external reset is similar to the interrupt. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU until after the timer has reached internal counter full. The RST pin must be held high for longer than the timeout period to ensure that the device is reset properly. The device will begin executing once RST is brought low. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On- chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. 13.2.10. KBI wakeup Recovery from Power-down The Keypad Interrupt of MG82F6D17, KBI.7~0 have wakeup CPU capability that are enabled by the control registers in KBI module. OR software can configure the KBI inputs on different port pins. Please refer Section “30 Auxiliary SFRs” for more detailed AUXR6 information. Wakeup from Power-down through an enabled wakeup KBI is same to the interrupt. At the matched condition of enabled KBI pattern and enabled KBI interrupt (EIE1.5, EKB), Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU until after the timer has reached internal counter full. After the timeout period, CPU will meet a KBI interrupt and execute the interrupt service routine.

megawin Version: 1.00 76 13.3. Power Control Register PCON0: Power Control Register 0 SFR Page = 0~F & P SFR Address = 0x87 POR = 0001-0000, RESET = 000X-0000 7 6 5 4 3 2 1 0 SMOD1 SMOD0 GF POF0 GF1 GF0 PD IDL R/W R/W R/W R/W R/W R/W R/W R/W Bit 4: POF0, Power-On Flag 0. 0: This bit must be cleared by software writing one to it. 1: This bit is set by hardware if a Power-On Reset occurs. Bit 1: PD, Power-Down control bit. 0: This bit could be cleared by CPU or any exited power-down event. 1: Setting this bit activates power down operation. Bit 0: IDL, Idle mode control bit. 0: This bit could be cleared by CPU or any exited Idle mode event. 1: Setting this bit activates idle mode operation. PCON1: Power Control Register 1 SFR Page = 0~F & P SFR Address = 0x97 POR = 0000-x000 7 6 5 4 3 2 1 0 SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF R/W R/W W R/W W R/W R/W R/W Bit 7: SWRF, Software Reset Flag. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if a Software Reset occurs. Bit 6: EXRF, External Reset Flag. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if an External Reset occurs. Bit 4: RTCF, RTC overflow flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware when RTCCT overflows. Writing “1” on this bit will clear RTCF. Bit 3: Reserved. Software must write “0” on this bit when PCON1 is written. Bit 2: BOF1, Brown-Out Detection flag 1. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if the operating voltage matches the detection level of Brown-Out Detector 1 Bit 1: BOF0, Brown-Out Detection flag 0. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if the operating voltage matches the detection level of Brown-Out Detector 0 (1.7V). Bit 0: WDTF, WDT overflow flag. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if a WDT overflow occurs.

megawin Version: 1.00 77 PCON2: Power Control Register 2 SFR Page = P Only SFR Address = 0x44 POR = 0000-0101 7 6 5 4 3 2 1 0 AWBOD1 0 BO1S1 BO1S0 BO1RE EBOD1 BO0RE 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: AWBOD1, Awaked BOD1 in PD mode. 0: BOD1 is disabled in power-down mode. 1: BOD1 keeps operation in power-down mode. Bit 6: Reserved. Software must write “0” on this bit when PCON2 is written. Bit 5~4: BO1S[1:0]. Brown-Out detector 1 monitored level Selection. BO1S[1:0] BOD1 detecting level 0 0 2.0V 0 1 2.4V 1 0 3.7V 1 1 4.2V Bit 3: BO1RE, BOD1 Reset Enabled. 0: Disable BOD1 to trigger a system reset when BOF1 is set. 1: Enable BOD1 to trigger a system reset when BOF1 is set. Bit 2: EBOD1, Enable BOD1 that monitors VDD power dropped at a BO1S1~0 specified voltage level. 0: Disable BOD1 to slow down the chip power consumption. 1: Enable BOD1 to monitor VDD power dropped. Bit 1: BO0RE, BOD0 Reset Enabled. 0: Disable BOD0 to trigger a system reset when BOF0 is set. 1: Enable BOD0 to trigger a system reset when BOF0 is set (VDD meets 1.7V). Bit 0: Reserved. Software must write “1” on this bit when PCON2 is written. PCON3: Power Control Register 3 SFR Page = P Only SFR Address = 0x45 POR = 0000-0000 7 6 5 4 3 2 1 0 IVREN 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: IVREN, Internal Voltage Reference Enable. 0: Disable on-chip IVR (1.4V). 1: Enable on-chip IVR (1.4V). Bit 6~0: Reserved. Software must write “0” on these bits when PCON3 is written.

megawin Version: 1.00 78 14. Configurable I/O Ports depends upon the package types. See Table 14–1. Table 14–1. Number of I/O Pins Available Package Type I/O Pins Number of I/O ports 17 or 16 (RST selected) 14.1. IO Structure The I/O operating modes are distinguished two groups in MG82F6D17. The first group is only for Port 3 to support four configurations on I/O operating. These are: quasi-bidirectional (standard 8051 I/O port), push-pull output, input-only (high-impedance input) and open-drain output. The Port 3 default setting is quasi-bidirectional mode with weakly pull-up resistance. All other general port pins belong to the second group. They can be programmed to four operating modes, which include analog input only, open-drain output with pull-up resistor, open-drain output and push-pull output. The default setting of this group I/O is analog input only, which means the port pin in high impedance state. Following sections describe the configuration of the all types I/O mode. 14.1.1. Port 3 Quasi-Bidirectional IO Structure Port 3 pins in quasi-bidirectional mode are similar to the standard 8051 port pins. A quasi-bidirectional port can be used as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin outputs low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes. One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port register for the pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the pin high if it is left floating. A second pull-up, called the “weak” pull-up, is turned on when the port register for the pin contains a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by the external device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to over -power the weak pull-up and pull the port pin below its input threshold voltage. The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port register changes from a logic “0” to a logic “1”. When this occurs, the strong pull-up turns on for one CPU clocks, quickly pulling the port pin high.

megawin Version: 1.00 82 14.1.9. General Push-Pull Output Structure The push-pull output configuration on general port pins has the same function with port 3 push- pull output mode. The push-pull port configuration is shown in Figure 14–8. Figure 14–8. General Push-Pull Output 14.1.10. Port Pin Output Driving Strength Selection The I/O of the MG82F6D17 has two driving strength can be selected for different kinds of the application to match the output impedance. Please reference 14.2.6 Port Output Driving Strength Control Register. 14.1.11. Port Pin Output Fast Driving Selection The I/O of the MG82F6D17 has two driving speed can be selected for different kinds of the I/O frequency. Please reference 14.2.7 Port Output Fast Driving Control Register Port Pin Strong Input data Port latch data VDD

megawin Version: 1.00 83 14.2. I/O Port Register All I/O port pins on the MG82F6D17 may be individually and independently configured by software to select its operating modes. Port 3 has four operating modes, as shown in Table 14–2. Two mode registers select the output type for each port 3 pin. Only Port 3 supports quasi-bidirectional mode and setting them to quasi-bidirectional mode after system reset. Table 14–2. Port 3 Configuration Settings P3M0.y P3M1.y Port Mode 0 0 Quasi-Bidirectional (default) 0 1 Push-Pull Output 1 0 Input Only (High Impedance Input) 1 1 Open-Drain Output Where y=0~7 (port pin). The registers P3M0 and P3M1 are listed in each port description. Other general port pins also support four operating modes, as shown in Table 14–3. Two mode registers select the I/O type for each port pin and setting to analog-input-only on these port pins after system reset. Table 14–3. General Port Configuration Settings PxM0.y PxM1.y Port Mode 0 1 Analog Input Only (default) 1 1 Open-Drain with Pull-up resistor 0 0 Open-Drain Output / General Digital Input (Port Pin set to “1”) 1 0 Push-Pull Output Where x= 0, 1, 2, 4, 6 (port number), and y=0~7 (port pin). The registers PxM0 and PxM1 are listed in each port

description

14.2.1. Port 1 Register P1: Port 1 Register SFR Page = 0~F SFR Address = 0x90 RESET = 1111-1111 7 6 5 4 3 2 1 0 R/W R/W R/W W W W R/W R/W Bit 7, 6, 5, 1,0: Port 1 output data latch could be only set/cleared by CPU. P1M0: Port 1 Mode Register 0 SFR Page = 0~F SFR Address = 0x91 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W W W W R/W R/W P1M1: Port 1 Mode Register 1 SFR Page = 0 only SFR Address = 0x92 RESET = 1111-1111 7 6 5 4 3 2 1 0 R/W R/W R/W W W W R/W R/W

megawin Version: 1.00 84 14.2.2. Port 2 Register P2: Port 2 Register SFR Page = 0~F SFR Address = 0xA0 RESET = 1111-1111 7 6 5 4 3 2 1 0 W W W R/W W R/W W W Bit 4, 2: Port 2 output data latch could be only set/cleared by CPU. P2M0: Port 2 Mode Register 0 SFR Page = 0 only SFR Address = 0x95 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W W R/W W R/W W W P2M1: Port 2 Mode Register 1 SFR Page = 1 only SFR Address = 0x92 RESET = 1111-1111 7 6 5 4 3 2 1 0 W W W R/W W R/W W W 14.2.3. Port 3 Register P3: Port 3 Register SFR Page = 0~F SFR Address = 0xB0 RESET = 1111-1111 7 6 5 4 3 2 1 0 W W R/W R/W R/W W R/W R/W Bit 7~0: Port 3 output data latch could be only set/cleared by CPU. P3M0: Port 3 Mode Register 0 SFR Page = 0~F SFR Address = 0xB1 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W R/W R/W R/W W R/W R/W P3M1: Port 3 Mode Register 1 SFR Page = 0~F SFR Address = 0xB2 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W R/W R/W R/W W R/W R/W AUXR11: Auxiliary Register 11 SFR Page = 8 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 P30AM -- -- -- -- -- C0M0 C0OFS R/W W W W W W R/W R/W Bit 7: P30AM, P3.0 Analog input Mode enable. 0: The P3.0 GPIO mode is controlled by P3M0 and P3M1. 1: Force P3.0 to be analog input mode for the AIN4 input of ADC12.

megawin Version: 1.00 85 14.2.4. Port 4 Register P4: Port 4 Register SFR Page = 0~F SFR Address = 0xE8 RESET = 1x11-xx11 7 6 5 4 3 2 1 0 R/W W R/W R/W W W W W Bit 7~0: Port 4 output data latch could be set/cleared by CPU. P4.5 and P4.4 have the alternated function for OCD_SDA and OCD_SCL. Due to MG82F6D17AS8 SOP8 not support OCD_ICE, it needs to disable OCD_SDA and OCD_SCL by firmware when using MG82F6D17AS8 SOP8. P4.7 has the alternated function for RST input. P4M0: Port 4 Mode Register 0 SFR Page = 0 only SFR Address = 0xB3 RESET = 1011-0000 7 6 5 4 3 2 1 0 W W R/W R/W W W W W P4M1: Port 4 Mode Register 1 SFR Page = 2 only SFR Address = 0x92 RESET = 1111-1111 7 6 5 4 3 2 1 0 R/W W R/W R/W W W W W 14.2.5. Port 6 Register P6: Port 6 Register SFR Page = 1 only SFR Address = 0xF8 RESET = xxx1-1111 7 6 5 4 3 2 1 0 W W W W W W R/W R/W Bit 1~0: Port 6 output data latch could be only set/cleared by CPU. P6M0: Port 6 Mode Register 0 SFR Page = 1 only SFR Address = 0xB5 RESET = xxx0-0000 7 6 5 4 3 2 1 0 W W W W W W R/W R/W P6M1: Port 6 Mode Register 1 SFR Page = 3 only SFR Address = 0x92 RESET = 1111-1111 7 6 5 4 3 2 1 0 W W W W W W R/W R/W

megawin Version: 1.00 86 14.2.6. Port Output Driving Strength Control Register In MG82F6D17, all port pins have two driving strength selection by software configured except P4.7, P6.1 and P6.0. Please refer to get the driving strength information on the port pins. PDRVC0: Port Drive Control Register 0 SFR Page = 2 only SFR Address = 0xB4 RESET = 0000-0000 7 6 5 4 3 2 1 0 P3DC1 P3DC0 P2DC1 P2DC0 P1DC1 P1DC0 -- -- R/W R/W R/W R/W R/W R/W W W Bit 7: P3DC1, Port 3 output driving strength control on high nibble. 0: Select the P3.7 ~ P3.4 output with high driving strength. 1: Select the P3.7 ~ P3.4 output with low driving strength. Bit 6: P3DC0, Port 3 output driving strength control on low nibble. 0: Select the P3.3 ~ P3.0 output with high driving strength. 1: Select the P3.3 ~ P3.0 output with low driving strength. Bit 5: P2DC1, Port 2 output driving strength control on high nibble. 0: Select the P2.7 ~ P2.4 output with high driving strength. 1: Select the P2.7 ~ P2.4 output with low driving strength. Bit 4: P2DC0, Port 2 output driving strength control on low nibble. 0: Select the P2.3 ~ P2.0 output with high driving strength. 1: Select the P2.3 ~ P2.0 output with low driving strength. Bit 3: P1DC1, Port 1 output driving strength control on high nibble. 0: Select the P1.7 ~ P1.4 output with high driving strength. 1: Select the P1.7 ~ P1.4 output with low driving strength. Bit 2: P1DC0, Port 1 output driving strength control on low nibble. 0: Select the P1.3 ~ P1.0 output with high driving strength. 1: Select the P1.3 ~ P1.0 output with low driving strength. PDRVC1: Port Drive Control Register 1 SFR Page = 3 only SFR Address = 0xB4 RESET = xxx0-xx00 7 6 5 4 3 2 1 0 W W W W W W RW W Bit 7~2: Reserved. Software must write “0” on these bits when PDRVC1 is written. Bit 1: P4DC1, Port 4 output driving strength control on high nibble. 0: Select the P4.6 ~ P4.4 output with high driving strength. 1: Select the P4.6 ~ P4.4 output with low driving strength.

megawin Version: 1.00 87 14.2.7. Port Output Fast Driving Control Register In MG82F6D17, all port pins have two driving speed selection by software configured except P4.7. Please refer to get the driving strength information on the port pins. P3FDC: Port 3 Fast Driving Control Register SFR Page = 7 only SFR Address = 0x92 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W R/W R/W R/W W RW RW Bit 7~0: Port 3 output fast driving control could be only set/cleared by CPU. 0: Disable fast driving on port pin output. 1: Enable fast driving on port pin output. P1FDC: Port 1 Fast Driving Control Register SFR Page = 8 only SFR Address = 0x92 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W W W W RW RW Bit 7~0: Port 1 output fast driving control could be only set/cleared by CPU. 0: Disable fast driving on port pin output. 1: Enable fast driving on port pin output. P2FDC: Port 2 Fast Driving Control Register SFR Page = 9 only SFR Address = 0x92 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W W R/W W R/W W W Bit 7~0: Port 2 output fast driving control could be only set/cleared by CPU. 0: Disable fast driving on port pin output. 1: Enable fast driving on port pin output. P4FDC: Port 4 Fast Driving Control Register SFR Page = A only SFR Address = 0x92 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W R/W R/W W W W W Bit 6~0: Port 4 output fast driving control could be only set/cleared by CPU. 0: Disable fast driving on port pin output. 1: Enable fast driving on port pin output.

megawin Version: 1.00 88 15. Interrupt The MG82F6D17 has 16 interrupt sources with a four-level interrupt structure. There are several SFRs associated with the four-level interrupt. They are the IE, IP0L, IP0H, EIE1, EIP1L, EIP1H, EIE2, EIP2L, EIP2H and XICON. The IP0H (Interrupt Priority 0 High), EIP1H (Extended Interrupt Priority 1 High) and EIP2H (Extended Interrupt Priority 2 High) registers make the four-level interrupt structure possible. The four priority level interrupt structure allows great flexibility in handling these interrupt sources. 15.1. Interrupt Structure Table 15–1 lists all the interrupt sources. The ‘Request Bits’ are the interrupt flags that will generate an interrupt if it is enabled by setting the ‘Enable Bit’. Of course, the global enable bit EA (in IE0 register) should have been set previously. The ‘Request Bits’ can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software. The ‘Priority Bits’ determine the priority level for each interrupt. The ‘Priority within Level’ is the polling sequence used to resolve simultaneous requests of the same priority level. The ‘Vector Address’ is the entry point of an interrupt service routine in the program memory. Figure 15–1 shows the interrupt system. Each of these interrupts will be briefly described in the following sections. Table 15–1. Interrupt Sources No Source Name Enable Bit Request Bits Priority Bits Polling Priority Vector Address #0 External Interrupt 0, nINT0 EX0 IE0 [ PX0H, PX0L ] (Highest) 0003H #1 Timer 0 ET0 TF0 [ PT0H, PT0L ] … 000Bh #2 External Interrupt 1, nINT1 EX1 IE1 [ PX1H, PX1L ] … 0013H #3 Timer 1 ET1 TF1 [ PT1H, PT1L ] … 001BH #4 Serial Port 0 ES0 RI0, TI0 [ PS0H, PS0L ] … 0023H #5 Timer 2 ET2 TF2, EXF2 (TF2L) [ PT2H, PT2L ] … 002Bh #6 External Interrupt 2, nINT2 EX2 IE2 [ PX2H, PX2L ] … 0033H #7 SPI ESPI SPIF [ PSPIH, PSPIL ] … 003BH #8 ADC EADC ADCI, ADCWI, SMPF [ PADCH, PADCL ] … 0043H #9 PCA0 EPCA CF, CCFn (n=0~7) [ PPCAH, PPCAL ] … 004Bh #10 System Flag ESF (Note 1) [ PSFH, PSFL ] … 0053H #11 Keypad Interrupt EKB KBIF [ PKBH, PKBL ] … 005BH #12 TWI0/I2C0 ETWI0 SI [ PTWI0H, PTWI0L ] … 0063H #13 Reserved -- -- -- -- 006BH #14 Serial Port 1 ES1 RI1, TI1 [ PS1H, PS1L ] … 0073H #15 Reserved -- -- -- -- 007BH #16 Timer 3 ET3 TF3, EXF3 (TF3L) [ PT3H, PT3L ] … 0083H #17 Reserved -- -- -- -- 008BH #18 DMA EDMA (Note 2) [PDMAH, PDMAL] (Lowest) 0093H Note 1: The System Flag interrupt flags include: WDTF, BOF0, BOF1 and RTCF in PCON1, TI0 in S0CON, STAF and STOF in AUXR2. Note 2: The DMA interrupt flags include: DCF0, TF5 and TF6.

megawin Version: 1.00 89 Figure 15–1. Interrupt System INT0ET INT1ET TCON.TF0 TCON.TF1 S0CON.RI0 S0CON.TI0 IP0L,IP0H,EIP1L, EIP1H,EIP2L,EIP2H Registers Highest Priority Level Interrupt Lowest Priority Level Interrupt Interrupt Polling Sequence Global Enable (IE.EA) IE.EX0 IE.ET0 IE.EX1 IE.ET1 IE.ES0 XICON.EX2 INT2ET IE2 IE0 IE1 ADCON0.ADCI TCON.IT0 TCON.IT1 XICON.IT2 EIE1.ESPI SPSTAT.SPIF EIE1.EADC EIE1.ESF EIE1.ES1 EIE1.EKB T2CON.TF2 T2CON.EXF2 IE.ET2 EIE1.EPCA S1CON.RI1 S1CON.TI1 KBCON.KBIF EIE1.ETWI0 SICON.SI Stystem Flags T3CON.TF3 T3CON.EXF3 EIE2.ET3 PCA0 Interrupt Flags IE.EDMA DMA Flags

megawin Version: 1.00 90 15.2. Interrupt Source Table 15–2. Interrupt Source Flag No Source Name Request Bits Bit Location #0 External Interrupt 0,nINT0 IE0 TCON.1 #1 Timer 0 TF0 TCON.5 #2 External Interrupt 1,nINT1 IE1 TCON.3 #3 Timer 1 TF1 TCON.7 #4 Serial Port 0 RI0, TI0 S0CON.0 S0CON.1 #5 Timer 2 TF2, EXF2, (TF2L) T2CON.7 T2CON.6 T2CON.5 #6 External Interrupt 2,nINT2 IE2 XICON.1 #7 SPI SPIF SPSTAT.7 #8 ADC ADCI, ADCWI, SMPF ADCON0.4 ADCON0.6 ADCFG0.2 #9 PCA0 CF, CCFn (n=0~5), CCFn (n=6~7) CCON.7 CCON.5~0 PCAPWMn.3 #10 System Flag W DTF, BOF1, BOF0, RTCF, STAF, STOF, BM0F, BM1F, (TI0) PCON1.0 PCON1.1 PCON1.2 PCON1.4 AUXR2.7 AUXR2.6 AUXR0.2 AUXR0.3 S0CON.1 #11 Keypad Interrupt KBIF KBCON.0 #12 TWI0/I2C0 SI SICON.3 #13 Reserved -- -- #14 Serial Port 1 RI1, TI1 S1CON.0 S1CON.1 #15 Reserved -- -- #16 Timer 3 TF3, EXF3, (TF3L) T3CON.7 T3CON.6 T3CON.5 #17 Reserved -- -- #18 DMA DCF0 TF5 TF6 DMACR0.0 T5CON.7 T6CON.7 The external interrupt nINT0, nINT1 and nINT2 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in register TCON and IT2 in register XICON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON and IE2 in XICON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition – activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware. The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. The serial port 0 interrupt is generated by the logical OR of RI0 and TI0. Neither of these flags is cleared by hardware

megawin Version: 1.00 91 when the service routine is vectored to. The service routine should poll RI0 and TI0 to determine which one to request service and it will be cleared by software. The serial port 1 interrupt is generated by the logical OR of RI1 and TI1. Neither of these flags is cleared by hardware when the service routine is vectored to. The service routine should poll RI1 and TI1 to determine which one to request service and it will be cleared by software. The timer2 interrupt is generated by the logical OR of TF2 and EXF2. If the timer 2 in split mode, the TL2 overflow will set another interrupt flag, TF2L. Just the same as serial port, neither of these flags is cleared by hardware when the service routine is vectored to. The timer3 interrupt is generated by the logical OR of TF3 and EXF3. If the timer 3 in split mode, the TL3 overflow will set another interrupt flag, TF3L. Just the same as serial port, neither of these flags is cleared by hardware when the service routine is vectored to. SPI interrupt is generated by SPIF in SPSTAT, which are set by SPI engine finishes a SPI transfer. It will not be cleared by hardware when the service routine is vectored to. The ADC interrupt is generated by ADCI in ADCON0. It will not be cleared by hardware when the service routine is vectored to. The PCA0 interrupt is generated by the logical OR of CF, CCF5, CCF4, CCF3, CCF2, CCF1 and CCF0 in CCON. Neither of these flags is cleared by hardware when the service routine is vectored to. The service routine should poll these flags to determine which one to request service and it will be cleared by software. The System Flag interrupt is generated by RTCF, BOF1, BOF0, WDTF, TI0, STAF and STOF. STAF and STOF are set by serial interface detection and stored in AUXR2. The Serial Port TI flag is optional to locate the interrupt vector shared with system flag interrupt which is enabled by UTIE set. The rest flags are stored in PCON1. RTCF is set by RTC counter overflow. BOF1 and BOF0 are set by on chip Brownout-Detector (BOD1 and BOD0) met the low voltage event. WDTF is set by Watch-Dog-Timer overflow. These flags will not be cleared by hardware when the service routine is vectored to. Figure 15–2 shows the system flag interrupt configuration. Figure 15–2. System flag interrupt configuration The keypad interrupt is generated by KBCON.KBIF, which is set by Keypad module meets the input pattern. It will not be cleared by hardware when the service routine is vectored to. The TWI0/ I2C0 interrupt is generate by SI in SICON, which is set by TWI0/ I2C0 engine detecting a new bus state updated. It will not be cleared by hardware when the service routine is vectored to. All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. In other words, interrupts can be generated or pending interrupts can be canceled in software. PCON1.BOF0 EIE1.ESF SFIE.BOF0IE PCON1.BOF1 SFIE.BOF1IE PCON1.WDTF SFIE.WDTFIE PCON1.RTCF SFIE.RTCFIE System Flag Interrupt S0CON.TI0 S0CFG.UTIE AUXR2.STAF AUXR2.STOF SFIE.SIDFIE

megawin Version: 1.00 92 15.3. Interrupt Enable Table 15–3. Interrupt Enable No Source Name Enable Bit Bit Location #0 External Interrupt 0,nINT0 EX0 IE.0 #1 Timer 0 ET0 IE.1 #2 External Interrupt 1,nINT1 EX1 IE.2 #3 Timer 1 ET1 IE.3 #4 Serial Port 0 ES0 IE.4 #5 Timer 2 ET2 IE.5 #6 External Interrupt 2,nINT2 EX2 XICON.2 #7 SPI ESPI EIE1.0 #8 ADC EADC EIE1.1 #9 PCA EPCA EIE1.2 #10 System Flag ESF EIE1.3 #11 Keypad Interrupt EKB EIE1.5 #12 TWI0/I2C0 ETWI0 EIE1.6 #13 Reserved -- -- #14 Serial Port 1 ES1 EIE1.4 #15 Reserved -- -- #16 Timer 3 ET3 EIE2.0 #17 Reserved -- -- #18 DMA EDMA IE.6 There are 16 interrupt sources available in MG82F6D17. Each of these interrupt sources can be individually enabled or disabled by setting or clearing an interrupt enable bit in the registers IE, EIE1, EIE2 and XICON. IE also contains a global disable bit, EA, which can be cleared to disable all interrupts at once. If EA is set to ‘1’, the interrupts are individually enabled or disabled by their corresponding enable bits. If EA is cleared to ‘0’, all interrupts are disabled.

megawin Version: 1.00 93 15.4. Interrupt Priority The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80C51. The Priority Bits (see Table 15–1) determine the priority level of each interrupt. IP0L, IP0H, EIP1L, EIP1H, EIP2L and EIP2H are combined to 4-level priority interrupt. Table 15–4 shows the bit values and priority levels associated with each combination. Table 15–4. Interrupt Priority {IPnH.x , IPnL.x} Priority Level 11 1 (highest) 10 2 01 3 00 4 Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPnH and the other in IPnL register. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine which request is serviced. Table 15–2 shows the internal polling sequence in the same priority level and the interrupt vector address. 15.5. Interrupt Process Each interrupt flag is sampled at every system clock cycle. The samples are polled during the next system clock. If one of the flags was in a set condition at first cycle, the second cycle (polling cycle) will find it and the interrupt system will generate an hardware LCALL to the appropriate service routine as long as it is not blocked by any of the following conditions. Block conditions:  An interrupt of equal or higher priority level is already in progress.  The current cycle (polling cycle) is not the final cycle in the execution of the instruction in progress.  The instruction in progress is RETI or any write to the IE, IP0L, IPH, EIE1, EIP1L, EIP1H, EIE2, EIP2L, EIP2H and XICON registers. Any of these three conditions will block the generation of the hardware LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine. Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one or more instruction will be executed before any interrupt is vectored to.

megawin Version: 1.00 94 15.6. nINTx Input Source Selection and input filter (x=0~2) The MG82F6D17 provides flexible nINT0, nINT1 and nINT2 source selection to share the port pin inputs… Figure 15–3. Configuration of nINT0~2 port pin selection nINT0 input IE0 INT0H (AUXR0.0) IT0 = 1 (TCON.0) INT0IS.2~0 (TCON.1) IT0 = 0 IE1 IT1 = 1 (TCON.2) (TCON.3) IT1 = 0 nINT1 input INT1H (AUXR0.1) INT1IS.2~0 nINTx input (low/falling trigger) INTxET input Sampling Timing Operating Example of nINTx Input Filter (x = 0~2) clock Filter {X0FLT1,X0FLT} (XICFG1.0, XICFG.0) SYSCLK x 3 SYSCLK/6 x 3 S0TOF x 3 SYSCLK SYSCLK Sampling Type Selection clock Filter {X1FLT1,X1FLT} (XICFG1.1, XICFG.1) SYSCLK x 3 SYSCLK/6 x 3 S0TOF x 3 SYSCLK SYSCLK INT0ET, low active, to internal logic IEx when ITx=1 Set by hardware Clear by software (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) INT1ET, low active, to internal logic S0TOF IE2 IT2 = 1 (XICON.0) (XICON.1) IT2 = 0 nINT2 input INT2H (XICON.3) P4.4 P3.0 P1.1 INT2IS.1~0 P1.6 clock Filter {X2FLT1,X2FLT} (XICFG1.2, XICFG.2) SYSCLK x 3 SYSCLK/6 x 3 S0TOF x 3 SYSCLK SYSCLK (0,0) (0,1) (1,0) (1,1) S0TOF INT2ET, low active, to internal logic S0TOF P4.5 P3.0 P3.4 P4.7 P6.0 P1.1 P1.7 P2.2 P3.3 P3.1 P3.5 P1.0 P6.1 P3.4 P1.5 P2.4

megawin Version: 1.00 95 15.7. Interrupt Register TCON: Timer/Counter Control Register SFR Page = 0~F SFR Address = 0x88 RESET = 0000-0000 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 3: IE1, Interrupt 1 (nINT1) Edge flag. 0: Cleared when interrupt processed on if transition-activated. 1: Set by hardware when external interrupt 1 (nINT1) edge is detected (transmitted or level-activated). Bit 2: IT1: Interrupt 1 (nINT1) Type control bit. 0: Cleared by software to specify low level triggered external interrupt 1 (nINT1). If INT1H (AUXR0.1) is set, this bit specifies high level triggered on nINT1. 1: Set by software to specify falling edge triggered external interrupt 1 (nINT1). If INT1H (AUXR0.1) is set, this bit specifies rising edge triggered on nINT1. Bit 1: IE0, Interrupt 0 (nINT0) Edge flag. 0: Cleared when interrupt processed on if transition-activated. 1: Set by hardware when external interrupt 0 (nINT0) edge is detected (transmitted or level-activated). Bit 0: IT0: Interrupt 0 (nINT0) Type control bit. 0: Cleared by software to specify low level triggered external interrupt 0 (nINT0). If INT0H (AUXR0.0) is set, this bit specifies high level triggered on nINT0. 1: Set by software to specify falling edge triggered external interrupt 0 (nINT0). If INT0H (AUXR0.0) is set, this bit specifies rising edge triggered on nINT0. IE: Interrupt Enable Register SFR Page = 0~F SFR Address = 0xA8 RESET = 0X00-0000 7 6 5 4 3 2 1 0 EA EDMA ET2 ES0 ET1 EX1 ET0 EX0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: EA, All interrupts enable register. 0: Global disables all interrupts. 1: Global enables all interrupts. Bit 6: EDMA, DMA group interrupt enable register. 0: Disable DMA group interrupt. 1: Enable DMA group interrupt. Bit 5: ET2, Timer 2 interrupt enable register. 0: Disable Timer 2 interrupt. 1: Enable Timer 2 interrupt. Bit 4: ES, Serial port 0 interrupt (UART0) enable register. 0: Disable serial port 0 interrupt. 1: Enable serial port 0 interrupt. Bit 3: ET1, Timer 1 interrupt enable register. 0: Disable Timer 1 interrupt. 1: Enable Timer 1 interrupt. Bit 2: EX1, External interrupt 1 (nINT1) enable register. 0: Disable external interrupt 1. 1: Enable external interrupt 1.

megawin Version: 1.00 96 Bit 1: ET0, Timer 0 interrupt enable register. 0: Disable Timer 0 interrupt. 1: Enable Timer 1 interrupt. Bit 0: EX0, External interrupt 0 (nINT0) enable register. 0: Disable external interrupt 0. 1: Enable external interrupt 1. AUXR0: Auxiliary Register 0 SFR Page = 0~F SFR Address = 0xA1 RESET = 0000-0000 7 6 5 4 3 2 1 0 P60OC1 P60OC0 P60FD PBKF -- -- INT1H INT0H R/W R/W R/W R/W W W R/W R/W Bit 4: PBKF, PWM Break Flag. This bit is set by PWM break source enabled. If this flag is set, the enabled PWM channel 0~5 will be blocked and the output pins keep the original GPIO state. 0: There is no PWM Break event happened. It is only cleared by software. 1: There is a PWM Break event happened or software triggers a PWM Break. Bit 1: INT1H, INT1 High/Rising trigger enable. 0: Remain INT1 triggered on low level or falling edge on selected port pin input. 1: Set INT1 triggered on high level or rising edge on selected port pin input. Bit 0: INT0H, INT0 High/Rising trigger enable. 0: Remain INT0 triggered on low level or falling edge on selected port pin input. 1: Set INT0 triggered on high level or rising edge on selected port pin input. XICON: External Interrupt Control Register SFR Page = 0~F SFR Address = 0xC0 RESET = xxxx-0000 7 6 5 4 3 2 1 0 -- -- -- -- INT2H EX2 IE2 IT2 W W W W R/W R/W R/W R/W Bit 3: INT2H, nINT2 High/Rising trigger enable. 0: Maintain nINT2 triggered on low level or falling edge on selected port pin input . 1: Set nINT2 triggered on high level or rising edge on selected port pin input. Bit 2: EX2, external interrupt 2 (nINT2) enable register. 0: Disable external interrupt 2. 1: Enable external interrupt 2. When CPU in IDLE and PD mode, nINT2 event will trigger IE2 and have wake- up CPU capability if EX2 is enabled. If EX2 is disabled, IE2 on nINT2 will not wake-up CPU from IDLE or PD mode. Bit 1: IE2, External interrupt 2 (nINT2) Edge flag. 0: Cleared by hardware when the interrupt is starting to be serviced. It also could be cleared by CPU. 1: Set by hardware when external interrupt edge detected. It also could be set by CPU. Bit 0: IT2, Interrupt 2 type control bit. 0: Cleared by CPU to specify low level triggered on nINT2. If INT2H is set, this bit specifies high level triggered on nINT2. 1: Set by CPU to specify falling edge triggered on nINT2. If INT2H is set, this bit spec ifies rising edge triggered on nINT2.

megawin Version: 1.00 97 IP0L: Interrupt Priority 0 Low Register SFR Page = 0~F SFR Address = 0xB8 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- PX2L PT2L PSL PT1L PX1L PT0L PX0L W R/W R/W R/W R/W R/W R/W R/W Bit 6: PX2L, external interrupt 2 priority-L register. Bit 5: PT2L, Timer 2 interrupt priority-L register. Bit 4: PSL, Serial port interrupt priority-L register. Bit 3: PT1L, Timer 1 interrupt priority-L register. Bit 2: PX1L, external interrupt 1 priority-L register. Bit 1: PT0L, Timer 0 interrupt priority-L register. Bit 0: PX0L, external interrupt 0 priority-L register. IP0H: Interrupt Priority 0 High Register SFR Page = 0~F SFR Address = 0xB7 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- PX2H PT2H PSH PT1H PX1H PT0H PX0H W R/W R/W R/W R/W R/W R/W R/W Bit 6: PX2H, external interrupt 2 priority-H register. Bit 5: PT2H, Timer 2 interrupt priority-H register. Bit 4: PSH, Serial port interrupt priority-H register. Bit 3: PT1H, Timer 1 interrupt priority-H register. Bit 2: PX1H, external interrupt 1 priority-H register. Bit 1: PT0H, Timer 0 interrupt priority-H register. Bit 0: PX0H, external interrupt 0 priority-H register. EIE1: Extended Interrupt Enable 1 Register SFR Page = 0~F SFR Address = 0xAD RESET = 0000-0000 7 6 5 4 3 2 1 0 -- ETWI0 EKB ES1 ESF EPCA EADC ESPI W R/W R/W R/W R/W R/W R/W R/W Bit 6: ETWI0, Enable TWI0/ I2C0 interrupt. 0: Disable TWI0/ I2C0 interrupt. 1: Enable TWI0/ I2C0 interrupt. Bit 5: EKBI, Enable Keypad Interrupt. 0: Disable the interrupt when KBCON.KBIF is set in Keypad control module. 1: Enable the interrupt when KBCON.KBIF is set in Keypad control module. Bit 4: ES1, Enable Serial Port 1 (UART1) interrupt. 0: Disable Serial Port 1 interrupt. 1: Enable Serial Port 1 interrupt. Bit 3: ESF, Enable System Flag interrupt. 0: Disable the interrupt when the group of {RTCF, BOF1, BOF0, WDTF} in PCON1, {STAF, STOF} in AUXR2, {BM1F, BM0F} in AUXR0, or TI0 with UTIE is set. 1: Enable the interrupt of the flags of { RTCF, BOF1, BOF0, WDTF} in PCON1, {STAF, STOF} in AUXR2, {BM1F, BM0F} in AUXR0, or TI0 with UTIE when the associated system flag interrupt is enabled in SFIE. Bit 2: EPCA, Enable PCA0 interrupt. 0: Disable PCA0 interrupt. 1: Enable PCA0 interrupt.

megawin Version: 1.00 98 Bit 1: EADC, Enable ADC Interrupt. 0: Disable the interrupt when ADCON0.ADCI is set in ADC module. 1: Enable the interrupt when ACCON0.ADCI is set in ADC module. Bit 0: ESPI, Enable SPI Interrupt. 0: Disable the interrupt when SPSTAT.SPIF is set in SPI module. 1: Enable the interrupt when SPSTAT.SPIF is set in SPI module. EIP1L: Extended Interrupt Priority 1 Low Register SFR Page = 0~F SFR Address = 0xAE RESET = 0000-0000 7 6 5 4 3 2 1 0 -- PTWI0L PKBL PS1L PSFL PPCAL PADCL PSPIL W R/W R/W R/W R/W R/W R/W R/W Bit 6: PTWI0L, TWI0/ I2C0 interrupt priority-L register. Bit 5: PKBL, keypad interrupt priority-L register. Bit 4: PS1L, UART1 interrupt priority-L register. Bit 3: PSFL, system flag interrupt priority-L register. Bit 2: PPCAL, PCA0 interrupt priority-L register. Bit 1: PADCL, ADC interrupt priority-L register. Bit 0: PSPIL, SPI interrupt priority-L register. EIP1H: Extended Interrupt Priority 1 High Register SFR Page = 0~F SFR Address = 0xAF RESET = 0000-0000 7 6 5 4 3 2 1 0 -- PTWI0H PKBH PS1H PSFH PPCAH PADCH PSPIH W R/W R/W R/W R/W R/W R/W R/W Bit 6: PTWI0H, TWI0/ I2C0 interrupt priority-H register. Bit 5: PKBH, keypad interrupt priority-H register. Bit 4: PS1H, UART1 interrupt priority-H register. Bit 3: PSFH, system flag interrupt priority-H register. Bit 2: PPCAH, PCA0 interrupt priority-H register. Bit 1: PADCH, ADC interrupt priority-H register. Bit 0: PSPIH, SPI interrupt priority-H register. EIE2: Extended Interrupt Enable 2 Register SFR Page = 0~F SFR Address = 0xA5 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W W W W W W R/W Bit 7~1: Reserved. Software must write “0” on these bits when EIE2 is written. Bit 0: ET3, Timer 3 interrupt enable register. 0: Disable Timer 3 interrupt. 1: Enable Timer 3 interrupt. EIP2L: Extended Interrupt Priority 2 Low Register SFR Page = 0~F SFR Address = 0xA6 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W W W W W W R/W Bit 7~1: Reserved. Software must write “0” on these bits when EIP2L is written. Bit 0: PT3L, Timer 3 interrupt priority-L register.

megawin Version: 1.00 99 EIP2H: Extended Interrupt Priority 2 High Register SFR Page = 0~F SFR Address = 0xA7 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W W W W W W R/W Bit 7~1: Reserved. Software must write “0” on these bits when EIP2H is written. Bit 0: PT3H, Timer 3 interrupt priority-H register. DMACG0: DMA ConfiGuration Register 0 SFR Page = 8 only SFR Address = 0x94 RESET = 0000-0000 7 6 5 4 3 2 1 0 PDMAH PDMAL CRCW0 -- EXTS10 EXTS00 FAEN0 LOOP0 R/W R/W R/W W R/W R/W R/W R/W Bit 7: PDMAH, DMA group interrupt priority-H register. Bit 6: PDMAL, DMA group interrupt priority-L register. XICFG: External Interrupt Configured Register SFR Page = 0 only SFR Address = 0xC1 RESET = 0000-0000 7 6 5 4 3 2 1 0 INT1IS.1 INT1IS.0 INT0IS.1 INT0IS.0 -- X2FLT X1FLT X0FLT R/W R/W R/W R/W W R/W R/W R/W Bit 7~6: INT1IS.1~0, nINT1 input port pin selection bits which function is defined with INT1IS.2 as following table. INT1IS.2~0 Selected Port Pin of nINT1 000 P3.3 001 P3.1 010 P3.5 011 P1.0 100 P6.1 101 P3.4 110 P1.5 111 P2.4 Bit 5~4: INT0IS.1~0, nINT0 input port pin selection bits which function is defined with INT0IS.2 as following table. INT0IS.2~0 Selected Port Pin of nINT0 000 P4.5 001 P3.0 010 P3.4 011 P4.7 100 P6.0 101 P1.1 110 P1.7 111 P2.2 Bit 2: X2FLT, nINT2 Filter mode control. It selects nINT2 input filter mode with X2FLT1 (XICFG1.2) X2FLT1, X2FLT nINT2 input filter mode

00 Disabled

01 SYSCLK x 3

10 SYSCLK/6 x 3

11 S0TOF x 3

megawin Version: 1.00 100 Bit 1: X1FLT, nINT1 Filter mode control. It selects nINT1 input filter mode with X1FLT1 (XICFG1.1) X1FLT1, X1FLT nINT1 input filter mode Bit 0: X0FLT, nINT0 Filter mode control. It selects nINT0 input filter mode with X0FLT1 (XICFG1.0) X0FLT1, X0FLT nINT0 input filter mode XICFG1: External Interrupt Configured 1 Register SFR Page = 1 only SFR Address = 0xC1 RESET = 0000-0000 7 6 5 4 3 2 1 0 INT1IS.2 INT0IS.2 INT2IS.1 INT2IS.0 -- X2FLT1 X1FLT1 X0FLT1 R/W R/W R/W R/W W R/W R/W R/W Bit 7: INT1IS2, nINT1 input port pin selection bit which function is defined with INT1IS.1~0. Bit 6: INT0IS2, nINT0 input port pin selection bit which function is defined with INT0IS.1~0. Bit 5~4: INT2IS1~0, nINT2 input port pin selection bits which function is defined as following table. INT2IS.1~0 Selected Port Pin of nINT2 00 P4.4 01 P3.0 10 P1.1 11 P1.6 Bit 2: X2FLT1, nINT2 Filter mode control. It selects nINT2 input filter mode with X2FLT (XICFG.2). Refer XICFG description for nINT2 input filter mode definition. Bit 1: X1FLT1, nINT1 Filter mode control. It selects nINT1 input filter mode with X1FLT (XICFG.1). Refer XICFG description for nINT1 input filter mode definition. Bit 0: X0FLT1, nINT0 Filter mode control. It selects nINT0 input filter mode with X0FLT (XICFG.0). Refer XICFG description for nINT0 input filter mode definition. SFIE: System Flag Interrupt Enable Register SFR Page = 0~F SFR Address = 0x8E POR = 0000-x000 7 6 5 4 3 2 1 0 SIDFIE -- -- RTCFIE -- BOF1IE BOF0IE WDTFIE R/W W W R/W W R/W R/W R/W Bit 7: SIDFIE, Serial Interface (STWI/SI2C) Detection Flag Interrupt Enabled. 0: Disable SIDF(STAF or STOF) interrupt. 1: Enable SIDF(STAF or STOF) interrupt to share the system flag interrupt. Bit 4: RTCFIE, Enable RTCF (PCON1.4) Interrupt. 0: Disable RTCF interrupt. 1: Enable RTCF interrupt. Bit 3: Reserved. Software must write “0” on this bit when SFIE is written. Bit 2: BOF1IE, Enable BOF1 (PCON1.2) Interrupt. 0: Disable BOF1 interrupt. 1: Enable BOF1 interrupt.

megawin Version: 1.00 101 Bit 1: BOF0IE, Enable BOF0 (PCON1.1) Interrupt. 0: Disable BOF0 interrupt. 1: Enable BOF0 interrupt. Bit 0: WDTFIE, Enable WDTF (PCON1.0) Interrupt. 0: Disable WDTF interrupt. 1: Enable WDTF interrupt. PCON1: Power Control Register 1 SFR Page = 0~F & P SFR Address = 0x97 POR = 0000-x000 7 6 5 4 3 2 1 0 SWRF EXRF -- RTCF -- BOF1 BOF0 WDTF R/W R/W W R/W W R/W R/W R/W Bit 7: SWRF, Software Reset Flag. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if a Software Reset occurs. Bit 6: EXRF, External Reset Flag. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if an External Reset occurs. Bit 4: RTCF, RTC overflow flag. 0: This bit must be cleared by software writing “1” on it. Software writing “0” is no operation. 1: This bit is only set by hardware when RTCCT overflows. Writing “1” on this bit will clear RTCF. Bit 3: Reserved. Software must write “0” on this bit when PCON1 is written. Bit 2: BOF1, Brown-Out Detection flag 1. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if the operating voltage matches the detection level of Brown-Out Detector 1 Bit 1: BOF0, Brown-Out Detection flag 0. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if the operating voltage matches the detection level of Brown- Out Detector 0 (1.7V). Bit 0: WDTF, WDT overflow flag. 0: This bit must be cleared by software writing “1” to it. 1: This bit is set by hardware if a WDT overflow occurs. AUXR2: Auxiliary Register 2 SFR Page = 0 only SFR Address = 0xA3 RESET = 0000-0000 7 6 5 4 3 2 1 0 STAF STOF -- -- T1X12 T0X12 T1CKOE T0CKOE R/W R/W W W R/W R/W R/W R/W Bit 7: STAF, Start Flag detection of STWI (SID). 0: Clear by firmware by writing “0” on it. STAF might be held within MCU reset period, so needs to clear STAF in firmware initial. 1: Set by hardware to indicate the START condition occurred on STWI bus. Bit 6: STOF, Stop Flag detection of STWI (SID). 0: Clear by firmware by writing “0” on it. 1: Set by hardware to indicate the STOP condition occurred on STWI bus. STOF might be held within MCU reset period, so needs to clear STOF in firmware initial.

megawin Version: 1.00 102 16. Timers/Counters MG82F6D17 has four 16-bit Timers/Counters: Timer 0, Timer 1, Timer 2 and Timer 3. All of them can be configured as timers or event counters. In the “timer” function, the timer rate is prescaled by 12 clock cycle to increase register value. In other words, it is to function for Timer 0/1/2/3 to set the timer rate on every clock cycle. It performs at a speed 12 times than standard C51 timer function. Other prescaler values can be selected by combining T0C/T, T0XL and T0X12 for Timer 0 clock input. In the “counter” function, the register is increased in response to a 1-to-0 transition at its corresponding external input pin, T0, T1, T2 or T3. In this function, the external input is sampled by every timer rate cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register at the end of the cycle following the one in which the transition was detected. 16.1. Timer 0 and Timer 1 16.1.1. Timer 0/1 Mode 0 The timer register is configured as a PWM generator. As the count rolls over from all 1s to all 0s, it sets the timer interrupt flag TFx. Timer0 uses the control bits {T0XL, T0X12, T0C/T} to set the clock source to count. And it also uses TR0 and {T0G1, T0GATE} to select the gating sources to block the trigger signal to stop the counting. Timer1 uses the control bits {T1X12, T1C/T} to set the clock source to count. And it uses TR1 and {T1G1, T1GATE} to select the gating sources to block the trigger signal to stop the counting. Mode 0 operation is the same for Timer0 and Timer1. The PWM function of Timer 0/1 is shown in Figure 16–1 and Figure 16–2. Figure 16–1. Timer 0 Mode 0 Structure TR0 T0 Pin T0 Interrupt Overflow 8-Bit Comparator S R Q Q Q Port Latch SYSCLK/48 SYSCLK/192 8-bit Up-Counter TL0[7:0] TF0 TH0[7:0] SYSCLK/12 (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) SYSCLK {T0XL, T0X12, T0C/T} (Timer1 overflow) T1OF ILRCO (WDT pre-scaler) WDTPS INT0ET T0OF 00H Reload IT0IE0IT1IE1TR0TF0TR1TF1TCON T0M0T0M1T0C/TT1M0T1M1T1C/TTMOD xxxx T0XLxxxxxxAUXR3 xxxx 0 0 T0GATET1GATE T1X12xxxxSTOFSTAFAUXR2 T0X12 T1CKOE T0CKOE (T0 overflow) T0SCT T0OR VDD (0,0) (0,1) (1,0) (1,1) {T0G1, T0GATE} KBIET TF2 T0CKOE

megawin Version: 1.00 103 Figure 16–2. Timer 1 Mode 0 Structure TR1 T1 Pin T1 Interrupt Overflow S R Q Q Q Port Latch T1CKO SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) {T1X12, T1C/T} 8-Bit Comparator TL1[7:0] TH1[7:0] T1OF TF1 00H Reload IT0IE0IT1IE1TR0TF0TR1TF1TCON T0M0T0M1T0C/TT1M0T1M1T1C/TTMOD T0GATET1GATE T1X12xxxxSTOFSTAFAUXR2 T0X12 T1CKOE T0CKOE (T1 overflow) T1SCT 8-bit Up-Counter T1OR INT1ET VDD (0,0) (0,1) (1,0) (1,1) {T1G1, T1GATE} TF3 TI1 SYSCLK/48 T1CKOE

megawin Version: 1.00 106 16.1.4. Timer 0/1 Mode 3 Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 0. Timer0 in Mode 3 enables TL0 and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such like T0XL, T0X12, T0C/T, T0G1, T0GATE, TR0 and TF0. TH0 is locked into a timer function (can not be external event counter) and take over the use of TR1, TF1 from Timer1. TH0 now controls the Timer1 interrupt. Figure 16–7 shows the mode 3 structure of Timer 0. Figure 16–7. Timer 0 Mode 3 Structure TR0 T0 Pin T0 Interrupt Overflow SYSCLK/48 SYSCLK/192 8-bit Up-Counter TL0[7:0] TF0 SYSCLK/12 (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) SYSCLK {T0XL, T0X12, T0C/T} (Timer1 overflow) T1OF ILRCO (WDT prescaler) WDTPS T0OF T1 Interrupt Overflow 8-bit Up-Counter TH0[7:0] TF1 SYSCLK/48 SYSCLK/192 SYSCLK/12 (0,0) (0,1) (1,0) (1,1) SYSCLK {T0XL, T0X12} TR1 00H Reload 00H Reload IT0IE0IT1IE1TR0TF0TR1TF1TCON T0M0T0M1T0C/TT1M0T1M1T1C/TTMOD T0GATET1GATE (T0 overflow) T0SCT T1SCT xxxx T0XLxxxxxxAUXR3 xxxx T1X12xxxxSTOFSTAFAUXR2 T0X12 T1CKOE T0CKOE INT0ET VDD (0,0) (0,1) (1,0) (1,1) {T0G1, T0GATE} KBIET TF2

megawin Version: 1.00 108 Figure 16–11. Timer 1 in Clock Output Mode How to Program Timer 0/1 in Clock-out Mode

• Select Timer 0/1 clock source.
• Determine the 8-bit reload value from the formula and enter it in the TH0/TH1 register.
• Enter the same reload value as the initial value in the TL0/TL1 register.
• Set T0CKOE/T1CKOE bit in AUXR2 register.
• Set TR0/TR1 bit in TCON register to start the Timer 0/1. In the Clock-Out mode, Timer 0/1 rollovers will not generate an interrupt This is similar to when Timer 1 is used as a baud-rate generator. It is possible to use Timer 1 as a baud rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the clock-out frequency depend on the same overflow rate of Timer 1. So, software usually disables the Timer 0/1 interrupt in this kind of application. Timer 1 in Mode 1/2/3T1 Pin SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) {T1X12, T1C/T} IT0IE0IT1IE1TR0TF0TR1TF1TCON T0M0T0M1T0C/TT1M0T1M1T1C/TTMOD T0GATET1GATE T1SCT T1X12xxxxSTOFSTAFAUXR2 T0X12 T1CKOE T0CKOE Overflow Toggle 0 Q Port Latch T1CKOE T1CKOT1OR D Q TR1 INT1ET VDD (0,0) (0,1) (1,0) (1,1) {T1G1, T1GATE} TF3 TI1 SYSCLK/48

megawin Version: 1.00 109 16.1.6. Timer 0/1 Register TCON: Timer/Counter Control Register SFR Page = 0~F SFR Address = 0x88 RESET = 0000-0000 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: TF1, Timer 1 overflow flag. 0: Cleared by hardware when the processor vectors to the interrupt routine, or clear ed by software. 1: Set by hardware on Timer/Counter 1 overflow, or set by software. Bit 6: TR1, Timer 1 Run control bit. 0: Disabled to stop Timer/Counter 1. 1: Enabled to start Timer/Counter 1. Bit 5: TF0, Timer 0 overflow flag. 0: Cleared by hardware when the processor vectors to the interrupt routine, or clear ed by software. 1: Set by hardware on Timer/Counter 0 overflow, or set by software. Bit 4: TR0, Timer 0 Run control bit. 0: Disabled to stop Timer/Counter 0. 1: Enabled to start Timer/Counter 0. TMOD: Timer/Counter Mode Control Register SFR Page = 0~F SFR Address = 0x89 RESET = 0000-0000 7 6 5 4 3 2 1 0 T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: T1GATE, Gating control for Timer1. T1G1, T1GATE T1 Gate source 0 0 Disable 0 1 INT1 active 1 0 TF3 active 1 1 TI1 active Bit 6: T1C/T, Timer 1 clock source selector. It controls the Timer 1 as timer or counter with 4 clock sources. Refer to T1X12 description in the AUXR2. Bit 5~4: Operating mode selection. T1M1 T1M0 Timer 1 Operating Mode 0 0 8-bit PWM generator for Timer1 0 1 16-bit timer/counter for Timer1 1 0 8-bit timer/counter with automatic reload for Timer1 1 1 Timer/Counter1 Stopped Bit 3: T0GATE, Gating control for Timer0. T0G1, T0GATE T0 Gate source 0 0 Disable 0 1 INT0 active 1 0 TF2 active 1 1 KBI active

megawin Version: 1.00 110 Bit 2: T0C/T, Timer 0 clock source selector. It controls the Timer 0 as timer or counter with 8 clock sources. Refer to T0X12 description in the AUXR2. Bit 1~0: Operating mode selection. T0M1 T0M0 Timer 0 Operating Mode 0 0 8-bit PWM generator for Timer0 0 1 16-bit timer/counter for Timer0 1 0 8-bit timer/counter with automatic reload for Timer0 1 1 TL0 is 8-bit timer/counter, TH0 is locked into 8-bit timer TL0: Timer 0 Low byte Register SFR Page = 0~F SFR Address = 0x8A RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TH0: Timer 0 High byte Register SFR Page = 0~F SFR Address = 0x8C RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TL1: Timer 1 Low byte Register SFR Page = 0~F SFR Address = 0x8B RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TH1: Timer 1 High byte Register SFR Page = 0~F SFR Address = 0x8D RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W AUXR2: Auxiliary Register 2 SFR Page = 0~F SFR Address = 0xA3 RESET = 0000-0000 7 6 5 4 3 2 1 0 STAF STOF -- -- T1X12 T0X12 T1CKOE T0CKOE R/W R/W W W R/W R/W R/W R/W Bit 3: T1X12, Timer 1 clock source selection with T1C/T control. T1X12, T1C/T Timer 1 Clock Selection 0 0 SYSCLK/12 0 1 T1 Pin 1 0 SYSCLK 1 1 SYSCLK/48

megawin Version: 1.00 111 Bit 2: T0X12, Timer 0 clock source selection with T0C/T and T0XL control. T0XL, T0X12, T0C/T Timer 0 Clock Selection 0 0 0 SYSCLK/12 0 0 1 T0 Pin 0 1 0 SYSCLK 0 1 1 ILRCO 1 0 0 SYSCLK/48 1 0 1 WDTPS 1 1 0 SYSCLK/192 1 1 1 T1OF Bit 1: T1CKOE, Timer 1 Clock Output Enable. 0: Disable Timer 1 clock output. 1: Enable Timer 1 clock output on T1CKO Port pin. Bit 0: T0CKOE, Timer 0 Clock Output Enable. 0: Disable Timer 0 clock output. 1: Enable Timer 0 clock output on T0CKO Port pin. AUXR3: Auxiliary Register 3 SFR Page = 0 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T0PS1 T0PS0 BPOC1 BPOC0 S0PS0 TWIPS1 TWIPS0 T0XL R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: T0PS1~0, Timer 0 Port pin Selection [1:0]. T0PS1~0 T0/T0CKO 00 P3.4 01 P4.4 10 P2.2 11 P1.7 Bit 0: T0XL is the Timer 0 per-scaler control bit. Please refer T0X12 (AUXR2.2) for T0XL function definition. AUXR4: Auxiliary Register 4 SFR Page = 1 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T2PS1 T2PS0 T1PS1 T1PS0 -- -- -- -- R/W R/W R/W R/W W W W W Bit 5~4: T1PS1~0, Timer 1 Port pin Selection [1:0]. T1PS1~0 T1/T1CKO 00 P3.5 01 P4.5 10 P1.7 11 P3.3

megawin Version: 1.00 112 AUXR9: Auxiliary Register 9 SFR Page = 6 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- T1G1 T0G1 C0FDC1 C0FDC0 S1PS1 S1PS0 W W R/W R/W R/W R/W R/W R/W Bit 5: T1G1, Gating source selection of Timer 1. T1G1, T1GATE T1 Gate source

01 INT1 active

10 TF3 active

11 TI1 active

Bit 4: T0G1, Gating source selection of Timer 0. T0G1, T0GATE T0 Gate source

01 INT0 active

10 TF2 active

11 KBI active

megawin Version: 1.00 113 16.2. Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate either as a timer or an event counter, as selected by C/T2 in T2CON register. Timer 2 has four operating modes: Capture, Auto-Reload (up or down counting), Baud Rate Generator and Programmable Clock-Out, which are selected by bits in the T2CON, T2MOD and T2MOD1 registers. 16.2.1. Timer 2 Mode 0 (Auto-Reload and External Interrupt) In this mode, Timer 2 provides a 16-bit auto-reload timer/counter. The TF2, Timer 2 overflow flag, is one of the Timer 2 interrupt source which interrupt function can be blocked by TF2IG. EXEN2 enables a 1-to-0 transition at T2EXI to set the flag, EXF2, for an external input interrupt to share the Timer 2 interrupt with TF2. T2EXI is the selection result of 8 Timer 2 external inputs. T2EXH performs the same function as EXEN2 but it enables the detecting a 0-to-1 transition at T2EXI input. The Timer 2 overflow event (T2OF) in this module will be output to other peripheral as clock input or event source. Timer 2 Mode 0 is illustrated in Figure 16–12. Figure 16–12. Timer 2 Mode 0 Structure (Auto-Reload and Exteranl Interrupt Mode) Timer 2 Interrupt EXF2 RCAP2HRCAP2L TL2 (8 Bits) TH2 (8 Bits) TF2 Reload Overflow EXEN2 T2EXH T2SPL = 0, T2MS1 = 0, CP/RL2 = 0, T2MS0 = 0 TR2 C/T2TR2EXEN2TCLKRCLKEXF2TF2T2CON T2MS0T2OETR2LCTR2LT2X12T2EXHT2SPLT2MOD CP2S0T2MS1T2CKSTL2ISTF2IGTL2CST2MOD1 CP2S1CP2S2 CP2S[2:0] (Timer0 Overflow) T0OF SYSCLK/12 (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) SYSCLK xxx {T2CKS, T2X12, C/T2} T2 Pin (S0BRG Overflow) S0TOF INT0ET KBIET INT2ET TWI0_SCL P6.0 (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) RXD0 T2EX Pin ILRCO xxx KBIET 16-bit Up Counter T2OF TL2X12 CP/RL2 (T2 overflow) TF2IG T2SCT T2EXI T2EXES

megawin Version: 1.00 116 16.2.4. Timer 2 Mode 3 (Capture with Auto-Zero) Timer 2 Mode 3 is the similar function with Timer 2 Mode 2. There is one difference that the T2EXES, EXF2 event set signal, not only is the capture source of Timer 2 but also clears the content of TL2 and TH2 to 0x0000H. Timer 2 Mode 3 is illustrated in Figure 16–15. Figure 16–15. Timer 2 Mode 3 Structure (Capture with Auto-Zero on TL2 & TH2) TL2 (8 Bits) TH2 (8 Bits) Overflow T2SPL = 0, T2MS1 = 0, CP/RL2 = 1, T2MS0 = 1 C/T2TR2EXEN2TCLKRCLKEXF2TF2T2CON T2MS0T2OETR2LCTR2LT2X12T2EXHT2SPLT2MOD CP2S0T2MS1T2CKSTL2ISTF2IGTL2CST2MOD1 CP2S1CP2S2 CP2S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T2CKS, T2X12, C/T2} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) RCAP2HRCAP2L Capture 16-bit Up Counter 00H00H ReloadReload T2OF TL2X12 CP/RL2 (T2 overflow) EXEN2 T2EXH EXF2 TF2 TF2IG Timer 2 Interrupt TR2 T2SCT T2EXI T2EXES INT2ET TWI0_SCL P6.0 RXD0 T2EX Pin ILRCO xxx KBIET (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T2 Pin (S0BRG Overflow) S0TOF INT0ET KBIET

megawin Version: 1.00 117 16.2.5. Split Timer 2 Mode 0 (AR and Ex. INT) When T2SPL is set in this mode, Timer 2 operates as two 8-bit timers (TH2 and TL2). Both 8-bit timers operate in up-counter as shown in Figure 16–16. TH2 holds the reload value for RCAP2H and keep the same 8 clock source inputs selection as 16-bit mode. It behaves the 8-bit function liked Timer 2 Mode 0 in 16-bit mode. TL2 holds the reload value for RCAP2L with 4 clock inputs selection. The TR2 bit in T2CON handles the run control for TH2. The TR2L bit in T2MOD handles the run control for TL2. And TH2 overflow can stop the TR2L running when TR2LC is set. There are 3 interrupt flags in split mode, EXF2, TF2 and TF2L. EXF2 has the same function as 16- bit mode to detect the transition on T2EXI. TF2 is set when TH2 overflows from 0xFF to 0x00 with TF2IG control. TF2L is set when TL2 overflows from 0xFF to 0x00 with interrupt enabled by TL2IE. The EXF2, TF2 and TF2L interrupt flags are not cleared by hardware and must be cleared by software. By the way, the Timer 2 overflow event (T2OF) in 16-bit timer is replaced by TL2 overflow event (TL2OF) in this split mode. If TL2IS in T2MOD1 is 0, the bits on T2CON.5~4 are the function of RCLK and TCLK. If TL2IS is 1, the bits on T2CON.5~4 are the function of TF2L and TL2IE. Figure 16–16. Split Timer 2 Mode 0 Structure (AR and Ex. INT) EXF2 RCAP2H RCAP2L TL2 (8 Bits) TH2 (8 Bits) Reload Overflow EXEN2 T2EXH T2SPL = 1, T2MS1 = 0, CP/RL2 = 0, T2MS0 = 0 C/T2TR2EXEN2TCLKRCLKEXF2TF2T2CON T2MS0T2OETR2LCTR2LT2X12T2EXHT2SPLT2MOD CP2S0T2MS1T2CKSTL2ISTF2IGTL2CST2MOD1 CP2S1CP2S2 CP2S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T2CKS, T2X12, C/T2} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 8-bit Up Counter Reload Overflow TL2 Overflow (TL2OF) 0. T2OF == TL2OF 1. to T2CKO 2. to Peripheral Clock 3. to UART0 RX Clock 4. to UART0 TX Clock 8-bit Up Counter TR2LC Clear TR2LSYSCLK/12 SYSCLK {TL2CS, TL2X12} (S0BRG Overflow) S0TOF (0,0) (0,1) (1,0) (1,1) TL2X12 CP/RL2 INT0ET TR2 T2SCT TL2IETF2L If TL2IS=1 TR2L TL2SCT TF2L Timer 2 Interrupt TF2 TF2IG TL2IE T2EXI T2EXES INT2ET TWI0_SCL P6.0 RXD0 T2EX Pin ILRCO xxx KBIET (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T2 Pin (S0BRG Overflow) S0TOF KBIET (TL2 Overflow) TL2OF

megawin Version: 1.00 118 16.2.6. Split Timer 2 Mode 1 (AR with Ex. INT) When T2SPL is set in this mode, Timer 2 is split to two 8-bit timers as shown in Figure 16–17. It is similar function as Timer 2 Mode 1 and keeps the same interrupt scheme in Split Timer 2 Mode 0. Figure 16–17. Split Timer 2 Mode 1 Structure (AR with Ex. INT) RCAP2H Reload EXF2 TH2 (8 Bits) TF2 Overflow EXEN2 T2EXH T2SPL = 1, T2MS1 = 0, CP/RL2 = 0, T2MS0 = 1 (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T2CKS, T2X12, C/T2} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) CP2S[2:0] 8-bit Up Counter RCAP2L TL2 (8 Bits) Reload Overflow 8-bit Up Counter C/T2TR2EXEN2TCLKRCLKEXF2TF2T2CON T2MS0T2OETR2LCTR2LT2X12T2EXHT2SPLT2MOD CP2S0T2MS1T2CKSTL2ISTF2IGTL2CST2MOD1 CP2S1CP2S2 TR2L {TL2CS, TL2X12} SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) (S0BRG Overflow) S0TOF TL2 Overflow (TL2OF) 0. T2OF == TL2OF 1. to T2CKO 2. to Peripheral Clock 3. to UART0 RX Clock 4. to UART0 TX Clock TL2X12 CP/RL2 INT0ET TR2LC Clear TR2L TL2SCT TL2IETF2L If TL2IS=1 TR2 T2SCT TF2L Timer 2 Interrupt TF2IG TL2IE T2EXI T2EXES INT2ET TWI0_SCL P6.0 RXD0 T2EX Pin ILRCO xxx KBIET (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T2 Pin (S0BRG Overflow) S0TOF KBIET (TL2 Overflow) TL2OF

megawin Version: 1.00 119 16.2.7. Split Timer 2 Mode 2 (Capture) When T2SPL is set in this mode, Timer 2 is split to two 8-bit timers as shown in Figure 16–18. It is similar function as Timer 2 Mode 2 and keeps the same interrupt scheme in Split Timer 2. Figure 16–18. Split Timer 2 Mode 2 Structure (Capture) TH2 (8 Bits) EXEN2 T2EXH T2SPL = 1, T2MS1 = 0, CP/RL2 = 1, T2MS0 = 0 CP2S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T2CKS, T2X12, C/T2} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) RCAP2H Capture RCAP2L TL2 (8 Bits) C/T2TR2EXEN2TCLKRCLKEXF2TF2T2CON T2MS0T2OETR2LCTR2LT2X12T2EXHT2SPLT2MOD CP2S0T2MS1T2CKSTL2ISTF2IGTL2CST2MOD1 CP2S1CP2S2 Reload Overflow 8-bit Up Counter EXF2 TF2 Overflow 8-bit Up Counter 00H Reload {TL2CS, TL2X12} SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) (S0BRG Overflow) S0TOF TL2 Overflow (TL2OF) 0. T2OF == TL2OF 1. to T2CKO 2. to Peripheral Clock 3. to UART0 RX Clock 4. to UART0 TX Clock TL2X12 CP/RL2 INT0ET TR2LC Clear TR2L TL2IE TF2IG Timer 2 Interrupt TF2L TL2IETF2L If TL2IS=1 TR2L TL2SCT TR2 T2SCT T2EXI T2EXES INT2ET TWI0_SCL P6.0 RXD0 T2EX Pin ILRCO xxx KBIET (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T2 Pin (S0BRG Overflow) S0TOF KBIET (TL2 Overflow) TL2OF

megawin Version: 1.00 120 16.2.8. Split Timer 2 Mode 3 (Capture with Auto-Zero) When T2SPL is set in this mode, Timer 2 is split to two 8-bit timers as shown in Figure 16–19. It is similar function as Timer 2 Mode 3 and keeps the same interrupt scheme in Split Timer 2 Mode 0. Figure 16–19. Split Timer 2 Mode 3 Structure (Capture with Auto-Zero on TH2) EXEN2 T2EXH T2SPL = 1, T2MS1 = 0, CP/RL2 = 1, T2MS0 = 1 CP2S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T2CKS, T2X12, C/T2} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) Capture 00H RCAP2L TL2 (8 Bits) C/T2TR2EXEN2TCLKRCLKEXF2TF2T2CON T2MS0T2OETR2LCTR2LT2X12T2EXHT2SPLT2MOD CP2S0T2MS1T2CKSTL2ISTF2IGTL2CST2MOD1 CP2S1CP2S2 Reload Overflow 8-bit Up Counter TH2 (8 Bits) RCAP2H EXF2 TF2 Overflow 8-bit Up Counter ReloadReload {TL2CS, TL2X12} SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) (S0BRG Overflow) S0TOF TL2 Overflow (TL2OF) 0. T2OF == TL2OF 1. to T2CKO 2. to Peripheral Clock 3. to UART0 RX Clock 4. to UART0 TX Clock TL2X12 CP/RL2 INT0ET TR2LC Clear TR2L TF2IG TL2IE Timer 2 Interrupt TF2L TL2IETF2L If TL2IS=1 TR2L TL2SCT TR2 T2SCT T2EXI T2EXES INT2ET TWI0_SCL P6.0 RXD0 T2EX Pin ILRCO xxx KBIET (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T2 Pin (S0BRG Overflow) S0TOF KBIET (TL2 Overflow) TL2OF

megawin Version: 1.00 121 16.2.9. Split Timer 2 Mode 4 (8-bit PWM Mode) In this mode, Timer 2 is an 8-bit PWM mode as shown in Figure 16–20. TH2 and RCAP2H are combined to an 8-bit auto-reload counter. Software configures these two registers to decide the PWM cycle time. TL2 is the PWM compare register to generate PWM waveform. RCAP2L is the PWM buffer register and software will update PWM data in this register. Each TH2 overflow event will set TF2 and load RCAP2L value into TL2. The PWM signal will be output on T2CKO function pin and the output is gated by T2OE in T2MOD register. Figure 16–20. Split Timer 2 Mode 4 Structure (8-bit PWM mode) EXF2 RCAP2H RCAP2L TL2 (8 Bits) TH2 (8 Bits) Reload Overflow EXEN2 T2EXH T2SPL = 1, T2MS1 = 1, CP/RL2 = 0, T2MS0 = 0 C/T2TR2EXEN2TCLKRCLKEXF2TF2T2CON T2MS0T2OETR2LCTR2LT2X12T2EXHT2SPLT2MOD CP2S0T2MS1T2CKSTL2ISTF2IGTL2CST2MOD1 CP2S1CP2S2 CP2S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T2CKS, T2X12, C/T2} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 8-bit Up Counter Reload T2 Overflow (T2OF) 0. T2OF 1. to Peripheral Clock 2. to UART0 RX Clock 3. to UART0 TX Clock TL2X12 CP/RL2 TR2 T2SCT TL2IETF2L If TL2IS=1 TF2L Timer 2 Interrupt TF2 TF2IG TL2IE 8-Bit Comparator S R Q Q Match TR2LC PWMH PWML T2OE T2CKO T2EXI T2EXES T2OR INT2ET TWI0_SCL P6.0 RXD0 T2EX Pin ILRCO xxx KBIET (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T2 Pin (S0BRG Overflow) S0TOF INT0ET KBIET

megawin Version: 1.00 123 EXF2 RCAP2H RCAP2L TL2 (8 Bits) TH2 (8 Bits) Reload Overflow EXEN2 T2EXH T2SPL = 1, T2MS1 = 0, CP/RL2 = 0/1, T2MS0 = 0/1 C/T2TR2EXEN2TCLKRCLKEXF2TF2T2CON T2MS0T2OETR2LCTR2LT2X12T2EXHT2SPLT2MOD CP2S0T2MS1T2CKSTL2ISTF2IGTL2CST2MOD1 CP2S1CP2S2 CP2S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T2CKS, T2X12, C/T2} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 8-bit Up Counter Reload TL2 Overflow (TL2OF) 0. T2OF == TL2OF 1. to T2CKO 2. to Peripheral Clock 8-bit Up Counter 0/1 0/1 SMOD1 TCLK RCLK TX Clock to S0 RX Clock to S0 Timer 1 Overflow Overflow {TL2CS, TL2X12} SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) (S0BRG Overflow) S0TOF TL2 for UART0 Baud Rate Generator & T2OF TL2X12 CP/RL2 INT0ET TR2 T2SCT TF2 TF2IG TL2IE TF2L TR2L TL2SCT TL2IETF2L If TL2IS=1 Timer 2 Interrupt T2EXI T2EXES INT2ET TWI0_SCL P6.0 RXD0 T2EX Pin ILRCO xxx KBIET (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T2 Pin (S0BRG Overflow) S0TOF KBIET (TL2 Overflow) TL2OF

megawin Version: 1.00 126 16.2.12. Timer 2 Register T2CON: Timer 2 Control Register SFR Page = 0 Only SFR Address = 0xC8 RESET = 0000-0000 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK/ TF2L TCLK/ TL2IE EXEN2 TR2 C/T2 CP/RL2 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: TF2, Timer 2 overflow flag. 0: TF2 must be cleared by software. 1: TF2 is set by a Timer 2 overflow happens. TF2 will not be set when either RCLK=1 or TCLK=1. Bit 6: EXF2, Timer 2 external flag. 0: EXF2 must be cleared by software. 1: Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX pin and EXEN2=1 or a positive transition on T2EX and T2EXH=1. When Timer 2 interrupt is enabled, EXF2=1 will cause the CPU to vector to the Timer 2 interrupt routine. TL2IS (T2MOD1.5) must be cleared to enable access to the RCLK bit. Bit 5: RCLK, Receive clock flag. 0: Causes Timer 1 overflow to be used for the receive clock. 1: Causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. TL2IS (T2MOD1.5) must be set to enable access to the TF2L bit. Bit 5: TF2L, TL2 overflow flag in Timer 2 split mode. 0: TF2L must be cleared by software. 1: TF2L is set by TL2 overflow happened in Timer 2 split mode. TL2IS (T2MOD1.5) must be cleared to enable access to the TCLK bit. Bit 4: TCLK, Transmit clock flag. 0: Causes Timer 1 overflows to be used for the transmit clock. 1: Causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TL2IS (T2MOD1.5) must be set to enable access to the TL2IE bit. Bit 4: TL2IE, TF2L interrupt enable. 0: Disable TF2L interrupt. 1: Enable TF2L interrupt to share the Timer 2 interrupt vector. Bit 3: EXEN2, Timer 2 external enable flag on a negative transition of T2EX pin. 0: Cause Timer 2 to ignore negative transition events at T2EX pin. 1: Allows a capture or reload to occur as a result of a 1 -to-0 transition on T2EX pin if Timer 2 is not being used to clock the serial port 0. If Timer 2 is configured to clock the serial port 0, the T2EX remains the external transition detection and reports on EXF2 flag with Timer 2 interrupt. Bit 2: TR2, Timer 2 Run control bit. If in Timer 2 split mode, it only controls the TH2. 0: Disabled to stop the Timer/Counter 2. 1: Enabled to start the Timer/Counter 2.

megawin Version: 1.00 127 Bit 1: C/T2 , Timer 2 clock or counter source selector. The function is active with T2X12 and T2CKS as following definition: T2CKS, T2X12, C/T2 Timer 2 Clock Selection TH2 Clock Selection in split mode 0 0 0 SYSCLK/12 SYSCLK/12 0 0 1 T2 Pin T2 Pin 0 1 0 SYSCLK SYSCLK 0 1 1 INT0ET TL2OF 1 0 0 S0TOF S0TOF 1 0 1 T0OF T0OF 1 1 0 Reserved Reserved 1 1 1 KBIET KBIET Bit 0: CP/RL2, Timer 2 mode control bit. Refer T2MOD.T2MS0 description for the function definition. T2MOD: Timer 2 Mode Register SFR Page = 0 Only SFR Address = 0xC9 RESET= 0000-0000 7 6 5 4 3 2 1 0 T2SPL TL2X12 T2EXH T2X12 TR2L TR2LC T2OE T2MS0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: T2SPL, Timer 2 split mode control. 0: Disable Timer 2 to split mode. 1: Enable Timer 2 to split mode. Bit 6: TL2X12, the clock control bit of TL2 in Timer 2 split mode. TL2CS, TL2X12 TL2 Clock Selection 0 0 SYSCLK/12 0 1 SYSCLK 1 0 S0TOF 1 1 INT0ET Bit 5: T2EXH, Timer 2 external enable flag on a positive transition of T2EX pin. 0: Cause Timer 2 to ignore positive transition events at T2EX pin. 1: Allows a capture or reload to occur as a result of a 0 -to1 transition on T2EX pin if Timer 2 is not being used to clock the serial port 0. If Timer 2 is configured to clock the serial port 0, the T2EX remains the external transition detection and reports on EXF2 flag with Timer 2 interrupt. Bit 4: T2X12, Timer 2 clock source selector. Refer to C/T2 description for the function defined. Bit 3: TR2L, TL2 Run control bit in Timer 2 split mode. 0: Disabled to stop the TL2. 1: Enabled to start the TL2. Bit 2: TR2LC, TR2L Cleared control. 0: Disabled the TR2L cleared by hardware event. 1: Enabled the TR2L cleared by the TH2 overflow (Timer 2 in mode 0/1) or capture input (Timer 2 in mode 2/3). Bit 1: T2OE, Timer 2 clock-out enable bit. 0: Disable Timer 2 clock output. 1: Enable Timer 2 clock output. Bit 0: T2MS0, Timer 2 mode select bit 0. T2MS1, CP/RL2, T2MS0 Timer 2 Mode Selection 0 0 0 Mode 0: Auto-Reload and External Interrupt 0 0 1 Mode 1: Auto-Reload with External Interrupt 0 1 0 Mode 2: Capture mode 0 1 1 Mode 3: Capture with Auto-Zero 1 0 0 Mode 4: 8-bit PWM if T2SPL = 1

megawin Version: 1.00 128 Others Reserved T2MOD1: Timer 2 Mode Register 1 SFR Page = 1 Only SFR Address = 0x93 RESET= 0000-0000 7 6 5 4 3 2 1 0 TL2CS TF2IG TL2IS T2CKS T2MS1 CP2S2 CP2S1 CP2S0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: TL2CS. TL2 clock selection in Timer 2 split mode. Refer to T2MOD.TL2X12 description for the function defined. Bit 6: TF2IG, TF2 interrupt Ignored. 0: Enabled TF2 interrupt. Default is enabled. 1: Disable TF2 interrupt. Bit 5: TL2IS, TF2L and TL2IE access control. 0: Enable RCLK and TCLK access function on T2CON.5~4. 1: Enable TF2L and TL2IE access function on T2CON.5~4. Bit 4: T2CKS, Timer 2 clock selection. Refer to C/T2 description for the function defined. Bit 3: T2MS1, Timer 2 mode selection bit 1. Refer T2MOD.T2MS0 description for the function definition. Bit 2~0: CP2S.2~0. These bits define the capture source selector of Timer 2. CP2S.2~0 Timer 2 Capture Source Selection 0 0 0 T2EX Pin 0 0 1 RXD0 0 1 0 P6.0 0 1 1 INT2ET 1 0 0 Reserved 1 0 1 Reserved 1 1 0 KBIET 1 1 1 TWI0_SCL TL2: Timer 2 Low byte Register SFR Page = 0 Only SFR Address = 0xCC RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TH2: Timer 2 High byte Register SFR Page = 0 Only SFR Address = 0xCD RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W RCAP2L: Timer 2 Capture Low byte Register SFR Page = 0 Only SFR Address = 0xCA RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W

megawin Version: 1.00 129 RCAP2H: Timer 2 Capture High byte Register SFR Page = 0 Only SFR Address = 0xCB RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W AUXR4: Auxiliary Register 4 SFR Page = 1 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T2PS1 T2PS0 T1PS1 T1PS0 -- -- -- -- R/W R/W R/W R/W W W W W Bit 7~6: T2PS1~0, Timer 2 Port pin Selection [1:0]. T2PS1~0 T2/T2CKO T2EX 00 P1.0 P1.1 01 P3.0 P3.1 10 P6.0 P3.5 11 P4.5 P4.4

megawin Version: 1.00 130 16.3. Timer 3 Timer 3 is a 16-bit Timer/Counter which can operate either as a timer or an event counter, as selected by C/T3 in T3CON register. Timer 3 has four operating modes: Capture, Auto-Reload (up or down counting) and Programmable Clock-Out, which are selected by bits in the T3CON, T3MOD and T3MOD1 registers. Timer 3 Pin configuration are as following: T3/T3CKO T3EX P3.3 P3.4 16.3.1. Timer 3 Mode 0 (Auto-Reload and External Interrupt) In this mode, Timer 3 provides a 16-bit auto-reload timer/counter. The TF3, Timer 3 overflow flag, is one of the Timer 3 interrupt source which interrupt function can be blocked by TF3IG. EXEN3 enables a 1-to-0 transition at T3EXI to set the flag, EXF3, for an external input interrupt to share the Timer 3 interrupt with TF3. T3EXI is the selection result of 8 Timer 3 external inputs. T3EXH performs the same function as EXEN3 but it enables the detecting a 0-to-1 transition at T3EXI input. The Timer 3 overflow event (T3OF) in this module will be output to other peripheral as clock input or event source. Timer 3 Mode 0 is illustrated in Figure 16–27. Figure 16–27. Timer 3 Mode 0 Structure (Auto-Reload and Exteranl Interrupt Mode) RCAP3HRCAP3L TL3 (8 Bits) TH3 (8 Bits) EXEN3 T3EXH T3SPL = 0, T3MS1 = 0, CP/RL3 = 0, T3MS0 = 0 16-bit Up Counter C/T3TR3EXEN3TL3IETF3LEXF3TF3T3CON T3MS0T3OETR3LCTR3LT3X12T3EXHT3SPLT3MOD CP3S0T3MS1T3CKS--TF3IGTL3CST3MOD1 CP3S1CP3S2 00CP3S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T3CKS, T3X12, C/T3} TL3X12 CP/RL3 Timer 3 Interrupt EXF3 TF3 Reload Overflow T3OF (T3 overflow) TF3IG T3EXES TR3 T3SCT T3EXI xxx ILRCO P6.0 T3EX Pin KBIET xxx xxx (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T3 Pin (S1BRG Overflow) S1TOF T1OF INT1ET INT0ET

megawin Version: 1.00 133 16.3.4. Timer 3 Mode 3 (Capture and Auto-Zero) Timer 3 Mode 3 is the similar function with Timer 3 Mode 2. There is one difference that the T3EXES, EXF3 event set signal, not only is the capture source of Timer 3 but also clears the content of TL3 and TH3 to 0x0000H. Figure 16–30. Timer 3 Mode 3 Structure (Capture with Auto-Zero on TL3 & TH3) TL3 (8 Bits) TH3 (8 Bits) EXEN3 T3EXH T3SPL = 0, T3MS1 = 0, CP/RL3 = 1, T3MS0 = 1 RCAP3HRCAP3L Capture 00H00H ReloadReload T3OF C/T3TR3EXEN3TL3IETF3LEXF3TF3T3CON T3MS0T3OETR3LCTR3LT3X12T3EXHT3SPLT3MOD T3MOD1 10CP3S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T3CKS, T3X12, C/T3} TL3X12 CP/RL3 (T3 overflow) EXF3 TF3 Overflow TF3IG Timer 3 Interrupt T3EXES 16-bit Up Counter CP3S0T3MS1T3CKS--TF3IGTL3CS CP3S1CP3S2 TR3 T3SCT T3EXI ILRCO T3EX Pin KBIET (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T3 Pin (S1BRG Overflow) S1TOF T1OF INT1ET INT0ET xxx P6.0 xxx xxx

megawin Version: 1.00 134 16.3.5. Split Timer 3 Mode 0 (Auto-Reload and External Interrupt) When T3SPL is set in this mode, Timer 3 operates as two 8-bit timers (TH3 and TL3). Both 8-bit timers operate in up counter as shown in Figure 16–31 . TH3 holds the reload value for RCAP3H and keep the same 8 clock source inputs selection as 16-bit mode. It behaves the 8-bit function liked Timer 3 Mode 0 in 16-bit mode. TL3 holds the reload value for RCAP3L with 4 clock inputs selection. The TR3 bit in T3CON handles the run control for TH3. The TR3L bit in T3MOD handles the run control for TL3. And TH3 overflow can stop the TR3L running when TR3LC is set. There are 3 interrupt flags in split mode, EXF3, TF3 and TF3L. EXF3 has the same function as 16-bit mode to detect the transition on T3EXI. TF3 is set when TH3 overflows from 0xFF to 0x00 with TF3IG control. TF3L is set when TL3 overflows from 0xFF to 0x00 with interrupt enabled by TL3IE. The EXF3, TF3 and TF3L interrupt flags are not cleared by hardware and must be cleared by software. By the way, the Timer 3 overflow event (T3OF) in 16-bit timer is replaced by TL3 overflow event (TL3OF) in this split mode. If TL3IS in T3MOD1 is 1, the bits on T3CON.5~4 are the function of TF3L and TL3IE. Figure 16–31. Split Timer 3 Mode 0 Structure (AR and Ex. INT) RCAP3H RCAP3L TL3 (8 Bits) TH3 (8 Bits) Reload Overflow EXEN3 T3EXH T3SPL = 1, T3MS1 = 0, CP/RL3 = 0, T3MS0 = 0 C/T3TR3EXEN3TL3IETF3LEXF3TF3T3CON T3MS0T3OETR3LCTR3LT3X12T3EXHT3SPLT3MOD T3MOD1 CP3S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T3CKS, T3X12, C/T3} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 8-bit Up Counter Reload Overflow {TL3CS, TL3X12} TL3 Overflow (TL3OF) 0. T3OF == TL3OF 1. to T3CKO 2. to Peripheral Clock 8-bit Up Counter TR3LC TF3L TL3IE SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) TL3X12 CP/RL3 Timer 3 Interrupt EXF3 TF3 TF3IG T3EXES CP3S0T3MS1T3CKS--TF3IGTL3CS CP3S1CP3S2 TR3 T3SCT Clear TR3L TL3SCT TR3L T3EXI (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T3 Pin (TL3 Overflow) TL3OF T3EX Pin ILRCO KBIET (S1BRG Overflow) S1TOF T1OF INT0ET INT1ET (S1BRG Overflow) S1TOF xxx P6.0 xxx xxx

megawin Version: 1.00 135 16.3.6. Split Timer 3 Mode 1 (Auto-Reload with External Interrupt) When T3SPL is set in this mode, Timer 3 is split to two 8-bit timers as shown in Figure 16–32. It is similar function as Timer 3 Mode 1 and keeps the same interrupt scheme in Split Timer 3 Mode 0. Figure 16–32. Split Timer 3 Mode 1 Structure (AR with Ex. INT) RCAP3H RCAP3L TL3 (8 Bits) TH3 (8 Bits) Overflow EXEN3 T3EXH T3SPL = 1, T3MS1 = 0, CP/RL3 = 0, T3MS0 = 1 C/T3TR3EXEN3TL3IETF3LEXF3TF3T3CON T3MS0T3OETR3LCTR3LT3X12T3EXHT3SPLT3MOD T3MOD1 CP3S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T3CKS, T3X12, C/T3} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 8-bit Up Counter Reload Overflow {TL3CS, TL3X12} TL3 Overflow (TL3OF) 0. T3OF == TL3OF 1. to T3CKO 2. to Peripheral Clock 8-bit Up Counter TR3LC TF3L TL3IE SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) TL3X12 CP/RL3 Reload CP3S0T3MS1T3CKS--TF3IGTL3CS CP3S1CP3S2 Timer 3 Interrupt EXF3 TF3 TF3IG T3EXES TR3 T3SCT T3EXI Clear TR3L TL3SCT TR3L (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T3 Pin (TL3 Overflow) TL3OF T3EX Pin ILRCO KBIET (S1BRG Overflow) S1TOF T1OF INT0ET INT1ET (S1BRG Overflow) S1TOF xxx P6.0 xxx xxx

megawin Version: 1.00 136 16.3.7. Split Timer 3 Mode 2 (Capture) When T3SPL is set in this mode, Timer 3 is split to two 8-bit timers as shown in Figure 16–33. It is similar function as Timer 3 Mode 2 and keeps the same interrupt scheme in Split Timer 3 Mode 0. Figure 16–33. Split Timer 3 Mode 2 Structure (Capture) RCAP3L TL3 (8 Bits) Overflow EXEN3 T3EXH T3SPL = 1, T3MS1 = 0, CP/RL3 = 1, T3MS0 = 0 C/T3TR3EXEN3TL3IETF3LEXF3TF3T3CON T3MS0T3OETR3LCTR3LT3X12T3EXHT3SPLT3MOD T3MOD1 CP3S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T3CKS, T3X12, C/T3} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 8-bit Up Counter Reload Overflow {TL3CS, TL3X12} TL3 Overflow (TL3OF) 0. T3OF == TL3OF 1. to T3CKO 2. to Peripheral Clock 8-bit Up Counter TR3LC TF3L TL3IE SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) TL3X12 CP/RL3 TH3 (8 Bits) RCAP3H 00H Capture Reload Timer 3 Interrupt EXF3 TF3 TF3IG T3EXES CP3S0T3MS1T3CKS--TF3IGTL3CS CP3S1CP3S2 TR3 T3SCT T3EXI Clear TR3L TL3SCT TR3L (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T3 Pin (TL3 Overflow) TL3OF T3EX Pin ILRCO KBIET (S1BRG Overflow) S1TOF T1OF INT0ET INT1ET (S1BRG Overflow) S1TOF xxx P6.0 xxx xxx

megawin Version: 1.00 137 16.3.8. Split Timer 3 Mode 3 (Capture with Auto-Zero) When T3SPL is set in this mode, Timer 3 is split to two 8-bit timers as shown in Figure 16–34. It is similar function as Timer 3 Mode 3 and keeps the same interrupt scheme in Split Timer 3 Mode 0. Figure 16–34. Split Timer 3 Mode 3 Structure (Capture with Auto-Zero on TH3) RCAP3L TL3 (8 Bits) Overflow EXEN3 T3EXH T3SPL = 1, T3MS1 = 0, CP/RL3 = 1, T3MS0 = 1 C/T3TR3EXEN3TL3IETF3LEXF3TF3T3CON T3MS0T3OETR3LCTR3LT3X12T3EXHT3SPLT3MOD T3MOD1 CP3S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T3CKS, T3X12, C/T3} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 8-bit Up Counter Reload Overflow {TL3CS, TL3X12} TL3 Overflow (TL3OF) 0. T3OF == TL3OF 1. to T3CKO 2. to Peripheral Clock 8-bit Up Counter TR3LC TF3L TL3IE SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) TL3X12 CP/RL3 TH3 (8 Bits) RCAP3H 00H Capture ReloadReload Timer 3 Interrupt EXF3 TF3 TF3IG T3EXES CP3S0T3MS1T3CKS--TF3IGTL3CS CP3S1CP3S2 TR3 T3SCT T3EXI Clear TR3L TL3SCT TR3L (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T3 Pin (TL3 Overflow) TL3OF T3EX Pin ILRCO KBIET (S1BRG Overflow) S1TOF T1OF INT0ET INT1ET (S1BRG Overflow) S1TOF xxx P6.0 xxx xxx

megawin Version: 1.00 138 16.3.9. Split Timer 3 Mode 4 (8-bit PWM Mode) In this mode, Timer 3 is an 8-bit PWM mode as shown in Figure 16–35. TH3 and RCAP3H are combined to an 8-bit auto-reload counter. Software configures these two registers to decide the PWM cycle time. TL3 is the PWM compare register to generate PWM waveform. RCAP3L is the PWM buffer register and software will update PWM data in this register. Each TH3 overflow event will set TF3 and load RCAP3L value into TL3. The PWM signal will be output on T3CKO function pin and the output is gated by T3OE in T3MOD register. Figure 16–35. Split Timer 3 Mode 4 Structure (8-bit PWM mode) EXF3 RCAP3H RCAP3L TL3 (8 Bits) TH3 (8 Bits) Reload Overflow EXEN3 T3EXH T3SPL = 1, T3MS1 = 1, CP/RL3 = 0, T3MS0 = 0 CP3S[2:0] (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) {T3CKS, T3X12, C/T3} (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) 8-bit Up Counter Reload T3 Overflow (T3OF) 0. T3OF 1. to Peripheral Clock TR3 T3SCT TF3L Timer 3 Interrupt TF3 TF3IG TL3IE 8-Bit Comparator S R Q Q Match TR3LC PWMH PWML T3OE T3CKO T3EXI T3EXES T3OR C/T3TR3EXEN3TL3IETF3LEXF3TF3T3CON T3MS0T3OETR3LCTR3LT3X12T3EXHT3SPLT3MOD T3MOD1 TL3X12 CP/RL3 CP3S0T3MS1T3CKS--TF3IGTL3CS CP3S1CP3S2 (Timer0 Overflow) T0OF SYSCLK/12 SYSCLK xxx T3 Pin T3EX Pin ILRCO KBIET (S1BRG Overflow) S1TOF T1OF INT0ET INT1ET xxx P6.0 xxx xxx

megawin Version: 1.00 141 16.3.11. Timer 3 Register T3CON: Timer 3 Control Register SFR Page = 1 Only SFR Address = 0xC8 RESET = 0000-0000 7 6 5 4 3 2 1 0 TF3 EXF3 TF3L TL3IE EXEN3 TR3 C/T3 CP/RL3 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: TF3, Timer 3 overflow flag. 0: TF3 must be cleared by software. 1: TF3 is set by a Timer 3 overflow happens. Bit 6: EXF3, Timer 3 external flag. 0: EXF3 must be cleared by software. 1: Timer 3 external flag set when either a capture or reload is caused by a negative transition on T3EX pin and EXEN3=1 or a positive transition on T3EX and T3EXH=1. When Timer 3 interrupt is enabled, EXF3=1 will cause the CPU to vector to the Timer 3 interrupt rout ine. When the MCU is in power -down mode and Timer 3 interrupt is enabled, the EXF3 is forced to level-sensitive triggered with wake-up MCU capability. Bit 5: TF3L, TL3 overflow flag in Timer 3 split mode. 0: TF3L must be cleared by software. 1: TF3L is set by TL3 overflow happened in Timer 3 split mode. Bit 4: TL3IE, TF3L interrupt enable. 0: Disable TF3L interrupt. 1: Enable TF3L interrupt to share the Timer 3 interrupt vector. Bit 3: EXEN3, Timer 3 external enable flag on a negative transition of the Timer 3 external input. 0: Cause Timer 3 to ignore negative transition events at Timer 3 external input. 1: Allows a capture or reload to occur as a result of a 1-to-0 transition on Timer 3 external input. If Timer 3 is configured to mode 0 which does no behave capture or reload function, the Timer 3 external input remains the external transition detection and reports on EXF3 flag with Timer 3 interrupt. Bit 2: TR3, Timer 3 Run control bit. If in Timer 3 split mode, it only controls the TH3. 0: Disabled to stop the Timer/Counter 3. 1: Enabled to start the Timer/Counter 3. Bit 1: C/T 3, Timer 3 clock or counter source selector. The function is active with T 3X12 and T3CKS as following definition: T3CKS, T3X12, C/T3 Timer 3 Clock Selection TH3 Clock Selection in split mode 0 0 0 SYSCLK/12 SYSCLK/12 0 0 1 T3 Pin T3 Pin 0 1 0 SYSCLK SYSCLK 0 1 1 INT1ET TL3OF 1 0 0 S1TOF S1TOF 1 0 1 T0OF T0OF 1 1 0 Reserved Reserved 1 1 1 T1OF T1OF Bit 0: CP/RL3, Timer 3 mode control bit. Refer T3MOD.T3MS0 description for the function definition.

megawin Version: 1.00 142 T3MOD: Timer 3 Mode Register SFR Page = 1 Only SFR Address = 0xC9 RESET= 0000-0000 7 6 5 4 3 2 1 0 T3SPL TL3X12 T3EXH T3X12 TR3L TR3LC T3OE T3MS0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: T3SPL, Timer 3 split mode control. 0: Disable Timer 3 to split mode. 1: Enable Timer 3 to split mode. Bit 6: TL3X12, the clock control bit of TL3 in Timer 3 split mode. TL3CS, TL3X12 TL3 Clock Selection 0 0 SYSCLK/12 0 1 SYSCLK 1 0 S1TOF 1 1 INT1ET Bit 5: T3EXH, Timer 3 external enable flag on a positive transition of T3EX pin. 0: Cause Timer 3 to ignore positive transition events at T3EX pin. 1: Allows a capture or reload to occur as a result of a 0-to1 transition on T3EX pin and set EXF3. Bit 4: T3X12, Timer 3 clock source selector. Refer to C/T3 description for the function defined. Bit 3: TR3L, TL3 Run control bit in Timer 3 split mode. 0: Disabled to stop the TL3. 1: Enabled to start the TL3. Bit 2: TR3LC, TR3L Cleared control. 0: Disabled the TR3L cleared by hardware event. 1: Enabled the TR3L cleared by the TH3 overflow (Timer 3 in mode 0/1) or capture input (Timer 3 in mode 2/3). Bit 1: T3OE, Timer 3 clock-out enable bit. 0: Disable Timer 3 clock output. 1: Enable Timer 3 clock output. Bit 0: T3MS0, Timer 3 mode select bit 0. T3MS1, CP/RL3, T3MS0 Timer 3 Mode Selection 0 0 0 Mode 0: Auto-Reload and External Interrupt 0 0 1 Mode 1: Auto-Reload with External Interrupt 0 1 0 Mode 2: Capture mode 0 1 1 Mode 3: Capture with Auto-Zero 1 0 0 Mode 4: 8-bit PWM if T3SPL = 1 Others Reserved T3MOD1: Timer 3 Mode Register 1 SFR Page = 2 Only SFR Address = 0x93 RESET= 00X0-0000 7 6 5 4 3 2 1 0 TL3CS TF3IG -- T3CK2 T3MS1 CP3S2 CP3S1 CP3S0 R/W R/W W R/W R/W R/W R/W R/W Bit 7: TL3CS. TL3 clock selection in Timer 3 split mode. Refer to T3MOD.TL3X12 description for the function defined. Bit 6: TF3IG, TF3 interrupt Ignored. 0: Enabled TF3 interrupt. Default is enabled. 1: Disable TF3 interrupt. Bit 5: Reserved. Software must write “0” on this bit when T3MOD1 is written.

megawin Version: 1.00 143 Bit 4: T3CKS, Timer 3 clock selection. Refer to C/T3 description for the function defined. Bit 3: T3MS1, Timer 3 mode selection bit 1. Refer T3MOD.T3MS0 description for the function definition. Bit 2~0: CP3S.2~0. These bits define the capture source selector of Timer 3. CP3S.2~0 Timer 3 Capture Source Selection 0 0 0 T3EX Pin 0 0 1 INT0ET 0 1 0 P6.0 0 1 1 Reserved 1 0 0 KBIET 1 0 1 Reserved 1 1 0 Reserved 1 1 1 ILRCO TL3: Timer 3 Low byte Register SFR Page = 1 Only SFR Address = 0xCC RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W TH3: Timer 3 High byte Register SFR Page = 1 Only SFR Address = 0xCD RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W RCAP3L: Timer 3 Capture Low byte Register SFR Page = 1 Only SFR Address = 0xCA RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W RCAP3H: Timer 3 Capture High byte Register SFR Page = 1 Only SFR Address = 0xCB RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W

megawin Version: 1.00 144 16.4. Timer Global Control When the applications are asking all timers work together in sync mode, it can set the registers to Start, Reload and Stop the timers. 16.4.1. Global Enable for all Timer Run When the applications are asking all timers work together in sync mode, just need to set the TRxE or TRxLE in TREN0 to start the timer at the same time. Those registers will be auto cleared by hardware after writing “1” into it. TREN0: Timer Run Enable Register 0 SFR Page = 1 Only SFR Address = 0x95 RESET= 0000-0000 7 6 5 4 3 2 1 0 -- TR3LE TR2LE -- TR3E TR2E TR1E TR0E W R/W R/W W R/W R/W R/W R/W Bit 7: Reserved. Software must write “0” on this bit when TREN0 is written. Bit 6, TR3LE, write “1” on this bit to set TR3L enabled (TR3L=1) when Timer 3 in split mode. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 5, TR2LE, write “1” on this bit to set TR2L enabled (TR2L=1) when Timer 2 in split mode. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 4: Reserved. Software must write “0” on this bit when TREN0 is written. Bit 3, TR3E, write “1” on this bit to set TR3 enabled (TR3=1). This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 2, TR2E, write “1” on this bit to set TR2 enabled (TR2=1). This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 1, TR1E, write “1” on this bit to set TR1 enabled (TR1=1). This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 0, TR0E, write “1” on this bit to set TR0 enabled (TR0=1). This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. 16.4.2. Global Control for all Timer Reload TRLC0: Timer Reload Control Register 0 SFR Page = 2 Only SFR Address = 0x95 RESET= 0000-0000 7 6 5 4 3 2 1 0 -- TL3RLC TL2RLC -- T3RLC T2RLC T1RLC T0RLC W R/W R/W W R/W R/W R/W R/W Bit 7: Reserved. Software must write “0” on this bit when TRLC0 is written. Bit 6, TL3RLC, write “1” on this bit to force TL3 reload condition happened when Timer 3 in split mode. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 5, TL2RLC, write “1” on this bit to force TL2 reload condition happened when Timer 2 in split mode. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 4: Reserved. Software must write “0” on this bit when TRLC0 is written.

megawin Version: 1.00 145 Bit 3, T3RLC, write “1” on this bit to force TH3 and TL3 reload condition happened when Timer 3 not in split mode. Or force TH3 reload condition happened when Timer 3 in split mode. The force reload is not available if the timer in capture mode. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 2, T2RLC, write “1” on this bit to force TH2 and TL2 reload condition happened when Timer 2 not in split mode. Or force TH2 reload condition happened when Timer 2 in split mode. The force reload is not available if the timer in capture mode. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 1, T1RLC, write “1” on this bit to force TH1/TL1 reload condition happened. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 0, T0RLC, write “1” on this bit to force TH0/TL0 reload condition happened. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. 16.4.3. Global Control for all Timer Stop TSPC0: Timer Stop Control Register 0 SFR Page = 3 Only SFR Address = 0x95 RESET= 0000-0000 7 6 5 4 3 2 1 0 -- TL3SC TL2SC -- T3SC T2SC T1SC T0SC W R/W R/W W R/W R/W R/W R/W Bit 7: Reserved. Software must write “0” on this bit when TSPC0 is written. Bit 6, TL3SC, write “1” on this bit to set TR3L disabled (TR3L=0) when Timer 3 in split mode. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 5, TL2SC, write “1” on this bit to set TR2L disabled (TR2L=0) when Timer 2 in split mode. This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 4: Reserved. Software must write “0” on this bit when TSPC0 is written. Bit 3, T3SC, write “1” on this bit to set TR3 disabled (TR3=0). This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 2, T2SC, write “1” on this bit to set TR2 disabled (TR2=0). This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 1, T1SC, write “1” on this bit to set TR1 disabled (TR1=0). This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action. Bit 0, T0SC, write “1” on this bit to set TR0 disabled (TR0=0). This bit is auto-cleared by hardware after writing “1” operation. Write “0” on this bit is no action.

megawin Version: 1.00 146 17. Programmable Counter Array (PCA0) The MG82F6D17 is equipped with a Programmable Counter Array (PCA0), which provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. 17.1. PCA Overview The PCA consists of a dedicated timer/counter which serves as the time base for an array of Six capture /compare/PWM modules and Two compare/PWM modules. Figure 17–1 shows a block diagram of the PCA. Notice that the PCA timer and modules are all 16-bits. If an external event is associated with a module, that function is shared with the corresponding Port pin. If the module is not using the port pin, the pin can still be used for standard I/O. Module 0~5 can be programmed in any one of the following modes: - Rising and/or Falling Edge Capture - Software Timer (Compare) - High Speed Output (Compare Output) - Pulse Width Modulator Output (PWM) - Compare Output on PWM Match case (COPM) Module 6~7 also support the upper modes except Rising and/or Falling Edge capture. All of these modes will be discussed later in detail. However, let's first look at how to set up the PCA timer and modules. Figure 17–1. PCA Block Diagram PCA0 Timer/Counter

16 Bits

(Cap/Comp/PWM) Module 1 (Cap/Comp/PWM) Module 2 (Cap/Comp/PWM) Module 3 (Cap/Comp/PWM) Module 4 (Cap/Comp/PWM) Module 5 (Cap/Comp/PWM) CEX0 Port Pin

16 Bits Each

(Comp/PWM) Module 7 (Comp/PWM) PWM6 Port Pin PWM7 Port Pin

megawin Version: 1.00 147 17.2. PCA Timer/Counter The timer/counter for the PCA is a auto-reload 16-bit timer consisting of registers CH and CL (the high and low bytes of the count values), CHRL, CLRL (the high and low bytes reload registers), as shown in Figure 17–2. CHRL and CLRL are reloaded to CH and CL at each time overflow on {CH+CL} counter which can change the PCA cycle time for variable PWM resolution, such as 7-bit or 9-bit PWM. {CH + CL} is the common time base for all modules and its clock input can be selected from the following source: - 1/12 the system clock frequency, - 1/2 the system clock frequency, - The Timer 0 overflow, which allows for a range of slower clock inputs to the timer, - External clock input, 1-to-0 transitions, on ECI pin, - CKMIX16, refer Section “9.1 Clock Structure”, - Directly from the system clock frequency, - The S0BRG overflow, S0TOF, - MCKDO, refer Section “9.1 Clock Structure”. Special Function Register CMOD contains the Count Pulse Select bits (CPS2, CPS1 and CPS0) to specify the PCA timer input. When CPS[2:0] indexes CKMIX16 or MCKDO, the frequency of the input clock sources must ≥ CPUCLK x3 and ≥ SYSCLK x2.This register also contains the ECF bit which enables an interrupt when the counter {CH+CL} overflows. And the counter overflow toggles C0COR, it will output on port pin when C0CKOE is enabled. In addition, the user has the option of turning off the PCA timer during Idle Mode by setting the Counter Idle bit (CIDL). This can further reduce power consumption during Idle mode. Figure 17–2. PCA Timer/Counter CMOD: PCA Counter Mode Register SFR Page = 0 Only SFR Address = 0xD9 RESET = 0000-0000 7 6 5 4 3 2 1 0 CIDL BME4 BME2 BME0 CPS2 CPS1 CPS0 ECF R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: CIDL, PCA counter Idle control. 0: Lets the PCA counter continue functioning during Idle mode. 1: Lets the PCA counter be gated off during Idle mode. (PCA0 External Input) ECI (Timer0 Overflow) T0OF SYSCLK/2 SYSCLK/12 CH 8 bits CL 8 bits 16-bits Up Counter To PCA0 Module 0~7 ECFCPS0CPS1CPS2BME0BME2BME4CIDL CCF0CCF1CCF2CCF3CCF4CCF5CRCF IDLE CMOD CCON Enable CLRLCHRL overflow PCA0 Interrupt Enable CF reload (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) SYSCLK (S0BRG Overflow) S0TOF MCKDO CPS[2:0] Indexed CKMIX16 Toggle 0 Q Port Latch C0CKOE C0CKOC0COR D Q When CPS indexes CKMIX16 or MCKDO, 1. Their frequency must ≥ CPUCLKx3 2. Their frequency must ≥ SYSCLKx2 3. CKMIX16 up to 144MHz C0TOF

megawin Version: 1.00 148 Bit 6: BME4, Buffer Mode Enable on PCA module 4/5. It is only valid on both of PCA module 4 and module 5 in capture mode, PWM mode or COPM mode. 0: PCA Module 4/5 buffer mode disabled. 1: PCA Module 4/5 buffer mode enabled. Bit 5: BME2, Buffer Mode Enable on PCA module 2/3. It is only valid on both of PCA module 2 and module 3 in capture mode, PWM mode or COPM mode. 0: PCA Module 2/3 buffer mode disabled. 1: PCA Module 2/3 buffer mode enabled. Bit 4: BME0, Buffer Mode Enable on PCA module 0/1. It is only valid on both of PCA module 0 and module 1 in capture mode, PWM mode or COPM mode. 0: PCA Module 0/1 buffer mode disabled. 1: PCA Module 0/1 buffer mode enabled. Bit 3~1: CPS2-CPS0, PCA counter clock source select bits. CPS2 CPS1 CPS0 PCA Clock Source 0 0 0 Internal clock, (system clock)/12 0 0 1 Internal clock, (system clock)/2 0 1 0 Timer 0 overflow 0 1 1 External clock at the ECI pin 1 0 0 CKMIX16 output 1 0 1 Internal clock, (system clock)/1 1 1 0 S0BRT overflow 1 1 1 MCK Divider Output, MCKDO Note: When CPS indexes CKMIX16 or MCKDO, needs to follow the conditions: 1. The source frequency must ≥ CPUCLK x3. 2. The source frequency must ≥SYSCLK x2. Bit 0: ECF, Enable PCA counter overflow interrupt. 0: Disables an interrupt when CF bit (in CCON register) is set. 1: Enables an interrupt when CF bit (in CCON register) is set. The CCON register shown below contains the run control bit for the PCA and the flags for the PCA timer and each module. To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. CCF0 to CCF5 are the interrupt flags for module 0 to module 5, respectively, and they are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA interrupt system is shown Figure 17–3. CCON: PCA Counter Control Register SFR Page = 0 only SFR Address = 0xD8 RESET = 0000-0000 7 6 5 4 3 2 1 0 CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: CF, PCA Counter Overflow flag. 0: Only be cleared by software. 1: Set by hardware when the counter rolls over. CF flag can generate an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software. Bit 6: CR, PCA Counter Run control bit. 0: Must be cleared by software to turn the PCA counter off. 1: Set by software to turn the PCA counter on. Bit 5: CCF5, PCA Module 5 interrupt flag. 0: Must be cleared by software. 1: Set by hardware when a match or capture occurs.

megawin Version: 1.00 149 Bit 4: CCF4, PCA Module 4 interrupt flag. 0: Must be cleared by software. 1: Set by hardware when a match or capture occurs. Bit 3: CCF3, PCA Module 3 interrupt flag. 0: Must be cleared by software. 1: Set by hardware when a match or capture occurs. Bit 2: CCF2, PCA Module 2 interrupt flag. 0: Must be cleared by software. 1: Set by hardware when a match or capture occurs. Bit 1: CCF1, PCA Module 1 interrupt flag. 0: Must be cleared by software. 1: Set by hardware when a match or capture occurs. Bit 0: CCF0, PCA Module 0 interrupt flag. 0: Must be cleared by software. 1: Set by hardware when a match or capture occurs. Figure 17–3. PCA Interrupt System CCF0CCF1CCF2CCF3CCF4CCF5CRCF CCON EIE1.EPCA CMOD.ECF CCAPMn.0 (n=0~7) Module 5 Module 4 Module 3 Module 2 Module 1 Module 0 IE.EA To Interrupt Priority Processing PCA0 Timer/Counter ECCF0~ECCF7 Module 7 Module 6 EPCnLEPCnHPnINVCCFn----PnRS0PnRS1 PCAPWMn n = 6 ~ 7

megawin Version: 1.00 150 PCAPWMn: PWM Mode Auxiliary Register, n=0~7 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Page = 1 only for n= 6~7 SFR Address = 0xF2~0xF7 RESET = 0000-0000 7 6 5 4 3 2 1 0 PnRS1 PnRS0 -- -- CCFn PnINV ECAPnH ECAPnL R/W R/W W W R/W R/W R/W R/W Bit 3: CCFn, only CCF6 and CCF7 are valid for the interrupt flag in module 6 and module 7. 0: Must be cleared by software. 1: Set by hardware when a match occurs. CH: PCA base timer High SFR Page = 0 ~ F SFR Address = 0xF9 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W CL: PCA base timer Low SFR Page = 0 ~ F SFR Address = 0xE9 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W CHRL: PCA CH Reload Register SFR Page = 0 ~ F SFR Address = 0xCF RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: CHRL, reload value of CH. CLRL: PCA CL Reload Register SFR Page = 0 ~ F SFR Address = 0xCE RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: CLRL, reload value of CL.

megawin Version: 1.00 151 17.3. Compare/Capture Modules Each of the compare/capture module 0~7 has a mode register called CCAPMn (n = 0,1,2,3,4,5,6 or 7) to select which function it will perform. Note the ECCFn bit which enables an interrupt to occur when a module's interrupt flag is set. CCAPMn: PCA Module Compare/Capture Register, n=0~5 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Address = 0xDA~0xDF RESET = 0000-0000 7 6 5 4 3 2 1 0 DTEn ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: DTEn. Enable Dead-Time control on PWMHn/PWMLn output pair. This bit is only valid on n= 0, 2 and 4 and the dead-time function is active when PWM channel is operating in buffer mode. The channel buffer mode is enabled by BME0, BME2 or BME4 in CMOD. 0: Disable the Dead-Time control on PWMn output. 1: Enable the Dead-Time control on PWMn output. Bit 6: ECOMn, Enable Comparator. 0: Disable the digital comparator function. 1: Enables the digital comparator function. Bit 5: CAPPn, Capture Positive enabled. Module 6 and module 7 don’t support the capture mode. 0: Disable the PCA capture function on CEXn positive edge detected. 1: Enable the PCA capture function on CEXn positive edge detected. Bit 4: CAPNn, Capture Negative enabled. Module 6 and module 7 don’t support the capture mode. 0: Disable the PCA capture function on CEXn negative edge detected. 1: Enable the PCA capture function on CEXn negative edge detected. Bit 3: MATn, Match control. 0: Disable the digital comparator match event to set CCFn. 1: A match of the PCA counter with this module’s compare/capture register causes the CCFn bit in CCON to be set. Bit 2: TOGn, Toggle control. 0: Disable the digital comparator match event to toggle CEXn. 1: A match of the PCA counter with this module’s compare/capture register causes the CEXn pin to toggle. Bit 1: PWMn, PWM control. 0: Disable the PWM mode in PCA module. 1: Enable the PWM function and cause CEXn pin to be used as a pulse width modulated output. Bit 0: ECCFn, Enable CCFn interrupt. 0: Disable compare/capture flag CCFn in the CCON register to generate an interrupt. 1: Enable compare/capture flag CCFn in the CCON register to generate an interrupt. Note: The bits CAPNn (CCAPMn.4) and CAPPn (CCAPMn.5) determine the edge on which a capture input will be active. If both bits are set, both edges will be enabled and a capture will occur for either transition. Each module also has a pair of 8-bit compare/capture registers (CCAPnH, CCAPnL) associated with it. These registers are used to store the time when a capture event occurred or when a compare event should occur. When a module is used in the PWM mode, in addition to the above two registers, an extended register PCAPWMn is used to improve the range of the duty cycle of the output. The improved range of the duty cycle starts from 0%, up to

megawin Version: 1.00 152 CCAPMn: PCA Module Compare/Capture Register, n=6~7 SFR Page = 1 only for n= 6~7 SFR Address = 0xDB, 0xDA RESET = 0000-0000 7 6 5 4 3 2 1 0 BME6 ECOMn -- CAPNn MATn TOGn PWMn ECCFn R/W R/W W R/W R/W R/W R/W R/W Bit 7: BME6(This is only valid in CCAPM6) Buffer Mode Enable on PCA module 6/7. It is only valid on both of PCA module 6 and module 7 in capture mode, PWM mode or COPM mode. 0: PCA Module 6/7 buffer mode disabled. 1: PCA Module 6/7 buffer mode enabled. Bit 6: ECOMn, Enable Comparator. 0: Disable the digital comparator function. 1: Enables the digital comparator function. Bit 5: Reserved. Module 6 and module 7 don’t support the capture mode. Bit 4: CAPNn, Capture Negative enabled. Module 6 and module 7 don’t support the capture mode. CAPN6 and CAPN7 is used for other PCA modes setting, please reference “Table 17–1. PCA Module Modes” for details. Bit 3: MATn, Match control. 0: Disable the digital comparator match event to set CCFn. 1: A match of the PCA counter with this module’s compare/capture register causes the CCFn bit in PCAPWMn to be set. Bit 2: TOGn, Toggle control. 0: Disable the digital comparator match event to toggle CEXn. 1: A match of the PCA counter with this module’s compare/capture register causes the CEXn pin to toggle. Bit 1: PWMn, PWM control. 0: Disable the PWM mode in PCA module. 1: Enable the PWM function and cause CEXn pin to be used as a pulse width modulated output. Bit 0: ECCFn, Enable CCFn interrupt. 0: Disable compare/capture flag CCFn in the PCAPWMn register to generate an interrupt. 1: Enable compare/capture flag CCFn in the PCAPWMn register to generate an interrupt. Each module also has a pair of 8-bit compare/capture registers (CCAPnH, CCAPnL) associated with it. These registers are used to store the time when a compare event occur. When a module is used in the PWM mode, in addition to the above two registers, an extended register PCAPWMn is used to improve the range of the duty cycle of the output. The improved range of the duty cycle starts from 0%, up to CCAPnH: PCA Module n Capture High Register, n=0~7 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Page = 1 only for n= 6~7 SFR Address = 0xFA~0xFF RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W CCAPnL: PCA Module n Capture Low Register, n=0~7 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Page = 1 only for n= 6~7 SFR Address = 0xEA~0xEF RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W

megawin Version: 1.00 153 PCAPWMn: PWM Mode Auxiliary Register, n=0~7 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Page = 1 only for n= 6~7 SFR Address = 0xF2~0xF7 RESET = 0000-0000 7 6 5 4 3 2 1 0 PnRS1 PnRS0 -- -- CCFn PnINV ECAPnH ECAPnL R/W R/W W W R/W R/W R/W R/W Bit 7~6: PnRS1~0, PWMn Resolution Setting 1~0. 00: 8 bit PWMn, the overflow is active when [CH, CL] counts XXXX-XXXX-1111-1111  XXXX-XXXX-0000-0000. 01: 10 bit PWMn, the overflow is active when [CH, CL] counts XXXX-XX11-1111-1111  XXXX-XX00-0000-0000. 10: 12 bit PWMn, the overflow is active when [CH, CL] counts XXXX-1111-1111-111  XXXX-0000-0000-0000. 11: 16 bit PWMn, the overflow is active when [CH, CL] counts 1111-1111-1111-1111 0000-0000-0000-0000. Bit 5~4: Reserved. Software must write “0” on these bits when PCAPWMn is written. Bit 3: CCFn, only CCF6 and CCF7 are valid for the interrupt flag in module 6 and module 7. 0: Must be cleared by software. 1: Set by hardware when a match occurs. Bit 2: PnINV, Invert Compare/PWM output (C0PnOR) on CEXn pin. 0: Non-inverted Compare/PWM output (C0PnOR). 1: Inverted Compare/PWM output (C0PnOR). Bit 1: ECAPnH, Extended 9th bit (MSB bit), associated with CCAPnH to become a 9-bit register used in PWM mode. Bit 0: ECAPnL, Extended 9th bit (MSB bit), associated with CCAPnL to become a 9-bit register used in PWM mode. 17.4. Operation Modes of the PCA Table 17–1 shows the CCAPMn register settings for the various PCA functions. Table 17–1. PCA Module Modes ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Module Function 0 0 0 0 0 0 0 No operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative-edge trigger on CEXn X 1 1 0 0 0 X 16-bit capture by a transition on CEXn 1 0 0 1 0 0 X 16-bit Software Timer (Compare) 1 0 0 1 1 0 X 16-bit High Speed Output (HSO) 1 0 0 0 0 1 X Pulse Width Modulator (PWM) 1 0 0 0 1 1 X Compare Output on PWM match case (COPM) 1 0 1 0 0 1 X FIFO Data Mode Note: PCA Module 6 and module 7 don’t support the capture mode.

megawin Version: 1.00 154 17.4.1. Capture Mode To use one of the PCA modules in the capture mode, either one or both of the bits CAPN and CAPP for that module must be set. The external CEX input for the module is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH). If the CCFn and the ECCFn bits for the module are both set, an interrupt will be generated. Figure 17–4. PCA Capture Mode CCF0CCF1CCF2CCF3CCF4CCF5CRCF CCON ECCFnPWMnTOGnMATnCAPNnCAPPnECOMnDETxCCAPMn CCAPnLCCAPnH CH CL Capture (To CCFn) PCA Timer/Counter PCA Interrupt 0000 0/1 0/1 CAPPn or CAPNn =1 CLRLCHRL overflow reload CEXn n = 0 ~ 5 n = 0 ~ 5 0 0/1 x = 0,2,4 C0IC4S0 (AUXR5.7) CEX4 Port Pin T2EXI (from Timer 2 module) C0IC2S0 (AUXR5.6) CEX2 Port PinCEX4 capture input CEX2 capture inputT3EXI (from Timer 3 module)

megawin Version: 1.00 157 17.4.5. Buffered 8-bit PWM Mode All of the PCA modules can be used as PWM outputs. The frequency of the output depends on the clock source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is determined by the module’s capture register CCAPnL and the extended 9 th bit, ECAPnL. When the 9-bit value of { 0, [CL] } is less than the 9-bit value of { ECAPnL, [CCAPnL] } the output will be low, and if equal to or greater than the output will be high. When CL overflows from 0xFF to 0x00, { ECAPnL, [CCAPnL] } is reloaded with the value of { ECAPnH, [CCAPnH] }. This allows updating the PWM without glitches. The PWMn and ECOMn bits in the module’s CCAPMn register must be set to enable the PWM mode. Using the 9-bit comparison, the duty cycle of the output can be improved to really start from 0%, and up to 100%. The formula for the duty cycle is: Duty Cycle = 1 – { ECAPnH, [CCAPnH] } / 256. Where, [CCAPnH] is the 8 -bit value of the CCAPnH register, and ECAPnH (bit-1 in the PCAPWMn register) is 1- bit value. So, { ECAPnH, [CCAPnH] } forms a 9-bit value for the 9-bit comparator. For examples, a. If ECAPnH=0 & CCAPnH=0x00 (i.e., 0x000), the duty cycle is 100%. b. If ECAPnH=0 & CCAPnH=0x40 (i.e., 0x040) the duty cycle is 75%. c. If ECAPnH=0 & CCAPnH=0xC0 (i.e., 0x0C0), the duty cycle is 25%. d. If ECAPnH=1 & CCAPnH=0x00 (i.e., 0x100), the duty cycle is 0%. Figure 17–9. PCA Buffered 8-bit PWM Mode ECCFnPWMnTOGnMATnCAPNnCAPPnECOMnDTEx CCAPMn, n= 0 ~ 7 CCAPnL CCAPnH CL Enable PCA Timer/Counter 11 0 0 9-Bit Comparator ECAPnH ECAPnL (Fixed 0) 0 0 overflow

9 Bits

S R Q Q CCF0CCF1CCF2CCF3CCF4CCF5CRCF CCON PCA Interrupt match ECCFn 9th Bit CEXn (PWMn) PWMnH PWMnL Q Port I/O PWMn CLRL reload C0PLKreload n = 0 ~ 7 Buffered 8-bit PWM: PnRS[1:0] = 00 C0PnOR PnINVCCFn----PnRS0PnRS1 PCAPWMn, n = 0 ~ 7 ECAPnLECAPnH 0 0 0 0/1 x = 0,2,4 n = 6,7(To CCFn) (To CCFn) n = 0, 2, 4

megawin Version: 1.00 158 17.4.6. Un-buffered 10/12/16-bit PWM Mode The PCA provides the variable PWM mode to enhance the control capability on PWM application. There are additional un-buffered 10/12/16 bits PWM can be assigned in each channel and each PWM channel with different resolution can operate concurrently. Figure 17–10. PCA Un-buffered10/12/16-bit PWM Mode ECCFnPWMnTOGnMATnCAPNnCAPPnECOMnDTEx CCAPMn, n= 0 ~ 7 Enable 0/111 0 0 0 0 overflow S R Q Q CCF0CCF1CCF2CCF3CCF4CCF5CRCF CCON PCA Interrupt match ECCFn CCAPnLCCAPnH CH CLPCA Timer/Counter 11/13/17-Bit Comparator 11/13/17th Bit

17 Bits

Q Port I/O PWMn ECAPnL 1b '0' ECAPnH reload 11/13/17th Bit C0PLK Un-buffered 10/12/16-bit PWM: PnRS[1:0] = 01/10/11 PnINVCCFn----PnRS0PnRS1 PCAPWMn, n = 0 ~ 7 ECAPnLECAPnH 0/1 0/1 C0PnOR 11/13/17 Bits CEXn (PWMn) n = 0 ~ 7 x = 0,2,4 n = 6,7(To CCFn) (To CCFn) n = 0~5

megawin Version: 1.00 159 17.4.7. Buffered 10/12/16-bit PWM Mode To use 10/12/16-bit PWM mode might cause unexpected duty cycle when change the duty cycle setting by writing data into CCAPnH and CCAPnL, because the 8 bit CPU can only write one byte at a time. To finish fully setting it will take two write cycles, and the comparator will output unexpected duty cycle when the first byte have been written. If the applications need accurate control when change the duty cycle, it needs to use the Buffered PWM mode. Figure 17–11. PCA Buffered 10/12/16-bit PWM Mode (with dead time control) ECCFnPWMnTOGnMATnCAPNnCAPPnECOMnDTEx CCAPMn, n= 0 to 7 Enable 0/111 0 0 0 0 Overflow S R Q Q PnINV, n= 0,2,4,6 CCF0CCF1CCF2CCF3CCF4CCF5CRCF CCON Match CCAPnLCCAPnH CH CLPCA Timer/Counter 11/13/17-Bit Comparator 11/13/17 Bits Q Port I/O PWMn, n= 0,2,4,6 ECAPnL 1b '0' ECAPnL CCAPnLCCAPnH n= 1,3,5,7 n= 0,2,4,6 11/13/17th Bit 11/13/17th Bit Dead Time Control dPWMnH dPWMnL PnINV, n= 1,3,5,7 Port I/O PWMn, n= 1,3,5,7 Enabled by: DTE0/DET2/DET4 PCA Interrupt ECCFn reload C0PLK Buffered 9~16-bit PWM: BM0/BM2/BM4 = 1, PnRS[1:0] = 01/10/11 PnINVCCFn----PnRS0PnRS1PCAPWMn, n = 0 ~ 7 ECAPnLECAPnH 0/1 0/1 C0PnOR ECFCPS0CPS1CPS2BME0BME2BME4CIDLCMOD 0/1 0/10/1 (To CCFn) n = 6 CEXn (PWMn) n = 0,2,4,6 CEXn (PWMn) n = 1,3,5,7 x = 0,2,4 (To CCFn) n = 0, 2, 4 1. Module 0 and module 1 are paired if BME0 is set. 2. Module 2 and module 3 are paired if BME2 is set. 3. Module 4 and module 5 are paired if BME4 is set. 4. Module 6 and module 7 are paired if BME6 is set. (BME6 is located at CCAPM6.7) 5. Only pair 0/1, 2/3, 4/5 support dead-time control, central-aligned & break control.

megawin Version: 1.00 160 17.4.8. COPM Mode Compare Output on PWM Match mode is similar to High Speed Output Mode, but it uses PCA0 PWM comparators instead of fixed 16-bit comparators. It gives more flexibility to the applications. For example, if it uses 8-Bit PWM for the PCA0 comparator, the output toggles frequency can higher than High Speed Output Mode. Figure 17–12. PCA COPM Mode ECCFnPWMnTOGnMATnCAPNnCAPPnECOMnDTEx CCAPMn, n= 0 ~ 7 Enable 0/111 0 0 0 1 CCF0CCF1CCF2CCF3CCF4CCF5CRCF CCON PCA Interrupt match ECCFn PCA Module n (n=0~7) PWM Comparator PWMnH PWMnL Q Port I/O PWMn Un-buffered COPM: PnRS[1:0] = 00/01/10/11 PnINVCCFn----PnRS0PnRS1 PCAPWMn, n = 0 ~ 7 ECAPnLECAPnH 0/1 0/1 Toggle D Q C0PnOR CEXn (PWMn) n = 0 ~ 7 n = 6,7(To CCFn) x = 0,2,4 (To CCFn) n = 0~5

megawin Version: 1.00 161 17.4.9. Buffered COPM Mode If the applications need to have any phase control of the PWM signals, it needs to set the PCA0 modules in buffered COPM mode. One pair of the PCA0 module (n=0&1 / 2&3 / 4&5) can program the time delay of the two edges of one cycle of the PWM signal. It means you can set the start and end point of the waveform. This is useful when the 2 or 3 correlation PWM signals can set the phase shift between each other. Figure 17–13. PCA Buffered COPM Mode ECCFnPWMnTOGnMATnCAPNnCAPPnECOMnDTEx CCAPMn, n= 0~7 Enable 0/111 0 0 0 1 CCF0CCF1CCF2CCF3CCF4CCF5CRCF CCON (To CCF0/2/4) PCA Interrupt match ECCFn PCA Module n (n=0/2/4/6) PWM Comparator Buffered COPM: PnRS[1:0] = 00/01/10/11, BME0/BME2/BME4 = 1 PnINVCCFn----PnRS0PnRS1 PCAPWMn, n = 0 ~ 7 ECAPnLECAPnH 0/1 0/1 PCA Module n (n=1/3/5/7) PWM Comparator S R Q Q PnINV n= 0,2,4,6 PWMnH PWMnL Q Port I/O PWMn n= 0,2,4,6 PnINV n= 1,3,5,7 Port I/O PWMn n= 1,3,5,7 C0PnOR (To CCF1/3/5) match 1. Module 0 and module 1 are paired if BME0 is set. 2. Module 2 and module 3 are paired if BME2 is set. 3. Module 4 and module 5 are paired if BME4 is set. 4. Module 6 and module 7 are paired if BME6 is set. (BME6 is located at CCAPM6.7) ECFCPS0CPS1CPS2BME0BME2BME4CIDL CMOD 0/1 0/10/1 CEXn (PWMn) n = 0,2,4,6 CEXn (PWMn) n = 1,3,5,7 x = 0,2,4 (To CCF6) (To CCF7)

megawin Version: 1.00 162 17.4.10. FIFO Data Mode In this mode the user can set the CCAPnL, CCAPnH, CCAP(n+1)L and CCAP(n+1)H as a buffer chain. After all these buffers are set, it can change the duty sequentially trigger by T0OF, T1OF, T3OF or S0TOF. This function is enabled, the CPU can leave it to run by itself to earn more time slot to do other operations. For example, when the power converter start to raise the voltage from light load to heave load, it might useful to set the duty larger than the target it the beginning period, and then reduce the duty step by step close to the target duty. It can just set all duties in the buffer and leave it to finish. Figure 17–14. PCA channel for FIFO Data Mode Channel FIFO data mode that is moved on C0FDCK. C0FDCK source selection, updated clock selection of PCA0 FIFO Data mode. C0FDC1~0 C0FDCK

00 T0OF

01 T1OF

10 T3OF

AUXR9: Auxiliary Register 9 SFR Page = 6 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- T1G0 T0G1 C0FDC1 C0FDC0 S1PS1 S1PS0 W W R/W R/W R/W R/W R/W R/W Bit 3~2: C0FDC1~0, C0FDCK Selection [1:0]. C0FDC1~0 C0FDCK Reload Control by PCA counter overflow CCAP(n+1)L CCAP(n+1)H Reload Control by C0FDCK event C0FDC[1:0] T0OF(0,0) (0,1) (1,0) (1,1) T1OF T3OF S0TOF CPU Write Channel n+1 in FD mode Channel n in PWM mode ECCFnPWMnTOGnMATnCAPNnCAPPnECOMnDTEx CCAPMn 8-bit FIFO Data Mode: PnRS[1:0] = 00 000 110 01 n= 1~7

megawin Version: 1.00 163 17.4.11. Enhanced PWM Control The PCA provides the variable PWM mode to enhance the control capability on PWM application. There are additional 10/12/16 bits PWM can be assigned in each channel and each PWM channel with different resolution and different phase delay can operate concurrently. Figure 17–15. PWM Waveform with Dead-Time Control CCAPMn: PCA Module Compare/Capture Register, n=0~5 SFR Page = 0 only for n= 0~1 (n=2~5 for all page) SFR Address = 0xDA~0xDF RESET = 0000-0000 7 6 5 4 3 2 1 0 DTEn ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: DTEn. Enable Dead-Time control on PWMHn/PWMLn output pair. This bit is only valid on n= 0, 2 and 4 and the dead-time function is active when PWM channel is operating in buffer mode. The channel buffer mode is enabled by BME0, BME2 or BME4 in CMOD. 0: Disable the Dead-Time control on PWMn output. 1: Enable the Dead-Time control on PWMn output. PWMnH dPWMnH dPWMnL PWMnL PWM period: m n m p p m: 65536 - {CHRL,CLRL} n: 65536 - {CCAPnH,CCAPnL} p: 2(DTPS1,DTPS0) x (DT[5:0]) m - n n - pm - n - p dPWMnH w/ dead-time control dPWMnL w/ dead-time control p pm - n n PWM period: m + px2 dPWMnH w/ dead-time control dPWMnL w/ dead-time control p p n x 2 PWM period: mx2 + px2 Normal 16-bit PWM PWM with dead-time control PWM with dead-time control & EXDT enabled & Edge Aligned PWM with dead-time control & EXDT enabled & Central Aligned m - n n p

megawin Version: 1.00 164 PDTCRA: PWM Dead-Time Control Register -A SFR Page = 1 only SFR Address = 0xBC RESET = 0000-0000 7 6 5 4 3 2 1 0 DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: DTPS1~0, Clock Pre-Scaler of Dead-Time counter. DTPS[1:0] Pre-Scaler Selection

00 SYSCLK

01 SYSCLK/2

10 SYSCLK/4

11 SYSCLK/8

Bit 5~0: DT5~0, Dead-Time period control bits. DT[5:0] Dead-Time Period

000000 Dead-Time Disabled

000001 Pre-Scaler Clock X 1

000010 Pre-Scaler Clock X 2

000011 Pre-Scaler Clock X 3

….. ……

111110 Pre-Scaler Clock X 62

111111 Pre-Scaler Clock X 63

PWMCR: PWM Control Register SFR Page = 0 only SFR Address = 0xBC RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: PCAE, PWM Central Aligned Enabled. PCAE controls the enabled PWM channels to central aligned modulation including buffer mode PWM or non-buffer mode PWM. In this PWM mode, the PWM frequency is the half of edge aligned mode. This function is only active on PWMO0~5. 0: Set the PWM function with edge aligned modulation. 1: Enable the PWM function with central aligned modulation. It only supports 8/10/12/16-bit resolution on CHRL and CLRL setting. Figure 17–16. Waveform of Edge Aligned PWM and Central Aligned PWM Bit 6: EXDT: Extend Dead-Time in PWM Period. This function will corrupt the non-PWM channel function. Such as capture mode, software timer mode and high speed output mode. 0: Disable M + 2P. 1: Enable M + 2P on enabled PWM channel. PWM Duty Cycle PWM Period 65536 – {CHRL,CLRL} PWMnH 65536 - {CCAPnH,CCAPnL} Edge Aligned PWM (16-bit) Duty Cycle = Duty Cycle = PWM Period (65536 –{CHRL,CLRL}) X 2 PWMnH (65536 - {CCAPnH,CCAPnL}) Central Aligned PWM (16-bit) PWM Duty Cycle

megawin Version: 1.00 166 Figure 17–19. PCA PWM Break control source AUXR0: Auxiliary Register 0 SFR Page = 0~F SFR Address = 0xA1 RESET = 0000-0000 7 6 5 4 3 2 1 0 P60OC1 P60OC0 P60FD PBKF -- -- INT1H INT0H R/W R/W R/W R/W W W R/W R/W Bit 4: PBKF, PWM Break Flag. This bit is set by PWM break source enabled. If this flag is set, the enabled PWM channel 0~5 will be blocked and the output pins keep the original GPIO state. 0: There is no PWM Break event happened. It is only cleared by software. 1: There is a PWM Break event happened or software triggers a PWM Break. PBKE0.2~0 INT2ET xxx PBKE1.1~0 KBIET xxx INT1ET T2EXI (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) KBIET xxx xxx xxx (0,0) (0,1) (1,0) (1,1) PWM Break ControlPBKF SET (AUXR0.4) Disable Disable

megawin Version: 1.00 167 17.4.12. PCA Module Output Control PCA0 modules have multi output control mode can be selected for different applications. The CEXn (n=1,3,4,5,6,7) can be programed as general I/O port or the output of the PCA0 module (PWM) 1, 3, 4, 5, 6 and 7. When PWM has been assigned to the CEXn, the PnINV can switch between the normal PWM signal or inverted PWM signal. POEn can be used to enable or disable the PWM output to the port pin. The CEXn (n=1,3,4,5) also can use PBKF, PWM Break Flag, to break PWM output. If this flag is set, the enabled PWM channel 0~5 will be blocked and the output pins keep the original GPIO state. In addition, PCA0 module 0 and 2 have 2 “Cloned” signals to the different port pin. These three the same PWM signals can be masked particular cycles by the POEnA or POEnB or PWMn for the applications which need phase control. Figure 17–20. PCA Module output control PWMn PWMnH PWMnL PnINV POEn PBKF PWMnO PWMnB n = 0, 2 PWMn POEnB PBKF PWMnA n = 0, 2 Q PWMn POEnA PBKF CEXn(PWMn), n= 0,2 Port Output Latch QPort Output Latch QPort Output Latch CEXn(PWMn), n= 1,3,4,5 PWMn PWMnH PWMnL PnINV POEn PBKF PWMnO QPort Output Latch

megawin Version: 1.00 168 PAOE: PWM Additional Output Enable Register SFR Page = 0~F SFR Address = 0xF1 RESET = 1001-1001 7 6 5 4 3 2 1 0 POE3 POE2B POE2A POE2 POE1 POE0B POE0A POE0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: POE3, PCA0 PWM3 main channel (PWM3O) output control. 0: Disable PWM3O output on port pin. 1: Enable PWM3O output on port pin. Default is enabled. Bit 6: POE2B, PCA0 PWM2 3rd channel (PWM2B) output control. 0: Disable PWM2B output on port pin. Default is disabled. 1: Enable PWM2B output on port pin. Bit 5: POE2A, PCA0 PWM2 2nd channel (PWM2A) output control. 0: Disable PWM2A output on port pin. Default is disabled. 1: Enable PWM2A output on port pin. Bit 4: POE2, PCA0 PWM2 main channel (PWM2O) output control. 0: Disable PWM2O output on port pin. 1: Enable PWM2O output on port pin. Default is enabled. Bit 3: POE1, PCA0 PWM1 main channel (PWM1O) output control. 0: Disable PWM1O output on port pin. 1: Enable PWM1O output on port pin. Default is enabled. Bit 2: POE0B, PCA0 PWM0 3rd channel (PWM0B) output control. 0: Disable PWM0B output on port pin. Default is disabled. 1: Enable PWM0B output on port pin. Bit 1: POE0A, PCA0 PWM0 2nd channel (PWM0A) output control. 0: Disable PWM0A output on port pin. Default is disabled. 1: Enable PWM0A output on port pin. Bit 0: POE0, PCA0 PWM0 main channel (PWM0O) output control. 0: Disable PWM0O output on port pin. 1: Enable PWM0O output on port pin. Default is enabled. AUXR7: Auxiliary Register 7 SFR Page = 4 Only SFR Address = 0xA4 RESET = 1100-0000 7 6 5 4 3 2 1 0 POE5 POE4 C0CKOE SPI0M0 -- -- -- -- R/W R/W R/W R/W W W W W CEXn(PWMn), n= 6,7 PWMn PWMnH PWMnL PnINV POEn PWMnO QPort Output Latch

megawin Version: 1.00 169 Bit 7: POE5, PCA0 PWM5 main channel (PWM5O) output control. 0: Disable PWM5O output on port pin. 1: Enable PWM5O output on port pin. Default is enabled. Bit 6: POE4, PCA0 PWM4 main channel (PWM4O) output control. 0: Disable PWM4O output on port pin. 1: Enable PWM4O output on port pin. Default is enabled. Bit 5: C0CKOE, PCA0 clock output enable. 0: Disable PCA0 clock output. 1: Enable PCA0 clock output with PCA0 base timer overflow rate/2. AUXR5: Auxiliary Register 5 SFR Page = 2 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 C0IC4S0 C0IC2S0 C0PPS1 C0PPS0 -- C0PS0 ECIPS0 C0COPS R/W R/W R/W R/W W R/W R/W R/W Bit 7: C0IC4S0, PCA0 Input Channel 4 input port pin Selection. C0IC4S0 CEX4 input Bit 6: C0IC2S0, PCA0 Input Channel 2 input port pin Selection. C1IC2S0 CEX2 input Bit 5: C0PPS1, {PWM2A, PWM2B} Port pin Selection 1. C0PPS1 PWM2A PWM2B 0 P6.0 P6.1 1 P3.4 P3.5 Bit 4: C0PPS0, {PWM0A, PWM0B} Port pin Selection 0. C0PPS0 PWM0A PWM0B 0 P1.6 P1.7 1 P6.0 P6.1 Bit 3: Reserved. Bit 2: C0PS0, PCA0 Port pin Selection 0. C0PS0 CEX0 CEX2 CEX4 0 P2.2 P2.4 P1.7 1 P3.0 P2.4 P3.1 Bit 1: ECIPS0, PCA0 ECI Port pin Selection0. ECIPS0 ECI 0 P4.4 1 P1.6 Bit 0: C0COPS, PCA0 Clock Output (C0CKO) port pin Selection. C0COPS C0CKO 0 P4.7 1 P3.3

megawin Version: 1.00 170 AUXR8: Auxiliary Register 8 SFR Page = 5 only SFR Address = 0xA4 RESET = 1100-0000 7 6 5 4 3 2 1 0 POE7 POE6 C0PPS2 -- KBI0PS0 S1COPS -- -- R/W R/W R/W W R/W R/W W W Bit 7: POE7, PCA0 PWM7 main channel (PWM7O) output control. 0: Disable PWM7O output on port pin. 1: Enable PWM7O output on port pin. Default is enabled. Bit 6: POE6, PCA0 PWM6 main channel (PWM6O) output control. 0: Disable PWM6O output on port pin. 1: Enable PWM6O output on port pin. Default is enabled. Bit 5: C0PPS2, {PWM6, PWM7} Port pin Selection 2. C0PPS2 PWM6 PWM7 0 P6.0 P6.1 1 P3.0 P3.1 17.4.13. Variable Resolution on Central Aligned PWM In Section “Enhanced PWM Control”, it defines the central aligned PWM only support the 8/10/12/16-bit resolution. And in that mode, all of PCA functions, capture or compare, on other non-PWM modules are still available. If it is necessary to apply the variable resolution on central aligned PWM, software must set C0M0 to enable the PCA0 to support this function operating. In this mode, PCA0 can support all compare or PWM modes. Otherwise, not support. Please note when using Central Aligned PWM with C0M0 = 1, Please note when using Central Aligned PWM with C0M0 = 1, we suggest to set the PWM module under 16-bit mode and the base timer need to use 16-bit 0xFFFF to minus the value to prevent unexpected error. Figure 17–21. Central Aligned PWM with Variable Resolution Duty Cycle = PWM cycle Bottom {CHRL, CLRL} PWM Period (65536 –{CHRL,CLRL}) X 2 PWMnH (65536 - {CCAPnH,CCAPnL}) Central Aligned PWM (C0M0 = 1) PWM Duty Cycle PWM cycle Top = {CH, CL} overflow Set CF when C0OFS=0 Set CF when C0OFS=1

megawin Version: 1.00 171 AUXR11: Auxiliary Register 11 SFR Page = 8 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 P30AM -- -- -- -- -- C0M0 C0OFS R/W W W W W W R/W R/W Bit 1: C0M0, PCA0 Mode control 0. 0: Not support variable resolution on central aligned PWM. 1: Enable PCA0 variable resolution central aligned PWM. To enable this function, the PCAE also needs to be set. Bit 0: C0OFS, PCA0 overflow flag selection when C0M0 is enabled. 0: CF is set on the top of central aligned PWM cycle. 1: CF is set on the bottom of central aligned PWM cycle.

megawin Version: 1.00 175 18.2. Serial Port 0 Mode 1 10 bits are transmitted through TXD0, or received through RXD0: a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB80 in S0CON. The baud rate is determined by the Timer 1 or Timer 2 overflow rate. Figure 18–1 shows the data frame in Mode 1 and Figure 18–6 shows a simplified functional diagram of the serial port in Mode 1. Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to S0BUF” signal requests the UART0 engine to start the transmission. After receiving a transmission request, the UART0 engine would start the transmission at the raising edge of TX Clock. The data in the S0BUF would be serial output on the TXD0 pin with the data frame as shown in Figure 18–1 and data width depend on TX Clock. After the end of 8th data transmission, TI0 would be asserted by hardware to indicate the end of data transmission and its interrupt vector can be switched to System Flag interrupt by BTI and UTIE gated. Reception is initiated when Serial Port 0 Controller detected 1-to-0 transition at RXD0 sampled by RCK. The data on the RXD0 pin would be sampled by Bit Detector in Serial Port 0 Controller. After the end of STOP-bit reception, RI0 would be asserted by hardware to indicate the end of data reception and load STOP-bit into RB80 in S0CON register. Figure 18–6. Serial Port Mode 1, 2, 3 UART engine TXBUF RXBUF RXD0 TXD0 SMOD1 RCLK TCLK TX Clock Timer 1 Overflow “1” “1” “0” “0” “0” “1” Timer 2 OverflowSYSCLK/2 “0” “1”

1 RX Clock

Mode 1, 3 clock source Mode 2 clock source RCK SMOD2 80C51 Internal BUS Read S0BUF 80C51 Internal BUS Write S0BUF

16 STOP-Bit

megawin Version: 1.00 177 18.5. Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications as shown in Figure 18–8. In these two modes, 9 data bits are received. The 9th bit goes into RB80. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB80=1. This feature is enabled by setting bit SM20 (in S0CON register). A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM20=1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and check if it is being addressed. The addressed slave will clear its SM20 bit and prepare to receive the data bytes that will be coming. The slaves that weren’t being addressed leave their SM20 set and go on about their business, ignoring the coming data bytes. SM20 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM20=1, the receive interrupt will not be activated unless a valid stop bit is received. Figure 18–8. UART0 Multiprocessor Communications 18.6. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART0 to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of firmware overhead by eliminating the need for the firmware to examine every serial address which passes by the serial port. This feature is enabled by setting the SM20 bit in S0CON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI0) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 18–9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM20 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM20 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. Slave 3 Slave 2 Slave 1 Master R VCC Pull-up TXRX RX RX RXTX TX TX

megawin Version: 1.00 178 The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0xA9) and SADEN (SFR address 0xB9) are loaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the micro-controller to use standard 80C51 type UART drivers which do not make use of this feature. Figure 18–9. Auto-Address Recognition Note: (1) After address matching (addr_match=1), Clear SM20 to receive data bytes (2) After all data bytes have been received, Set SM20 to wait for next address. D1 D2 D3 D4 D5 D6Start D0 StopD8D7 9-bit data Comparator Receive Address D0~D7 Programmed Address addr_match S0CON RI0TI0RB80TB80REN0SM20SM10SM00/ FE

megawin Version: 1.00 179 18.7. Baud Rate Setting Bits T2X12 (T2MOD.4), T1X12 (AUXR2.3), URM0X3 (S0CFG.5) and SMOD2 (S0CFG.6) provide a new option for the baud rate setting, as listed below. 18.7.1. Baud Rate Selection in S0 In the Mode 1 and Mode 3 operation of the UART0, the software can select Timer 1 as the Baud Rate Generator by clearing bits TCLK and RCLK in T2CON register. At this time, if URTS bit (S0CFG.7) is set, then Timer 1 overflow signal will be replaced by the overflow signal of the UART1 Baud Rate Generator (S1BRG). In other words, the user can adopt S1BRG as the Baud Rate Generator for Mode 1 or Mode 3 of the UART 0 as long as RCLK=0, TCLK=0 and URTS=1. In this condition, Timer 1 is free for other application. Of course, if UART 1 (Mode 1 or Mode 3) is also operated at this time, these two UARTs will have the same baud rates. Figure 18–10. Baud Rate Source for the UART0 18.7.2. Baud Rate in Mode 0 Note: If URM0X3=0, the baud rate formula is as same as standard 8051. TX Clock RX Clock Timer 2 Overflow (T2OF) S0 TX/RX EngineTimer 1 Overflow (T1OF) SMOD1 (PCON0.7) TCLK (T2CON.4) RCLK (T2CON.5) /16 /16 URTS (S0CFG.7) 1S1BRT Overflow (S1TOF) Mode 0 Baud Rate = n FSYSCLK ; n=12, if URM0X3=0 ; n=4, if URM0X3=1

megawin Version: 1.00 180 18.7.3. Baud Rate in Mode 2 When URM0X3 = 0, When URM0X3 = 1, Note: If SMOD2=0, the baud rate formula is as same as standard 8051. If SMOD2=1, there is an enhanced function for baud rate setting. Table 18–1 defines the Baud Rate setting with SMOD2 factor in Mode 2 baud rate generator. Table 18–1. SMOD2 application criteria in Mode 2 SMOD2 SMOD1 Baud Rate Note Recommended Max. Receive Error (%) 0 0 Default Baud Rate Standard function ± 3% 0 1 Double Baud Rate Standard function ± 3% 1 0 Double Baud Rate X2 Enhanced function ± 2% 1 1 Double Baud Rate X4 Enhanced function ± 1% Note: When Timer 1 in Double Baud Rate x4 (SMOD1=1 & SMOD2=1) mode, the TH1 can not equal to 254 & 255. Table 18–2. S0 Mode 2 Baud Rates @ FSYSCLK=11.0592MHz Baud Rate URM0X3 SMOD2 SMOD1 Error 172,800 0 0 0 0.0% 345,600 0 0 1 0.0% 691,200 0 1 0 0.0% 1,382,400 0 1 1 0.0% 57,600 1 0 0 0.0% 115,200 1 0 1 0.0% 230,400 1 1 0 0.0% 460,800 1 1 1 0.0% Table 18–3. S0 Mode 2 Baud Rates @ FSYSCLK=12.00MHz Baud Rate URM0X3 SMOD2 SMOD1 Error 187,500 0 0 0 0.0% 375,000 0 0 1 0.0% 750,000 0 1 0 0.0% 1,500,000 0 1 1 0.0% 62,500 1 0 0 0.0% 125,000 1 0 1 0.0% 250,000 1 1 0 0.0% 500,000 1 1 1 0.0% Mode 2 Baud Rate = 2SMOD1 X 2(SMOD2 X 2) X FSYSCLK Mode 2 Baud Rate = 192 2SMOD1 X 2(SMOD2 X 2) X FSYSCLK

megawin Version: 1.00 181 18.7.4. Baud Rate in Mode 1 & 3 18.7.4.1. Using Timer 1 as the Baud Rate Generator Note: If SMOD2=0, T1X12=0, the baud rate formula is as same as standard 8051. If SMOD2=1, there is an enhanced function for baud rate setting. Table 18–4 defines the Baud Rate setting with SMOD2 factor in Timer 1 baud rate generator. Table 18–4. SMOD2 application criteria in Mode 1 & 3 using Timer 1 SMOD2 SMOD1 Baud Rate Note Recommended Max. Receive Error (%) 0 0 Default Baud Rate Standard function ± 3% 0 1 Double Baud Rate Standard function ± 3% 1 0 Double Baud Rate X2 Enhanced function ± 2% 1 1 Double Baud Rate X4 Enhanced function ± 1% Note: When Timer 1 in Double Baud Rate x4 (SMOD1=1 & SMOD2=1) mode, the TH1 can not equal to 254 & 255. Table 18–5 ~ Table 18–20 list various commonly used baud rates and how they can be obtained from Timer 1 in its 8-Bit Auto-Reload Mode. For the non-standard Baud Rate, the maximum frequency is 6MHz when FSYSCLK = 48MHz). Table 18–5. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=11.0592MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 2400 244 232 0.0% 112 -- 0.0% 4800 250 244 0.0% 184 112 0.0% 9600 253 250 0.0% 220 184 0.0% 14400 254 252 0.0% 232 208 0.0% 19200 -- 253 0.0% 238 220 0.0% 28800 255 254 0.0% 244 232 0.0% 57600 -- 255 0.0% 250 244 0.0% Table 18–6. Timer 1 Generated High Baud Rates @ FSYSCLK =11.0592MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error 230.4K -- 255 0.0% 250 244 0.0% Mode 1, 3 Baud Rate = X FSYSCLK 12 x (256 – TH1) ; T1X12=0 or = X ; T1X12=1 FSYSCLK 1 x (256 – TH1) 2SMOD1 X 2(SMOD2 X 2) 2SMOD1 X 2(SMOD2 X 2)

megawin Version: 1.00 182 Table 18–7. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=22.1184MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 4800 244 232 0.0% 112 -- 0.0% 9600 250 244 0.0% 184 112 0.0% 14400 252 248 0.0% 208 160 0.0% 19200 253 250 0.0% 220 184 0.0% 28800 254 252 0.0% 232 208 0.0% 38400 -- 253 0.0% 238 220 0.0% 57600 255 254 0.0% 244 232 0.0% 115200 -- 255 0.0% 250 244 0.0% Table 18–8. Timer 1 Generated High Baud Rates @ FSYSCLK=22.1184MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error 460.8K -- 255 0.0% 250 244 0.0% Table 18–9. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=12.0MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD=0 SMOD=1 Error SMOD=0 SMOD=1 Error 2400 243 230 0.16% 100 -- 0.16% 4800 -- 243 0.16% 178 100 0.16%

megawin Version: 1.00 183 Table 18–10. Timer 1 Generated High Baud Rates @ FSYSCLK=12.0MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error Table 18–11. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=24.0MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD=0 SMOD=1 Error SMOD=0 SMOD=1 Error 4800 243 230 0.16% 100 -- 0.16% 9600 -- 243 0.16% 178 100 0.16% Table 18–12. Timer 1 Generated High Baud Rates @ FSYSCLK=24.0MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error Table 18–13. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=29.4912MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 4800 240 224 0.0% 64 -- 0.0% 9600 248 240 0.0% 160 64 0.0% 19200 252 248 0.0% 208 160 0.0%

megawin Version: 1.00 184 Table 18–14. . Timer 1 Generated High Baud Rates @ FSYSCLK=29.4912MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error Table 18–15. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=44.2368MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 9600 244 232 0.0% 112 0.0% 14400 248 240 0.0% 160 64 0.0% 19200 250 244 0.0% 184 112 0.0% 28800 252 248 0.0% 208 160 0.0% 38400 253 250 0.0% 220 184 0.0% 57600 254 252 0.0% 232 208 0.0% 115200 255 254 0.0% 244 232 0.0% 230.4K -- 255 0.0% 250 244 0.0% Table 18–16. Timer 1 Generated High Baud Rates @ FSYSCLK=44.2368MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error

megawin Version: 1.00 185 Table 18–17. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=32MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 4800 239 222 2.12% 48 -- 0.16% 9600 -- 239 2.12% 152 48 0.16% Table 18–18. Timer 1 Generated High Baud Rates @ FSYSCLK=32MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error Table 18–19. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=48.0MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=0 T1X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 9600 243 230 0.16% 100 -- 0.16% 14400 -- 239 2.12% 152 48 0.16% 19200 -- 243 0.16% 178 100 0.16%

megawin Version: 1.00 186 Table 18–20. Timer 1 Generated High Baud Rates @ FSYSCLK=48.0MHz Baud Rate TH1, the Reload Value T1X12=0 & SMOD2=1 T1X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 18.7.4.2. Using Timer 2 as the Baud Rate Generator When Timer 2 is used as the baud rate generator (either TCLK or RCLK in T2CON is ‘1’), the baud rate is as follows. Note: If SMOD2=0, the baud rate formula is as same as standard 8051. If SMOD2=1, there is an enhanced function for baud rate setting. Table 18–21 defines the Baud Rate setting with SMOD2 factor in Timer 2 baud rate generator. Table 18–21. SMOD2 application criteria in Mode 1 & 3 using Timer 2 SMOD2 SMOD1 Baud Rate Note Recommended Max. Receive Error (%)

0 X Default Baud Rate Standard function ± 3%

1 0 Double Baud Rate Enhanced function ± 3% 1 1 Double Baud Rate X2 Enhanced function ± 2% Note: When Timer 2 in Double Baud Rate x2 (SMOD1=1 & SMOD2=1) mode, the RCAP2H & RPAC2L can not equal to 65534 & 65535. Table 18–22 ~ Table 18–37 list various commonly used baud rates and how they can be obtained from Timer 2 in its Baud-Rate Generator Mode. Table 18–22. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=11.0592MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 65248 65248 0.0% 64960 64960 0.0% 2400 65392 65392 0.0% 65248 65248 0.0% 4800 65464 65464 0.0% 65392 65392 0.0% 9600 65500 65500 0.0% 65464 65464 0.0% 14400 65512 65512 0.0% 65488 65488 0.0% 19200 65518 65518 0.0% 65500 65500 0.0% 28800 65524 65524 0.0% 65512 65512 0.0% 38400 65527 65527 0.0% 65518 65518 0.0% 57600 65530 65530 0.0% 65524 65524 0.0% 2SMOD2 X (SMOD1 + 1) x FSYSCLK 32 x (65536 – (RCAP2H, RCAP2L)) Mode 1, 3 Baud Rate = ; T2X12=0 or = ; T2X12=1 2SMOD2 X (SMOD1 + 1) x FSYSCLK 16 x (65536 – (RCAP2H, RCAP2L))

megawin Version: 1.00 187 115200 65533 65533 0.0% 65530 65530 0.0% 230400 -- -- -- 65533 65533 0.0% Table 18–23. Timer 2 Generated High Baud Rates @ FSYSCLK=11.0592MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error 230.4K 65533 65530 0.0% 65530 65524 0.0% 460.8K -- 65533 0.0% 65533 65530 0.0% 691.2K 65535 65534 0.0% 65534 65532 0.0% 1.3824M -- 65535 0.0% 65535 65534 0.0% Table 18–24. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=22.1184MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 64960 64960 0.0% 64384 64384 0.0% 2400 65248 65248 0.0% 64960 64960 0.0% 4800 65392 65392 0.0% 65248 65248 0.0% 9600 65464 65464 0.0% 65392 65392 0.0% 14400 65488 65488 0.0% 65440 65440 0.0% 19200 65500 65500 0.0% 65464 65464 0.0% 28800 65512 65512 0.0% 65488 65488 0.0% 38400 65518 65518 0.0% 65500 65500 0.0% 57600 65524 65524 0.0% 65512 65512 0.0% 115200 65530 65530 0.0% 65524 65524 0.0% 230400 65533 65533 0.0% 65530 65530 0.0% 460800 -- -- -- 65533 65533 0.0% Table 18–25. Timer 2 Generated High Baud Rates @ FSYSCLK=22.1184MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error 460.8K 65533 65530 0.0% 65530 65524 0.0% 691.2K 65534 65532 0.0% 65532 65528 0.0% 921.6K -- 65533 0.0% 65533 65530 0.0% 1.3824M 65535 65534 0.0% 65534 65532 0.0% 2.7648M -- 65535 0.0% 65535 65534 0.0% Table 18–26. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=12.0MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD=0 SMOD=1 Error SMOD=0 SMOD=1 Error

megawin Version: 1.00 188 1200 65224 65224 0.16% 64912 64912 0.16% 2400 65380 65380 0.16% 65224 65224 0.16% 4800 65458 65458 0.16% 65380 65380 0.16% 9600 65497 65497 0.16% 65458 65458 0.16% 14400 65510 65510 0.16% 65484 65484 0.16% 19200 65516 65516 2.34% 65497 65497 0.16% 28800 65523 65523 0.16% 65510 65510 0.16% 38400 -- -- -- 65516 65516 2.34% 57600 -- -- -- 65523 65523 0.16% Table 18–27. Timer 2 Generated High Baud Rates @ FSYSCLK=12.0MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error 115.2K -- 65523 0.16% 65523 65510 0.16% Table 18–28. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=24.0MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD=0 SMOD=1 Error SMOD=0 SMOD=1 Error 1200 64912 64912 0.16% 64288 64288 0.16% 2400 65224 65224 0.16% 64912 64912 0.16% 4800 65380 65380 0.16% 65224 65224 0.16% 9600 65458 65458 0.16% 65380 65380 0.16% 14400 65484 65484 0.16% 65432 65432 0.16% 19200 65497 65497 0.16% 65458 65458 0.16% 28800 65510 65510 0.16% 65484 65484 0.16% 38400 65516 65516 2.34% 65497 65497 0.16% 57600 65523 65523 0.16% 65510 65510 0.16% 115200 -- -- -- 65523 65523 0.16% Table 18–29. Timer 2 Generated High Baud Rates @ FSYSCLK=24.0MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD=0 SMOD=1 Error 230.4K -- 65523 0.16% 65523 65510 0.16% Table 18–30. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=29.4912MH z Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 64768 64768 0.0% 64000 64000 0.0% 2400 65152 65152 0.0% 64768 64768 0.0%

megawin Version: 1.00 189 4800 65344 65344 0.0% 65152 65152 0.0% 9600 65440 65440 0.0% 65344 65344 0.0% 14400 65472 65472 0.0% 65408 65408 0.0% 19200 65488 65488 0.0% 65440 65440 0.0% 28800 65504 65504 0.0% 65472 65472 0.0% 38400 65512 65512 0.0% 65488 65488 0.0% 57600 65520 65520 0.0% 65504 65504 0.0% 115200 65528 65528 0.0% 65520 65520 0.0% 230.4K 65532 65532 0.0% 65528 65528 0.0% 460.8K 65534 65534 0.0% 65532 65532 0.0% 921.6K 65535 65535 0.0% 65534 65534 0.0% Table 18–31. Timer 2 Generated High Baud Rates @ FSYSCLK=29.4912MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 921.6K 65534 65532 0.0% 65532 65528 0.0% Table 18–32. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=44.2368MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 64384 64384 0.0% 63232 63232 0.0% 2400 64960 64960 0.0% 64384 64384 0.0% 4800 65248 65248 0.0% 64960 64960 0.0% 9600 65392 65392 0.0% 65248 65248 0.0% 14400 65440 65440 0.0% 65344 65344 0.0% 19200 65464 65464 0.0% 65392 65392 0.0% 28800 65488 65488 0.0% 65440 65440 0.0% 38400 65500 65500 0.0% 65464 65464 0.0% 57600 65512 65512 0.0% 65488 65488 0.0% 115200 65524 65524 0.0% 65512 65512 0.0% 230.4K 65530 65530 0.0% 65524 65524 0.0% 460.8K 65533 65533 0.0% 65530 65530 0.0% 691.2K 65534 65534 0.0% 65532 65532 0.0% 1.3824M 65535 65535 0.0% 65534 65534 0.0%

megawin Version: 1.00 190 Table 18–33. Timer 2 Generated High Baud Rates @ FSYSCLK=44.2368MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 2.7648M 65535 65534 0.0% 65534 65532 0.0% 5.5296M -- 65535 0.0% 65535 65534 0.0% Table 18–34. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=32MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 64703 64703 0.04% 63870 63870 0.04% 2400 65120 65120 0.16% 64703 64703 0.04% 4800 65328 65328 -0.16% 65120 65120 0.16% 9600 65432 65432 -0.16% 65328 65328 0.16% 14400 65467 65467 0.64% 65398 65398 0.64% 19200 65484 65484 0.16% 65432 65432 0.16% 28800 65502 65502 2.12% 65467 65467 0.64% 38400 65510 65510 0.16% 65484 65484 0.16% 57600 65519 65519 2.12% 65502 65502 2.12% 115200 -- -- -- 65519 65519 2.12% Table 18–35. Timer 2 Generated High Baud Rates @ FSYSCLK=32MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 115200 65519 65502 2.12% 65501 65467 0.64% Table 18–36. Timer 2 Generated Commonly Used Baud Rates @ FSYSCLK=48.0MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=0 T2X12=1 & SMOD2=0 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 1200 64286 64286 0.00% 63036 63036 0.00% 2400 64911 64911 0.00% 64286 64286 0.00% 4800 65224 65224 0.16% 64911 64911 0.00% 9600 65380 65380 0.16% 65224 65224 0.16% 14400 65432 65432 0.16% 65328 65328 0.16% 19200 65458 65458 0.16% 65380 65380 0.16% 28800 65484 65484 0.16% 65432 65432 0.16%

megawin Version: 1.00 191 38400 65497 65497 0.16% 65458 65458 0.16% 57600 65510 65510 0.16% 65484 65484 0.16% 115200 65523 65523 0.16% 65510 65510 0.16% Table 18–37. Timer 2 Generated High Baud Rates @ FSYSCLK=48.0MHz Baud Rate [RCAP2H, RCAP2L], the Reload Value T2X12=0 & SMOD2=1 T2X12=1 & SMOD2=1 SMOD1=0 SMOD1=1 Error SMOD1=0 SMOD1=1 Error 230.4K 65523 65510 0.16% 65510 65484 0.16% 460.8K -- 65522 0.16% 65523 65510 0.16% 18.7.4.3. Using S0 Baud Rate Timer as the Baud Rate Generator (S0BRG) The S0 of MG82F6D17 has embedded a dedicated baud rate generator (S0BRG), which detailed function is described in Section “18.10.2 Independent Baud Rate Generator S0BRG for S0” . When S0BRG is used as the baud rate generator of S0, the baud rate is as follows. 18.7.4.4. Using S1 Baud Rate Timer as the Baud Rate Generator The secondary UART (S1) in MG82F6D17 has an independent baud-rate generator. S0 can set URTS (S0CFG.7) to select the S1BRT as the timer source for UART Mode 1 and Mode 3. See Section “19.7 S1 Baud Rate Generator for S0” for the details on S0 baud rate select. 18.8. Serial Port 0 Mode 4 (SPI Master) The Serial Port 0 of MG82F6D17 is embedded an additional Mode 4 to support SPI master engine. The Mode 4 is selected by SM30, SM00 and SM10. Table 18–38 shows the serial port mode definition in MG82F6D17. Table 18–38. Serial Port 0 Mode Selection SM30 SM00 SM10 Mode Description Baud Rate 0 0 0 0 shift register SYSCLK/12 or SYSCLK/4 0 0 1 1 8-bit UART Variable 0 1 0 2 9-bit UART SYSCLK/64, /32, /16, /8 or 0 1 1 3 9-bit UART variable 1 0 0 4 SPI Master SYSCLK/12 or SYSCLK/4 1 0 1 5 Reserved Reserved 1 1 0 6 Reserved Reserved 1 1 1 7 Reserved Reserved URM0X3 also controls the SPI transfer speed. If URM0X3 = 0, the SPI clock frequency is SYSCLK/12. If URM0X3 = 1, the SPI clock frequency is SYSCLK/4. Mode 1, 3 Baud Rate = X FSYSCLK 12 x (256 – S0BRT) ; S0TX12=0, SMOD1=0 or = X ; S0TX12=1, SMOD1=0 FSYSCLK 1 x (256 – S0BRT) 2(SMOD2) 2(SMOD2)

megawin Version: 1.00 193 Figure 18–13. Serial Port 0 Mode 4 transmission waveform (n = 0) 18.9. Serial Port 0 Register All the four operation modes of the serial port are the same as those of the standard 8051 except the baud rate setting. Three registers, PCON, AUXR2 and S0CFG, are related to the baud rate setting: S0CON: Serial port 0 Control Register SFR Page = 0 only SFR Address = 0x98 RESET = 0000-0000 7 6 5 4 3 2 1 0 SM00/FE SM10 SM20 REN0 TB80 RB80 TI0 RI0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: FE, Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit. 0: The FE bit is not cleared by valid frames but should be cleared by software. 1: This bit is set by the receiver when an invalid stop bit is detected. Bit 7: Serial port 0 mode bit 0, (SMOD0 must = 0 to access bit SM00) Bit 6: Serial port 0 mode bit 1. SM30 SM00 SM10 Mode Description Baud Rate 0 0 0 0 shift register SYSCLK/12 or SYSCLK/4 0 0 1 1 8-bit UART variable 0 1 0 2 9-bit UART SYSCLK/64, /32, /16, /8 or 0 1 1 3 9-bit UART variable 1 0 0 4 SPI Master SYSCLK/12 or SYSCLK/4 1 0 1 5 Reserved Reserved 1 1 0 6 Reserved Reserved 1 1 1 7 Reserved Reserved Bit 5: Serial port 0 mode bit 2. 0: Disable SM20 function. 1: Enable the automatic address recognition feature in Modes 2 and 3. If SM20=1, RI0 will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. In mode1, if SM20=1 then RI0 will not be set unless a valid stop Bit was received, and the received byte is a Given or Bro adcast address. In Mode 0, SM20 should be 0. Bit 4: REN0, Enable serial reception. 0: Clear by software to disable reception. 1: Set by software to enable reception. Bit 3: TB80, The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. Write to SnBUF TXDn (SPICLK) RXDn (MOSI) TIn RIn D0 D1 D2 D3 D4 D5 D6 D7 Software set/clear TXDn output register to initial clock polarity D0 D1 D2 D3 D4 D5 D6 D7SnMI (MISO)

megawin Version: 1.00 194 Bit 2: RB80, In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM20 = 0, RB80 is the stop bit that was received. In Mode 0, RB80 is not used. Bit 1: TI0. Transmit interrupt flag. 0: Must be cleared by software. 1: Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Bit 0: RI0. Receive interrupt flag. 0: Must be cleared by software. 1: Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM20). S0BUF: Serial port 0 Buffer Register SFR Page = 0 only SFR Address = 0x99 RESET = XXXX-XXXX 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: It is used as the buffer register in transmission and reception. SADDR: Slave Address Register SFR Page = 0~F SFR Address = 0xA9 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W SADEN: Slave Address Mask Register (SMOD3 = 0) SFR Page = 0~F SFR Address = 0xB9 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W SADDR register is combined with SADEN register to form Given/Broadcast Address for automatic address recognition. In fact, SADEN functions as the “mask” register for SADDR register. The following is the example for it. SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00x0 The Given slave address will be checked except bit 1 is treated as “don’t care” The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zero in this result is considered as “don’t care”. Upon reset, SADDR and SADEN are loaded with all 0s. This produces a Given Address of all “don’t care” and a Broadcast Address of all “don’t care”. This disables the automatic address detection feature.

megawin Version: 1.00 195 PCON0: Power Control Register 0 SFR Page = 0~F SFR Address = 0x87 POR = 0001-0000, RESET = 0000-0000 7 6 5 4 3 2 1 0 SMOD1 SMOD0 GF POF GF1 GF0 PD IDL R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: SMOD1, double Baud rate control bit. 0: Disable double Baud rate of the UART. 1: Enable double Baud rate of the UART in mode 1, 2, or 3. Bit 6: SMOD0, Frame Error select. 0: S0CON.7 is SM0 function. 1: S0CON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0. S0CFG: Serial Port 0 Configuration Register SFR Page = 0 only SFR Address = 0x9C RESET = 0000-1000 7 6 5 4 3 2 1 0 URTS SMOD2 URM0X3 SM30 S0DOR BTI UTIE SMOD3 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: URTS, UART0 Timer Selection. 0: Timer 1 or Timer 2 can be used as the Baud Rate Generator in Mode 1 and Mode 3. 1: Timer 1 overflow signal is replaced by the UART 1 Baud Rate Timer overflow signal when Timer 1 is selected as the Baud Rate Generator in Mode1 or Mode 3 of the UART0. (Refer Section “18.7.4 Baud Rate in Mode 1 & 3”.) Bit 6: SMOD2, UART0 extra double baud rate selector. 0: Disable extra double baud rate for UART0. 1: Enable extra double baud rate for UART0. Bit 5: URM0X3, this bit control the baud rate in S0 mode 0, mode 2 and mode 4. S1 in mode 0 and mode4: 0: Clear to select SYSCLK/12 as the baud rate for S0 Mode 0 and Mode 4. 1: Set to select SYSCLK/4 as the baud rate for S0 Mode 0 and Mode 4. S0 in mode 2: 0: Clear to select UART0 baud rate as SYSCLK/32 or /64. 1: Set to select UART0 baud rate as SYSCLK/96 or /192. Bit 4: SM30, Serial Port Mode control bit 3. Bit 3: S0DOR, Serial Port 0 data order control in all operating modes. If S0 is not in Timer mode: 0: The MSB of the data byte is transmitted first. 1: The LSB of the data byte is transmitted first. S0DOR is set to “1” in default. If S0 is in Timer mode: 0: Set the S0BRG to 8-bit reload timer/counter mode. 1: Set the S0BRG to 16-bit timer/counter mode. Bit 2: BTI, Block TI0 in Serial Port 0 Interrupt. 0: Retain the TI0 to be a source of Serial Port 0 Interrupt. 1: Block TI0 to be a source of Serial Port 0 Interrupt. Bit 1: UTIE, S0 TI0 Enabled in system flag interrupt. 0: Disable the interrupt vector sharing for TI0 in system flag interrupt. 1: Set TI0 flag will share the interrupt vector with system flag interrupt. Bit 0: SMOD3, S0CR1 access control. 0: Disable S0CR1 access. CPU accesses SFR address 0xB9 to read/write SADEN. 1: Enable S0CR1 access. CPU accesses SFR address 0xB9 to read/write S0CR1.

megawin Version: 1.00 196 AUXR2: Auxiliary Register 2 SFR Page = 0~F SFR Address = 0xA3 RESET = 0000-0000 7 6 5 4 3 2 1 0 STAF STOF -- -- T1X12 T0X12 T1CKOE T0CKOE R/W R/W W W R/W R/W R/W R/W Bit 3: T1X12, Timer 1 clock source selector while C/T=0. 0: Clear to select SYSCLK/12. 1: Set to select SYSCLK as the clock source. If set, the UART0 baud rate by Timer 1 in Mode 1 and Mode 3 is 12 times than standard 8051 function. AUXR3: Auxiliary Register 3 SFR Page = 0 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T0PS1 T0PS0 BPOC1 BPOC0 S0PS0 TWIPS1 TWIPS0 T0XL R/W R/W R/W R/W R/W R/W R/W R/W Bit 3: S0PS0, Serial Port 0 pin Selection 0. (S0PS1 at AUXR10.3) S0PS1~0 RXD0 TXD0 00 P3.0 P3.1 01 P4.4 P4.5 10 P3.1 P3.0 11 P1.7 P2.2 AUXR6: Auxiliary Register 6 SFR Page = 3 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 KBI4PS1 KBI4PS0 KBI6PS0 KBI2PS0 T3FCS T2FCS SnMIPS S0COPS R/W R/W R/W R/W R/W R/W R/W R/W Bit 1: SnMIPS, S0MI & S1MI Port pin Selection. SnMIPS S0MI S1MI 0 P1.6 P6.1 1 P3.3 P4.7

megawin Version: 1.00 197 18.10. Serial Port 0 Enhance function If SMOD3 (S0CFG.0) is set, SFR address 0xB9 will be accessed on S0CR1. S0CR1 control the enhanced function of serial port 0 including :  Enable S0 embedded baud rate generator, S0BRG  Enable the S0 TX or RX to select the baud rate time base by S0BRG  Enable S0BRG to behave a general timer  Enable S0 to enter LIN bus mode S0CR1: Serial Port 0 Control Register 1 (SMOD3 = 1) SFR Page = 0~F SFR Address = 0xB9 RESET = 0000-0000 7 6 5 4 3 2 1 0 S0TR S0TX12 S0TCK S0RCK S0CKOE ARTE -- -- R/W R/W R/W R/W R/W R/W W W Bit 7: S0TR, UART0 Baud Rate Generator control bit. 0: Clear to stop S0BRG operation. 1: Set to start S0BRG operation. Bit 6: S0TX12, S0BRG clock source selection. 0: Clear to select SYSCLK/12 as the clock source of S0BRG. 1: Set to select SYSCLK as the clock source of S0BRG. Bit 5: S0TCK, S0 control bit to select S0BRG overflow for UART0 transmit clock. 0: Cause Timer 1 or Timer 2 overflow to be used for the transmit clock. 1: Cause the S0 to use S0BRG overflow for it’s transmit clock and operating mode control. Bit 4: S0RCK, S0 control bit to select S0BRG overflow for UART0 receive clock. 0: Cause Timer 1 or Timer 2 overflow to be used for the receive clock. 1: Cause the S0 to use S0BRG overflow for it’s receive clock and operating mode control. Bit 3: S0CKOE, S0BRG clock output control. 0: Disable S0BRG clock output on S0CKO. 1: Enable S0BRG clock output on S0CKO. Bit 2: ARTE, Auto Repeat Transmit Enable. 0: Disable auto repeat transmit. 1: Auto repeat transmit enable. Bit 1~0: Reserved. Software must write “0” on these bits when S0CR1 is written. S0BRT: Serial port 0 Baud Rate Timer Reload Register SFR Page = 0 only SFR Address = 0x9A RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: It is used as the reload value register for baud rate timer generator that works in a similar manner as Timer 1. S0BRC: Serial port 0 Baud Rate Counter Register SFR Page = 0 only SFR Address = 0x9B RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: It is used as the reload value register for baud rate timer generator that works in a similar manner as Timer 1. This register can be always read/written by software. If S0TR (S0CR1.7) = 0, software writing S0BRT will store the data content to S0BRT and S0BRC concurrently. If S0TR = 1, software writing S0BRT will not store the data to S0BRC.

megawin Version: 1.00 199 18.10.3. S0 Enhanced Mode SM30,SM00,SM10 S0RCK S0TCK Function Baud Rate Time Base Note 000 0 0 shift register SYSCLK/12 or SYSCLK/4 (URM0X3=1) 001 0 0 8-bit UART Timer 1 or Timer 2 overflow When SMOD1 & SMOD2 =1， counter cannot be Full-1 or Full-2 (Ex. 254, 255, 65534, 65535) 010 0 0 9-bit UART SYSCLK/64, /32, /16, or /8 011 0 0 9-bit UART Timer 1 or Timer 2 overflow When SMOD1 & SMOD2 =1， counter cannot be Full-1 or Full-2 (Ex. 254, 255, 65534, 65535) 100 0 0 SPI Master SYSCLK/12 or SYSCLK/4 (URM0X3=1) 000 0 1 shift register S0BRG overflow S0BRT cannot be 255 001 0/1 0/1 8-bit UART Selectable S0BRG overflow on TX or RX SMOD1 & SMOD2 cannot be 1 at the same time 010 0 1 9-bit UART TX: S0BRG overflow RX: SYSCLK/64, /32 or /16 SMOD1 & SMOD2 cannot be 1 at the same time 010 1 0 9-bit UART TX: SYSCLK/64, /32 or /16 RX: S0BRG overflow SMOD1 & SMOD2 cannot be 1 at the same time 010 1 1 Pure Timer Only Timer function 011 0/1 0/1 9-bit UART Selectable S0BRG overflow on TX or RX SMOD1 & SMOD2 cannot be 1 at the same time 100 0 1 SPI Master S0BRG overflow S0BRT cannot be 255 101 1 1 LIN Bus S0BRG overflow and auto baud rate SMOD1 & SMOD2 cannot be 1 at the same time Others Reserved.

megawin Version: 1.00 200 18.10.4. S0 LIN Bus Register S0CFG1: Serial Port 0 Configuration Register 1 SFR Page = 0 only SFR Address = 0x9D RESET = 0000-00xx 7 6 5 4 3 2 1 0 SBF0 TXER0 S0SB16 ATBR0 TXRX0 SYNC0 -- -- R/W R/W R/W R/W R/W R/W W W Bit 7: SBF0, Sync-Break Flag on S0. 0: Write 1 to clear by software. 1: Set by hardware at the end of the break event detection on LIN bus. In master mode, it is set combined with TI0 flag. In slave mode, it is set combined with RI0. Bit 6: TXER0, LIN Transmit Error on S0. 0: Write 1 to clear by software. 1: In TX mode, set by hardware at the transmit error detection on LIN bus. Bit 5: S0SB16, Sync-Break 16 Bit enable on S0. 0: Select 13-bit Sync-Break transmitting in master mode. 1: Select 16-bit Sync-Break transmitting in master mode. Bit 4: ATBR0, Auto Baud Rate on S0. 0: Auto cleared by hardware at the end of SYNC field. 1: Before SYNC field, set by software to perform auto baud rate adjustment on LIN bus SYNC field in slave RX mode. Bit 3: TXRX0, TX/RX selection on S0 LIN bus. 0: Select the LIN bus interface engine to RX function. 1: Select the LIN bus interface engine to TX function. Bit 2: SYNC, Sync-break Control bit on S0. 0: Auto cleared when Sync-Break is sent in master mode or received in slave mode. 1: Set by software. If set in master mode, next writing S0BUF will send a Sync-Break on LIN bus. If set in slave mode, the LIN interface engine will wait to receive a Sync-Break. Bit 1~0: Reserved. Software must write “0” on these bits when S0CFG1 is written. 18.10.5. S0 acts as 8-bit Timer Mode S0 8-bit Timer Mode is shown in Figure 18–16. Figure 18–16. S0 8-bit Timer Mode RXD0 Pin (S0CR1.7) S0TR (Timer1 overflow) T1OF Overflow 8-bit Up-Counter SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) {S0TX12, SM20} (S0CR1.6, S0CON.5) (Timer 0 overflow) T0OF S0BRC (8 Bit) S0BRT (8 Bit) TI0 Reload REN0 (S0CON.4) Transition Detection RB80 (S0CON.2) (S0CON.0) S0BRG Overflow (S0TOF) 1. to S0CKO 2. to Peripheral Clock TB80 (S0CON.3) RI0 (S0CON.1) UART0 (S0) Interrupt SMOD1 (PCON0.7) S0SCT 8-bit Timer Mode: {SM30,SM00, SM10} = 010, {S0TCK, S0RCK} = 11, S0DOR = 1

megawin Version: 1.00 201 18.10.6. S0 acts as 16-bit Timer Mode S0 16-bit Timer Mode is shown in Figure 18–17. Figure 18–17. S0 16-bit Timer Mode RXD0 Pin (S0CR1.7) S0TR (Timer1 overflow) T1OF Overflow 16-bit Up-Counter SYSCLK/12 SYSCLK (0,0) (0,1) (1,0) (1,1) {S0TX12, SM20} (S0CR1.6, S0CON.5) (Timer 0 overflow) T0OF S0BRC (8 Bit) 00H TI0 Reload REN0 (S0CON.4) Transition Detection RB80 (S0CON.2) (S0CON.0) S0BRG Overflow (S0TOF) 1. to S0CKO 2. to Peripheral Clock TB80 (S0CON.3) RI0 (S0CON.1) UART0 (S0) Interrupt SMOD1 (PCON0.7) S0SCT S0BRT (8 Bit) 00H 16-bit Timer Mode: {SM30,SM00, SM10} = 010, {S0TCK, S0RCK} = 11, S0DOR = 0

megawin Version: 1.00 203 19. Serial Port 1 (UART1) The MG82F6D17 is equipped with a secondary UART (hereafter, called UART1), which has 5 operation modes, Mode 0 ~ Mode 4, the same as the first UART (UART0) except the following differences: (1) The UART1 has no enhanced functions: Framing Error Detection and Auto Address Recognition. (2) The UART1 use the dedicated Baud Rate Timer as its Baud Rate Generator (S1BRG). (3) The UART1 uses TXD1 and RXD1 for transmit and receive, respectively. (4) The Baud Rate Generator provides the toggle source for S1CKO and peripheral clock. (5) S1 + S1BRG can be configured to an 8-bit auto-reload timer with port change detection. (6) In mode 0 and mode 4, S1TX12 of UART1 is the same function as URM0X3 in UART0. The UART1 and UART0 in MG82F6D17 can operate simultaneously in identical or different modes and communication speeds. 19.1. Serial Port 1 Baud Rate Generator (S1BRG) The MG82F6D17 has an embedded Baud Rate Generator to generate the UART clock for serial port 1 operation in mode 1 and mode 3. It is constructed by an 8-bit up-counter, S1BRC, and an 8-bit reload register, S1BRT. The overflow (S1TOF) of S1BRC is the time base of UART1 serial engine in mode 1 and mode 3 and triggers the S1BRT content reloaded into S1BRC for the consecutive counting. If S1TR = 0, software writing S1BRT will modify S1BRC simultaneously. After S1TR enabled to start the S1BRC counting, it is no influence on S1BRC when S1BRT is writing. Modifying S1BRC is always independent with S1BRT content. This baud rate generator can also provide the time base for serial port 0 by software configured. There is an addition clock output, S1CKO, from the S1BRC overflow rate by 2 (S1TOF/2). S1TOF also supplies the toggle source for other peripherals’ clock input. Regardless S1 engine is running or pending, S1BRG always serves the time base function for these peripherals. The configuration of the Serial Port 1 Baud Rate Generator is shown in Figure 19–1. Figure 19–1. S1BRG configuration (S1TME=0) S1TR ( S1CFG.4 ) Reload SYSCLK/12 SYSCLK Overflow TX Clock RX Clock UART1 (S1) in Mode1, 3 RI1 TI1 UART1 (S1) Interrupt S1TX12 ( S1CFG.2 ) S1BRC Overflow (S1TOF) 1. to S1CKO 2. to Peripheral Clock0 S1BRC (8 Bit) S1BRT (8 Bit) /16 /16

megawin Version: 1.00 204 19.2. Serial Port 1 Baud Rate Setting 19.2.1. Baud Rate in Mode 0 19.2.2. Baud Rate in Mode 2 When S1M0X3 = 0, When S1M0X3 = 1, Table 19–1. S1 Mode 2 Baud Rates @ FSYSCLK=11.0592MHz Baud Rate S1M0X3 S1MOD1 Error 172800 0 0 0.0% 345600 0 1 0.0% 57600 1 0 0.0% 115200 1 1 0.0% Table 19–2. S1 Mode 2 Baud Rates @ FSYSCLK=12.00MHz Baud Rate S1M0X3 S1MOD1 Error 187500 0 0 0.0% 375000 0 1 0.0% 62500 1 0 0.0% 125000 1 1 0.0% S1 Mode 0 Baud Rate = n FSYSCLK ; n=12, if S1TX12=0 ; n=4, if S1TX12=1 S1 Mode 2 Baud Rate = 2S1MOD1 X FSYSCLK S1 Mode 2 Baud Rate = 192 2S1MOD1 X FSYSCLK

megawin Version: 1.00 205 19.2.3. Baud Rate in Mode 1 & 3 Table 19–3 ~ Table 19–6 list various commonly used baud rates and how they can be obtained from S1BRG, serial port 1 baud rate generator. Table 19–3. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=11.0592MHz Baud Rate S1BRT, Reload Value of S1BRG S1TX12=0 S1TX12=1 S1MOD1=0 S1MOD1=1 Error S1MOD1=0 S1MOD1=1 Error 2400 244 232 0.0% 112 -- 0.0% 4800 250 244 0.0% 184 112 0.0% 9600 253 250 0.0% 220 184 0.0% 14400 254 252 0.0% 232 208 0.0% 19200 -- 253 0.0% 238 220 0.0% 28800 255 254 0.0% 244 232 0.0% 57600 -- 255 0.0% 250 244 0.0% Table 19–4. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=22.1184MHz Baud Rate S1BRT, Reload Value of S1BRG S1TX12=0 S1TX12=1 S1MOD1=0 S1MOD1=1 Error S1MOD1=0 S1MOD1=1 Error 4800 244 232 0.0% 112 -- 0.0% 9600 250 244 0.0% 184 112 0.0% 14400 252 248 0.0% 208 160 0.0% 19200 253 250 0.0% 220 184 0.0% 28800 254 252 0.0% 232 208 0.0% 38400 -- 253 0.0% 238 220 0.0% 57600 255 254 0.0% 244 232 0.0% 115200 -- 255 0.0% 250 244 0.0% S1 Mode 1, 3 Baud Rate = X 12 x (256 – S1BRT) ; S1TX12=0 or = X ; S1TX12=1 1 x (256 – S1BRT) 2S1MOD1 2S1MOD1 FSYSCLK FSYSCLK

megawin Version: 1.00 206 Table 19–5. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=12.0MHz Baud Rate S1BRT, Reload Value of S1BRG S1TX12=0 S1TX12=1 S1MOD=0 S1MOD=1 Error S1MOD=0 S1MOD=1 Error 2400 243 230 0.16% 100 -- 0.16% 4800 -- 243 0.16% 178 100 0.16% Table 19–6. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=24.0MHz Baud Rate S1BRT, Reload Value of S1BRG S1TX12=0 S1TX12=1 S1MOD=0 S1MOD=1 Error S1MOD=0 S1MOD=1 Error 4800 243 230 0.16% 100 -- 0.16% 9600 -- 243 0.16% 178 100 0.16%

megawin Version: 1.00 207 Table 19–7. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=29.4912MHz Baud Rate S1BRT, Reload Value of S1BRG S1TX12=0 S1TX12=1 S1MOD1=0 S1MOD1=1 Error S1MOD1=0 S1MOD1=1 Error 4800 240 224 0.0% 64 -- 0.0% 9600 248 240 0.0% 160 64 0.0% 19200 252 248 0.0% 208 160 0.0% Table 19–8. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=44.2368MHz Baud Rate S1BRT, Reload Value of S1BRG S1TX12=0 S1TX12=1 S1MOD1=0 S1MOD1=1 Error S1MOD1=0 S1MOD1=1 Error 9600 244 232 0.0% 112 0.0% 14400 248 240 0.0% 160 64 0.0% 19200 250 244 0.0% 184 112 0.0% 28800 252 248 0.0% 208 160 0.0% 38400 253 250 0.0% 220 184 0.0% 57600 254 252 0.0% 232 208 0.0% 115200 255 254 0.0% 244 232 0.0% 230.4K -- 255 0.0% 250 244 0.0% Table 19–9. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=32.0MHz

megawin Version: 1.00 208 Baud Rate S1BRT, Reload Value of S1BRG S1TX12=0 S1TX12=1 S1MOD1=0 S1MOD1=1 Error S1MOD1=0 S1MOD1=1 Error 4800 239 222 2.12% 48 -- 0.16% 9600 -- 239 2.12% 152 48 0.16% Table 19–10. S1BRG Generated Commonly Used Baud Rates @ FSYSCLK=48.0MHz Baud Rate S1BRT, Reload Value of S1BRG S1TX12=0 S1TX12=1 S1MOD1=0 S1MOD1=1 Error S1MOD1=0 S1MOD1=1 Error 9600 243 230 0.16% 100 -- 0.16% 14400 -- 239 2.12% 152 48 0.16% 19200 -- 243 0.16% 178 100 0.16%

megawin Version: 1.00 210 The SPI master satisfies the transfer with the full function SPI module of Megawin MG82/84 series MCU with CPOL, CPHA and DORD selection. For CPOL and CPHA condition, MG82F6D17 uses an easy way by initialize SPI clock polarity to fit them. Table 18–12 shows the serial port Mode 4 mapping with the four SPI operating mode. Table 19–12. SPI mode mapping with Serial Port Mode 4 configuration SPI Mode CPOL CPHA Configuration in TXD1 0 0 0 Clear TXD1 output register to “0” 1 0 1 Clear TXD1 output register to “0” 2 1 0 Set TXD1 output register to “1” 3 1 1 Set TXD1 output register to “1” For bit order control (DORD) on SPI serial transfer, MG82F6D17 provides a control bit, S1DOR, to control the data bit order by software program. The default value of S1DOR is “1”, LSB first. Transmission is initiated by any instruction that uses S1BUF as a destination register. The “write to S1BUF” signal triggers the UART engine to start the transmission. The data in the S1BUF would be shifted into the RXD1 pin as MOSI serial data. The SPI shift clock is built on the TXD1 pin for SPICLK output. After eight raising edge of shift clocks passing, TI1 would be asserted by hardware to indicate the end of transmission. And the contents on the S1MI pin would be sampled and shifted into shift register. Then, “read S1BUF” can get the SPI shift-in data. Figure 19–4 shows the transmission waveform in Mode 0. RI1 will not be asserted in Mode 4. Figure 19–4. Serial Port 1 Mode 4 transmission waveform (n =1) Write to SnBUF TXDn (SPICLK) RXDn (MOSI) TIn RIn D0 D1 D2 D3 D4 D5 D6 D7 Software set/clear TXDn output register to initial clock polarity D0 D1 D2 D3 D4 D5 D6 D7SnMI (MISO)

megawin Version: 1.00 213 19.7. S1 Baud Rate Generator for S0 In the Mode 1 and Mode 3 operation of the UART0, the software can select Timer 1 as the Baud Rate Generator by clearing bits TCLK and RCLK in T2CON register. At this time, if URTS bit (S0CFG.7) is set, then Timer 1 overflow signal will be replaced by the overflow signal of the UART1 Baud Rate Generator (S1BRG). In other words, the user can adopt S1BRG as the Baud Rate Generator for Mode 1 or Mode 3 of the UART 0 as long as RCLK=0, TCLK=0 and URTS=1. In this condition, Timer 1 is free for other application. Of course, if UART 1 (Mode 1 or Mode 3) is also operated at this time, these two UARTs will have the same baud rates. Figure 19–9. Additional Baud Rate Source for the UART0 When S1BRG is used as the baud rate generator of S0, the baud rate is as follows. TX Clock RX ClockTimer 2 Overflow (T2OF) S0 TX/RX Engine Timer 1 Overflow (T1OF) SMOD1 (PCON0.7) TCLK (T2CON.4) RCLK (T2CON.5) /16 /16 URTS (S0CFG.7) 1S1BRT Overflow (S1TOF) Mode 1, 3 Baud Rate = X FSYSCLK 12 x (256 – S1BRT) ; S1TX12=0 or = X ; S1TX12=1 FSYSCLK 1 x (256 – S1BRT) 2SMOD1 X 2(SMOD2 X 2) 2SMOD1 X 2(SMOD2 X 2)

megawin Version: 1.00 214 19.8. Serial Port 1 Register The following special function registers are related to the operation of the UART1: S1CON: Serial port 1 Control Register SFR Page = 1 only SFR Address = 0x98 RESET = 0000-0000 7 6 5 4 3 2 1 0 SM01 SM11 SM21 REN1 TB81 RB81 TI1 RI1 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: SM01, Serial port 1 mode bit 0. Bit 6: SM11, Serial port 1 mode bit 1. SM31 SM01 SM11 Mode Description Baud Rate 0 0 0 0 shift register SYSCLK/12 or SYSCLK/4 0 0 1 1 8-bit UART variable 0 1 0 2 9-bit UART SYSCLK/64, /32 or /192, /96 0 1 1 3 9-bit UART variable 1 0 0 4 SPI Master SYSCLK/12 or SYSCLK/4 1 0 1 5 Reserved Reserved 1 1 0 6 Reserved Reserved 1 1 1 7 Reserved Reserved Bit 5: Serial port 1 mode bit 2. 0: Disable SM21 function. 1: Enable the automatic address recognition feature in Modes 2 and 3. If SM21=1, RI1 will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or Broadcast address. In mode1, if SM21=1 then RI1 will not be set unless a valid stop Bit was received, and the received byte is a given or Broadcast address. In Mode 0, SM21 should be 0. Bit 4: REN1, Enable serial reception. 0: Clear by software to disable reception. 1: Set by software to enable reception. Bit 3: TB81, The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. Bit 2: RB81, In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM21 = 0, RB81 is the stop bit that was received. In Mode 0, RB81 is not used. Bit 1: TI1. Transmit interrupt flag. 0: Must be cleared by software. 1: Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Bit 0: RI1. Receive interrupt flag. 0: Must be cleared by software. 1: Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM21). S1BUF: Serial port 1 Buffer Register SFR Page = 1 only SFR Address = 0x99 RESET = XXXX-XXXX 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: It is used as the buffer register in transmission and reception.

megawin Version: 1.00 215 S1BRT: Serial port 1 Baud Rate Timer Reload Register SFR Page = 1 only SFR Address = 0x9A RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: It is used as the reload value register for baud rate timer generator that works in a similar manner as Timer 1. S1BRC: Serial port 1 Baud Rate Counter Register SFR Page = 1 only SFR Address = 0x9B RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: It is used as the reload value register for baud rate timer generator that works in a similar manner as Timer 1. This register can be always read/written by software. If S1CFG.S1TME = 0, software writing S1BRT will store the data content to S1BRT and S1BRC concurrently. S1CFG: Serial Port 1 Configuration Register SFR Page = 1 only SFR Address = 0x9C RESET = 0010-0000 7 6 5 4 3 2 1 0 SM31 S1M0X3 S1DOR S1TR S1MOD1 S1TX12 S1CKOE S1TME R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: SM31, Serial Port 1 Mode control bit 3. SM31 SM01 SM11 Mode Description Baud Rate 0 0 0 0 shift register SYSCLK/12 or SYSCL/4 0 0 1 1 8-bit UART variable 0 1 0 2 9-bit UART SYSCLK/64, /32 or /192, /96 0 1 1 3 9-bit UART Variable 1 0 0 4 SPI Master SYSCLK/12 or SYSCLK/4 1 0 1 5 Reserved Reserved 1 1 0 6 Reserved Reserved 1 1 1 7 Reserved Reserved Bit 6: S1M0X3, this bit control the baud rate in S1 mode 0, mode 2 and mode 4. S1 in mode 0 and mode4: 0: Clear to select SYSCLK/12 as the baud rate for S1 Mode 0 and Mode 4. 1: Set to select SYSCLK/4 as the baud rate for S1 Mode 0 and Mode 4. S1 in mode 2: 0: Clear to select UART1 baud rate as SYSCLK/32 or /64. 1: Set to select UART1 baud rate as SYSCLK/96 or /192. Bit 5: S1DOR, Serial Port 1 data order control in all operating modes. If S1TME = 0: 0: The MSB of the data byte is transmitted first. 1: The LSB of the data byte is transmitted first. S1DOR is set to “1” in default. If S1TME = 1: 0: Set the S1BRG to 8-bit reload timer/counter mode. 1: Set the S1BRG to 16-bit timer/counter mode. Bit 4: S1TR, UART1 Baud Rate Generator control bit. 0: Clear to turn off the S1BRG. 1: Set to turn on S1BRG.

megawin Version: 1.00 216 Bit 3: S1MOD1, UART1 double baud rate enable bit. 0: Disable the double baud rate function for UART1. 1: Enable the double baud rate function for UART1. Bit 2: S1TX12, UART1 Baud Rate Generator clock source select 0: Clear to select SYSCLK/12 as the clock source for S1BRG. 1: Set to select SYSCLK as the clock source for S1BRG. Bit 1: S1CKOE, Serial Port 1 BRG Clock Output Enable. 0: Disable the S1CKO output on the port pin. 1: Enable the S1CKO output on the port pin. Bit 0: S1TME, Serial port 1 BRG Timer Mode Enabled. 0: Keep S1BRT to service Serial Port 1 (UART1). 1: Disable Serial Port 1 function and release the S1BRT as an 8-bit auto-reload timer. In this mode, there is an additional function for RXD1 port pin change detector. AUXR9: Auxiliary Register 9 SFR Page = 6 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- T1G0 T0G1 C0FDC1 C0FDC0 S1PS1 S1PS0 W W R/W R/W R/W R/W R/W R/W Bit 1~0: S1PS1~0, Serial Port 1 pin Selection [1:0]. S1PS1~0 RXD1 TXD1 00 P1.0 P1.1 01 P6.0 P6.1 10 P4.4 P4.5 11 P3.4 P3.5 AUXR6: Auxiliary Register 6 SFR Page = 3 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 KBI4PS1 KBI4PS0 KBI6PS0 KBI2PS0 T3FCS T2FCS SnMIPS S0COPS R/W R/W R/W R/W R/W R/W R/W R/W Bit 1: SnMIPS, S0MI & S1MI Port pin Selection. SnMIPS S0MI S1MI 0 P1.6 P6.1 1 P3.3 P4.7

megawin Version: 1.00 217 20. Serial Peripheral Interface (SPI) The MG82F6D17 provides a high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed and synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 24 Mbps can be supported in Master or 12MHz in Slave mode under a 48MHz system clock. It has a Transfer Completion Flag (SPIF), Write Collision Flag (WCOL) and Mode Fault flag (MODF) in the SPI status register (SPSTAT). And a specially designed Transmit Holding Register (THR) improves the transmit performance compared to the conventional SPI and THRF flag indicates the THR is full or empty. SPIBSY read-only flag reports the Busy state in SPI engine. Figure 20–1. SPI Block Diagram The SPI interface has four pins: MISO, MOSI, SPICLK and nSS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on the MOSI pin (Master Out / Slave In) and flows from slave to master on the MISO pin (Master In / Slave Out). The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0, these pins function as normal I/O pins.
• /SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its nSS pin to determine whether it is selected. The /SS is ignored if any of the following conditions are true: - If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value). - If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and nSS GPIO is configured as an output. - If the /SS pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port functions. Note: See the AUXR8 in Section “4.3 Alternate Function Redirection”, for its alternate pin-out option. Note that even if the SPI is configured as a master (MSTR=1), it can still be converted to slave mode by the logic low of nSS pin input (if SSIG=0). Should this happen, the SPIF bit (SPSTAT.7) will be set and SPEN will be cleared. (See Section “20.2.3 Mode Change on nSS-pin”) /16 /32 /64 Output Shift Register (OSR) Input Shift Register (ISR) SPI Control I/O Control SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 SPIF WCOL THRF SPIBS Y MODF -- -- SPR2 SPCON SPSTAT SYSCLK SPICLK MISO MOSI nSS S0TOF/6S0TOF T0OF/6T0OF Transmit Holding Register (THR) Receive Holding Register (RHR) CPU Write SPDAT SET THRF if THRF=0, or SET WCOL if THRF=1 CLEAR THRF CPU Read SPDAT Auto-Load Auto-Load

megawin Version: 1.00 219 20.2. Configuring the SPI Table 20–1 shows configuration for the master/slave modes as well as usages and directions for the modes. Table 20–1. SPI Master and Slave Selection SPEN (SPCON.6) SSIG (SPCON.7) nSS -pin MSTR (SPCON.4) Mode MISO -pin MOSI -pin SPICLK -pin Remarks

0 X X X SPI disabled input input input SPI assigned port pint are used as

general port pins. 1 0 0 0 Salve (selected) output input input Selected as slave. 1 0 1 0 Slave (not selected) Hi-Z input input Not selected. 1 0 0 1  0 Slave (by mode change) output input input Mode change to slave if nSS pin is driven low, then MSTR will be cleared to ‘0’ by H/W automatically, and SPEN is cleared, MODF is set. 1 0 1 1 Master (idle) input Hi-Z Hi-Z MOSI and SPICLK are at high impedance to avoid bus contention when the Master is idle. Master (active) output output MOSI and SPICLK are push-pull when the Master is active. 1 1 X 0 Slave output input input 1 1 X 1 Master input output output “X” means “don’t care”. 20.2.1. Additional Considerations for a Slave When CPHA is 0, SSIG must be 0 and nSS pin must be negated and reasserted between each successive serial byte transfer. Note the SPDAT register cannot be written while nSS pin is active (low), and the operation is undefined if CPHA is 0 and SSIG is 1. When CPHA is 1, SSIG may be 0 or 1. If SSIG=0, the nSS pin may remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred for use in systems having a single fixed master and a single slave configuration. 20.2.2. Additional Considerations for a Master In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN=1) and selected as master, writing to the SPI data register (SPDAT) by the master starts the SPI clock generator and data transfer. The data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to SPDAT. Before starting the transfer, the master may select a slave by driving the nSS pin of the corresponding device low. Data written to the SPDAT register of the master is shifted out of MOSI pin of the master to the MOSI pin of the slave. And, at the same time the data in SPDAT register of the selected slave is shifted out on MISO pin to the MISO pin of the master. After shifting one byte, the SPI clock generator stops, setting the transfer completion flag (SPIF) and an interrupt will be created if the SPI interrupt is enabled. The two shift registers in the master CPU and slave CPU can be considered as one distributed 16-bit circular shift register. When data is shifted from the master to the slave, data is also shifted in the opposite direction simultaneously. This means that during one shift cycle, data in the master and the slave are interchanged.

megawin Version: 1.00 220 20.2.3. Mode Change on nSS-pin If SPEN=1, SSIG=0, MSTR=1 and /SS pin=1, the SPI is enabled in master mode. In this case, another master can drive this pin low to select this device as an SPI slave and start sending data to it. To avoid bus contention, the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be an input and MISO becomes an output. The SPIF flag in SPSTAT is set, and if the SPI interrupt is enabled, an SPI interrupt will occur. User software should always check the MSTR bit. If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again, otherwise it will stay in slave mode. 20.2.4. Transmit Holding Register Full Flag To speed up the SPI transmit performance, a specially designed Transmit Holding Register (THR) improves the latency time between byte to byte transmitting in CPU data moving. And a set THR-Full flag, THRF (SPSTAT.5), indicates the data in THR is valid and waiting for transmitting. If THR is empty (THRF=0), software writes one byte data to SPDAT will store the data in THR and set the THRF flag. If Output Shift Register (OSR) is empty, hardware will move THR data into OSR immediately and clear the THRF flag. In SPI mater mode, valid data in OSR triggers a SPI transmit. In SPI slave mode, valid data in OSR is waiting for another SPI master to shift out the data. If THR is full (THRF=1), software writes one byte data to SPDAT will set a write collision flag, WCOL (SPSTAT.6). 20.2.5. Write Collision The SPI in MG82F6D17 is double buffered data both in the transmit direction and in the receive direction. New data for transmission cannot be written to the THR until the THR is empty. The read-only flag, THRF, indicates the THR is full or empty. The WCOL (SPSTAT.6) bit is set to indicate data collision when the data register is written during set THRF. In this case, the SPDAT writing operation is ignored. While write collision is detected for a master or a slave, it is uncommon for a master because the master has full control of the transfer in progress. The slave, however, has no control over when the master will initiate a transfer and therefore collision can occur. WCOL can be cleared in software by writing ‘1’ to the bit. 20.2.6. SPI Clock Rate Select The SPI clock rate selection (in master mode) uses the SPR1 and SPR0 bits in the SPCON register and SPR2 in the SPSTAT register, as shown in Table 20–2. Table 20–2. SPI Serial Clock Rates SPR2 SPR1 SPR0 SPI Clock Selection SPI Clock Rate @ SYSCLK=12MHz SPI Clock Rate @ SYSCLK=48MHz 0 0 0 SYSCLK/4 3 MHz 12 MHz 0 0 1 SYSCLK/8 1.5 MHz 6 MHz 0 1 0 SYSCLK/16 750 KHz 3 MHz 0 1 1 SYSCLK/32 375 KHz 1.5 MHz 1 0 0 SYSCLK/64 187.5 KHz 750 KHz 1 0 1 SYSCLK/2 6 MHz 24 MHz 1 1 0 S0TOF/6 Variable Variable 1 1 1 T0OF/6 Variable Variable Note: 1. SYSCLK is the system clock. 2. S0TOF is UART0 Baud-Rate Generator Overflow. 3. T0OF is Timer 0 Overflow.

megawin Version: 1.00 221 20.3. Data Mode Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit, CPOL, allows the user to set the clock polarity. The following figures show the different settings of Clock Phase Bit, CPHA. Table 20–3. SPI mode definition SPI Mode CPOL CPHA Leading Edge Trailing Edge 0 0 0 Sample (Rising) Setup (Falling) 1 0 1 Setup (Rising) Sample (Falling) 2 1 0 Sample (Falling) Setup (Rising) 3 1 1 Setup (Falling) Sample (Rising) Figure 20–5. SPI Slave Transfer Format with CPHA=0 Figure 20–6. Slave Transfer Format with CPHA=1 SPICLK (CPOL=0) SPICLK (CPOL=1) MOSI MISO DORD=0 DORD=1 MSB LSB

6 MSB

nSS (if SSIG=0) Not defined SPICLK (CPOL=0) SPICLK (CPOL=1) MOSI MISO DORD=0 DORD=1 MSB LSB nSS (if SSIG=0) Slave Intput Slave Output

megawin Version: 1.00 222 Figure 20–7. SPI Master Transfer Format with CPHA=0 Figure 20–8. SPI Master Transfer Format with CPHA=1 SPICLK (CPOL=0) SPICLK (CPOL=1) MOSI MISO DORD=0 DORD=1 MSB LSB nSS (if SSIG=0) SPICLK (CPOL=0) SPICLK (CPOL=1) MOSI MISO DORD=0 DORD=1 MSB LSB nSS (if SSIG=0)

megawin Version: 1.00 223 20.4. Daisy-Chain Connection If SPI0 is defined in slave mode, it can be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line (nSS) from the master device. Figure 20–9. SPI single master multiple slaves configuration 20.4.1. Configuring the Daisy-Chain How to Configure SPI Slave in Daisy-Chain

• Configure SPCON to define the data mode and select SPI0 in slave mode.
• Set SPI0M0 (AUXR7.4) to enable SPI0 in Daisy-Chain mode.
• Service SPIF to get daisy-chain communication. Master Slave #1MISO MOSI SPICLK Port Pin 1 MISO MOSI SPICLK nSS Slave #2MISO nSS SPICLK MOSI Slave #3MISO nSS SPICLK MOSI

megawin Version: 1.00 224 20.5. SPI Register The following special function registers are related to the SPI operation: SPCON: SPI Control Register SFR Page = 0~F SFR Address = 0x85 RESET= 0000-0100 7 6 5 4 3 2 1 0 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: SSIG, nSS is ignored. 0: The nSS pin decides whether the device is a master or slave. 1: MSTR decides whether the device is a master or slave. Bit 6: SPEN, SPI enable. 0: The SPI interface is disabled and all SPI pins will be general-purpose I/O ports. 1: The SPI is enabled. Bit 5: DORD, SPI data order. 0: The MSB of the data byte is transmitted first. 1: The LSB of the data byte is transmitted first. Bit 4: MSTR, Master/Slave mode select 0: Selects slave SPI mode. 1: Selects master SPI mode. Bit 3: CPOL, SPI clock polarity select 0: SPICLK is low when Idle. The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge. 1: SPICLK is high when Idle. The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge. Bit 2: CPHA, SPI clock phase select 0: Data is driven when /SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK. Data is sampled on the leading edge of SPICLK. 1: Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge. (Note: If SSIG=1, CPHA must not be 1, otherwise the operation is not defined.) Bit 1~0: SPR1-SPR0, SPI clock rate select 0 & 1 (associated with SPR2, when in master mode) SPR2 SPR1 SPR0 SPI Clock Selection SPI Clock Rate @ SYSCLK=12MHz SPI Clock Rate @ SYSCLK=48MHz 0 0 0 SYSCLK/4 3 MHz 12 MHz 0 0 1 SYSCLK/8 1.5 MHz 6 MHz 0 1 0 SYSCLK/16 750 KHz 3 MHz 0 1 1 SYSCLK/32 375 KHz 1.5 MHz 1 0 0 SYSCLK/64 187.5 KHz 750 KHz 1 0 1 SYSCLK/2 6 MHz 24 MHz 1 1 0 S0TOF/6 Variable Variable 1 1 1 T0OF/6 Variable Variable Note: 1. SYSCLK is the system clock. 2. S0TOF is UART0 Baud-Rate Generator Overflow. 3. T0OF is Timer 0 Overflow.

megawin Version: 1.00 225 SPSTAT: SPI Status Register SFR Page = 0~F SFR Address = 0x84 RESET= 0000-XXX0 7 6 5 4 3 2 1 0 SPIF WCOL THRF SPIBSY MODF -- -- SPR2 R/W R/W R R R/W W W R/W Bit 7: SPIF, SPI transfer completion flag 0: The SPIF is cleared in software by writing “1” to this bit. 1: When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if SPI interrupt is enabled. If n SS pin is driven low when SPI is in master mode with SSIG=0, SPIF will also be set to signal the “mode change”. Bit 6: WCOL, SPI write collision flag. 0: The WCOL flag is cleared in software by writing “1” to this bit. 1: The WCOL bit is set if the SPI data register, SPDAT, is written during a data transfer (see Section “20.2.5 Write Collision”). Bit 5: THRF, Transmit Holding Register (THR) Full flag. Read only. 0: Means the THR is “empty”. This bit is cleared by hardware when the THR is empty. That means the data in THR is loaded (by H/W) into the Output Shift Register to be transmitted, and now the user can write the next data byte to SPDAT for next transmission. 1: Means the THR is “full”. This bit is set by hardware just when SPDAT is written by software. Bit 4, SPIBSY, SPI Busy flag. Read only. 0: It indicates SPI engine is idle and all shift registers are empty. 1: It is set to logic 1 when a SPI transfer is in progress (Master or slave Mode). Bit 3: Mode Fault Flag. This bit is set to logic 1 by hardware when a master mode collision is detected (nSS is low, MSTEN = 1, and SSIG = 0). If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by software writing “1”. Bit 2~1: Reserved. Software must write “0” on these bits when SPSTAT is written. Bit 0: SPR2, SPI clock rate select 2 (associated with SPR1 and SPR0) SPDAT: SPI Data Register SFR Page = 0~F SFR Address = 0x86 RESET= 0000-0000 7 6 5 4 3 2 1 0 (MSB) (LSB) R/W R/W R/W R/W R/W R/W R/W R/W SPDAT has two physical buffers for writing to and reading from during transmit and receive, respectively. AUXR7: Auxiliary Register 7 SFR Page = 4 only SFR Address = 0xA4 RESET = 1100-0000 7 6 5 4 3 2 1 0 POE5 POE4 C0CKOE SPI0M0 -- -- -- -- R/W R/W R/W R/W W W W W Bit 4: SPI0M0, SPI0 model control bit 0. It controls the SPI application with daisy-chain connection. 0: Disable the mode control. 1: Enable the mode control.

megawin Version: 1.00 226 AUXR10: Auxiliary Register 10 SFR Page = 7 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- -- SPIPS0 S0PS1 -- TWICF PAA W W W R/W R/W W R/W R/W Bit 4: SPIPS0, SPI Port pin Selection 0. SPIPS0 nSS MOSI MISO SPICLK 0 P3.3 P1.5 P1.6 P1.7 1 P1.7 P3.5 P3.4 P3.3

megawin Version: 1.00 228 21.1. Operating Modes There are four operating modes for the TWI/ I2C: 1) Master/Transmitter mode, 2) Master/Receiver mode, 3) Slave/Transmitter mode and 4) Slave/Receiver mode. Bits STA, STO and AA in SICON decide the next action which the TWI hardware will take after SI is cleared by software. When the next action is completed, a new status code in SISTA will be updated and SI will be set by hardware in the same time. Now, the interrupt service routine is entered (if the TWI/ I2C interrupt is enabled), and the new status code can be used to determine which appropriate routine the software is to branch to. 21.1.1. Master Transmitter Mode In the master transmitter mode, a number of data bytes are transmitted to a slave receiver. Before the master transmitter mode can be entered, SICON must be initialized as follows: SICON 7 6 5 4 3 2 1 0 CR2 ENSI STA STO SI AA CR1 CR0 Bit rate 1 0 0 0 x Bit rate CR0, CR1, and CR2 define the serial bit rate. ENSI must be set to logic 1 to enable TWI/ I2C. If the AA bit is reset, TWI/ I2C will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. In other words, if AA is reset, TWI/ I2C cannot enter a slave mode. STA, STO, and SI must be reset. The master transmitter mode may now be entered by software setting the STA bit. The TWI/ I2C logic will now test the serial bus and generate a START condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (SISTA) will be 08H. This status code must be used to vector to an interrupt service routine that loads SIDAT with the slave address and the data direction bit (SLA+W). The SI bit in SICON must then be reset before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in SISTA are possible. There are 18H, 20H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA=1). The appropriate action to be taken for each of these status codes is detailed in the following operating flow chart. After a repeated START condition (state 10H), TWI/ I2C may switch to the master receiver mode by loading SIDAT with SLA+R. 21.1.2. Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmitter. SICON must be initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load SIDAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in SICON must then be cleared before the serial transfer can continue. When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in SISTA are possible. They are 40H, 48H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA=1). The appropriate action to be taken for each of these status codes is detailed in the following operating flow chart. After a repeated start condition (state 10H), TWI/ I2C may switch to the master transmitter mode by loading SIDAT with SLA+W.

megawin Version: 1.00 229 21.1.3. Slave Transmitter Mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver. To initiate the slave transmitter mode, SIADR and SICON must be loaded as follows: SIADR 7 6 5 4 3 2 1 0 X X X X X X X GC The upper 7 bits are the address to which TWI/ I2C will respond when addressed by a master. If the LSB (GC) is set, TWI/ I2C will respond to the general call address (00H); otherwise it ignores the general call address. SICON 7 6 5 4 3 2 1 0 CR2 ENSI STA STO SI AA CR1 CR0 x 1 0 0 0 1 x x CR0, CR1, and CR2 do not affect TWI/ I2C in the slave mode. ENSI must be set to “1” to enable TWI/ I2C. The AA bit must be set to enable TWI/ I2C to acknowledge its own slave address or the general call address. STA, STO, and SI must be cleared to “0”. When SIADR and SICON have been initialized, TWI/ I2C waits until it is addressed by its own slave address followed by the data direction bit which must be “1” (R) for TWI/ I2C to operate in the slave transmitter mode. After its own slave address and the “R” bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from SISTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in the following operating flow chart. The slave transmitter mode may also be entered if arbitration is lost while TWI/ I2C is in the master mode (see state B0H). If the AA bit is reset during a transfer, TWI/ I2C will transmit the last byte of the transfer and enter state C0H or C8H. TWI/ I2C is switched to the not-addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, TWI/ I2C does not respond to its own slave address or a general call address. However, the serial bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate TWI/ I2C from the bus. 21.1.4. Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a master transmitter. Data transfer is initialized as in the slave transmitter mode. When SIADR and SICON have been initialized, TWI/ I2C waits until it is addressed by its own slave address followed by the data direction bit which must be “0” (W) for TWI/ I2C to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from SISTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in the following operating flow chart. The slave receiver mode may also be entered if arbitration is lost while TWI/ I2C is in the master mode (see status 68H and 78H). If the AA bit is reset during a transfer, TWI/ I2C will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, TWI/ I2C does not respond to its own slave address or a general call address. However, the serial bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate from the bus.

megawin Version: 1.00 230 21.2. Miscellaneous States There are two SISTA codes that do not correspond to a defined TWI/ I2C hardware state, as described below. S1STA = F8H: This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs between other states and when TWI/ I2C is not involved in a serial transfer. S1STA = 00H: This status code indicates that a bus error has occurred during a TWI/ I2C serial transfer. A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may also be caused when external interference disturbs the internal TWI/ I2C signals. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared by software. This causes TWI/ I2C to enter the “not-addressed” slave mode (a defined state) and to clear the STO flag (no other bits in SICON are affected). The TWI/ I2C0_SDA and TWI/ I2C0_SCL lines are released (a STOP condition is not transmitted). 21.3. Using the TWI/ I2C The TWI/ I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI/ I2C is interrupt-based, the application software is free to carry on other operations during a TWI/ I2C byte transfer. Note that the TWI/ I2C0 interrupt enable bit E TWI/ I2C0 bit (EIE1.6) together with the EA bit allow the application to decide whether or not assertion of the SI Flag should generate an interrupt request. When the SI flag is asserted, the TWI/ I2C has finished an operation and awaits application response. In this case, the status register SISTA contains a status code indicating the current stat e of the TWI/ I2C bus. The application software can then decide how the TWI/ I2C should behave in the next TWI/ I2C bus operation by properly programming the STA, STO and AA bits (in SICON). The following operating flow charts will instruct the user to us e the TWI/ I2C using state-by-state operation. First, the user should fill SIADR with its own Slave address (refer to the previous description about SIADR). To act as a master, after initializing the SICON, the first step is to set “STA” bit to generate a START condition to the bus. To act as a slave, after initializing the SICON, the TWI/ I2C waits until it is addressed. And then follow the operating flow chart for a number a next actions by properly programming (STA,STO,SI,AA) in the SICON. Since the TWI/ I2C hardware will take next action when SI is just cleared, it is recommended to program (STA,STO,SI,AA) by two steps, first STA, STO and AA, then clear SI bit (may use instruction “CLR SI”) for safe operation. “don’t care” The figure below shows how to read the flow charts. Set STA to generate a START 08H A START has been transmitted The status code in SISTA, it is the current bus state. The TWSI bus operation has just finished. (STA,STO,SI,AA)=(0,0,0,X) Setting for the next bus operation. "X" means "don't care". SLA+W will be transmitted; ACK bit will be received. The expected next bus operation.

megawin Version: 1.00 231 C Set STA to generate a START 08H A START has been transmitted From Slave Mode (STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted; ACK bit will be received. (1) Master/Transmitter Mode B From Master/Receiver 18H SLA+W will be transmitted; ACK bit will be received. or 20H SLA+W will be transmitted; NOT ACK bit will be received. (STA,STO,SI,AA)=(0,0,0,X) Data byte will be transmitted; ACK bit will be received. (STA,STO,SI,AA)=(1,0,0,X) A repeated START will be transmitted. (STA,STO,SI,AA)=(0,1,0,X) A STOP will be transmitted; STO flag will be reset. (STA,STO,SI,AA)=(1,1,0,X) A STOP followed by a START will be transmitted; STO flag will be reset. Send a STOP Send a STOP followed by a START A repeated START has been transmitted. 28H Data byte in SIDAT has been transmitted; ACK has been received. or 30H Data byte in SIDAT has been transmitted; NOT ACK has been received. (STA,STO,SI,AA)=(0,0,0,X) SLA+R will be transmitted; ACK will be received; TWSI will be switched to Master/Receiver mode A To Master/Receiver 10H Arbitration lost in SLA+W or Data bytes 38H (STA,STO,SI,AA)=(1,0,0,X) A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(0,0,0,X) The bus will be released; Not addressed Slave mode will be entered. Enter NAslave Send a START when bus becomes free

megawin Version: 1.00 232 (2) Master/Receiver Mode (STA,STO,SI,AA)=(0,0,0,X) SLA+R will be transmitted; ACK will be received. 50H Data byte has been received; ACK has been returned. SLA+R has been transmitted; ACK has been received. 40H From Master/Transmitter To Master/Transmitter 58H Data byte has been received; NOT ACK has been returned. SLA+R has been transmitted; NOT ACK has been received. 48H Set STA to generate a START. 08H A START has been transmitted. 38H Arbitration lost in SLA+R or NOT ACK bit. (STA,STO,SI,AA)=(0,0,0,X) The bus will be released; Not addressed SLV mode will be entered. Enter NAslave (STA,STO,SI,AA)=(1,0,0,X) A START will be transmitted when the bus becomes free. Send a START when bus becomes free (STA,STO,SI,AA)=(0,0,0,0) Data byte will be received; NOT ACK will be returned. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ACK will be returned. 10H A repeated START has been transmitted. (STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted; ACK will be received; TWSI will be switched to MST/TRX mode. (STA,STO,SI,AA)=(1,0,0,X) A repeated START will be transmitted. (STA,STO,SI,AA)=(0,1,0,X) A STOP will be transmitted; STO flag will be reset. (STA,STO,SI,AA)=(1,1,0,X) A STOP followed by a START will be transmitted; STO flag will be reset. Send a STOPSend a STOP followed by a START From Slave ModeC B A

megawin Version: 1.00 233 (3) Slave/Transmitter Mode A8H Own SLA+R has been received; ACK has been returned. B0H Arbitration lost in SLA+R/W as master; Own SLA+R has been received; ACK has been returned. or C8H Last data byte in SIDAT has been transmitted; ACK has been received. B8H Data byte in SIDAT has been transmitted; ACK has been received. C0H Data byte or Last data byte in SIDAT has been transmitted; NOT ACK has been received. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be transmitted; ACK will be received. (STA,STO,SI,AA)=(0,0,0,0) Last data byte will be transmitted; ACK will be received. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be transmitted; ACK will be received. (STA,STO,SI,AA)=(0,0,0,0) Last data byte will be transmitted; ACK will be received. Set AA (STA,STO,SI,AA)=(1,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(1,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(0,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized. (STA,STO,SI,AA)=(0,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA. Enter NAslave Send a START when bus becomes free To Master Mode C

megawin Version: 1.00 234 88H Data byte has been received; NOT ACK has been returned. 60H Own SLA+W has been received; ACK has been returned. 68H Arbitration lost in SLA+R/W as master; Own SLA+W has been received; ACK has been returned. or (4) Slave/Receiver Mode A0H A STOP or repeated START has been received while still addressed as SLV/REC. 80H Data byte has been received; ACK has been returned. (STA,STO,SI,AA)=(0,0,0,0) Data will be received; NOT ACK will be returned. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ACK will be returned. (STA,STO,SI,AA)=(0,0,0,0) Data byte will be received; NOT ACK will be returned. Set AA (STA,STO,SI,AA)=(1,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(1,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(0,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized. (STA,STO,SI,AA)=(0,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA. Enter NAslave Send a START when bus becomes free To Master Mode (STA,STO,SI,AA)=(0,0,0,1) Data will be received; ACK will be returned. C

megawin Version: 1.00 235 98H Previously addressed with General Call address; Data byte has been received; NOT ACK has been returned. 70H General Call address has been received; ACK has been returned. 78H Arbitration lost in SLA+R/W as master; General Call address has been received; ACK has been returned. or (5) Slave/Receiver Mode (For General Call) A0H A STOP or repeated START has been received while still addressed as SLV/REC. 90H Previously addressed with General Call address; Data byte has been received; ACK has been returned. (STA,STO,SI,AA)=(0,0,0,0) Data will be received; NOT ACK will be returned. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ACK will be returned. (STA,STO,SI,AA)=(0,0,0,0) Data byte will be received; NOT ACK will be returned. Set AA (STA,STO,SI,AA)=(1,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(1,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA; A START will be transmitted when the bus becomes free. (STA,STO,SI,AA)=(0,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized. (STA,STO,SI,AA)=(0,0,0,0) Switch to not addressed SLV mode; No recognition of own SLA. Enter NAslave Send a START when bus becomes free To Master Mode (STA,STO,SI,AA)=(0,0,0,1) Data will be received; ACK will be returned. C

megawin Version: 1.00 236 21.4. TWI0/ I2C0 Register SIADR: TWI0/ I2C0 Address Register SFR Page = 0~F SFR Address = 0xD1 RESET= 0000-0000 7 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 A1 A0 GC R/W R/W R/W R/W R/W R/W R/W R/W The CPU can read from and write to this register directly. SIADR is not affected by the TWI0/ I2C0 hardware. The contents of this register are irrelevant when TWI0/ I2C0 is in a master mode. In the slave mode, the seven most significant bits must be loaded with the microcontroller’s own slave address, and, if the least significant bit (GC) is set, the general call address (00H) is recognized; otherwise it is ignored. The most significant bit corresponds to the first bit received from the TWI0/ I2C0 bus after a START condition. SIDAT: TWI0/ I2C0 Data Register SFR Page = 0~F SFR Address = 0xD2 RESET= 0000-0000 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W This register contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can read from or write to this register directly while it is not in the process of shifting a byte. This occurs when TWI0/ I2C0 is in a defined state and the serial interrupt flag (SI) is set. Data in SIDAT remains stable as long as SI is set. While data is being shifted out, data on the bus is simultaneously being shifted in; SIDAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in SIDAT. SIDAT and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. The ACK flag is controlled by the TWI0/ I2C0 hardware and cannot be accessed by the CPU. Serial data is shifted through the ACK flag into SIDAT on the rising edges of serial clock pulses on the TWI0/ I2C0_SCL line. When a byte has been shifted into SIDAT, the serial data is available in SIDAT, and the acknowledge bit is returned by the control logic during the 9th clock pulse. Serial data is shifted out from SIDAT on the falling edges of clock pulses on the TWI0/ I2C0_SCL line. When the CPU writes to SIDAT, the bit SD7 is the first bit to be transmitted to the SDA line. After nine serial clock pulses, the eight bits in SIDAT will have been transmitted to the SDA line, and the acknowledge bit will be present in the ACK flag. Note that the eight transmitted bits are shifted back into SIDAT. SICON: TWI0/ I2C0 Control Register SFR Page = 0~F SFR Address = 0xD4 RESET= 0000-0000 7 6 5 4 3 2 1 0 CR2 ENSI STA STO SI AA CR1 CR0 R/W R/W R/W R/W R/W R/W R/W R/W The CPU can read and write to this register directly. Two bits are affected by the TWI0/I2C0 hardware: the SI will be set when a serial interrupt occurred, and the STO will be cleared when a STOP condition is present on the bus. The STO bit is also cleared when ENSI="0". Bit 7: CR2, TWI0/ I2C0 Clock Rate select bit 2 (associated with CR1 and CR0). Bit 6: ENSI, the TWI0/I2C0 Hardware Enable Bit When ENSI is "0", the TWI0 _SDA and TWI0_SCL outputs are in a high impedance state, and it will ignore the input signals. Under this condition, the TWI0/I2C0 is in the not-addressed slave state, and STO is forced to "0". No other bits are affected, and the TWI0_SDA and TWI0_SCL can be used as general purpose I/O pins. When ENSI is "1", TWI0 is enabled, the TWI0_SDA and TWI0_SCL assign to port pin latch, such as P4.1 and P4.0. The port pin latch must be set to logic 1 and I/O mode must be configured to open-drain mode for the serial communication.

megawin Version: 1.00 237 Bit 5: STA, the START Flag When sets the STA to enter a master mode, the TWI0/I2C0 hardware will checks the status of the serial bus. It will generate a START condition if the bus is free. Otherwise TWI0/I2C0 will waits for a STOP condition and generates a START condition after a delay. If STA is set while TWI0/I2C0 is already in a master mode and one or more bytes are transmitting or receiving, TWI0/I2C0 will send a repeated START condition. STA may be set at any time. STA may also be set when TWI0/I2C0 is an addressed slave mode. When the STA bit is reset, no START condition or repeated START condition will be generated. Bit 4: STO, the STOP Flag When the STO is set while TWI0/I2C0 is in a master mode, a STOP condition is transmitted to the serial bus. When the STOP condition is detected on the bus, the TWI0/I2C0 hardware clears the STO flag. In a slave mode, the STO flag may be set to recover from a bus error condition. In this case, no STOP condition is transmitted to the bus. However, the TWI0/I2C0 hardware behaves as if a STOP condition has been received and switches to the defined not addressed slave receiver mode. The STO flag is automatically cleared by hardware. If the STA and STO bits are both set, then a STOP condition is transmitted to the bus if TWI0/I2C0 is in a master mode (in a slave mode, TWI0/I2C0 generates an internal STOP condition which is not transmitted), and then transmits a START condition. Bit 3: SI, the Serial Interrupt Flag When a new TWI0/I2C0 state is present in the SISTA register, the SI flag is set by hardware. And, if the TWI0/I2C0 interrupt is enabled, an interrupt service routine will be serviced. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. When SI is set, the low period of the serial clock on the TWI0_SCL line is stretched, and the serial transfer is suspended. A high level on the TWI0_ SCL line is unaffected by the serial interrupt flag. SI must be cleared by software writing “0” on this bit. When the SI flag is reset, no serial interrupt is requested, and there is no stretching on the serial clock on the TWI0_ SCL line. Bit 2: AA, the Assert Acknowledge Flag If the AA flag is set to “1”, an Acknowledge (low level to TWI0_SDA) will be returned during the acknowledge clock pulse on the TWI0_SCL line when: 1) The own slave address has been received. 2) A data byte has been received while TWI0/I2C0 is in the master/receiver mode. 3) A data byte has been received while TWI0/I2C0 is in the addressed slave/receiver mode. If the AA flag is reset to “0”, a not acknowledge (high level to TWI0_SDA) will be returned during the acknowledge clock pulse on TWI0_SCL when: 1) A data has been received while TWI0/I2C0 is in the master/receiver mode. 2) A data byte has been received while TWI0/I2C0 is in the addressed slave/receiver mode. Bit 7, 1~0: CR2, CR1 and CR0, the Clock Rate select Bits These three bits determine the serial clock frequency when TWI0/I2C0 is in a master mode. The highest master mode clock frequency is limited to 1MHz. In slave mode, it is no need to select the clock rate. TWI0/I2C0will automatically synchronize with any clock frequency from master, which is up to 400KHz. The various serial clock rates are shown in Table 21–1.

megawin Version: 1.00 238 Table 21–1. TWI0/ I2C0 Serial Clock Rates CR2 CR1 CR0 TWI0/ I2C0 Clock Selection TWI0/ I2C0 Clock Rate @ SYSCLK=12MHz 0 0 0 SYSCLK/8 1.5 MHz Note1 0 0 1 SYSCLK/16 750 KHz 0 1 0 SYSCLK/32 375 KHz 0 1 1 SYSCLK/64 187.5 KHz 1 0 0 SYSCLK/128 93.75 KHz 1 0 1 SYSCLK/256 46.875 KHz 1 1 0 S0TOF/6 Variable 1 1 1 T0OF/6 Variable Note:1. The Maximum TWI0/I2C0 clock Rate should under 1MHz, to set SYSCLK = 8MHz to generate 1MHz. 2. SYSCLK is the system clock. 3. S0TOF is UART0 Baud-Rate Generator Overflow. 4. T0OF is Timer 0 Overflow. SISTA: TWI0/ I2C0 Status Register SFR Page = 0~F SFR Address = 0xD3 RESET= 1111-1000 7 6 5 4 3 2 1 0 SIS7 SIS6 SIS5 SIS4 SIS3 SIS2 SIS1 SIS0 R R R R R R R R SISTA is an 8-bit read-only register. The three least significant bits are always 0. The five most significant bits contain the status code. There are a number of possible status codes. When SISTA contains F8H, no serial interrupt is requested. All other SISTA values correspond to defined TWI0/ I2C0 states. When each of these states is entered, a status interrupt is requested (SI=1). A valid status code is present in SISTA when SI is set by hardware. In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position, such as inside an address/data byte or just on an acknowledge bit. AUXR3: Auxiliary Register 3 SFR Page = 0 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T0PS1 T0PS0 BPOC1 BPOC0 S0PS0 TWIPS1 TWIPS0 T0XL R/W R/W R/W R/W R/W R/W R/W R/W Bit 2~1: TWIPS1~0, TWI0/ I2C0 Port Selection [1:0]. TWIPS1~0 TWI0/ I2C0_SCL TWI0/ I2C0_SDA 00 P3.1 P3.0 01 P6.0 P6.1 10 P3.0 P3.1 11 P2.2 P2.4 AUXR10: Auxiliary Register 10 SFR Page = 7 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- -- SPIPS0 S0PS1 -- TWICF PAA W W W R/W R/W W R/W R/W Bit 1: TWICF, TWI0/I2C0 serial Clock input Filter. 0: Disable TWICF function. 1: Enable TWICF function. Bit 0: PAA, Pre-Assert Acknowledge. 0: Disable PAA function. 1: Enable PAA function on DMA transfer with TWI0/I2C0 master RX and slave TX/RX.

megawin Version: 1.00 240 23. Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range about 1, 2 or 4 kHz which is divided from ILRCO. Figure 23–1 shows the beeper generator circuit. But ILRCO is not the precision clock source. Please refer Section “33.4 ILRCO Characteristics” for more detailed ILRCO frequency deviation range. Figure 23–1. Beeper Generator 23.1. Beeper Register AUXR3: Auxiliary Register 3 SFR Page = 0 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T0PS1 T0PS0 BPOC1 BPOC0 S0PS0 TWIPS1 TWIPS0 T0XL R/W R/W R/W R/W R/W R/W R/W R/W Bit 5~4: BPOC1~0, Beeper output control bits. BPOC[1:0] P4.4 function I/O mode 00 P4.4 By P4M0.4 & P4M1.4 01 ILRCO/32 By P4M0.4 & P4M1.4 10 ILRCO/16 By P4M0.4 & P4M1.4 11 ILRCO/8 By P4M0.4 & P4M1.4 For beeper on P4.4 function, it is recommended to configure P4.4 as push-push output mode. Beeper will use P4.4, and please disable OCD function before enable Beeper function. DCON0: Device Control 0 SFR Page = P Only SFR Address = 0x4C RESET = 100x-x011 7 6 5 4 3 2 1 0 HSE IAPO HSE1 -- -- IORCTL RSTIO OCDE R/W R/W W W W W R/W W Bit 0: OCDE, OCD enable. 0: Disable OCD interface on P4.4 and P4.5 1: Enable OCD interface on P4.4 and P4.5. Due to MG82F6D17AS8 SOP8 not support OCD_ICE, it needs to disable OCD_SDA and OCD_SCL by firmware when using MG82F6D17AS8 SOP8. BEEP ILRCO(32KHz) ÷16 ÷32 BPOC[1:0] (AUXR3.5~4) 00: P4.4 01: ILRCO/32 (~= 1K) 10: ILRCO/16 (~= 2K) 11: ILRCO/8 (~= 4K) SFR P4.4

megawin Version: 1.00 241 24. Keypad Interrupt (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated whe n KBI.7~0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. There are three SFRs used for this function. The Keypad Interrupt Mask Register (KBMASK) is used to defin e which KBI input pins are enabled to trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of keypad input. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set by hardware when the condition is matched. An interrupt will be generated if it has been enabled by setting the EKBI bit in EIE1 register and EA=1. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define “equal” or “not-equal” for the comparison. The keypad input can be assigned on the different port pins, please refer Section “4.3 Alternate Function Redirection” for more detailed information. In order to use the Keypad Interrupt as the “Keyboard” Interrupt, the user needs to set KBPATN=0xFF and PATN_SEL=0 (not equal), then any key connected to keypad input which is enabled by KBMASK register will cause the hardware to set the interrupt flag KBIF and generate an interrupt if it has been enabled. The interrupt may wake up the CPU from Idle mode or Power-Down mode. This feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption but also need to be convenient to use. 24.1. KBI Structure Figure 24–1. Keypad Interrupt (KBI) structure KBIFPATN_ SELKBCS0KBCS1 KBMASK[7:0] KBPATN[7:0] KBMASK Register KBPATN Register KBCON Register KBI0 KBPATN.0 Comparator equal.0 KBMASK.0 KBI1 KBPATN.1 equal.1 KBMASK.1 KBI7 KBPATN.7 equal.7 not-equal.7 KBMASK.7 KBI2 KBI3 KBI4 KBI5 KBI6 not-equal.0 equal.7 equal.6 equal.5 equal.4 equal.3 equal.2 equal.1 equal.0 not-equal.6 not-equal.0 not-equal.1 not-equal.2 not-equal.3 not-equal.4 not-equal.5 not-equal.6 not-equal.7 Pattern Not Equal Pattern Equal 3 clock Filter KBCS[1:0] (KBCON.7~6) SYSCLK x 3 SYSCLK/6 x 3 S0TOF x 3 KBI Interrupt KBMASK.x = 1, to enable compare output SYSCLK Comparator Comparator SYSCLK Sampling Type Selection S0TOF -- ----KBES KBIET, low active, to internal logic

megawin Version: 1.00 242 24.2. KBI Register The following special function registers are related to the KBI operation: KBPATN: Keypad Pattern Register SFR Page = 0~F SFR Address = 0xD5 RESET= 1111-1111 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: KBPATN.7~0: The keypad pattern, reset value is 0xFF. KBCON: Keypad Control Register SFR Page = 0~F SFR Address = 0xD6 RESET= 0000-0001 7 6 5 4 3 2 1 0 KBCS1 KBCS0 KBES -- -- -- PATN_SEL KBIF R/W R/W R/W R W W R/W R/W Bit 7~6: KBCS1~0, KBI Filter mode control. KBCS1~0 KBI input filter mode Bit 5: KBES, KBI Edge mode select. 0: Set KBI module to level detection mode. 1: Set KBI module to edge detection mode. Bit 1: PATN_SEL, Pattern Matching Polarity selection. 0: The keypad input has to be not equal to user-defined keypad pattern in KBPATN to generate the interrupt. 1: The keypad input has to be equal to the user-defined keypad pattern in KBPATN to generate the interrupt. Bit 0: KBIF, Keypad Interrupt Flag. The default value of KBIF is set to “1”. 0: Must be cleared by software by writing “0”. 1: Set when keypad input matches user defined conditions specified in KBPATN, KBMASK, and PATN_SEL. KBMASK: Keypad Interrupt Mask Register SFR Page = 0~F SFR Address = 0xD7 RESET= 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W KBMASK.7: When set, enables KBI7 input as a cause of a Keypad Interrupt. KBMASK.6: When set, enables KBI6 input as a cause of a Keypad Interrupt. KBMASK.5: When set, enables KBI5 input as a cause of a Keypad Interrupt. KBMASK.4: When set, enables KBI4 input as a cause of a Keypad Interrupt. KBMASK.3: When set, enables KBI3 input as a cause of a Keypad Interrupt. KBMASK.2: When set, enables KBI2 input as a cause of a Keypad Interrupt. KBMASK.1: When set, enables KBI1 input as a cause of a Keypad Interrupt. KBMASK.0: When set, enables KBI0 input as a cause of a Keypad Interrupt.

megawin Version: 1.00 243 AUXR6: Auxiliary Register 6 SFR Page = 3 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 KBI4PS1 KBI4PS0 KBI6PS0 KBI2PS0 T3FCS T2FCS SnMIPS S0COPS R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: KBI4PS1~0, KBI4~5 Port pin Selection [1:0]. KBI4PS1~0 KBI4 KBI5 00 P3.3 P1.5 01 P3.4 P3.5 10 P6.0 P6.1 11 P1.5 P3.3 Bit 5: KBI6PS0, KBI6~7 Port pin Selection 0. KBI6PS0 KBI6 KBI7 0 P1.6 P1.7 1 P3.0 P3.1 Bit 4: KBI2PS0, KBI2~3 Port pin Selection 0. KBI2PS0 KBI2 KBI3 0 P3.0 P3.1 1 P2.2 P2.4 AUXR8: Auxiliary Register 8 SFR Page = 5 only SFR Address = 0xA4 RESET = 1100-0000 7 6 5 4 3 2 1 0 POE7 POE6 C0PPS2 -- KBI0PS0 S1COPS -- -- R/W R/W R/W W R/W R/W W W Bit 3: KBI0PS0, KBI0~1 Port pin Selection 0. KBI0PS KBI0 KBI1 0 P1.0 P1.1 1 P4.7 P3.3

megawin Version: 1.00 244 25. General Purpose Logic (GPL-CRC) The MG82F6D17 builds in a general purpose logic cyclic redundancy check function with CCITT16 (CRC16 0x1021) polynomial. The CRC accepts a stream of 8-bit data written to the CRC0DI. Its initial value (seed value) is programmable for multi-purpose applications. The 16-bit initial value (seed value) is set to high byte CRC0SH (CRCDS0~1=01) and low byte CRC0SL (CRCDS0~1=00). The result is stored in CRC0RH (CRCDS0~1=01) and CRC0RL (CRCDS0~1=00). The GPL-CRC has another data path direct from Flash memory by the Flash Auto-Reload Engine to dynamically check the data correctness in the Flash. The GPL-CRC can also combine the data inverse function. To write the data byte into BOREV register and it will be flipped automatically when read it back from BOREV. The MSB becomes the LSB. 25.1. GPL-CRC Structure In the normal mode, it needs to set the seed in CRC0SH and CRC0SL and then write the data into CRC0DI to start the conversion. In the Flash Auto-Reload mode, it needs to keep CRCDS1~0 at “0x11”. And follow the steps show in below: 1. To set the start address of the reload sector, this is defined in IFADRH and IFADRL. 2. To set its end-address is combined the IAPLB (7 bits) and 9’b1-1111-1111. 3. Set IFMT register (ISP/IAP Flash Mode) to 0x80 for Flash Auto-Reload mode. 4. Sequentially write 0x46h then 0xB9h to SCMD register to trigger CRC calculation. Figure 25–1. CRC structure CRC0SH CRC16 Engine CRC0 Seed Register CRC0SL CRC0RH CRC0RL CRC0 Result Register CRC0DI Flash Auto-Read EngineFlash Memory CPU Write: CRC0DA CPU Read: CRC0DA CRC0DS[1:0] = 00CRC0DS[1:0] = 01CRC0DS[1:0] = 11 CRC0DS[1:0] = 00CRC0DS[1:0] = 01

megawin Version: 1.00 245 25.2. GPL-BOREV Structure Figure 25–2. BOREV structure 25.3. GPL Register The following special function registers are related to the CRC operation: CRC0DA: CRC0 Data Port SFR Page = 0~F SFR Address = 0xB6 RESET= 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: CRC0 Data Port. The CRC0 data access is defined as following table: CRCDS1~0 CPU R/W CRC0 Data Selection 00 Write CRC0SL CRC0 Data Seed register-L. 01 Write CRC0SH CRC0 Data Seed register-H. 10 Write -- Reserved. 11 Write CRC0DI CRC0 Data Input register. 00 Read CRC0RL CRC0 Result register-L. 01 Read CRC0RH CRC0 Result register-H. 10 Read -- Reserved. 11 Read -- Reserved. AUXR1: Auxiliary Control Register 1 SFR Page = 0~F SFR Address = 0xA2 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- CRCDS1 CRCDS0 -- -- -- DPS W W R/W R/W W W W R/W Bit 5~4: CRCDS1~0. CRC0 Data port Selection bit 1~0. D0D1D2D3D4D5D6D7BOREV CPU Write D0 D1 D2 D3 D4 D5 D6 D7 CPU Read

megawin Version: 1.00 246 BOREV: Bit Order Reversed data register SFR Page = 0~F SFR Address = 0x96 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: BOREV7~0, data read/write for Bit-Order-Reversed function. Any byte written to BOREV is read back in a bit-reversed order, i.e., the written LSB becomes the MSB. For example: If 0xA0 is written to BOREV, the data read back will be 0x05. If 0x01 is written to BOREV, the data read back will be 0x80. IFMT: ISP/IAP Flash Mode Table SFR Page = 0~F SFR Address = 0xE5 RESET = xxxx-x000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~4: Reserved. Software must write “0000_0” on these bits when IFMT is written. Bit 3~0: ISP/IAP/Page-P operating mode selection MS[7:0] Mode 0 0 0 0-0 0 0 0 Standby 0 0 0 0-0 0 0 1 Flash byte read of AP/IAP-memory 0 0 0 0-0 0 1 0 Flash byte program of AP/IAP-memory 0 0 0 0-0 0 1 1 Flash page erase of AP/IAP-memory 0 0 0 0-0 1 0 0 Page P SFR Write 0 0 0 0-0 1 0 1 Page P SFR Read 1 0 0 0-0 0 0 0 Automatic flash read for CRC. 1 0 0 0-0 0 0 1 Flash byte read with address increased function 1 0 0 0-0 0 1 0 Flash byte program with address increased function. Others Reserved IFMT is used to select the flash mode for performing numerous ISP/IAP function or to select page P SFR access. If software selects the mode on automatic flash read for CRC, the flash start-address is defined in IFARDH and IFADRL. The flash end-address is defined at {IAPLB + 9’b1-1111-1111}.

megawin Version: 1.00 248 26.2. ADC Operation ADC has a maximum conversion speed of 800 ksps. The ADC conversion clock is a divided version of the system clock, S0 BRG overflow or Timer 2 overflow, determined by the ADCKS2~0 bits in the ADCFG0 register. The ADC conversion clock should be no more than 24 MHz. After the conversion is complete (ADCI is high), the conversion result can be found in the ADC Result Registers (ADCDH, ADCDL). For single ended conversion, the result is 26.2.1. ADC Input Channels The analog multiplexer (AMUX) selects the inputs to the ADC, allowing any of the pins on AIN7~0 to be measured in single-ended mode and one internal voltage reference (IVR, 1.4V). The ADC input channels are configured and selected by CHS3~0 in the ADCON0 register and ACHS in the ADCFG0 register as shown in Figure 26–1. The selected pin is measured with respect to GND. 26.2.2. ADC Internal Voltage Reference The default ADC reference is VDD. If the VDD is not fixed at a certain voltage, then use the following steps to read voltage: 1) To set the analog multiplexer (AMUX) to IVR. 2) Convert and store the IVR value by ADC. (Hint: Different VDD voltage will get different IVR read back value, but IVR is fixed at 1.4V. So this read back value can be tread as the reference value.) 3) To use the IVR read back reference value to calculate the VDD value. Now the VDD get a certain value, and can be treated as the reference voltage. 4) To use the reference voltage converts the input voltage. 26.2.3. Starting a Conversion Prior to using the ADC function, the user should: 1) Turn on the ADC hardware by setting the AD CEN bit, 2) Configure the ADC input clock by bits ADCKS2, ADCKS1 and ADCKS0 3) Select the analog input channel by bits ACHS, CHS3, CHS2, CHS1 and CHS0 4) Configur e the selected input (shared with P1) to the Analog-Input-Only mode, and 5) Configure ADC result arrangement using ADRJ bit. Now, user can set the ADCS bit to start the A-to-D conversion. The conversion time is controlled by the bits ADCKS2, ADCKS1 and ADCKS0. Once the conversion is completed, the hardware will automatically clear the ADCS bit, set the interrupt flag ADCI and load the 12 bits of conversion result into ADCDH and ADCDL (according to ADRJ bit) simultaneously. If user sets the ADCS and selects the ADC trigger mode to S0BRG/Timer2 over flow or free-run, then the ADC will keep conversion continuously unless ADCEN is cleared or configure ADC to manual mode. As described above, the interrupt flag ADCI, when set by hardware, shows a completed conversion. Thus two ways may be used to check if the conversion is completed: (1) Always polling the interrupt flag ADCI by software; (2) Enable the ADC interrupt by setting bits EADC (in EIE1 register) and EA (in IE register), and then the CPU will jump into its Interrupt Service Routine when the conversion is completed. Regardless of (1) or (2), the ADCI flag should be cleared by software before next conversion. ADC Result = VDD Voltage VIN x 4096

megawin Version: 1.00 249 26.2.4. ADC Conversion Rate The user can select the appropriate conversion speed according to the frequency of the analog input signal. The maximum input clock of the ADC is 24MHz and it operates a minimum conversion time with 30 ADC clocks. User can configure the ADCKS2~0 (ADCFG0.7~5), SHT (ADCFG2.7~0) and HA (ADCFG3.5) to specify the conversion rate. The following equation is the clock number of one ADC conversion: Please note is the input signal is AC signal, fN, and assume the sample rate is fS, based on Nyquist theorem, fS should large than 2 times fN to ensure the measurement accuracy. For example, 1. To get 800K Sample Rate: If SYSCLK= 24MHz and the ADCKS = SYSCLK is selected, SHT = 0, Then conversion rate fS = 24MHz/(30+0) = 800K sps. (In this case, the AC input signal fN frequency should lower than 400KHz to ensure the measurement accuracy.) 2. To get 150K Sample Rate: If SYSCLK= 24MHz and the ADCKS = SYSCLK/4 is selected, SHT = 10, Then conversion rate fS = 24MHz/4/(30+10) = 150K sps. (In this case, the AC input signal fN frequency should lower than 75KHz to ensure the measurement accuracy.) 26.2.5. ADC Interrupts The ADC interrupt of MG82F6D17 includes 3 sources: 1. ADCI, when an A/D conversion is completed, ADCI will be set to invoke an interrupt. The interrupt on this flag can be blocked by IGADCI (ADCFG1.7). 2. SMPF, it is set when an ADC channel sample & hold is completed to invoke an interrupt. The interrupt on this flag can be blocked by SMPFIE (ADCFG1.5). 3. ADCWI, under ADC Window Compare mode, this Interrupt flag will be held when Window Comparison Data match has occurred. An interrupt is invoked if it is enabled. The interrupt on this flag can be enabled by EADCWI. (ADCFG1.6) Figure 26–2. ADC Interrupt ADC Conversion Rate = (30 + X) ADC Clock Freq. ; X = SHT, 0~255 SMPF SMPFIE EADCWI ADCWI EIE1.EADC ADC Interrupt ADCI IGADCI ADC Conversion Complete ADC Channel Sample Complete ADC Result match Window Detect

megawin Version: 1.00 250 Figure 26–3. ADC Conversion Timing 26.2.6. ADC Window Detect The MG82F6D17 ADC's programmable window detector continuously compares the ADC output registers with user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt driven system, saving code space and CPU bandwidth while delivering faster response times. The window detector interrupt flag (ADCWI) can also be used in polled mode. The Window-High-Boundary (WHB[11:0] , {ADCFG12, ADCFG11}) and Window-Low-Boundary (WLB[11:0], {ADCFG14, ADCFG13}) registers hold the boundary values. The Window-Boundary flags can be programmed to catch the ADC convert value (ADCDH:ADCDL) when it is inside or outside of the user-defined boundary. The following figure shows the two window detect modes: 1. ADWM0 = 0: When ADC convert value is “inside” the boundary the interrupt flag ADCWI will be held. Which means the condition WLB[11:0] ≤ ADCDH:ADCDL ≤ WHB[11:0] is true, ADCWI will be held. 2. ADWM0 = 1: When ADC convert value is “outside” the boundary the interrupt flag ADCWI will be held. Which means the condition WLB[11:0] > ADCDH:ADCDL or ADCDH:ADCDL< WHB[11:0] is true, ADCWI will be held. Figure 26–4. ADC Window Detect Another application of ADC Window Detect is to specify the voltage is lager or less than a specific voltage. For example: 1. The target voltage ≥ the condition: ADWM0 = 0, to set condition value in WLB and set WHB = 0xFFF 2. The voltage less ≤ the condition: ADWM0 =0, to set the condition value in WHB and set WLB = 0 3. The target voltage > the condition: ADWM0 = 1, to set condition value in WHB and set WLB = 0 4. The target voltage < the condition: ADWM0 = 1, to set condition value in WLB and set WHB = 0xFFF 0 1 2 3 4 5 6 7 26 27 28 29 30 ≤ 24MHz ADCS ADCI 1 2 3-2

30 ADCK

5uS ADCK SMPF 0x0FFF 0x0000 ADCDH:ADCDL WHB[11:0] WLB[11:0] ADWM0 = 0 ADCWI = 1 When WLB ≤ ADCDH:ADCDL ≤ WHB ADCWI not affected ADCWI not affected 0x0FFF 0x0000 ADCDH:ADCDL WHB[11:0] WLB[11:0] ADWM0 = 1 ADCWI = 1 When WHB < ADCDH:ADCDL ADCWI not affected ADCWI = 1 When ADCDH:ADCDL < WLB

megawin Version: 1.00 251 26.2.7. ADC Channel Scan Mode MG82F6D17 has 8 channels used as ADC input. If the application needs to watch serval voltage by different input pad sequentially, to use ADC Channel Scan Mode can be the easy way to implement and save the channel switch time. To set the ASCE.7 ~ ASCE.0 in ADCFG5 to indicate the input channels, and the channels will be changed to next channel after ADC convert finish. To use this function with different ADC trigger mode to auto switch between the channels. To stop this mode just clear ASCE.7 ~ ASCE.0 to disable this function. When the ADC Channel Scan mode is enabled, please do not write the CHS3~0 manually to change channel, otherwise it will cause unexpected channel to be selected. If you want to clear ADCWI (ADC Window Compare Interrupt flag), you need to read modi fy write of the ADCON0 to prevent the CHS3 ~ CHS0 to be changed. And please note, when using this mode, the ACHS needs to be “0”, to prevent the internal ADC channel be selected. 1) Turn on the ADC hardware by setting the AD CEN bit, 2) Configuring the ADC input clock by bits ADCKS2, ADCKS1 and ADCKS0 3) Configur ing the selected input (shared with P1) to the Analog-Input-Only mode 4) Configure ADC result arrangement using ADRJ bit. 5) Select the analog input channels by setting ASCE.7 ~ ASCE.0 in ADCFG 5 6) Select ADC Trigger Mode by setting ADTM [3:0] 26.2.8. Transfer ADC Data by DMA When using ADC with DMA transfer, it needs to check following settings: 1. DMA controller will transfer ADCDL and then ADCDH 2. ADRJ (ADC result Right-Justified selection). 3. ADC Data Resolution: There are 3 ADC data resolution can be selected, 12-bit, 10-bit and 8-bit. To use ARES[1:0] to set the resolution. 4. ADC Data Bit Transfer by DMA: There are 2 different options can be chosen for DMA transfer, 2- byte and 1-byte which is selected by DBSD. When 8-bit is selected, the DMA controller will automatically to detect the register which hold the ADC value to transfer. For example when ADC Data Resolution is 8 bit mode: i. ADRJ = 0 (Left-Justified): The ADC value will store in ADCDH. If DMA transfer mode is 8-bit, then ADCDH will be transferred. ii. ADRJ = 1 (Right-Justified): The ADC value will store in ADCDL. If DMA transfer mode is 8-bit, then ADCDL will be transferred. For example, when VIN = VDD the ADC value is 0xFFF, with different combinations the ADC Data will be transfer by DMA as following: ADRJ ARES[1:0] ADC Data Resolution DBSD ADC Data Byte Transfer by DMA Data Transfer Order 1st Data 2nd Data (12-bit) 0 (2-byte Data) 0xF0 0xFF 1 (1-byte Data) 0xFF X (10-bit) 0 (2-byte Data) 0xC0 0xFF 1 (1-byte Data) 0xFF X (8-bit) 0 (2-byte Data) 0x00 0xFF 1 (1-byte Data) 0xFF X (12-bit) 0 (2-byte Data) 0xFF 0x0F 1 (1-byte Data) 0xFF X (10-bit) 0 (2-byte Data) 0xFF 0x03 1 (1-byte Data) 0xFF X (8-bit) 0 (2-byte Data) 0xFF 0x00 1 (1-byte Data) 0xFF X

megawin Version: 1.00 252 26.2.9. I/O Pins Used with ADC Function The analog input pins used for the A/D converters also have its I/O port‘s digital input and output function. In order to give the proper analog performance, a pin that is being used with the ADC should have its digital output as disabled. It is done by putting the port pin into the input-only mode. And when an analog signal is applied to the ADCI7~0 pin and the digital input from this pin is not needed, software could set the corresponding pin to analog-input-only mode to reduce power consumption in the digital input buffer. The port pin configuration for analog input function is described in Table 14–3. General Port Configuration Settings and Section “” and “14.2.1 Port 1 Register”. 26.2.10. Idle and Power-Down Mode If the ADC is turned on in Idle mode and Power-Down mode, it will consume a little power. So, power consumption can be reduced by turning off the ADC hardware (ADCEN=0) before entering Idle mode and Power-Down mode. In Power-Down mode, the ADC does not function. If software triggers the ADC operation in Idle mode, the ADC will finish the conversion and set the ADC interrupt flag, ADCI. When the ADC interrupt enable (EADC, EIE1.1) is set, the ADC interrupt will wake up CPU from Idle mode. 26.2.11. How to improve ADC Accuracy To use ADC measure the voltage, its accuracy might be affected by many factors, for example, the power noise of the MCU VDD or tolerance of the reference voltage. MG82F6D64/32 has trimmed the internal reference voltage – IVR under VDD equals to 3.3V, and use the ADC to read its ADC value to store in flash ROM as the Pre-stored value. To use this value by following formulas to calculate the AIN voltage instead of measuring VDD to calculate the 1 LSB voltage.  To push back the IVR voltage (which was measured under VDD=3.3V) 𝐼𝐼𝐼𝐼𝐼𝐼 𝐼𝐼𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 = 𝐼𝐼𝐼𝐼𝑅𝑅𝐴𝐴𝐴𝐴𝐴𝐴_𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃_𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑃𝑃 ∗3300  To use the proportional relationship calculate the I/O pin voltage 𝐴𝐴𝐼𝐼𝐴𝐴 𝐼𝐼𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 = 𝐼𝐼𝐼𝐼𝑅𝑅 𝐼𝐼𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉∗𝐴𝐴𝐼𝐼𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴_𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑃𝑃 𝐼𝐼𝐼𝐼𝑅𝑅𝐴𝐴𝐴𝐴𝐴𝐴_𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑃𝑃 Note: To read the IVR ADC Presorted value please reference 27.3 How to read IVR (1.4V) ADC Prestored value . 26.3. ADC Register ADCON0: ADC Control Register 0 SFR Page = 0~F SFR Address = 0xC4 RESET = 0000-0000 7 6 5 4 3 2 1 0 ADCEN ADCWI CHS3 ADCI ADCS CHS2 CHS1 CHS0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: ADCEN, ADC Enable. 0: Clear to turn off the ADC block. 1: Set to turn on the ADC block. At least 5us ADC enabled time is required before set ADCS. Bit 6: ADCWI, ADC Window Compare Interrupt flag. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. The flag must be cleared by software. 1: This flag is set when ADC Window Comparison Data match has occurred. An interrupt is invoked if it is enabled. The interrupt on this flag can be enabled by EADCWI. (ADCFG1.6)

megawin Version: 1.00 253 Bit 5: CHS3. Combined CH2~0 to select ADC input channel. Bit 4: ADCI, ADC Interrupt Flag. 0: The flag must be cleared by software. 1: This flag is set when an A/D conversion is completed. An interrupt is invoked if it is enabled. The interrupt on this flag can be blocked by IGADCI (ADCFG1.7). Bit 3: ADCS. ADC Start of conversion. 0: ADCS cannot be cleared by software. 1: Setting this bit by software starts an A/D conversion. On completion of the conversion, the ADC hardware will clear ADCS and set the ADCI. A new conversion may not be started while either ADCS or ADCI is high. Bit 2~0: CHS2 ~ CHS1, Input Channel Selection for ADC analog multiplexer. In Single-ended mode: ACHS CHS3~0 Selected Channel 0 0 0 0 0 AIN0 (P1.0) 0 0 0 0 1 AIN1 (P1.1) 0 0 0 1 0 AIN2 (P2.2) 0 0 0 1 1 AIN3 (P2.4) 0 0 1 0 0 AIN4 (P3.0) 0 0 1 0 1 AIN5 (P1.5) 0 0 1 1 0 AIN6 (P1.6) 0 0 1 1 1 AIN7 (P1.7) 1 0 0 0 0 Int. VREF (IVR/1.4V) 1 0 0 0 1 AVSS 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved Others Reserved ADCFG0: ADC Configuration Register 0 SFR Page = 0 Only SFR Address = 0xC3 RESET = 0000-0000 7 6 5 4 3 2 1 0 ADCKS2 ADCKS1 ADCKS0 ADRJ ACHS SMPF ADTM1 ADTM0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~5: ADC Conversion Clock Select bits. ADCKS[2:0] ADC Clock Selection 0 0 0 SYSCLK 0 0 1 SYSCLK/2 0 1 0 SYSCLK/4 0 1 1 SYSCLK/8 1 0 0 SYSCLK/16 1 0 1 SYSCLK/32 1 1 0 S0TOF/2 1 1 1 T2OF/2 Note: 1. SYSCLK is the system clock. 2. S0TOF is UART0 Baud-Rate Generator Overflow. 3. T2OF is Timer2 Overflow. Bit 4: ADRJ, ADC result Right-Justified selection. 0: The most significant 8 bits of conversion result are saved in ADCDH [7:0], while the least significant 2 bits in ADCDL[7:6]. 1: The most significant 2 bits of conversion result are saved in ADCDH [1:0], while the least significant 8 bits in ADCDL[7:0].

megawin Version: 1.00 254 If ADRJ = 0 ADCDH: ADC Date High Byte Register SFR Page = 0~F SFR Address = 0xC6 RESET = xxxx-xxxx 7 6 5 4 3 2 1 0 R R R R R R R R ADCDL: ADC Data Low Byte Register SFR Page = 0~F SFR Address = 0xC5 RESET = xxxx-xxxx 7 6 5 4 3 2 1 0 R R R R R R R R If ADRJ = 1 ADCDH 7 6 5 4 3 2 1 0 R R R R R R R R ADCDL 7 6 5 4 3 2 1 0 R R R R R R R R When in Single-ended Mode, conversion codes are represented as 12-bit unsigned integers. Inputs are measured from ‘0’ to VDD(VREF) x 4095/4096. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADCDH and ADCDL registers are set to ‘0’. Input Voltage (Single-Ended) ADCDH:ADCDL (ADRJ = 0) ADCDH:ADCDL (ADRJ = 1) VDD x 4095/4096 0xFFF0 0x0FFF VDD x 2048/4096 0x8000 0x0800 VDD x 1024/4096 0x4000 0x0400 VDD x 512/4096 0x2000 0x0200 VDD x 256/4096 0x1000 0x0100 VDD x 128/4096 0x0800 0x0080 0 0x0000 0x0000 Bit 3: ACHS, ADC Auxiliary CHannel Select. Decode ACHS and CHS3~0 to select ADC input channel. Bit 2: SMPF. ADC channel sample & hold flag. 0: The flag must be cleared by software. 1: This flag is set when an ADC channel sample & hold is completed. An interrupt is invoked if it is enabled. The interrupt on this flag can be enabled by SMPFIE (ADCFG1.5). Bit 1~0: ADC Trigger Mode selection. ADTM[1:0] ADC Conversion Start Selection 0 0 Set ADCS 0 1 Timer 0 overflow 1 0 Free running mode 1 1 S0 BRG overflow

megawin Version: 1.00 255 ADCFG1: ADC Configuration Register 1 SFR Page = 1 Only SFR Address = 0xC3 RESET = xxx0-0000 7 6 5 4 3 2 1 0 IGADCI EADCWI SMPFIE SIGN AOS.3 AOS.2 AOS.1 AOS.0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: IGADCI, Ignore ADCI interrupt. 0: Enabled ADCI interrupt. Default is enabled. 1: Disable ADCI interrupt. Bit 6: EADCWI, ADCWI interrupt enable. 0: Disable ADCWI interrupt. 1: Enable ADCWI interrupt to share the ADC interrupt vector. Bit 5: SMPFIE, SMPF interrupt enable. 0: Disable SMPF interrupt. 1: Enable SMPF interrupt to share the ADC interrupt vector. Bit 4~0: SIGN and AOS.3~0. The register value adjusts the ADC result in {ADCDH, ADCDL} for offset cancellation. Software can dynamically collect the ADC offset value. Software can also stores the value in MG82F6D17 IAP zone to use it as a constant parameter for ADC offset cancellation. The following table lists the AD0ROC adjustment value for ADC transfer result. {Sign, AOS.[3:0]} Value in {ADCDH, ADCDL} 0_1111 ADC transfer value + 15 0_1110 ADC transfer value + 14 …… …… 0_0010 ADC transfer value + 2 0_0001 ADC transfer value + 1 0_0000 ADC transfer value + 0 1_1111 ADC transfer value – 1 1_1110 ADC transfer value – 2 …… …… 1_0001 ADC transfer value – 15 1_0000 ADC transfer value – 16 ADCFG2: ADC Configuration Register 2 SFR Page = 2 only SFR Address = 0xC3 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: SHT[7:0], extend ADC sample time. The value of SHT is 0~255 ADC clocks. ADCFG3: ADC Configuration Register 3 SFR Page = 3 only SFR Address = 0xC3 RESET = 0100-0000 7 6 5 4 3 2 1 0 ADPS1 ADPS0 -- -- ARES1 ARES0 ADES0 -- R/W R/W W W R/W R/W R/W W Bit 7~6: ADPS1~0, ADC Trigger Mode selection bit 3~2. ADPS[1:0] ADC Power Saving control 0 0 High power, high speed 0 1 Medium high power, medium high speed (default) 1 0 Medium low power, medium low speed 1 1 Low power, low speed

megawin Version: 1.00 256 Bit 5~4: Reserved. Software must write “0” on these bits when ADCFG3 is written. Bit 3~2: ARES1~0, ADC data Resolution selection bit 1~0. ARES[1:0] ADC Data Resolution Selection 0 0 12-bit Data 0 1 10-bit Data 1 0 8-bit Data 1 1 Res. (8-bit Data) Bit 1: ADES0, ADC DMA Event request Selection. 0: Request DMA to service ADC data transfer on ADCI setting. 1: Request DMA to service ADC data transfer on ADCWI setting Bit 0: Reserved. Software must write “0” on this bit when ADCFG3 is written. ADCFG4: ADC Configuration Register 4 SFR Page = 4 only SFR Address = 0xC3 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- ADWM0 ADTM3 ADTM2 -- -- DBSD -- W R/W R/W R/W W W R/W W Bit 7: Reserved. Software must write “0” on this bit when ADCFG4 is written. Bit 6: ADWM0. Mode selection of ADC Window Detector. 0: ADCWI will be set when ADCDH: ADCDL value is within the range defined by WHB and WLB. 1: ADCWI will be set when ADCDH: ADCDL value is outside of the range defined by WHB and WLB. Bit 5~4: ADC Trigger Mode selection bit 3~2. ADTM[3:0] ADC Conversion Start Selection Source 0 0 0 0 Set ADCS Software 0 0 0 1 Timer 0 overflow (T0OF) Timer 0 0 0 1 0 Free running mode ADC 0 0 1 1 S0 BRG overflow (S0TOF) S0 BRG 0 1 0 0 KBIET KBI 0 1 0 1 INT1ET nINT1 0 1 1 0 INT2ET nINT2 0 1 1 1 Reserved Reserved 1 0 0 0 T2EXES Timer 2 1 0 0 1 Reserved Reserved 1 0 1 0 T3EXES Timer 3 1 0 1 1 Reserved Reserved 1 1 0 0 PCA0 Overflow (C0TOF) PCA0 Counter 1 1 0 1 C0CMP6 (Note1) PCA0 CH6 Compare 1 1 1 0 C0CMP6 or C0CMP7 (Note1) PCA0 CH6/CH7 Compare 1 1 1 1 Reserved Reserved Note1: C0CMPx: ReferenceFigure 17–7 & Figure 17–8 Bit 3~2: Reserved. Software must write “0” on these bits when ADCFG4 is written. Bit 1: DBSD, ADC Data Bit transfer by DMA. DBSD ADC Data Byte Transfer by DMA 0 2 Bytes Data 1 1 Byte Data Bit 0: Reserved. Software must write “0” on this bit when ADCFG4 is written.

megawin Version: 1.00 257 ADCFG5: ADC Configuration Register 5 SFR Page = 5 only SFR Address = 0xC3 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: AIN7~AIN0 auto-scan enabled. 0: Disable ADC channel auto-scan. 1: Enable ADC channel auto-scan. ADCFG11: ADC Configuration Register 11 SFR Page = B only SFR Address = 0xC3 RESET = 1111-1111 7 6 5 4 3 2 1 0 WHB.3 WHB.2 WHB.1 WHB.0 1 1 1 1 R/W R/W R/W R/W W W W W ADCFG12: ADC Configuration Register 12 SFR Page = C only SFR Address = 0xC3 RESET = 1111-1111 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W WHB.9~0: ADC Window High Boundary value. ADCFG13: ADC Configuration Register 13 SFR Page = D only SFR Address = 0xC3 RESET = 1111-1111 7 6 5 4 3 2 1 0 WLB.3 WLB.2 WLB.1 WLB.0 0 0 0 0 R/W R/W R/W R/W W W W W ADCFG14: ADC Configuration Register 14 SFR Page = E only SFR Address = 0xC3 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W WLB.9~0: ADC Window Low Boundary value. PCON3: Power Control Register 3 SFR Page = P Only SFR Address = 0x45 POR = 0000-0000 7 6 5 4 3 2 1 0 IVREN 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: IVREN, Internal Voltage Reference Enable. 0: Disable on-chip IVR (1.4V). 1: Enable on-chip IVR (1.4V). Bit 6~0: Reserved. Software must write “0” on these bits when PCON3 is written.

megawin Version: 1.00 258 27. Internal Voltage Reference (IVR, 1.4V) The IVR can be used as the reference voltage of the ADC. The typical output is 1.4V. It can be disabling by IVREN. 27.1. IVR (1.4V) Structure Figure 27–1. IVR Diagram 27.2. IVR Register PCON3: Power Control Register 3 SFR Page = P Only SFR Address = 0x45 POR = 0000-0000 7 6 5 4 3 2 1 0 IVREN 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: IVREN, Internal Voltage Reference Enable. 0: Disable on-chip IVR (1.4V). 1: Enable on-chip IVR (1.4V). Bit 6~0: Reserved. Software must write “0” on these bits when PCON3 is written. On-chip Bias Generator To ADC, BODx, IHRCO Internal Voltage Reference 1.4V IVR14 Channel Input of ADC EN IVREN (PCON3.7)

megawin Version: 1.00 259 27.3. How to read IVR (1.4V) ADC Prestored value IVR had been trimmed @VDD=3.3V in factory. And its ADC value had been stored in reserved area in Flash ROM for customer calculation the voltage value from the ADC value. It means customer don’t needs to do the calibration of the ADC in the production line. It can save the test time and cost. Please reference the following sample code to read the prestored IVR ADC value. And reference 26.2.11 How to improve ADC Accuracy to understand how to improve ADC measurement accuracy. void Get_Prestored_IVR(void) ISPCR = ISP_ENABLE; BOREV = 0x22; IFMT = 0x06; IFADRH = 0x00; IFADRL = 0xC0; SCMD = 0x46; SCMD = 0xB9; Trim_IVR_ADC_Value.B[0] = IFD; IFADRL ++; SCMD = 0x46; SCMD = 0xB9; Trim_IVR_ADC_Value.B[1] = IFD; ISPCR = ISP_DISABLE;

megawin Version: 1.00 260 28. ISP and IAP The flash memory of MG82F6D17 is partitioned into AP-memory, IAP-memory and ISP-memory. AP-memory is used to store user’s application program; IAP-memory is used to store the non-volatile application data; and, ISP-memory is used to store the boot loader program for In-System Programming. When MCU is running in ISP region, MCU could modify the AP and IAP memory for software upgraded. If MCU is running in AP region, software could only modify the IAP memory for storage data updated. 28.1. MG82F6D17 Flash Memory Configuration There are total 16K bytes of Flash Memory in MG82F6D17 and Figure 28–1 shows the device flash configuration of MG82F6D17. The ISP-memory can be configured as disabled or up to 7.5K bytes space by hardware option setting with 0.5KB step. The flash size of IAP memory is located between the IAP low boundary and IAP high boundary. The IAP low boundary is defined by the value of IAPLB register. The IAP high boundary is associated with ISP start address which decides ISP memory size by hardware option. The IAPLB register value is configured by hardware option or AP software programming. All of the AP, IAP and ISP memory are shared the total 16K bytes flash memory. Figure 28–1. MG82F6D17 Flash Memory Configuration Note: In default, the MG82F6D17 that Megawin shipped had configured the flash memory for 1.5K ISP, 1K IAP and Lock enabled. The 1.5K ISP region is inserted Megawin proprietary COMBO ISP code to perform In-System-Programming through Megawin 1-Line ISP protocol and COM port ISP. The 1K IAP size can be re-configured by software for application required. 0x2200 if ISP Size = 7.5KB 0x2400 if ISP Size = 7KB 0x3000 if ISP Size = 4KB 0x3C00 if ISP Size = 1KB 0x3E00 if ISP Size = 0.5KB (1) ISP Start Address: Note: AP-memory ISP-memory IAP-memory 0x0000 0x3FFF IAP High Boundary ISP Start Address IAP Low Boundary Flash Memory Total: 16KB Application Code IAP Data ISP Code IAPLB = 0x36 (default) IAP start 0x3600 ISP start 0x3A00 (default)(4) If ISP is disabled: IAP High Boundary = 0x3FFF IAP Low Boundary = 0x3FFF – IAP Size + 1 (3) If ISP is enabled: IAP High Boundary = ISP Start Address – 1 IAP Low Boundary = ISP Start Address – IAP Size (2) IAP Size : IAPLB = IAP Low Boundary (ROM High-Byte address) IAP Start Address = {IAPLB, 00H} IAP Size = ISP Start Address – IAP Start Address Set LAPLB = Change IAP Size

megawin Version: 1.00 261 28.2. MG82F6D17 Flash Access in ISP/IAP There are 3 flash access modes are provided in MG82F6D17 for ISP and IAP application: page erase mode, byte program mode and read mode. MCU software uses these three modes to update new data into flash storage and get flash content. This section shows the flow chart and demo code for the various flash modes. To do Page Erase (512 Bytes per Page) Step 1: Set MS[2:0]=[0,1,1] in ISPCR register to select Page Erase Mode. Step 2: Fill page address in IFADRH & IFADRL registers. Step 3: Sequentially write 0x46h then 0xB9h to SCMD register to trigger an ISP processing. To do Byte Program Step 1: Set MS[2:0]=[0,1,0] in ISPCR register to select Byte Program Mode. Step 2: Fill byte address in IFADRH & IFADRL registers. Step 3: Fill data to be programmed in IFD register. Step 4: Sequentially write 0x46h then 0xB9h to SCMD register to trigger an ISP processing. To do Read Step 1: Set MS[2:0]=[0,0,1] in ISPCR register to select Read Mode. Step 2: Fill byte address in IFADRH & IFADRL registers. Step 3: Sequentially write 0x46h then 0xB9h to SCMD register to trigger an ISP processing. Step 4: Now, the Flash data is in IFD register. The detailed descriptions of flash page erase, byte program and flash read in MG82F6D17 is listed in the following sections:

megawin Version: 1.00 265 28.3. ISP Operation ISP means In-System-Programming which makes it possible to update the user’s application program (in AP-memory) and non-volatile application data (in IAP -memory) without removing the MCU chip from the actual end product. This useful capability makes a wide range of field-update applications possible. The ISP mode is used in the loader program to program both the AP-memory and IAP-memory. Note: (1) Before using the ISP feature, the user should configure an ISP-memory space and pre-program the ISP code (boot loader program) into the ISP-memory by a universal Writer/Programmer or Megawin proprietary Writer/Programmer. (2) ISP code in the ISP-memory can only program the AP-memory and IAP-memory. After ISP operation has been finished, software writes “001” on ISPCR.7 ~ ISPCR.5 which triggers an software RESET and makes CPU reboot into application program memory (AP-memory) on the address 0x0000. As we have known, the purpose of the ISP code is to program both AP -memory and IAP-memory. Therefore, the MCU must boot from the ISP-memory in order to execute the ISP code. There are two methods to implement In-System Programming according to how the MCU boots from the ISP-memory. 28.3.1. Hardware approached ISP To make the MCU directly boot from the ISP -memory when it is just powered on, the MCU’s hardware options HWBS and ISP Memory must be enabled. The ISP entrance method by hardware option is named hardware approached. Once HWBS and ISP Memory are enabled, the MCU will always boot from the ISP -memory to execute the ISP code (boot loader program) when it is just powered on. The first thing the ISP code should do is to check if there is an ISP request. If there is no ISP requested, the ISP code should trigger a software reset (setting ISPCR.7~5 to “ 101” simultaneously) to make the MCU re-boot from the AP-memory to run the user’s application program.. If the additional hardware option, HWBS2, is enabled with HWBS and ISP Memory, the MCU will always boot from ISP memory after power-on or external reset finished. It provides another hardware approached way to enter ISP mode by external reset signal. After first time power-on, MG82F6D17 can perform ISP operation by external reset trigger and doesn’t wait for next time power-on, which suits the non-power-off system to apply the hardware approached ISP function. 28.3.2. Software approached ISP The software approached ISP to make the MCU boot from the ISP-memory is to trigger a software reset while the MCU is running in the AP -memory. In this case, neither HWBS nor HWBS2 is enabled. The only way for the MCU to boot from the ISP -memory is to trigger a software reset , setting ISPCR.7~5 to “111” simultaneously, when running in the AP-memory. Note: the ISP memory must be configured a valid space by hardware option to reserve ISP mode for software approached ISP application.

megawin Version: 1.00 266 28.3.3. Notes for ISP Developing of the ISP Code Although the ISP code is programmed in the ISP-memory that has an ISP Start Address in the MCU’s Flash (see Figure 28–1 for MG82F6D17, it doesn’t mean you need to put this offset (= ISP Start Address) in your source code. The code offset is automatically manipulated by the hardware. User just needs to develop it like an application program in the AP-memory. Interrupts during ISP After triggering the ISP /IAP flash processing, the MCU will halt for a while for internal ISP processing until the processing is completed. At this time, the interrupt will queue up for being serviced if the interrupt is enabled previously. Once the processing is completed, the MC U continues running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active. The user, however, should be aware of the following: (1) Any interrupt can not be in-time serviced when the MCU halts for ISP processing. (2) The low/high-level triggered external interrupts, nINTx, should keep activated until the ISP is completed, or they will be neglected. ISP and Idle mode MG82F6D17 does not make use of idle- mode to perform ISP function. Instead, it freezes CPU running to release the flash memory for ISP /IAP engine operating. Once ISP /IAP operation finished, CPU will be resumed and advanced to the instruction which follows the previous instruction that invokes ISP/AP activity. Accessing Destination of ISP As mentioned previously, the ISP is used to program both the AP -memory and the IAP -memory. Once the accessing destination address is beyond that of the last byte of the IAP -memory, the hardware will automatically neglect the triggering of ISP processing. That is the triggering of ISP is invalid and the hardware does nothing. Flash Endurance for ISP The endurance of the embedded Flash is 20,000 erase/write cycles, that is to say, the erase-then-write cycles shouldn’t exceed 20,000 times. Thus the user should pay attention to it in the application which needs to frequently update the AP-memory and IAP-memory.

megawin Version: 1.00 267 28.4. In-Application-Programming (IAP) The MG82F6D17 has built a function as In Application Programmable (IAP), which allows some region in the Flash memory to be used as non -volatile data storage while the application program is running. This useful feature can be applied to the application where the data must be kept after power off. Thus, there is no need to use an external serial EEPROM (such as 93C46, 24C01, .., and so on) for saving the non-volatile data. In fact, the operating of IAP is the same as that of ISP except the Flash range to be programmed is different. The programmable Flash range for ISP operating is located within the AP and IAP memory, while the range for IAP operating is only located within the configured IAP-memory. Note: (1) For MG82F6D17 IAP feature, the software should specify an IAP-memory space by writing IAPLB in IFMT defined. The IAP-memory space can be also configured by a universal Writer/Programmer or Megawin proprietary Writer/Programmer which configuration is corresponding to IAPLB initial value. (2) The program code to execute IAP is located in the AP-memory and just only program IAP-memory not ISP-memory. 28.4.1. IAP-memory Boundary/Range If ISP-memory is specified, the range of the IAP-memory is determined by IAP and the ISP starts address as listed below. IAP high boundary = ISP start address –1. IAP low boundary = ISP start address - I A P. If ISP-memory is not specified, the range of the IAP-memory is determined by the following formula. IAP high boundary = 0x3FFF. IAP low boundary = 0x3FFF – IAP + 1. For example, if ISP-memory is 1K, so that ISP start address is 0x3C00, and IAP-memory is 1K, then the IAP-memory range is located at 0x3800 ~ 0x3BFF. The IAP low boundary in MG82F6D17 is defined by IAPLB register which can be modified by software to adjust the IAP size in user’s AP program. 28.4.2. Update data in IAP-memory The special function registers are related to ISP/IAP would be shown in Section “28.5 ISP/IAP Register“. Because the IAP-memory is a part of Flash memory, only Page Erase, no Byte Erase, is provided for Flash erasing. To update “one byte” in the IAP-memory, users can not directly program the new datum into that byte. The following steps show the proper procedure: Step 1: Save the whole page flash data (with 512 bytes) into XRAM buffer which contains the data to be updated. Step 2: Erase this page (using ISP/IAP Flash Page Erase mode). Step 3: Modify the new data on the byte(s) in the XRAM buffer. Step 4: Program the updated data out of the XRAM buffer into this page (using ISP/IAP Flash Program mode). To read the data in the IAP-memory, users can use the ISP/IAP Flash Read mode to get the targeted data.

megawin Version: 1.00 268 28.4.3. Notes for IAP Interrupts during IAP After triggering the ISP /IAP flash processing for In- Application Programming, the MCU will halt for a while for internal IAP processing until the processing is completed. At this time, the interrupt will queue up for being serviced if the interrupt is enabled previously. Once the processing is completed, the MCU continues running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active. Users, however, should be aware of the following: (1) Any interrupt can not be in-time serviced during the MCU halts for IAP processing. (2) The low/high-level triggered external interrupts, nINTx, should keep activated until the IAP is completed, or they will be neglected. IAP and Idle mode MG82F6D17 does not make use of idle- mode to perform IAP function. Instead, it freezes CPU running to release the flash memory for ISP/IAP engine operating. Once ISP /IAP operation finished, CPU will be resumed and advanced to the instruction which follows the previous instruction that invokes ISP/AP activity. Accessing Destination of IAP As mentioned previously, the IAP is used to program only the IAP-memory. Once the accessing destination is not within the IAP-memory, the hardware will automatically neglect the triggering of IAP processing. That is the triggering of IAP is invalid and the hardware does nothing. An Alternative Method to Read IAP Data To read the Flash data in the IAP-memory, in addition to using the Flash Read Mode, the alternative method is using the instruction “MOVC A,@A+DPTR”. Where, DPTR and ACC are filled with the wanted address and the offset, respectively. And, the accessing destination must be within the IAP -memory, or the read data will be indeterminate. Note that using ‘MOVC’ instruction is much faster than using the Flash Read Mode. Flash Endurance for IAP The endurance of the embedded Flash is 20,000 erase/write cycles, that is to say, the erase-then-write cycles shouldn’t exceed 20,000 times. Thus the user should pay attention to i t in the application which needs to frequently update the IAP-memory.

megawin Version: 1.00 269 28.5. ISP/IAP Register The following special function registers are related to the access of ISP, IAP and Page-P SFR: IFD: ISP/IAP Flash Data Register SFR Page = 0~F SFR Address = 0xE2 RESET = 1111-1111 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W IFD is the data port register for ISP/IAP/Page-P operation. The data in IFD will be written into the desired address in operating ISP/IAP/Page-P write and it is the data window of readout in operating ISP/IAP read. IFADRH: ISP/IAP Address for High-byte addressing SFR Page = 0~F SFR Address = 0xE3 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W IFADRH is the high-byte address port for all ISP/IAP modes. It is not defined in Page-P mode. IFADRL: ISP/IAP Address for Low-byte addressing SFR Page = 0~F SFR Address = 0xE4 RESET = 0000-0000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W IFADRL is the low byte address port for all ISP/IAP/Page-P modes. In flash page erase operation, it is ignored. IFMT: ISP/IAP Flash Mode Table SFR Page = 0~F SFR Address = 0xE5 RESET = xxxx-x000 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~4: Reserved. Software must write “0000_0” on these bits when IFMT is written. Bit 3~0: ISP/IAP/Page-P operating mode selection MS[7:0] Mode 0 0 0 0-0 0 0 0 Standby 0 0 0 0-0 0 0 1 Flash byte read of AP/IAP-memory 0 0 0 0-0 0 1 0 Flash byte program of AP/IAP-memory 0 0 0 0-0 0 1 1 Flash page erase of AP/IAP-memory 0 0 0 0-0 1 0 0 Page P SFR Write 0 0 0 0-0 1 0 1 Page P SFR Read 1 0 0 0-0 0 0 0 Automatic flash read for CRC. 1 0 0 0-0 0 0 1 Flash byte read with address increased function 1 0 0 0-0 0 1 0 Flash byte program with address increased function. Others Reserved IFMT is used to select the flash mode for performing numerous ISP/IAP function or to select page P SFR access. If software selects the mode on automatic flash read for CRC, the flash start-address is defined in IFARDH and IFADRH. The flash end-address is defined at {IAPLB + 9’b1-1111-1111}.

megawin Version: 1.00 270 SCMD: Sequential Command Data register SFR Page = 0~F SFR Address = 0xE6 RESET = xxxx-xxxx 7 6 5 4 3 2 1 0 SCMD R/W R/W R/W R/W R/W R/W R/W R/W SCMD is the command port for triggering ISP/IAP/Page-P activity. If SCMD is filled with sequential 0x46h, 0xB9h and if ISPCR.7 = 1, ISP/IAP/Page-P activity will be triggered. ISPCR: ISP Control Register SFR Page = 0~F SFR Address = 0xE7 POR = 0000-0000 7 6 5 4 3 2 1 0 ISPEN SWBS SWRST CFAIL -- -- -- -- R/W R/W R/W R/W W W W W Bit 7: ISPEN, ISP/IAP/Page-P operation enable. 0: Global disable all ISP/IAP/Page-P program/erase/read function. 1: Enable ISP/IAP/Page-P program/erase/read function. Bit 6: SWBS, software boot selection control. 0: Boot from main-memory after reset. 1: Boot from ISP memory after reset. Bit 5: SWRST, software reset trigger control. 0: No operation 1: Generate software system reset. It will be cleared by hardware automatically. Bit 4: CFAIL, Command Fail indication for ISP/IAP operation. 0: The last ISP/IAP command has finished successfully. 1: The last ISP/IAP command fails. It could be caused since the access of flash memory was inhibited. Bit 3~0: Reserved. Software must write “0” on these bits when ISPCR is written. IAPLB: IAP Low Boundary SFR Page = P Only SFR Address = 0x03 RESET = 0111-000x 7 6 5 4 3 2 1 0 IAPLB 0 W W W W W W W W Bit 7~0: The IAPLB determines the IAP-memory lower boundary. Since a Flash page has 512 bytes, the IAPLB must be an even number. To read IAPLB, MCU need to define the IMFT for mode selection on IAPLB Read and set ISPCR.ISPEN. And then write 0x46h & 0xB9h sequentially into SCMD. The IAPLB content is available in IFD. If write IAPLB, MCU will put new IAPLB setting value in IFD firstly. And then select IMFT, enable ISPCR.ISPEN and then set SCMD. The IAPLB content has already finished the updated sequence. The range of the IAP-memory is determined by IAPLB and the ISP start address as listed below. IAP lower boundary = IAPLB[7:0] x 256, and IAP higher boundary = ISP start address – 1. For example, if IAPLB=0x20 and ISP start address is 0x3000, then the IAP-memory range is located at 0x2000 ~ 0x2FFF. Additional attention point, the IAP low boundary address must not be higher than ISP start address.

megawin Version: 1.00 271 28.5.1. ISP/IAP Sample Code The following Figure 28–8 shows a sample code for ISP operation. Figure 28–8. Sample Code for ISP ; Demo Program for the ISP IFD DATA 0E2h IFADRH DATA 0E3h IFADRL DATA 0E4h IFMT DATA 0E5h SCMD DATA 0E6h ISPCR DATA 0E7h MOV ISPCR,#10000000 b ; ISPCR.7=1, enable ISP ; 1. Page Erase Mode (512 bytes per page) ORL I FMT,#03h ;MS[2:0]=[0,1,1], select Page Erase Mode MOV IFADRH,?? ;fill page address in IFADRH & IFADRL MOV IFADRL,?? ; MOV SCMD,#46h ;trigger ISP processing MOV SCMD,#0B9h ; ;Now in processing...(CPU will halt here until complete) ; 2. Byte Program Mode ORL I FMT,#02h ;MS[2:0]=[0,1,0], select Byte Program Mode ANL ISPCR,#0FAh ; MOV IFADRH,?? ;fill byte address in IFADRH & IFADRL MOV IFADRL,?? ; MOV IFD,?? ;fill the data to be programmed in IFD MOV SCMD,#46h ;trigger ISP processing MOV SCMD,#0B9h ; ;Now in processing...(CPU will halt here until complete) ; 3. Verify using Read Mode ANL IFMT,#0F9h ;MS1[2:0]=[0,0,1], select Byte Read Mode ORL I FMT,#01h ; MOV IFADRH,?? ;fill byte address in IFADRH & IFADRL MOV IFADRL,?? ; MOV SCMD,#46h ;trigger ISP processing MOV SCMD,#0B9h ; ;Now in processing...(CPU will halt here until complete) MOV A,IFD ;data will be in IFD CJNE A,wanted,ISP_error ;compare with the wanted value ... ISP_error: ...

megawin Version: 1.00 272 29. Page P SFR Access MG82F6D17 builds a special SFR page (Page P) to store the control registers for MCU operation. These SFRs can be accessed by the ISP/IAP operation with different IFMT. In page P access, IFADRH must set to “00” and IFADRL indexes the SFR address in page P. If IFMT= 04H for Page P writing, the content in IFD will be loaded to the SFR in IFADRL indexed after the SCMD triggered. If IFMT = 05H for Page P reading, the content in IFD is stored the SFR value in IFADRL indexed after the SCMD triggered. Following descriptions are the SFR function definition in Page P: IAPLB: IAP Low Boundary SFR Page = P SFR Address = 0x03 RESET = 1111-111x 7 6 5 4 3 2 1 0 IAPLB 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~0: The IAPLB determines the IAP-memory lower boundary. Since a Flash page has 512 bytes, the IAPLB must be an even number. To read IAPLB, MCU need to define the IFADRL for SFR address in Page-P, the IMFT for mode selection on Page-P Read and set ISPCR.ISPEN. And then write 0x46h & 0xB9h sequentially into SCMD. The IAPLB content is available in IFD. If write IAPLB, MCU will put new IAPLB setting value in IFD firstly. And index IFADRL, select IMFT, enable ISPCR.ISPEN and then set SCMD. The IAPLB content has already finished the updated sequence. The range of the IAP-memory is determined by IAPLB and the ISP Start address as listed below. IAP lower boundary = IAPLBx256, and IAP higher boundary = ISP start address – 1. For example, if IAPLB=0xE0 and ISP start address is 0xF000, then the IAP-memory range is located at 0xE000 ~ 0xEFF F. Additional attention point, the IAP low boundary address must not be higher than ISP start address. CKCON2: Clock Control Register 2 SFR Page = P Only SFR Address = 0x40 RESET = 0001-0000 7 6 5 4 3 2 1 0 -- -- -- IHRCOE MCKS1 MCKS0 OSCS1 OSCS0 W W W R/W R/W R/W R/W R/W Bit 4: IHRCOE, Internal High frequency RC Oscillator Enable. 0: Disable internal high frequency RC oscillator. 1: Enable internal high frequency RC oscillator. If this bit is set by CPU software, it needs 32 us to have stable output after IHRCOE is enabled. Bit 3~2: MCKS[1:0], MCK Source Selection. MCKS[1:0] MCK Source Selection OSCin =12MHz CKMIS = [01] OSCin =11.059MHz CKMIS = [01] CKMS0 = 0 CKMS0 = 1 CKMS0 = 0 CKMS0 = 1 0 0 OSCin 12MHz 11.059MHz 0 1 CKMI x4 / x6 24MHz 36MHz 22.118MHz 33.177MHz 1 0 CKMI x5.33 / x8 32MHz 48MHz 29.491MHz 44.236MHz 1 1 CKMI x8 / x12 48MHz 72MHz 44.236MHz 66.354MHz Note: It needs to set ENCKM = 1 to enable CKM. Note: Needs to be careful of the limitation of CPUCLK and SYSCLK. Needs to use SCKS[2:0] and CCKS to choose proper range of CPUCLK and SYSCLK to not exceed the limitation. CPUCLK ≤ 36MHz, SYSCLK ≤ 50MHz.

megawin Version: 1.00 273 Bit 1~0: OSCS[1:0], OSCin Source selection. OSCS[1:0] OSCin source Selection 0 0 IHRCO 0 1 ECKI 1 0 ILRCO 1 1 Reserved CKCON3: Clock Control Register 3 SFR Page = P SFR Address = 0x41 RESET = 0000-0000 7 6 5 4 3 2 1 0 WDTFS WDTFS FWKP WDTFS MCKD1 MCKD0 -- -- R/W R/W R/W R/W R/W R/W W W Bit 7~6: WDTCS1~0, WDT Clock Source selection [1:0]. WDTCS1~0 WDT Clock Source Bit 5: FWKP, MCU Fast wake up control. 0: Select MCU for normal wakeup time about 120us from power-down mode. 1: Select MCU for fast wakeup time about 30us from power-down mode. Bit 4: WDTFS. WDT overflow source selection. 0: Select WDT bit-8 overflow as WDT event source. 1: Select WDT bit-0 overflow as WDT event source. Bit 3~2: MCKD[1:0], MCK Divider Output selection. MCKD[1:0] MCKDO Frequency if MCK = 12MHz if MCK = 48MHz 0 0 MCKDO = MCK MCKDO = 12MHz MCKDO = 48MHz 0 1 MCKDO = MCK/2 MCKDO = 6MHz MCKDO = 24MHz 1 0 MCKDO = MCK/4 MCKDO = 3MHz MCKDO = 12MHz 1 1 MCKDO = MCK/8 MCKDO = 1.5MHz MCKDO = 6MHz CKCON4: Clock Control Register 4 SFR Page = P only SFR Address = 0x42 RESET = 0000-0000 7 6 5 4 3 2 1 0 RCSS2 RCSS1 RCSS0 RPCS2 RPCS1 RPCS0 RTCCS3 RTCCS2 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~5: RTC Clock Source selection [2:0] RCSS2, RCSS1, RCSS0 RTC Clock Selection 0 0 0 ECKI (P6.0) 0 0 1 ILRCO 0 1 0 WDTPS 0 1 1 WDTOF 1 0 0 SYSCLK 1 0 1 SYSCLK / 12 1 1 0 Reserved 1 1 1 Reserved

megawin Version: 1.00 274 CKCON5: Clock Control Register 5 SFR Page = P only SFR Address = 0x43 RESET = 0000-0000 7 6 5 4 3 2 1 0 W W W W W W R/W R/W Bit 0: CKMS0, CKM mode selection 0. 0: Select CKM operating for 8X mode. (96MHz) 1: Select CKM operating for 12X mode. (144MHz) PCON2: Power Control Register 2 SFR Page = P Only SFR Address = 0x44 POR = 0000-0101 7 6 5 4 3 2 1 0 AWBOD1 0 BO1S1 BO1S0 BO1RE EBOD1 BO0RE 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: AWBOD1, Awaked BOD1 in PD mode. 0: BOD1 is disabled in power-down mode. 1: BOD1 keeps operation in power-down mode. Bit 6: Reserved. Software must write “0” on this bit when PCON2 is written. Bit 5~4: BO1S[1:0]. Brown-Out detector 1 monitored level Selection. The initial values of these two bits are loaded from OR1.BO1S1O and OR1.BO1S0O. BO1S[1:0] BOD1 detecting level 0 0 2.0V 0 1 2.4V 1 0 3.7V 1 1 4.2V Bit 3: BO1RE, BOD1 Reset Enabled. 0: Disable BOD1 to trigger a system reset when BOF1 is set. 1: Enable BOD1 to trigger a system reset when BOF1 is set. Bit 2: EBOD1, Enable BOD1 that monitors VDD power dropped at a BO1S1~0 specified voltage level. 0: Disable BOD1 to slow down the chip power consumption. 1: Enable BOD1 to monitor VDD power dropped. Bit 1: BO0RE, BOD0 Reset Enabled. 0: Disable BOD0 to trigger a system reset when BOF0 is set. 1: Enable BOD0 to trigger a system reset when BOF0 is set (VDD meets 1.7V). Bit 0: Reserved. Software must write “1” on this bit when PCON2 is written. PCON3: Power Control Register 3 SFR Page = P Only SFR Address = 0x45 POR = 0000-0000 7 6 5 4 3 2 1 0 IVREN 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7: IVREN, Internal Voltage Reference Enable. 0: Disable on-chip IVR (1.4V). 1: Enable on-chip IVR (1.4V). Bit 6~0: Reserved. Software must write “0” on these bits when PCON3 is written.

megawin Version: 1.00 275 SPCON0: SFR Page Control 0 SFR Page = P Only SFR Address = 0x48 POR = 0000-0000 7 6 5 4 3 2 1 0 -- P6CTL P4CTL WRCTL -- CKCTL0 PWCTL1 PWCTL0 W R/W R/W R/W W R/W R/W R/W Bit 7: Reserved. Software must write “0” on this bit when SPCON is written. Bit 6: P6CTL. P6 SFR access Control. If P6CTL is set, it will disable the P6 SFR modified in Page 0~F. P6 in Page 0~F only keeps the SFR read function. But software always owns the modification capability in SFR Page P. Bit 5: P4CTL. P4 SFR access Control. If P4CTL is set, it will disable the P4 SFR modified in Page 0~F. P4 in Page 0~F only keeps the SFR read function. But software always owns the modification capability in SFR Page P. Bit 4: WRCTL. WDTCR SFR access Control. If WRCTL is set, it will disable the WDTCR SFR modified in Page 0~F. WDTCR in Page 0~F only keeps the SFR read function. But software always owns the modification capability in SFR Page P. Bit 2: CKCTL0. CKCON0 SFR access Control. If CKCTL0 is set, it will disable the CKCON0 SFR modified in Page 0~F. CKCON0 in Page 0~F only keeps the SFR read function. But software always owns the modification capability in SFR Page P. Bit 1: PWCTL1. PCON1 SFR access Control. If PWCTL1 is set, it will disable the PCON1 SFR modified in Page 0~F. PCON1 in Page 0~F only keeps the SFR read function. But software always owns the modification capability in SFR Page P. Bit 0: PWCTL0. PCON0 SFR access Control. If PWCTL0 is set, it will disable the PCON0 SFR modified in Page 0~F. PCON0 in Page 0~F only keeps the SFR read function. But software always owns the modification capability in SFR Page P.

megawin Version: 1.00 276 DCON0: Device Control 0 SFR Page = P Only SFR Address = 0x4C RESET = 100x-x011 7 6 5 4 3 2 1 0 HSE IAPO HSE1 -- -- IORCTL RSTIO OCDE R/W R/W W W W W R/W W Bit 7: HSE, High Speed operation Enable. 0: Select CPU running in lower speed mode (FCPUCLK ≤ 6MHz) which is slow down internal circuit to reduce power consumption. 1: Enable CPU full speed operation if FCPUCLK > 6MHz. Before select high frequency clock (> 6MHz) on CPUCLK, software must set HSE to switch internal circuit for high speed operation. Bit 6: IAPO, IAP function only. 0: Maintain IAP region to service IAP function and code execution. 1: Disable the code execution in IAP region and the region only service IAP function. Bit 5: HSE1, High Speed operation Enable 1. 0: No function. 1: Enable MCU for ultra-high speed operation. (FCPUCLK > 25MHz). It also needs to set HSE when use HSE1 = 1. Bit 4~3: Reserved. Software must write “0” on these bits when DCON0 is written. Bit 2: IORCTL, GPIO Reset Control. 0: Port 6 keeps reset condition for all reset events. 1: If this bit is set, Port 6 is only reset by POR/LVR/Ext Reset/BOR0/BOR1 (if BOR0/1 is enabled). Bit 1: RSTIO, RST function on I/O, 0: Select I/O pad function for P47. 1: Select I/O pad function for external reset input, RST. Bit 0: OCDE, OCD enable. 0: Disable OCD interface on P4.4 and P4.5 1: Enable OCD interface on P4.4 and P4.5. Due to MG82F6D17AS8 SOP8 not support OCD_ICE, it needs to disable OCD_SDA and OCD_SCL by firmware when using MG82F6D17AS8 SOP8.

megawin Version: 1.00 277 30. Auxiliary SFRs AUXR0: Auxiliary Register 0 SFR Page = 0~F SFR Address = 0xA1 RESET = 0000-0000 7 6 5 4 3 2 1 0 P60OC1 P60OC0 P60FD PBKF -- -- INT1H INT0H R/W R/W R/W R/W W W R/W R/W Bit 7~6: P6.0 function configured control bit 1 and 0. The two bits only act when internal RC oscillator (IHRCO or ILRCO) is selected for system clock source. In external clock input mode, P6.0 is the dedicated clock input pin. In internal oscillator condition, P6.0 provides the following selections for GPIO or clock source generator. When P60OC[1:0] index to non-P6.0 GPIO function, P6.0 will drive the on-chip RC oscillator output to provide the clock source for other devices. P60OC[1:0] P60 function I/O mode 00 P60 By P6M0.0 01 MCK By P6M0.0 10 MCK/2 By P6M0.0 11 MCK/4 By P6M0.0 Please refer Section “9 System Clock” to get the more detailed clock information. For clock-out on P6.0 function, it is recommended to set P6M0.0 to “1” which selects P6.0 as push-push output mode. Bit 5: P60FD, P6.0 Fast Driving. 0: P6.0 output with default driving. 1: P6.0 output with fast driving enabled. If P6.0 is configured to clock output, enable this bit when P6.0 output frequency is more than 12MHz at 5V application or more than 6MHz at 3V application. Bit 4: PBKF, PWM Break Flag. This bit is set by PWM break source enabled. If this flag is set, the enabled PWM channel 0~5 will be blocked and the output pins keep the original GPIO state. 0: There is no PWM Break event happened. It is only cleared by software. 1: There is a PWM Break event happened or software triggers a PWM Break. Bit 1: INT1H, INT1 High/Rising trigger enable. 0: Remain nINT1 triggered on low level or falling edge on nINT1 port pin. 1: Set nINT1 triggered on high level or rising edge on nINT1 port pin. Bit 0: INT0H, INT0 High/Rising trigger enable. 0: Remain nINT0 triggered on low level or falling edge on nINT0 port pin. 1: Set nINT0 triggered on high level or rising edge on nINT0 port pin. AUXR1: Auxiliary Control Register 1 SFR Page = 0~F SFR Address = 0xA2 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- CRCDS1 CRCDS0 -- -- -- DPS W W R/W R/W W W W R/W Bit 7~6: Reserved. Software must write “0” on these bits when AUXR1 is written. Bit 5~4: CRCDS1~0. CRC0 Data port Selection bit 1~0. Bit 3~1: Reserved. Software must write “0” on these bits when AUXR1 is written. Bit 0: DPS, DPTR select bit. Use to switch between DPTR0 and DPTR1. 0: Select DPTR0. 1: Select DPTR1. DPS Selected DPTR

megawin Version: 1.00 278 AUXR2: Auxiliary Register 2 SFR Page = 0~F SFR Address = 0xA3 RESET = 0000-0000 7 6 5 4 3 2 1 0 STAF STOF -- -- T1X12 T0X12 T1CKOE T0CKOE R/W R/W W W R/W R/W R/W R/W Bit 7: STAF, Start Flag detection of STWI (SID). 0: Clear by firmware by writing “0” on it. STAF might be held within MCU reset period, so needs to clear STAF in firmware initial. 1: Set by hardware to indicate the START condition occurred on STWI bus. Bit 6: STOF, Stop Flag detection of STWI (SID). 0: Clear by firmware by writing “0” on it. 1: Set by hardware to indicate the STOP condition occurred on STWI bus. STOF might be held within MCU reset period, so needs to clear STOF in firmware initial. Bit 5 ~ 4: Reserved. Software must write “0” on this bit when AUXR2 is written. Bit 3: T1X12, Timer 1 clock source selector while C/T=0. 0: Clear to select SYSCLK/12. 1: Set to select SYSCLK as the clock source. Bit 2: T0X12, Timer 1 clock source selector while C/T=0. 0: Clear to select SYSCLK/12. 1: Set to select SYSCLK as the clock source. Bit 1: T1CKOE, Timer 1 Clock Output Enable. 0: Disable Timer 1 clock output. 1: Enable Timer 1 clock output on T1CKO port pin. Bit 0: T0CKOE, Timer 0 Clock Output Enable. 0: Disable Timer 0 clock output. 1: Enable Timer 0 clock output on T0CKO port pin. AUXR3: Auxiliary Register 3 SFR Page = 0 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T0PS1 T0PS0 BPOC1 BPOC0 S0PS0 TWIPS1 TWIPS0 T0XL R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: T0PS1~0, Timer 0 Port pin Selection [1:0]. T0PS1~0 T0/T0CKO 00 P3.4 01 P4.4 10 P2.2 11 P1.7 Bit 5~4: BPOC1~0, Beeper output control bits. BPOC[1:0] P4.4 function I/O mode 00 P4.4 By P4M0.4 & P4M1.4 01 ILRCO/32 By P4M0.4 & P4M1.4 10 ILRCO/16 By P4M0.4 & P4M1.4 11 ILRCO/8 By P4M0.4 & P4M1.4 For beeper on P4.4 function, it is recommended to configure P4.4 as push-push output mode.

megawin Version: 1.00 279 Bit 3: S0PS0, Serial Port 0 pin Selection 0. (Add new S0PS1 at AUXR10.3) S0PS1~0 RXD0 TXD0 00 P3.0 P3.1 01 P4.4 P4.5 10 P3.1 P3.0 11 P1.7 P2.2 Bit 2~1: TWIPS1~0, TWI0/I2C0 Port pin Selection [1:0]. TWIPS1~0 TWI0_SCL TWI0_SDA 00 P3.1 P3.0 01 P6.0 P6.1 10 P3.0 P3.1 11 P2.2 P2.4 Bit 0: T0XL is the Timer 0 clock source selection bit. Please refer T0X12 for T0XL function definition. AUXR4: Auxiliary Register 4 SFR Page = 1 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 T2PS1 T2PS0 T1PS1 T1PS0 -- -- -- -- R/W R/W R/W R/W W W W W Bit 7~6: T2PS1~0, Timer 2 Port pin Selection [1:0]. T2PS1~0 T2/T2CKO T2EX 00 P1.0 P1.1 01 P3.0 P3.1 10 P6.0 P3.5 11 P4.5 P4.4 Bit 5~4: T1PS1~0, Timer 1 Port pin Selection [1:0]. T1PS1~0 T1/T1CKO 00 P3.5 01 P4.5 10 P1.7 11 P3.3 AUXR5: Auxiliary Register 5 SFR Page = 2 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 C0IC4S0 C0IC2S0 C0PPS1 C0PPS0 -- C0PS0 ECIPS0 C0COPS R/W R/W R/W R/W W R/W R/W R/W Bit 7: C0IC4S0, PCA0 Input Channel 4 input port pin Selection. C0IC4S0 CEX4 input Bit 6: C0IC2S0, PCA0 Input Channel 2 input port pin Selection. C1IC2S0 CEX2 input Bit 5: C0PPS1, {PWM2A, PWM2B} Port pin Selection 1. C0PPS1 PWM2A PWM2B 0 P6.0 P6.1 1 P3.4 P3.5

megawin Version: 1.00 280 Bit 4: C0PPS0, {PWM0A, PWM0B} Port pin Selection 0. C0PPS0 PWM0A PWM0B 0 P1.6 P1.7 1 P6.0 P6.1 Bit 3: Reserved. Bit 2: C0PS0, PCA0 Port pin Selection 0. C0PS0 CEX0 CEX2 CEX4 0 P2.2 P2.4 P1.7 1 P3.0 P2.4 P3.1 Bit 1: ECIPS0, PCA0 ECI Port pin Selection0. ECIPS0 ECI 0 P4.4 1 P1.6 Bit 0: C0COPS, PCA0 Clock Output (C0CKO) port pin Selection. C0COPS C0CKO 0 P4.7 1 P3.3 AUXR6: Auxiliary Register 6 SFR Page = 3 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 KBI4PS1 KBI4PS0 KBI6PS0 KBI2PS0 T3FCS T2FCS SnMIPS S0COPS R/W R/W R/W R/W R/W R/W R/W R/W Bit 7~6: KBI4PS1~0, KBI4~5 Port pin Selection [1:0]. KBI4PS1~0 KBI4 KBI5 00 P3.3 P1.5 01 P3.4 P3.5 10 P6.0 P6.1 11 P1.5 P3.3 Bit 5: KBI6PS0, KBI6~7 Port pin Selection 0. KBI6PS0 KBI6 KBI7 0 P1.6 P1.7 1 P3.0 P3.1 Bit 4: KBI2PS0, KBI2~3 Port pin Selection 0. KBI2PS0 KBI2 KBI3 0 P3.0 P3.1 1 P2.2 P2.4 Bit 3: T3FCS, Reserved for chip test. Bit 2: T2FCS, Reserved for chip test. Bit 1: SnMIPS, S0MI & S1MI Port pin Selection. SnMIPS S0MI S1MI 0 P1.6 P6.1 1 P3.3 P4.7 Bit 0: S0COPS, S0BRG Clock Output (S0CKO) port pin Selection. S0COPS S0CKO 0 P4.7 1 P3.3

megawin Version: 1.00 281 AUXR7: Auxiliary Register 7 SFR Page = 4 only SFR Address = 0xA4 RESET = 1100-0000 7 6 5 4 3 2 1 0 POE5 POE4 C0CKOE SPI0M0 -- -- -- -- R/W R/W R/W R/W W W W W Bit 7: POE5, PCA0 PWM5 main channel (PWM5O) output control. 0: Disable PWM5O output on port pin. 1: Enable PWM5O output on port pin. Default is enabled. Bit 6: POE4, PCA0 PWM4 main channel (PWM4O) output control. 0: Disable PWM4O output on port pin. 1: Enable PWM4O output on port pin. Default is enabled. Bit 5: C0CKOE, PCA0 clock output (C0CKO) enable. 0: Disable PCA0 clock output. 1: Enable PCA0 clock output with PCA0 base timer overflow rate/2. AUXR8: Auxiliary Register 8 SFR Page = 5 only SFR Address = 0xA4 RESET = 1100-0000 7 6 5 4 3 2 1 0 POE7 POE6 C0PPS2 -- KBI0PS0 S1COPS -- -- R/W R/W R/W W R/W R/W W W Bit 7: POE7, PCA0 PWM7 main channel (PWM7O) output control. 0: Disable PWM7O output on port pin. 1: Enable PWM7O output on port pin. Default is enabled. Bit 6: POE6, PCA0 PWM6 main channel (PWM6O) output control. 0: Disable PWM6O output on port pin. 1: Enable PWM6O output on port pin. Default is enabled. Bit 5: C0PPS2, {PWM6, PWM7} Port pin Selection 2. C0PPS2 PWM6 PWM7 0 P6.0 P6.1 1 P3.0 P3.1 Bit 3: KBI0PS0, KBI0~1 Port pin Selection 0. KBI0PS KBI0 KBI1 0 P1.0 P1.1 1 P4.7 P3.3 Bit 2: S1COPS, S1BRG Clock Output (S1CKO) port pin Selection. S1COPS S1CKO 0 P4.7 1 P6.1

megawin Version: 1.00 282 AUXR9: Auxiliary Register 9 SFR Page = 6 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- T1G1 T0G1 C0FDC1 C0FDC0 S1PS1 S1PS0 W W R/W R/W R/W R/W R/W R/W Bit 7~6: --. Bit 5: T1G1, Gating source selection of Timer 1. T1G1, T1GATE T1 Gate source Bit 4: T0G1, Gating source selection of Timer 0. T0G1, T0GATE T0 Gate source Bit 3~2: C0FDC1~0, C0FDCK Selection [1:0]. C0FDC1~0 C0FDCK Bit 1~0: S1PS1~0, Serial Port 1 pin Selection [1:0]. S1PS1~0 RXD1 TXD1 00 P1.0 P1.1 01 P6.0 P6.1 10 P4.4 P4.5 11 P3.4 P3.5 AUXR10: Auxiliary Register 10 SFR Page = 7 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 -- -- -- SPIPS0 S0PS1 -- TWICF PAA W W W R/W R/W W R/W R/W Bit 4: SPIPS0, SPI Port pin Selection 0. SPIPS0 nSS MOSI MISO SPICLK 0 P3.3 P1.5 P1.6 P1.7 1 P1.7 P3.5 P3.4 P3.3 Bit 1: TWICF, TWI0/I2C0 serial Clock input Filter. 0: Disable TWICF function. 1: Enable TWICF function. Bit 0: PAA, Pre-Assert Acknowledge. 0: Disable PAA function. 1: Enable PAA function on DMA transfer with TWI0/I2C0 master RX and slave TX/RX.

megawin Version: 1.00 283 AUXR11: Auxiliary Register 11 SFR Page = 8 only SFR Address = 0xA4 RESET = 0000-0000 7 6 5 4 3 2 1 0 P30AM -- -- -- -- -- C0M0 C0OFS R/W W W W W W R/W R/W Bit 1: C0M0, PCA0 Mode control 0. 0: Not support variable resolution on central aligned PWM. 1: Enable PCA0 to support variable resolution on central aligned PWM. To enable this function, the PCAE (PWMCR.7) also needs to be set. Bit 0: C0OFS, PCA0 overflow flag selection when C0M0 is enabled. 0: CF is set on the bottom of PWM cycle. 1: CF is set on the top of PWM cycle. SFRPI: SFR Page Index Register SFR Page = 0~F SFR Address = 0xAC RESET = xxxx-0000 7 6 5 4 3 2 1 0 -- -- -- -- IDX3 IDX2 IDX1 IDX0 W W W W R/W R/W R/W R/W Bit 7~4: Reserved. Software must write “0” on these bits when SFRPI is written. Bit 3~0: SFR Page Index. PIDX[3:0] Selected Page …… …… …… …… …… ……

megawin Version: 1.00 284 31. Hardware Option The MCU’s Hardware Option defines the device behavior which cannot be programmed or controlled by software. The hardware options can only be programmed by a Universal Programmer, the “Megawin 8051 Writer U1” or the “Megawin 8051 ICE Adapter ” (The ICE adapt er also supports ICP programm ing function. Refer Section “ 32.4 In-Chip-Programming Function”). After whole-chip erased, all the hardware options are left in “disabled” state and there is no ISP-memory and IAP-memory configured. The MG82F6D17 has the following Hardware Options: LOCK: : Enabled. Code dumped on a universal Writer or Programmer is locked to 0xFF for security. : Disabled. Not locked. ISP-memory Space: The ISP -memory space is specified by its starting address. And, its higher boundary is limited by the Flash end address, i.e., 0x3FFF. The following table lists the ISP space option in this chip. In default setting, MG82F6D17 ISP space is configured to 1 .5K that had been embedded Megawin proprietary COMBO ISP code to perform device firmware upgrade through Megawin 1-Line ISP protocol and COM port ISP . ISP-memory Size MG82F6D17 ISP Start Address 7.5K bytes 2200 7.0K bytes 2400 6.5K bytes 2600 6.0K bytes 2800 5.5K bytes 2A00 5.0K bytes 2C00 4.5K bytes 2E00 4.0K bytes 3000 3.5K bytes 3200 3.0K bytes 3400 2.5K bytes 3600 2.0K bytes 3800 1.5K bytes 3A00 1.0K bytes 3C00 0.5K bytes 3E00 No ISP Space -- HWBS: : Enabled. When powered up, MCU will boot from ISP-memory if ISP-memory is configured. : Disabled. MCU always boots from AP-memory. HWBS2: : Enabled. Not only power-up but also any reset will cause MCU to boot from ISP-memory if ISP-memory is configured. : Disabled. Where MCU boots from is determined by HWBS. IAP-memory Space: The I AP-memory space specifies the user defined IAP space. The IAP -memory Space can be configured by hardware option or MCU software by modifying IAPLB. In default, it is configured to 1 K bytes. BO1S1O, BO1S0O: ,: Select BOD1 to detect 2.0V. ,: Select BOD1 to detect 2.4V. ,: Select BOD1 to detect 3.7V. ,: Select BOD1 to detect 4.2V.

megawin Version: 1.00 285 BO0REO: : Enabled. BOD0 will trigger a RESET event to CPU on AP program start address. (1.7V) : Disabled. BOD0 can not trigger a RESET to CPU. BO1REO: : Disabled. BOD1 can not trigger a RESET to CPU. WRENO: : Enabled. Set WDTCR.WREN to enable a system reset function by WDTF. : Disabled. Clear WDTCR.WREN to disable the system reset function by WDTF. NSWDT: Non-Stopped WDT : Enabled. Set WDTCR.NSW to enable the WDT running in power down mode (watch mode). : Disabled. Clear WDTCR.NSW to disable the WDT running in power down mode (disable Watch mode). HWENW: Hardware loaded for “ENW” of WDTCR. : Enabled. Enable WDT and load the content of WRENO, NSWDT, HWWIDL and HWPS2~0 to WDTCR after power-on. : Disabled. WDT is not enabled automatically after power-on. HWWIDL, HWPS2, HWPS1, HWPS0: When HWENW is enabled, the content on these four fused bits will be loaded to WDTCR SFR after power-on. WDSFWP: : Enabled. The WDT SFRs, WREN, NSW, WIDL, PS2, PS1 and PS0 in WDTCR, will be write-protected. : Disabled. The WDT SFRs, WREN, NSW, WIDL, PS2, PS1 and PS0 in WDTCR, are free for writing of software.

megawin Version: 1.00 287 32.3. ICP and OCD Interface Circuit MG82F6D17 devices include an on-chip Megawin proprietary debug interface to allow In-Chip-Programming (ICP) and in-system On-Chip-Debugging (OCD) with the production part installed in the end application. The ICP and OCD share the same interface to use a clock signal (ICP_SCL/OCD_SCL) and a bi-directional data signal (ICP_SDA/OCD_SDA) to transfer information between the device and a host system. The ICP interface allows the ICP_SCL/ICP_SDA pins to be shared with user functions so that In- Chip Flash Programming function could be performed. This is practicable because ICP communication is performed when the device is in the halt state, where the on-chip peripherals and user software are stalled. In this halted state, the ICP interface can safely ‘borrow’ the ICP_SCL (P4.4) and ICP_SDA (P4.5) pins. In most applications, external resistors are required to isolate ICP interface traffic from the user application. A typical isolation configuration is shown in Figure 32– It is strongly recommended to build the ICP interface circuit on target system. It will reserve the whole capability for software programming and device options configured. After power-on, the P4.4 and P4.5 of MG82F6D17 are configured to OCD_SCL/OCD_SDA for in-system On-Chip-Debugging function. This is possible because OCD communication is typically performed when the CPU is in the halt state, where the user software is stalled. In this halted state, the OCD interface can safely ‘use’ the OCD_SCL (P4.4) and OCD_SDA (P4.5) pins. As mentioned ICP interface isolation in Figure 32–3, external resistors are required to isolate OCD interface traffic from the user application. If user gives up the OCD function, software can configure the OCD_SCL and OCD_SDA to port pins: P4.4 and P4.5 by clearing OCDE on bit 0 of DCON0. When user would like to regain the OCD function, user can predict an event that triggers the software to switch the P4.4 and P4.5 back to OCD_SCL and OCD_SDA by setting OCED as “1”. Or “Erase” the on-chip flash by ICP which cleans the user software to stop the port pins switching. However, for the MG82F6D17AS8 SOP8 package it does not support ICP due to the pin limitation. For SOP8 package, it is necessary to use other package within code development phase. Once the code has been done and then use the ISP to download the code for physical evaluation. Figure 32–3. ICP and OCD Interface Circuit OCD_SCL MCU RST OCD_SDA RESET Input Input 1 Output 1 Input 2 Output 2 OCD ICE Adaptor or Megawin Writer 4.7KΩ 4.7KΩ 4.7KΩ Target System

megawin Version: 1.00 288 32.4. In-Chip-Programming Function The ICP, like the traditional parallel programming method, can be used to program anywhere in the MCU, including the Flash and MCU’s Hardware Option. And, owing to its dedicated serial programming interface (via the On-Chip Debug path), the ICP can update the MCU without removing the MCU chip from the actual end product, just like the ISP does. The proprietary 6-pin “Megawin 8051 ICE Adapter” can support the In-Circuit Programming of MG82F6D17. “Megawin 8051 ICE Adapter” has the in-system storage to store the user program code and device options. So, the tools can perform a portable and stand-alone programming without a host on-line, such as connecting the tool to PC. Following lists the features of the ICP function:  No need to have a loader program pre-programmed in the target MCU.  Dedicated serial interface; no port pin is occupied.  The target MCU needn’t be in running state; it just needs to be powered.  Capable of portable and stand-alone working without host’s intervention. The above valuable features make the ICP function very friendly to the user. Particularly, it is capable of stand-alone working after the programming data is downloaded. This is especially useful in the field without a PC. The system diagrams of the ICP function for the stand-alone programming are shown in Figure 32–4. Only five pins are used for the ICP interface: the SDA line and SCL line function as serial data and serial clock, respectively, to transmit the programming data from the 6-pin “Megawin 8051 ICE Adapter” to the target MCU; the RST line to halt the MCU, and the VCC & GND are the power supply entry of the 6-pin “Megawin 8051 ICE Adapter” for portable programming application. The USB connector can be directly plugged into the PC’s USB port to download the programming data from PC to the 6-pin “Megawin 8051 ICE Adapter”. Figure 32–4. Stand-alone programming via ICP Note: For MG82F6D17AS8 SOP8, does not support ICP, reference “32.3 ICP and OCD Interface Circuit” for detail. "Megawin 8051 OCD ICE" Target System ICP & OCD InterfaceMCU (less than 20cm) MEGAWIN MAKE YOU WIN

8051 ICE Adapter

P3.0 SCL VCC SDA GND RST USB OCD_SCL VDD OCD_SDA VSS RST N.C. SCL VCC SDA GND RST Program code download path START button: for code programming

megawin Version: 1.00 289 32.5. On-Chip-Debug Function The MG82F6D17 is equipped with a Megawin proprietary On-Chip Debug (OCD) interface for In-Circuit Emulator (ICE). The OCD interface provides on-chip and in-system non-intrusive debugging without any target resource occupied. Several operations necessary for an ICE are supported, such as Reset, Run, Stop, Step, Run to Cursor and Breakpoint Setting. Using the OCD technology, Megawin provides the “Megawin 8051 OCD ICE” for the user, as shown in Figure 32–5. The user has no need to prepare any development board during developing, or the socket adapter used in the traditional ICE probe. All the thing the user needs to do is to reserve a 6-pin connector on the system for the dedicated OCD interface: P3.0, RST, VCC, OCD_SDA, OCD_SCL and GND as shown in Figure 32–5. In addition, the most powerful feature is that it can directly connect the user ’s target system to the Keil 8051 IDE software for debugging, which directly utilizes the Keil IDE’s dScope-Debugger function. Of course, all the advantages are based on your using Keil 8051 IDE software. Note: “Keil” is the trade mark of “Keil Elektronik GmbH and Keil Software, Inc.”.  Megawin proprietary OCD (On-Chip-Debug) technology  On-chip & in-system real-time debugging  5-pin dedicated serial interface for OCD, no target resource occupied  Directly linked to the debugger function of the Keil 8051 IDE Software  USB connection between target and host (PC)  Helpful debug actions: Reset, Run, Stop, Step and Run to Cursor  Programmable breakpoints, up to 4 breakpoints can be inserted simultaneously  Several debug-helpful windows: Register/Disassembly/Watch/Memory Windows  Source-level (Assembly or C-language) debugging capability Figure 32–5. System Diagram for the ICE Function Note: 1. For more detailed information about the OCD ICE, please feel free to contact Megawin. 2. For MG82F6D17AS8 SOP8, does not support OCD ICE, reference “32.3 ICP and OCD Interface Circuit” for detail. "Megawin 8051 OCD ICE" Keil 8051 IDE PC Target System ICP & OCD InterfaceMCU (less than 20cm) MEGAWIN MAKE YOU WIN P3.0 SCL VCC SDA GND RST USB OCD_SCL VDD OCD_SDA VSS RST N.C. SCL VCC SDA GND RST

megawin Version: 1.00 290 33. Electrical Characteristics 33.1. Absolute Maximum Rating Parameter Rating Unit Ambient temperature under bias -40 ~ +105 °C Storage temperature -65 ~ + 150 °C Voltage on any Port I/O Pin or RST with respect to VSS -0.5 ~ VDD + 0.5 V Voltage on VDD with respect to VSS -0.5 ~ +6.0 V Maximum total current through VDD and VSS 200 mA Maximum output current sunk by any Port pin 40 mA *Note: stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

megawin Version: 1.00 291 33.2. DC Characteristics VDD = 5.0V±10%, VSS = 0V, TA = 25 °C and execute NOP for each machine cycle, unless otherwise specified Symbol Parameter Test Condition Limits Unit min typ max Input/ Output Characteristics VIH1 Input High voltage (All I/O Ports) Except P6.0, P6.1 0.6 VDD VIH2 Input High voltage (RST, P6.0, P6.1) 0.75 VDD VIL1 Input Low voltage (All I/O Ports) Except P6.0, P6.1 0.15 VDD VIL2 Input Low voltage (RST, P6.0, P6.1) 0.2 VDD IIH Input High Leakage current (All I/O Ports) VPIN = VDD 0 ±1 uA IIL1 Logic 0 input current (P3 in quasi-mode) VPIN = 0.4V -20 -30 uA IIL2 Logic 0 input current (All Input only or open-drain Ports) VPIN = 0.4V 0 -1 uA IH2L Logic 1 to 0 input transition current (P3 in quasi-mode) (2) VPIN =1.8V -300 -450 uA IOH1 Output High current (P3 in quasi-Mode) VDD=5V; VPIN =2.4V -180 -260 uA VDD=3.3V; VPIN =2.4V -50 -80 uA VDD=1.8V; VPIN =1.4V -10 -15 uA IOH2 Output High current (All push-pull output ports) VDD=5V; VPIN =2.4V -25 -34 mA VDD=3.3V; VPIN =2.4V -8 -11 mA VDD=1.8V; VPIN =1.4V -2 -2.6 mA IOH3 Output High current (All push-pull output ports on low driving strength, except RST Pin) VDD=5V; VPIN =2.4V -8 -13.6 mA VDD=3.3V; VPIN =2.4V -3 -4.6 mA VDD=1.8V; VPIN =1.4V 0.7 -1.1 mA IOL1 Output Low current (All I/O Ports) VDD=5V; VPIN =0.4V 18 24 mA VDD=3.3V; VPIN =0.4V 14 17 mA VDD=1.8V; VPIN =0.4V 6 8 mA IOL1 Output Low current (All push-pull output ports on low driving strength, except RST Pin) VDD=5V; VPIN =0.4V 1.8 3.1 mA VDD=3.3V; VPIN =0.4V 1.2 2.2 mA VDD=1.8V; VPIN =0.4V 0.55 1.1 mA RRST Internal reset pull-down resistance VDD=5V 125 Kohm VDD=3.3V 207 Kohm VDD=2.1V 396 Kohm Power Consumption IOP1 Normal mode operating current SYSCLK = 32MHz @ IHRCO with PLL 6.5 mA IOP2 SYSCLK = 24MHz @ IHRCO with PLL 5.7 mA IOP3 SYSCLK = 12MHz @ IHRCO 3.3 mA IOP4 SYSCLK = 12MHz @ IHRCO, VDD = 5V with ADC 400K sps 5.8 mA IOP5 SYSCLK = 12MHz @ IHRCO, VDD = 3.3V with ADC 400K sps 5.3 mA IOP6 SYSCLK = 24MHz @ IHRCO with PLL, VDD = 5V with ADC 800K sps 8.3 mA IOPS1 Slow mode operating current SYSCLK = 12MHz/128 @ IHRCO 0.6 mA IIDLE1 Idle mode operating current SYSCLK = 12MHz @ IHRCO 1.1 mA IIDLE2 SYSCLK = 12MHz/128 @ IHRCO 0.45 mA IIDLE3 SYSCLK = 32KHz @ ILRCO 50 uA

megawin Version: 1.00 292 ISUB1 Sub-clock mode operating current SYSCLK = 32KHz @ ILRCO, BOD1 disabled 65 uA ISUB2 SYSCLK = 32KHz/128 @ ILRCO, BOD1 disabled 60 uA IWAT Watch mode operating current WDT = 32KHz @ ILRCO in PD mode 5 uA IMON1 Monitor Mode operating current BOD1 enabled in PD mode 10 uA IRTC1 RTC Mode operating current RTC operating in PD mode, VDD = 5.0V 4.5 uA IPD1 Power down mode current 2.5 uA BOD0/BOD1 Characteristics VBOD0 BOD0 detection level TA = -40°C to +105°C 1.7 V VBOD10 BOD1 detection level for 2.0V TA = -40°C to +105°C 2.0 V VBOD10 BOD1 detection level for 2.4V TA = -40°C to +105°C 2.37 V VBOD11 BOD1 detection level for 3.7V TA = -40°C to +105°C 3.7 V VBOD11 BOD1 detection level for 4.2V TA = -40°C to +105°C 4.2 V IBOD1 BOD1 Power Consumption TA = +25°C, VDD=5.0V 6.5 uA TA = +25°C, VDD=3.3V 5 Operating Condition VPSR Power-on Slop Rate TA = -40°C to +85°C 0.05 V/ms VPOR1 Power-on Reset Valid Voltage TA = -40°C to +85°C 0.1 V VOP1 CPU Operating Speed 0-36MHz TA = -40°C to +105°C 2.7 5.5 V VOP2 CPU Operating Speed 0-24MHz TA = -40°C to +105°C 2.2 5.5 V VOP3 CPU Operating Speed 0-12MHz TA = -40°C to +105°C 1.8 5.5 V (1) Data based on characterization results, not tested in production. (2) I/O under Quasi-Bidirectional mode, when input voltage High transfer to Low and across the threshold voltage, the internal “Weak” pull up will be turn off. IH2L indicates the current near the threshold voltage. Please reference “Figure 14–1. Port 3 Quasi-Bidirectional I/O”. (3) All current flowing into the chip has a positive value, and current flowing out of the chip has negative value.

megawin Version: 1.00 293 33.3. IHRCO Characteristics Parameter Test Condition Limits Unit min typ max Supply Voltage 1.8 5.5 V IHRCO Frequency TA = +25°C, AFS = 0 12 MHz TA = +25°C, AFS = 1 11.059 MHz IHRCO Frequency Deviation (factory calibrated) IHRCO Start-up Time TA = -40°C to +105°C 32(1) us IHRCO Power Consumption TA = +25°C, VDD=5.0V 350 (1) uA (1) Data based on characterization results, not tested in production. 33.4. ILRCO Characteristics Parameter Test Condition Limits Unit min typ max Supply Voltage 1.8 5.5 V ILRCO Frequency TA = +25°C 32 KHz ILRCO Frequency Deviation TA = +25°C -8(1) +8(1) % (1) Data based on characterization results, not tested in production. 33.5. CKM Characteristics Parameter Test Condition Limits Unit min typ max Supply Voltage TA = -40°C to +105°C 2.2 5.5 V Clock Input Range TA = -40°C to +105°C 4.5(1) 6.5(1) MHz CKM Start-up Time TA = -40°C to +105°C 30(2) 100(2) us CKM Power Consumption TA = +25°C, VDD=5.0V, CKM = 96MHz 350 uA TA = +25°C, VDD=5.0V, CKM = 144MHz 450 (1) Data guaranteed by design, not tested in production. (2) Data based on characterization results, not tested in production. 33.6. Flash Characteristics Parameter Test Condition Limits Unit min typ max Supply Voltage TA = -40°C to +105°C 1.8 5.5 V Flash Write (Erase/Program) Voltage TA = -40°C to +105°C 1.8 5.5 V Flash Erase/Program Cycle TA = -40°C to +105°C 20,000 times Flash Data Retention TA = +25°C 100 year

megawin Version: 1.00 294 33.7. ADC Characteristics VDD=5.0V, TA= -40°C ~ +85°C unless otherwise specified Parameter Test Condition Limits Unit min typ max Supply Range Supply Voltage 2.4 5.5 V DC Accuracy Resolution 12 bits Integral Nonlinearity VDD ≥ 4 V, 800K sps -3.5 +3.5 LSB VDD = 2.4V~5.5V, 400K sps -3.2 +3 LSB Differential Nonlinearity VDD ≥ 4 V, 800K sps -3 +3 LSB VDD = 2.4V~5.5V, 400K sps -2 +2 Offset Error VDD= 2.4V~5.5V +6 +10 LSB Conversion Rate SAR Conversion Clock 24 MHz Conversion Time in SAR Clocks 30 clocks Conversion Rate VDDA >=4.0 800 K sps VDDA >=2.7 533 VDDA >=2.4 400 Analog Inputs VADC Input Voltage Range Single Ended (AIN+ – GND) 0 VDD V Input Capacitance 9.17 10.58 pF Input Sampling switch resistance note1 VDD = 5V 714 Ω VDD = 4.2V 857 Ω VDD = 3.3V 968 Ω VDD = 2.7V 1050 Ω Switch Channel Stable Time Switch from VDD to Pulldown R CH0(VDD)→CH1(51K Pulldown) 4.9 us CH0(VDD)→CH1(10K Pulldown) 0.8 Switch from GND to Pullup R CH0(GND)→CH1(51K Pullup) 5.2 CH0(GND)→CH1(10K Pullup) 1.4 Switch from VDD to resistor divider (VDD/2) CH0(VDD)→CH1(VDD/2，51K resistor divider) 4.3 Switch from VDD to resistor divider (VDD/2) CH0(GND)→CH1(VDD/2，10K resistor divider) 0.7 Switch from GND to resistor divider (VDD/2) CH0(GND)→CH1(VDD/2，51K resistor divider) 4.1 Switch from GND to resistor divider (VDD/2) CH0(GND)→CH1(VDD/2，10K resistor divider) 0.6 Power Consumption Power Supply Current mA ADPS<1:0>=01 2.2 2.8 ADPS<1:0>=11 2 2.5 Note1: Data guaranteed by design, not tested in production.

megawin Version: 1.00 295 33.8. IVR Characteristics VDD=5.0V±10%, VSS=0V, TA =-40°C to +105°C, CLOAD=4.7upF/0.1ohm-ESR unless otherwise specified Parameter Test Condition Limits Unit Min. Typ. Max. Supply Range Supply Voltage 2.4 5.0 5.5 V Operation Current Normal Power State 43 67 uA Low Power State 0.1 uA DC Accuracy Output Supply Voltage -40°C ~ +85°C 1.37 1.4 1.43 V Spread over the temperature range VDD = 3.3V±10mV 13 mV 33.9. Serial Port Timing Characteristics VDD = 5.0V±10%, VSS = 0V, TA = -40°C to +105°C, unless otherwise specified Symbol Parameter URM0X3 = 0 URM0X3 = 1 Unit Min. Max Min. Max tXLXL Serial Port Clock Cycle Time 12T 4T TSYSCLK tQVXH Output Data Setup to Clock Rising Edge 10T-20 2T-20 ns tXHQX Output Data Hold after Clock Rising Edge T-10 T-10 ns tXHDX Input Data Hold after Clock Rising Edge 5 5 ns tXHDV Clock Rising Edge to Input Data Valid 2T-10 2T-10 ns Figure 33–1. Shift Register Mode Timing Waveform VALID VALID VALID VALID VALID VALID VALID VALID 1 2 3 4 5 6 70 tXHQX SET RI SET TI WRITE TO SBUF OUTPUT DATA CLEAR RI INPUT DATA CLOCK tXHDX tXLXL tQVXH tXHDV

megawin Version: 1.00 298 34. Instruction Set Table 34–1. Instruction Set MNEMONIC DESCRIPTION BYTE EXECUTION Cycles DATA TRASFER MOV A,Rn Move register to Acc 1 1 MOV A,direct Move direct byte o Acc 2 2 MOV A,@Ri Move indirect RAM to Acc 1 2 MOV A,#data Move immediate data to Acc 2 2 MOV Rn,A Move Acc to register 1 2 MOV Rn,direct Move direct byte to register 2 4 MOV Rn,#data Move immediate data to register 2 2 MOV direct,A Move Acc to direct byte 2 3 MOV direct,Rn Move register to direct byte 2 3 MOV direct,direct Move direct byte to direct byte 3 4 MOV direct,@Ri Move indirect RAM to direct byte 2 4 MOV direct,#data Move immediate data to direct byte 3 3 MOV @Ri,A Move Acc to indirect RAM 1 3 MOV @Ri,direct Move direct byte to indirect RAM 2 3 MOV @Ri,#data Move immediate data to indirect RAM 2 3 MOV DPTR,#data16 Load DPTR with a 16-bit constant 3 3 MOVC A,@A+DPTR Move code byte relative to DPTR to Acc 1 4 MOVC A,@A+PC Move code byte relative to PC to Acc 1 4 MOVX A,@Ri Move on-chip auxiliary RAM(8-bit address) to Acc 1 3 MOVX A,@DPTR Move on-chip auxiliary RAM(16-bit address) to Acc 1 3 MOVX @Ri,A Move Acc to on-chip auxiliary RAM(8-bit address) 1 3 MOVX @DPTR,A Move Acc to on-chip auxiliary RAM(16-bit address) 1 3 MOVX A,@Ri Move external RAM(8-bit address) to Acc 1 not support MOVX A,@DPTR Move external RAM(16-bit address) to Acc 1 not support MOVX @Ri,A Move Acc to external RAM(8-bit address) 1 not support MOVX @DPTR,A Move Acc to external RAM(16-bit address) 1 not support PUSH direct Push direct byte onto Stack 2 4 POP direct Pop direct byte from Stack 2 3 XCH A,Rn Exchange register with Acc 1 3 XCH A,direct Exchange direct byte with Acc 2 4 XCH A,@Ri Exchange indirect RAM with Acc 1 4 XCHD A,@Ri Exchange low-order digit indirect RAM with Acc 1 4 ARITHEMATIC OPERATIONS ADD A,Rn Add register to Acc 1 2 ADD A,direct Add direct byte to Acc 2 3 ADD A,@Ri Add indirect RAM to Acc 1 3 ADD A,#data Add immediate data to Acc 2 2 ADDC A,Rn Add register to Acc with Carry 1 2 ADDC A,direct Add direct byte to Acc with Carry 2 3 ADDC A,@Ri Add indirect RAM to Acc with Carry 1 3 ADDC A,#data Add immediate data to Acc with Carry 2 2 SUBB A,Rn Subtract register from Acc with borrow 1 2 SUBB A,direct Subtract direct byte from Acc with borrow 2 3 SUBB A,@Ri Subtract indirect RAM from Acc with borrow 1 3

megawin Version: 1.00 299 MNEMONIC DESCRIPTION BYTE EXECUTION Cycles SUBB A,#data Subtract immediate data from Acc with borrow 2 2 INC A Increment Acc 1 2 INC Rn Increment register 1 3 INC direct Increment direct byte 2 4 INC @Ri Increment indirect RAM 1 4 DEC A Decrement Acc 1 2 DEC Rn Decrement register 1 3 DEC direct Decrement direct byte 2 4 DEC @Ri Decrement indirect RAM 1 4 INC DPTR Increment DPTR 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 5 DA A Decimal Adjust Acc 1 4 LOGIC OPERATION ANL A,Rn AND register to Acc 1 2 ANL A,direct AND direct byte to Acc 2 3 ANL A,@Ri AND indirect RAM to Acc 1 3 ANL A,#data AND immediate data to Acc 2 2 ANL direct,A AND Acc to direct byte 2 4 ANL direct,#data AND immediate data to direct byte 3 4 ORL A,Rn OR register to Acc 1 2 ORL A,direct OR direct byte to Acc 2 3 ORL A,@Ri OR indirect RAM to Acc 1 3 ORL A,#data OR immediate data to Acc 2 2 ORL direct,A OR Acc to direct byte 2 4 ORL direct,#data OR immediate data to direct byte 3 4 XRL A,Rn Exclusive-OR register to Acc 1 2 XRL A,direct Exclusive-OR direct byte to Acc 2 3 XRL A,@Ri Exclusive-OR indirect RAM to Acc 1 3 XRL A,#data Exclusive-OR immediate data to Acc 2 2 XRL direct,A Exclusive-OR Acc to direct byte 2 4 XRL direct,#data Exclusive-OR immediate data to direct byte 3 4 CLR A Clear Acc 1 1 CPL A Complement Acc 1 2 RL A Rotate Acc Left 1 1 RLC A Rotate Acc Left through the Carry 1 1 RR A Rotate Acc Right 1 1 RRC A Rotate Acc Right through the Carry 1 1 SWAP A Swap nibbles within the Acc 1 1 BOOLEAN VARIABLE MANIPULATION CLR C Clear Carry 1 1 CLR bit Clear direct bit 2 4 SETB C Set Carry 1 1 SETB bit Set direct bit 2 4 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 4 ANL C,bit AND direct bit to Carry 2 3

megawin Version: 1.00 300 MNEMONIC DESCRIPTION BYTE EXECUTION Cycles ANL C,/bit AND complement of direct bit to Carry 2 3 ORL C,bit OR direct bit to Carry 2 3 ORL C,/bit OR complement of direct bit to Carry 2 3 MOV C,bit Move direct bit to Carry 2 3 MOV bit,C Move Carry to direct bit 2 4 BOOLEAN VARIABLE MANIPULATION JC rel Jump if Carry is set 2 3 JNC rel Jump if Carry not set 2 3 JB bit,rel Jump if direct bit is set 3 4 JNB bit,rel Jump if direct bit not set 3 4 JBC bit,rel Jump if direct bit is set and then clear bit 3 5 PROAGRAM BRACHING ACALL addr11 Absolute subroutine call 2 6 LCALL addr16 Long subroutine call 3 6 RET Return from subroutine 1 4 RETI Return from interrupt subroutine 1 4 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump 2 3 JMP @A+DPTR Jump indirect relative to DPTR 1 3 JZ rel Jump if Acc is zero 2 3 JNZ rel Jump if Acc not zero 2 3 CJNE A,direct,rel Compare direct byte to Acc and jump if not equal 3 5 CJNE A,#data,rel Compare immediate data to Acc and jump if not equal 3 4 CJNE Rn,#data,rel Compare immediate data to register and jump if not equal 3 4 CJNE @Ri,#data,rel Compare immediate data to indirect RAM and jump if not equal 3 5 DJNZ Rn,rel Decrement register and jump if not equal 2 4 DJNZ direct,rel Decrement direct byte and jump if not equal 3 5 NOP No Operation 1 1

megawin Version: 1.00 301 35. Package Dimension 35.1. SSOP-20(150 mil) Dimension Figure 35-1. SSOP-20 (150 mil) Package Dimension Unit mm inch e 0.635 BASIC 0.025 BASIC L1 1.041 BASIC 0.040 BASIC

megawin Version: 1.00 302 35.2. TSSOP-20(173 mil) Dimension Figure 35-2. TSSOP-20 6.5 x 4.4mm, 0.65mm pitch Package Dimension TSSOP-20 Unit mm inch E 6.40 BSC 0.251 BSC e 0.65 BSC 0.025 BSC L1 1.00 REF 0.039 REF

megawin Version: 1.00 303 35.3. QFN-20 (3x3x0.55mm) Package Dimension Figure 35-3. QFN-20 (3x3 x 0.55mm ) Package Dimension Unit mm inch JEDEC MO-220 MO-220 PKG WQFN(X319) WQFN(X319) A3 0.150 REF. 0.005 REF. D 3.00 BSC 0.11 BSC E 3.00 BSC 0.11 BSC e 0.40 BSC 0.015 BSC

megawin Version: 1.00 304 35.4. SOP-8 (150mil) Package Dimension Figure 35-4. SOP-8 (150 mil) Package Dimension Unit mm inch Symbols Min. Max. Min. Max. A 1.346 1.752 0.052 0.068 A1 0.101 0.254 0.003 0.010 A2 1.346 1.498 0.052 0.058 D 4.800 4.978 0.188 0.195 E 3.810 3.987 0.150 0.156 H 5.791 6.197 0.227 0.243 L 0.406 1.270 0.015 0.050 ɵ 0° 8° 0 8

megawin Version: 1.00 305 36. Revision History Table 36–1. Revision History Rev Descriptions Date V0.35T Initial version preliminary released 2019/03/18 V0.36T 1. Modified example of ADC Channel Scan Mode by DMA 2. Add IVR Characteristics 3. Fixed ADCFG0 Bit7~5 table description 4. Modified S0BRG description 2019/04/08 V0.37T 1. Modified ADC DMA description 2. Removed P6FDC, P6DC0 3. Add BME6 description 4. Modified DBSD[1:0] to DBSD 5. Modified CKMI output maximum frequency from 96MHz to 144MHz 6. Modified electrical characteristics 7. Modified ILRCO tolerance 8. Fixed error in SFR table, EPCnH to ECAPnH and EPCnL to ECAPnL 9. Modified HSE, HSE1 description 10. Added description on C0M0 11. Modified STOF, STAF description 2019/05/07 V0.38 1. Added SOP8 Package, and add ICP limitation description for SOP8 2019/09/03 V1.00 1. Added Page information of each SFR in Table 3-1 2. Modify description of bit SBF0 and TXER0 3. Modify section 32.3 OCD description, to change the PCON3 to DCON0. 4. Removed ADC AZEN description. 5. Modified T2MS0 and T3MS0 table 6. Removed AC0 description in Chapter 27. 7. Added ADCWI, SMPF in ADC interrupt source and CCFn (n=6~7) in PCA0 interrupt source in interrupt Table 15-1 and Table 15-2 8. Modified AIN3 pin number in ADC Block diagram 9. Add how to read IVR pre- stored ADC value(Section 27.2) and how to improve ADC accuracy (Section 26.2.11) 10. Fixed typo in CAPNn option “0” from positive to negative. 2021/04/12

megawin Version: 1.00 306 37. Disclaimers Herein, Megawin stands for “Megawin Technology Co., Ltd.” Life Support — This product is not designed for use in medical, life-saving or life-sustaining applications, or systems where malfunction of this product can reasonably be expected to result in personal injury. Customers using or selling this product for use in such applications do so at their own risk and agree to fully indemnify Megawin for any damages resulting from such improper use or sale. Right to Make Changes — Megawin reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in mass produc tion, relevant changes will be communicated via an Engineering Change Notification (ECN).