MG65M513

Megawin Technology Co.,...

42 Programmable GPIO

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Version: 1.10 笙泉科技股份有限公司 Megawin Technology Co., Ltd. MG65M513 Data Sheet 8-Bit Micro-Controller with 116 dots LCD driver and IAP function Version 1.10 This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 1/31

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1 Features

 Single Chip 8-bit CPU  Memory  Program MTP ROM : 8K Bytes  Data RAM : 128 Bytes  LCD display RAM : 16 Bytes  Operating voltage: 1.8V to 3.6V  42 Programmable GPIO  High sink current output  Shared input or output pins:  Input/output pins P0[4:7]  Input pins P0[0:3] / ICP interface  Quasi-bi-directional IO pins P1[0:4] / SEG24 ~ SEG28  Output pins P2[0:7] / SEG16 ~ SEG23  LCD driver output  29 segment, 4 common  1/4 duty 1/3 bias driving mode  Watchdog timer built-in  Two re-loadable 8-bit timers  HALT mode and STOP mode for power saving  Build-in dual oscillation circuit:  RC type main oscillator  X32 for sub-oscillator  Dual clock operation  Build-in low voltage detectors (typical voltage: below 2.1V) and low voltage reset (typical voltage: below 1.8V)

1.1 Application Field

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2 General Description

MG65M513 is a cost effective, high performance 8-bit micro-controller of MEGAWIN. It integrates an 8-bit CPU core, ROM, RAM, timers, LCD driver, I/O ports and system control circuits into a single chip. The MG65M513 provides a build-in oscillator as clock source. It is suitable for general LCD controller, hand-held game, toy controllers, and other products. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 5/31

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3 Pin Configurations

3.1 Pad Assignment

10 11 12 14 1513 16 17 18 19 20 21 22 23 24 25 26 SEG12 SEG11 SEG17 SEG18 SEG15 SEG19 SEG13 SEG16 SEG14 SEG10 SEG9 SEG8 SEG20 SEG21 SEG7 SEG6 SEG 5 COM 3 COM 0 COM 2 SEG 0 COM 1 SEG 1 SEG 2 SEG 3 SEG 4 P0.1 / SCK P0.0 / CMD_b P0.2 / SDA P0.4 P0.5 P0.3 P0.6 P0.7 VDD HSO VSS /RES 3940 OSCI X32I SEG22 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 44 43 X32O Figure 3-1 MG65M513AH Pad Assignment This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 6/31

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3.2 Package Instruction

P0.0/CMD_b P0.1/SCK SEG27 P0.2/SDA SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 P0.3 P0.4 P0.5 P0.6 P0.7 VDD HSO VSS /RES MG65M513 LQFP 48 Figure 3-2 MG65M513AD48 Pin Assignment This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 7/31

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3.3 Pin Description

1 OSCI I RC oscillator input pin. 2,3 X32O, X32I B 32.768KHz crystal oscillator pins. 4 ~ 8 SEG28 ~ SEG24 B LCD segment signal output pins. SEG28~SEG24 pads share with P1 [4:0] Quasi-bi-directional I/O pin. 9 ~ 16 SEG23 ~ SEG16 O LCD segment signal output pins. SEG23~SEG16 pads share with P2 [7:0] output pin. 17 ~ 24 SEG15 ~ SEG8 O LCD segment signals output pins. 25 ~ 32 SEG7 ~ SEG0 O LCD segment signals output pins. 33 ~ 36 COM0 ~ COM3 O LCD common signals output pins. 37 P0.0/CMD_b I Input pin with interrupt function. Port0.0 pad shares with ICP interface CMD_b. 38 P0.1/SCK I Input pin with interrupt function. Port0.1 pad shares with ICP interface SCK. 39 P0.2/SDA I Input pin with interrupt function. Port0.2 pad shares with ICP interface SDA. 40 P0.3 I Input pin with interrupt function. 41 ~ 44 P0.4 ~ P0.7 B Programmable I/O ports with interrupt function.

45 VDD P Positive power pins (need to connect together)

46 HSO O Direct sink (sink current: 250mA) for high light LED. Default value is high after reset.

47 VSS P Ground pins (need to connect together)

48 /RES I System reset pin (low active). Note: In the “Type” field, “I” means input only. “O” means output only. “B” means bi-direction. “P” means Power, “G” means Ground. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 8/31

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4 Block Diagram

(HF ROSC/ 32K OSC) I / O SRAM / Register MTP LVR HSO LCD Driver X32O X32I OSCI /RES VDD GND HSO P0.0 ~ P0.7 COM0 ~ 3 SEG 0~ SEG28 (P1.0 ~ P1.4) (P2.0 ~ P2.7) Figure 4-1 Block Diagram This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 9/31

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5 Function Description

5.1 Registers

A Y X P PCH PCL 1 S

5.2 Accumulator

The accumulator is a general-purpose 8-bit register, which stores the results of most arithmetic and logic operations. In addition, the accumulator usually contains one of two data words used in these operations.

5.3 Index Register(X,Y)

There are two 8-bit index registers (X and Y), which may be used to count program steps or to provide an index value to be used in generating an effective address. When executing an instruction, wh ich specifies indexed addressing, the CPU fetches the OP Code and the base address, and modifies the address by adding the index register to it prior to performing the desired operation. Pre- or post-index of index address is possible.

5.4 Processor Status Register

The 8-bit processor status register contains seven status flags. Some of the flags are controlled by the program, others may be controlled both the program and the CPU. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N V 1 B D I Z C N: Signed flag, 1 = negative, 0 = positive V: Overflow flag, 1 = true, 0 = false B: BRK interrupt command, 1 = BRK, 0 = IRQB D: Decimal mode, 1 = true, 0 = false I: IRQB disable flag, 1 = disable, 0 = enable Z: Zero flag, 1 = true, 0 = false C: Carry flag, 1 = true, 0 = false

5.5 Program Counter(PC)

The 16-bit program counter register provides the addresses, which step the micro- controller through sequential program instructions. Each time the micro-controller fetches an instruction from program memory, the lower byte of the program counter (PCL) is placed on the low-order 8 bits of the address bus and the higher byte of the program counter (PCH) is placed on the high-order 8 bits. The counter is incremented each time an instruction or data is fetched from program memory.

5.6 Stack Point(S)

The stack pointer is an 8-bit register, which is used to control the addressing of the variable-length stack. The stack pointer is automatically incremented and decremented under control of the micro- controller to perform stack manipulations under direction of either the program or interrupts (/NMI or /IRQ). The stack allows simple implementation of nested subroutines and multiple level interrupts. The stack pointer is initialized by the user’s firmware. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 10/31

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6 Memory Organization

There are 128 bytes SRAM, located in address 0000H to 007FH, in the MG65M513. They could be used as either working RAM or stacks according to application programs. For the purposes above, the location 0000H to 007FH and 0100H to 017FH overlap. In other words, accessing any locations inside the range 0000H to 007FH is equivalent to access the corresponding ones in the range 0100 to 017FH. All special function registers, SFRs, are located at the region 00C0H to 00FFH. Such an arrangement could benefit from the faster access time of zero- page. For LCD function, there are 16 bytes LCD RAM (1000H to 100FH) in MG65M513. They can also be used as a general purpose RAM when LCD function is unused. There are 8K bytes program / data M TP ROM in MG65M513. The ROM address from E000H to FFFFH can store program and data. The address mapping of MG65M513 is shown as below. Zero Page SRAM SFR SRAM / Stack Area LCD RAM Program/ Table Interrupt Vector Area 0000H~007FH 00C0H~00FFH 0080H~00BFH Share area 0180H~01 FFH 0100H~017 FH 1000H~ 100FH E000H~FFFBH FFFCH ~ FFFFH MG65M513 Memory Map Figure 6-1 Memory Map This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 11/31

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6.1 SFR Mapping

The address 00C0H to 00FFH are reserved for special function registers (SFR). The SFR is used to control or store the status of I/O, timers, system clock and other peripheral. ※ All SFRs are not supported by bit-manipulation instructions. Table 6-1 SFR Table SFR (special function register): 00C0H~00FFH Address Content Default Address Content Default 00C2 IRQ_EN / IRQ_ST 0-00000- 00D2 P0 XXXXXXXX 00C3 IRQ_CLR 0-00000- 00D3 P0dir 0000---- 00C4 RESFlag X-0X1-XX 00D4 P0plh 11111111 00C5 RESOK XXXX---0 00D5 P0opd 0000---- 00C8 TM0 11111111 00D8 P2 00000000 Address Content Default Address Content Default This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 12/31

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6.2 Write Protect Function Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00F9H CWPR PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 - √ Condition Write Protect flag register (CWPR) is used to protect IRQ_CLR.7 (WDT), PWR_CR.1 (CKC0), (CKC1) or SCK_SEL, The CWPR musts write “78H”. PT7~PT0: Write Protect Pattern. In MG65M513 write protect pattern is “78H”. Note: 1. When CWPR is written by firmware, it would be automatically cleared by hardware after the “next write action” of firmware. ※Bit-manipulation instructions are not available on this register.

6.3 IAP Write Protect Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00E1H IAP_PR PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 - √ PR7 ~ PR0: Write Protect Pattern. IAP-memory block would be written by firmware, when IAP_WP is written “46H” then “B9H”. The IAP_WP will be automatically cleared by next uC write action or flash write time-out. ※ The flash write time -out period is obtained by the watch dog timer bit1. (WDT clock source is (Fosc/4096) /4 @ 4MHz or WDT clock source is (Fosc/512) /4 @ 32KHz) when clock source is 4M, the IAP time-out period is 2ms ~4ms ) ※ Clear watch timer before the IAP function is used. ※ W hen VDD < V LVD1(2.4V), IAP function would be disabled by hardware. Example: sei lda #78H sta CWPR ;;(F9h) lda #80H sta IRQ_CLR ;;(C3h) lda #46H sta IAP_PR ;;(E1h) lda #B9H sta IAP_PR ;;(E1h) lda #$40 ;;The data will be written into flash. Sta $E000 ;;IAP_AREA (E000h ~ FFFFh) cli This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 13/31

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7 Interrupt

MG65M513 provides five kinds of interrupt sources. The flag IRQ_EN and IRQ_ST are used to control the interrupts. When flag IRQ_ST is set to ‘1’ by hardware and the corresponding bits of flag IRQ_EN has been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the CLI or STA IRQ_EN, # I instruction is invoked. Executing the SEI instruction can also disable the interrupts. Table 7-1 Interrupt Vector Table Vector Address Item Flag Properties Memo FFFEH, FFFFH P1 IRQ IRQ_ST.1 Ext. P1.0 ~ P1.4 interrupt vector P0 IRQ IRQ_ST.2 Ext. P0.0 ~ P0.7 interrupt vector TM0 IRQ IRQ_ST.3 Int. TM0 underflow interrupt TM1 IRQ IRQ_ST.4 Int. TM1 underflow interrupt DIV IRQ IRQ_ST.5 Int. Divider carry out interrupt FFFCH, FFFDH RESET None Ext. Initial reset WDT IRQ_ST.7 Int. Watch dog timer reset LVR None Int. Low voltage reset

7.1 Interrupt Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C2H IRQ_EN PDBOR - DIVx TM1 TM0 P0 P1 - - √ Program can enable or disable the ability of triggering IRQ through this register. 0: Disable (default “0” at initialization) 1: Enable P0: Falling edge occurs at port 0 input mode P1: Falling edge occurs at port 1 TM0: Timer 0 underflow TM1: Timer 1 underflow DIVx: Divider selected interrupt frequency occurred PDBOR: Power down BOR function IRQ status flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C2H IRQ_ST WDT - DIVx TM1 TM0 P0 P1 - √ - When IRQ occurs, program can read this register to know which source is triggering IRQ. If the interrupt triggering is enabled and the interrupt event is accepted, the corresponding IRQ status flag should be cleared by program after the interrupt vector is loaded into program counter. IRQ clear flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C3H IRQ_CLR WDT - DIVx TM1 TM0 P0 P1 - - √ Program can clear the interrupt event by writing ‘1’ into the corresponding bit. The IRQ_CLR.7 (WDT) is protected by CWPR. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 14/31

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7.2 Interrupt System

IRQ _ EN.3/4 Interrupt Vector Generator Logic Initial Reset STA IRQ_ EN , # I Enable Initial Reset STA IRQ _ CLR , # I SEI instructionDisable Timer 0/1 underflow signal S R Q CLI instruction IRQ _ EN .2 S R Q IRQ_ST.3/4 IRQ _ ST . 2 DIV 1_IST.4 Divider overflow signal IRQ _ EN .5 FFFEH, FFFFH P 0 / P1 DIV 1_IST.13 DIV 1_IST.10 DIV 1_IST.7 Figure 7-1 Interrupt System Diagram This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 15/31

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8 Reset

8.1 Low Voltage Reset (LVR)

The MG65M513 provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V ~ VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications 1. The low voltage (0.9V~VLVR) has to remain in its original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. 2. In the LVR mode, the clock source (INT./EXT. OSC) continuous oscillating and the IO status becomes default value. Reset status flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C4H RESFlag BOR - IAR_F EXTR_F LVPOR - LVD1 LVD0 √ √ BOR: Brown out reset occurs. 1: If the supply voltage of the device is within the range VDD ~ VDD-1.2V 0: This bit is set by hardware and cleared by writing ‘1’. IAR_F: Illegal address reset flag. 1: An illegal address reset occurs. 0: This bit is set by hardware and cleared by writing ‘1’. EXTR_F: External reset flag 1: An external reset occurs. 0: This bit is set by hardware and cleared by writing ‘1’. LVPOR: Low voltage reset and POR reset occur. 1: VDD is under 1.8V or power-on. 0: This bit is set by hardware and cleared by writing ‘1’. LVD1: Low voltage1 detected. 1:VDD is under 2.4V. 0:This bit is set by hardware and cleared by writing ‘1’. LVD0: Low voltage0 detected. 1:VDD is under 2.1V. 0:This bit is set by hardware and cleared by writing ‘1’. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 16/31

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8.2 Watchdog Timer (WDT)

(The example is based on 32.768KHz and SCK_SEL.1 = 1) Name Bit 8 R W WDT 1.9 (Hz) - - The watchdog timer time-out period is obtained by the equation: (FDIV /512)/512 or (FDIV /4096)/512 select by SCK_SEL.1 (CKS1). Before watchdog timer time-out occurs, the program must clear the 9-bit WDT timer by writing 1 to IRQ_CLR.7. WDT overflow will cause system reset and set IRQ_CLR.7 to high. Watchdog Block Diagram R Write EVTclr Data bus _bit7 = 0 Pulse generator Over flow detection SD C R Q Write EVTclr Hard _ rst WDTevt WDT reset 512 SEL SCK_SEL.1 FWDT F DIV / 512 F DIV / 4096 Data bus _bit 7 Figure 8-1 Watch Dog Diagram

8.3 Reset OK

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C5H RESOK RK7 RK6 RK5 RK4 - - - IO_RES - √ RESOK (Reset OK): If the device resets OK and works well, users must write #$90 into this register. For example: Program_start: LDA #10010000b STA $C5 IO_RES: IO reset selector. 0:IO status is reset by WDT, IA reset, LVR and POR, EXT_RESET (Default). 1:IO status is reset by LVR, EXT_RESET and POR. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 17/31

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9 Power Control

9.1 Power Control Register

System clock selector (※The Clock Control Register is protected by CWPR.) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00F0H SCK_SEL CKS7 - - - - CKS2 CKS1 CKS0 - √ CKS0: FCPU clock source select. 0: FOSC, 1: FX32 CKS1: Watchdog clock source select. 0: FDIV/4096, 1: FDIV/512 CKS2: De-bounce (awakened from stop mode) time selector. 0: FOSC/16384, 1: FOSC/256 CKS7: Select the input clock source of divider. 0: FOSC, 1: FX32 Power saving control Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00FCH PWR_CR - - - - - CKC1 CKC0 HALT - √ ※ CKC1 and CKC0 are protected by CWPR CKC1 CKC0 System clock control 0 0 FOSC enable, FX32 enable (Dual mode) 0 1 FOSC enable, FX32 disable (Single mode) 1 0 FOSC disable, FX32 enable (Slow mode) 1 1 FOSC disable, FX32 disable (Stop mode) Note: Dual mode and slow mode are inhibited when code option is selected to FX32 disable. HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line Program can switch the normal operation mode to the power -saving mode for saving power consumption through this register. There are three power saving modes in this system. Slow mode: (PWR_CR.CKC1 = 1, PWR_CR.CKC0 = 0) The main uC clock (FOSC) stops oscillating. Only very low power is needed for uC to keep running. Stop mode: (PWR_CR.CKC1 = 1, PWR_CR.CKC0 = 1) Both system clocks stop oscillating. The uC can be awakened from stop mode by 4-ways: port 0 falling edge, port 1 falling edge, hardware reset, or power -on reset. When the stop mode is released, only the oscillat or, which is providing the uC clock, will be enabled again. If uC clock source is F X32, The Fosc and Fx32 clock are disabled (set the PWR_CR[2:1] = 11). The F X32 will be enabled and FOSC still keep same status, when uC is woken up by port0 or port1. Halt mode: (PWR_CR.HALT = 1) The F CPU clock is in off -line status. The oscillator(s) still keep same status. The uC can be awakened from halt mode by 3-ways: the interrupt events, hardware reset, or power-on reset. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 18/31

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10 Divider

10.1 Divider

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00CCH DIV_SEL - - - - - - DIVS1 DIVS0 - √ The divider clock source comes from FX32 (sub-main clock) or FOSC (main clock). Program can select divider interrupt frequency by DIV_SEL register. DIV _ L(8-bit) DIV_ H (8-bit) DIV FOSC DIVS1 DIVS0 FX32 FDIV SCK _SEL .7 DIVx FDIV /32, /256, /2048, /16384 DIVS1 DIVS0 DIV interrupt occurs status 0 0 FDIV / 16384 0 1 FDIV / 2048 1 0 FDIV / 256 1 1 FDIV / 32 This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 19/31

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11 Timer

11.1 Timer0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C8H TM0 T7 T6 T5 T4 T3 T2 T1 T0 √ √ 00CAH TM0_CTL STC RL/S - - - TCS0 TKI1 TKI0 √ Timer 0 is an 8-bit down-count counter. STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload TCS0: select the input clock source of timer0. 0:FOSC, 1: FX3 FTM0_DIV FTM 0 _ DIV FOSC FX32 TM 0_ CTL .2 TKI1 TKI0 FTM0_DIV FTM0 TM0(R) TM0 re- load buffer (W) Control Logic MUX Reload _CTL.1 _CTL.0 FTM0 T M0 TM0 over-flow TM0 TM0 TM0_CTL.7 _ CTL.6TM0 FTM0/1 FTM0/4 FTM0/16 FTM0/64 FTM0_UV, can be calculated with the equation: FTM0_UV = FTM0 / (TM0+1), where the FTM0 is the timer input frequency set by TKI1 and TKI0. For example: (if F TM0 = 2.000MHz, TKI1=TKI0=0) TM0 Frequency 00H Reserved 01H 1.000MHz 02H 667kHz … … FFH 7.84kHz TKI1 TKI0 Selected TM0 input frequency (FTM0_DIV) 0 0 FTM0 / 1 0 1 FTM0 / 4 1 0 FTM0 / 16 1 1 FTM0 / 64 This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 20/31

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11.2 Timer1

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00CDH TM1 T7 T6 T5 T4 T3 T2 T1 T0 √ √ 00CFH TM1_CTL STC RL/S - - - TCS1 TKI1 TKI0 √ Timer 1 is an 8-bit down-count counter. STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload TCS1: select the input clock source of timer1. 0: FOSC, 1: FX32 FTM1_DIV FTM 1 _ DIV FOSC FX32 TM 1_ CTL .2 TKI1 TKI0 FTM1_DIV FTM1 TM1(R) TM1 re- load buffer (W) Control Logic MUX Reload _CTL.1 _CTL.0 FTM1 T M1 TM1 over-flow TM1 TM1 TM1_CTL.7 _ CTL.6TM1 FTM1/1 FTM1/4 FTM1/16 FTM1/64 FTM1_UV, can be calculated with the equation: FTM1_UV = FTM1 / (TM1+1), where the FTM1 is the timer input frequency set by TKI1 and TKI0. For example: (if F TM1 = 2.000MHz,TKI1=TKI0=0) TM1 Frequency 00H Reserved 01H 1.000MHz 02H 667kHz … … FFH 7.84kHz TKI1 TKI0 Selected TM1 input frequency (FTM1_DIV) 0 0 FTM1 / 1 0 1 FTM1 / 4 1 0 FTM1 / 16 1 1 FTM1 / 64 This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 21/31

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12 Configurable I/O Ports

12.1 Port 0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D2H P0 P07 P06 P05 P04 P03 P02 P01 P00 √ - Port 0 is combined with 4-bit input port and 4-bit I/O port. P0.7~P0.4 can be programmed as input or output individually. When P0.n (n= 4~7) is configured as an output pin, the P0.n pin would output the logic content of internal P0obuf.n (P0 output buffer). The default value of P0obuf is 0000----b. When the P0.n is configured as output mode, reading P0.n would always read logic ‘0’. When the P0.n is configured as input mode, reading P0.n would always read the logic value from pad. Port 0 Output Buffer Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D2H P0 P07 P06 P05 P04 - - - - - √ This register is used to buffer the output value of P0.7 ~ P0.4 in output mode and it is write-only. ※ Bit-manipulation instructions are not available on this register. Port 0 Direction Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D3H P0dir DR7 DR6 DR5 DR4 - - - - - √ P0_DR (Port 0 Direction) P0_DR.n = 0: P0.n is configured as an input pin. (Default) 1: P0.n is configured as an output pin. ※ Bit-manipulation instructions are not available on this register. Port 0 Pull-high Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D4H P0plh PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 - √ 1: Enable internal pull-high (default); 0: Disable internal pull-high PHn: Control bit is used to enable the pull-high of P0.n pin. ※ Bit-manipulation instructions are not available on this register. Port 0 Open-Drain Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D5H P0opd OD7 OD6 OD5 OD4 - - - - - √ 0: Disable open-drain output (CMOS output); 1: Enable open-drain output ODn: Control bit is used to enable the open-drain of P0.n pin. ※ Bit-manipulation instructions not available on this register. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 22/31

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12.2 Port 1

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D6H P1 - - - P14 P13 P12 P11 P10 √ √ Port1 is a 5-bit quasi-bi-directional open drain output (high sink current 16mA) with internal pull-high resistors when Reading P1.n would always read the logic value from pad. The pull-high resistors will be temporarily disabled if the output value is low. ※ Bit-manipulation instructions are not available on this register. Port 1 Pull-high Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D7H P1plh - - - PH4 PH3 PH2 PH1 PH0 - √ 1: Enable internal pull-high (Default) 0: Disable internal pull-high PHn: Control bit is used to enable the pull-high of P1.n pin. ※ Bit-manipulation instructions are not available on this register.

12.3 Port 2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D8H P2 P27 P26 P25 P24 P23 P22 P21 P20 - √ Port2 is an open drain output port with internal pull-high resistors when OR0.7~5 (LCD/OD) option is selected to I/O function. This register is used to buffer the output value of P 2.0 ~ P 2.7. The pull -high resistors will be temporarily disabled if the output value is low. ※ Bit-manipulation instructions are not available on this register. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 23/31

Version 1.10

12.4 High sink output

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00DAH HSOB HSO - - - - - - PS0 - √ HSO pad is a high sink current output pin. The HSO PAD output from HSOB or Tone is selected by PS0. HSOB. 7 can set up 1/3 or 2/3 duty cycle by using instruction, writer “1”, through HSO buffer to PAD output High, until writer “0”, and then the output status will change to Low. ※ Bit-manipulation instructions are not available on this register. PS0 (HSOB.0) can set the HSO pad output source as HSO buffer or tone generator. The HSO output waveform can be programmed to any duty cycle by software. MUX HSO PAD 1Tone HSO bufferTM 0 ( R) TM 0 re- load Control Logic Reload Carrier Generator En TM0 under - flow PS 0 PS 0 HSO PAD output source

1 Tone

HSO buffer (HSOB.7) TM 0_ CTL.6 TM0_ CTL.7 (HSOB.7) (HSOB.0) PS0 If the tone path is selected (PS0=1), the duty cycle of the carrier output is fixed to 50%. . . .T T T = (TM0 + 1) / FOSC The counter underflow frequency of timer0 can be calculated with the equation: F TM0_UV = FTM0 / (TM0reg+1). The FTM0 is Timer0 clock input. For example: FTM0 = 455KHz,TM0reg = 0BH FTM0_UV = FTM0 / (TM0reg+1) = 455K/(0BH+1) = 37.92KHz. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 24/31

Version 1.10

13 LCD Controller/Driver

The MG65M513 can directly drive an LCD with 29 segment output pins and 4 common output pins for a total of 29 × 4 dots. LCD control r egister can be used to select LCD display configuration. LCD driving mode is 1/3 bias and 1/4 duty and frame frequency is about 81.38Hz. When CPU access es the LCD RAM area, the access path of the LCD RAM will be transferred from LCD driver to CPU automatically. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00DEH LCD_CR LCDON - - - - - CKS1 CKS0 - √ LCDON: LCD on/off control bit. 0: off (default), 1:on LCD scan rate, F COM, is derived from the clock source of divider . The relation between the CKS1, CKS0, FCOM and FDIV is shown as below. CKS1 CKS0 Selected FCOM frequency 0 0 FDIV / 96 0 1 FDIV / 6144 1 0 FDIV / 12288 1 1 FDIV / 24576 The LCD frame rate can be calculated with the equation: FFRAME = FCOM / COM No. Typical selection combinations for 1/4 duty are shown below: COM No. FDIV_IN Selected FCOM frequency FFRAME 4 6M FDIV / 24576 61.04 4 4M FDIV / 12288 81.38 4 2M FDIV / 6144 81.38 4 32K FDIV / 96 85.33 There are 16 LCD data RAM in MG 65M513. When the bit value of LCD data RAM is “1”, the LCD is turned on. When the bit value of LCD data RAM is “0”, the LCD is turned off. The contents of the LCD data RAM are sent out through the SEG0 to SEG28 pins by a direct memory access. The relationship between the LCD data RAM and SEG/COM pins is shown as below. LCD Data COMX Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM SEG SEG SEG SEG SEG SEG SEG SEG 1000H COM 0 07 06 05 04 03 02 01 00 1001H 15 14 13 12 11 10 09 08 1002H 23 22 21 20 19 18 17 16 1003H RAM RAM RAM 28 27 26 25 24 1004H COM 1 07 06 05 04 03 02 01 00 1005H 15 14 13 12 11 10 09 08 1006H 23 22 21 20 19 18 17 16 1007H RAM RAM RAM 28 27 26 25 24 1008H COM 2 07 06 05 04 03 02 01 00 1009H 15 14 13 12 11 10 09 08 100AH 23 22 21 20 19 18 17 16 100BH RAM RAM RAM 28 27 26 25 24 100CH COM 3 07 06 05 04 03 02 01 00 100DH 15 14 13 12 11 10 09 08 100EH 23 22 21 20 19 18 17 16 100FH RAM RAM RAM 28 27 26 25 24 This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 25/31

Version 1.10 1/4 duty 1/3 bias COM0 COM1 COM2 SEGn FRAME VDD VSS VSS VLCD VSS VLCD VLCD VSS COM3 Off On On Off VLCD VLCD VSS VSS VSS VSS VLCD VSS VLCD VSS VLCD Off On On Off 0 1 2 0 130 1 2 0 1 2 330 1 2 331 2 This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 26/31

Version 1.10

14 Option Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OR0 SEG_OD2 SEG_OD1 SEG_OD0 LOCK Fm WDT Bit 7 ~ Bit 5: Function Table SEG_ OD2 SEG_ OD1 SEG_ OD0 COM3~0 SEG15~ SEG0 SEG23~ SEG16 SEG 24 25 26 27 28 0 1 1 LCD LCD SEG24 P1.1 P1.2 P1.3 P1.4 1 0 0 LCD LCD SEG24 SEG25 P1.2 P1.3 P1.4 1 0 1 LCD LCD SEG24 SEG25 SEG26 P1.3 P1.4 1 1 0 LCD LCD SEG24 SEG25 SEG26 SEG27 P1.4 1 1 1 LCD LCD SEG24 SEG25 SEG26 SEG27 SEG28 Bit4: LOCK 0 (Enable): Dump code is locked. (Default) 1 (Disable): Dump code is not locked. Bit3: Fm 0 (Fm/2): FCPU clock / 2 1 (Fm): FCPU clock / 1 (Default) Bit2: WDT 0 (Disable): Disable watchdog timer function (default) 1 (Enable): Enable watchdog function Bit 1 ~ Bit 0: Reserved. Software must write “0” on these bits. This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 27/31

Version 1.10 MG65M513 GND VDD COM0~ COM3 X 32I 32 kHz X 32O 20pF 20pF P0.0~P0.7 / RESReset Key Key Pad VDD OSCI 10uF+

470 K ohm

@4 MHz @3 V SEG0 ~ SEG28 LCD Panel 0.1uF 2 ohm VDD HSO High light LED 100 uF P1.0~P1.4 ( SEG24~ 28) 0.1 uF Figure 15-1 Application Circuit - LCD Display Controller This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 28/31

Version 1.10

16.1 Absolute Maximum Rating

Supply Voltage to Ground Potential -0.3 to +5.0 V Applied Input / Output Voltage -0.3 to +5.0 V Power Dissipation 60 mW Ambient Operating Temperature -10 to +50 °C Storage Temperature -55 to +150 °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

16.2 DC Characteristics

(VDD-VSS = 3.0 V, FOSC = 4MHz, Ta = 25° C; unless otherwise specified) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Op. Voltage VDD - 1.8 - 3.6 V Op. Current 1 IOP Dual mode, No load, LCD on FCPU = 4MHz - 1.8 5.6 mA Halt Current 1 ISTB2 Slow mode, HALT, No load, LCD on, FCPU = 32768Hz, DIVX INT on - 9 12 μA Halt Current 2 ISTB3 Slow mode, HALT, No load, LCD off, FCPU = 32768Hz, DIVX INT off - 6 8 μA Stop Current ISTB1 STOP mode, No load, LCD off - - 1 μA Input High Voltage VIH - 0.7 VDD - VDD V Input Low Voltage VIL - 0 - 0.3 VDD V Port 0 Drive Current IOH1 VOH = 2.4V, VDD = 3.0V 10 - - mA Port 0 Sink Current IOL1 VOL = 0.4V, VDD = 3.0V 10 - - mA HSO Drive Current IOH2 VOH = 2.4V, VDD = 3.0V 10 - - mA HSO Sink Current IOL2 VOL = 1.0V, VDD = 3.0V 250 - - mA COM, SEG Drive Current IOH3 VOH = 2.7V, VLCD = 3.0V 0.1 2 - mA COM, SEG Sink Current IOL3 VOL = 0.3V, VLCD = 3.0V 0.3 3 - mA P1.0 to P1.4 Sink Current IOL4 VOL = 0.4V, VDD = 3.0V 10 - - mA P2 Sink Current IOL5 VOL = 0.4V, VDD = 3.0V 8 mA P0~2 Internal Pull-high Resistor RPH1 VIL = 0V 25K 50K 75K Ω /RES Pull-high Resistor RRES VIL = 0V - 30K - Ω Low Voltage Detector for IAP Function VLVD1 VDD > 2.4V - 2.4 - V Low Voltage Detector for uC VLVD0 VDD > 2.1V - 2.1 - V Low Voltage Reset VLVR - - 1.8 - V This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 29/31

Version 1.10

16.3 AC Characteristics

PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Built-in CPU Op. Frequency FCPU RC, VDD = 3.0V 0.5 4 6 MHz Frequency Deviation by Voltage Drop for RC Oscillator f f(3.6V) - f(2.6) f(3.0V) - 3 10 % POR Duration TPOR FOSC = 4 MHz - 4 1 mS System Start-Up Time TSST Power-up, reset - 16384 - 1/FCPU System Wake-Up Time TSWT Wake-up from STOP mode 256 - 16384 1/FCPU This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 30/31

Version 1.10 Revision Page Descriptions Date V1.00 Initial version 2011/10/14 V1.01 Fix some errors 2011/10/28 V1.02 Modify block diagram 2011/11/09 V1.04 Fix some description errors 2012/01/06 V1.05 Modify LVD and LVD voltages 2012/02/15 Modify halt mode current V1.06 Add LVD2 flag 2012/02/24 Modify halt mode current V1.07 Modify application circuit 2012/05/10 V1.08 Modify LVD0 and LVD1 SPEC. voltage 2012/07/04 Remove LVD2 flag V1.09 Add ICP programmer interface description 2012/09/11 V1.10 Add PACKAGE description 2016/04/22 This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 31/31

Product Information

MG65M513 specifications and overview.

Summary

42 Programmable GPIO

Description

42 Programmable GPIO

Source title MG65M513 Datasheet(PDF) - Megawin Technology Co., Ltd

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