MG65L513A

Megawin Technology Co.,...

Watchdog timer built-in

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Version: 0.04 This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 1/30 笙泉科技股份有限公司 Megawin Technology Co., Ltd. MG65L513A Data Sheet 8-Bit Micro-Controller with 116 dots LCD driver and IO function Version 0.04

This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 2/30 MG65L513A Datasheet Version 0.04 Table of Contents

1 Features

 Single Chip 8-bit CPU  Memory  Program Mask ROM : 8K Bytes  Data RAM : 128 Bytes  LCD RAM : 16 Bytes  Operating voltage: 1.8V to 3.6V  42 Programmable GPIO  High sink current output  Shared input or output pins:  Input/output pins P0[7:4]  Input pins P0[3:0]  Quasi-bi-directional IO pins P1[4:0] / Segment28 ~ Segment24  Output pins P2[7:0] / Segment23 ~ Segment16  LCD driver output  Max 29 segment x 4 common  1/4 duty and 1/3 bias driving mode  Watchdog timer built-in  Two re-loadable 8-bit timers  HALT mode and STOP mode for power saving  Build-in dual oscillation circuit:  RC type main oscillator  X32 for sub-oscillator  Dual clock operation  Build-in low voltage detectors (typical voltage: below 2.1V or 2.3V) and low voltage reset (typical voltage: below 1.8V)

1.1 Application Field

General LCD Controller, Hand-held Game, Toy

2 General Description

MG65L513A 513 is a cost effective, high performance 8-bit micro-controller of MEGAWIN. It integrates an 8-bit CPU core, ROM, RAM, timers, LCD driver, I/O ports and system control circuits into a single chip. The MG65L513 provides a build-in oscillator as clock source. It is suitable for general LCD controller, hand-held game, toy controllers, and other products.

3 Pin Configurations

3.1 Pad Assignment

12 14 1513 16 17 18 19 20 21 22 23 24 25 26 SEG 12 SEG 11 SEG 17 SEG 18 SEG 15 SEG 19 SEG 13 SEG 16 SEG 14 SEG 10 SEG 9 SEG 8 SEG 20 SEG 21 SEG 7 SEG 6 SEG 5 COM 3 COM 0 COM 2 SEG 0 COM 1 SEG 1 SEG 2 SEG 3 SEG 4 P0.1 P0.0 P0.2 P0.4 P0.5 P0.3 P0.6 P0.7 VDD HSO VSS /RESB 3940 OSC/XI X32I SEG 22 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 44 43X32O Figure 3-1 Pad Assignment

3.2 Pin Description

1,2 X32O, X32I B 32.768KHz crystal oscillator pins. 3 ~ 7 SEG28 ~ SEG24 I/0 LCD segment signal output pins. SEG28~SEG24 share pads with P1 [4:0] Quasi-bi-directional IO pin. 8 ~ 15 SEG23 ~ SEG16 O LCD segment signal output pins. SEG23~SEG16 share pads with P2 [7:0] output pin. 16 ~ 23 SEG15 ~ SEG8 O LCD segment signal output pins. 24 ~ 31 SEG7 ~ SEG0 O LCD segment signal output pins. 32 ~ 35 COM0 ~ COM3 O LCD common signals output pins. 36 ~ 39 P0.0 ~ P0.3 I Input pin with interrupt function. 40 ~ 43 P0.4 ~ P0.7 B Programmable I/O ports with interrupt function.

44 VDD P Positive power pins (need to connect together)

45 HSO O Direct sink (sink current: 250mA) for high light LED. Default value is high after reset.

46 VSS P Ground pins (need to connect together)

47 /RES I System reset pin (low active). 48 OSCI I RC oscillator input pin. Note: In the “Type” field, “I” means input only. “O” means output only. “B” means bi-direction. “P” means Power, “G” means Ground.

4 Block Diagram

6502 CPU

(HF ROSC / X32OSC) I / O SRAM / Register ROM LVR HSO LCD Driver X32O X32I XI nRES VDD GND HSO P0.0 ~ P0.7 COM0 ~ 3 SEG0 ~ SEG28 (P1.0 ~ P1.4) (P2.0 ~ P2.7) Figure 4-1 Block Diagram

5 Function Description

5.1 Registers

A Y X P PCH PCL 1 S

5.2 Accumulator

The accumulator is a general-purpose 8-bit register, which stores the results of most arithmetic and logic operations. In addition, the accumulator usually contains one of two data words used in these operations.

5.3 Index Register(X,Y)

There are two 8-bit index registers (X and Y), which may be used to count program steps or to provide an index value to be used in generating an effective address. When executing an instruction, which specifies indexed addressing, the CPU fetches the OP Code and the base address, and modifies the address by adding the index register to it prior to performing the desired operation. Pre- or post-index of index address is possible.

5.4 Processor Status Register

The 8-bit processor status register contains seven status flags. Some of the flags are controlled by the program, others may be controlled both the program and the CPU. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N V 1 B D I Z C N: Signed flag, 1 = negative, 0 = positive V: Overflow flag, 1 = true, 0 = false B: BRK interrupt command, 1 = BRK, 0 = IRQB D: Decimal mode, 1 = true, 0 = false I: IRQB disable flag, 1 = disable, 0 = enable Z: Zero flag, 1 = true, 0 = false C: Carry flag, 1 = true, 0 = false

5.5 Program Counter(PC)

The 16-bit program counter register provides the addresses, which step the micro-controller through sequential program instructions. Each time the micro-controller fetch an instruction from program memory, the lower byte of the program counter (PCL) is placed on the low-order 8 bits of the address bus and the higher byte of the program counter (PCH) is placed on the high-order 8 bits. The counter is incremented each time an instruction or data is fetched from program memory.

5.6 Stack Point(S)

The stack pointer is an 8-bit register, which is used to control the addressing of the variable-length stack. The stack pointer is automatically incremented and decremented under control of the micro-controller to perform stack manipulations under direction of either the program or interrupts (/NMI or /IRQ). The stack allows simple implementation of nested subroutines and multiple level interrupts. The stack pointer is initialized by the user’s firmware.

6 Memory Organization

There are 128 bytes SRAM, located in address 0000H to 007FH, in the MG65L513A. They could be used as either working RAM or stacks according to application programs. For the purpose above, the location 0000H to 007FH and 0100H to 017FH are overlaps. In other words, accessing any locations inside the range 0000H to 007FH is equivalent to access the corresponding ones in the range 0100 to 017FH. All special function registers, SFRs, are located at the region 00C0H to 00FFH. Such an arrangement could benefit from the faster access time of zero- page. For LCD function, there are 16 bytes LCD RAM (1000H to 100FH) in MG65L513A. They can also be used as a general purpose RAM when LCD function is unused There are 8K bytes program / data ROM in MG65L513A. The ROM address from E000H to FFFFH can store program and data. The address mapping of MG65L513A is shown as below Zero Page SRAM SFR SRAM / Stack Area LCD RAM Program/ Table Interrupt Vector Area 0000H~007FH 00C0H~00FFH 0080H~00BFH Share area 0180H~01 FFH 0100H~017 FH 1000H~ 100FH E000H~FFFBH FFFCH ~ FFFFH MG65L513A Memory Map Figure 6-1 Memory Map

6.1 SFR Mapping

The address 00C0H to 00FFH is reserved for special function registers (SFR). The SFR is used to control or store the status of I/O, timers, system clock and other peripheral. ※ All SFRs are not supported by bit-manipulation instructions. Table 6-1 SFR Table SFR (special function register): 00C0H~00FFH Address Content Default Address Content Default 00C2 IRQ_EN / IRQ_ST 0-00000- 00D2 P0port XXXXXXXX 00C3 IRQ_CLR 0-00000- 00D3 P0dir 0000---- 00C4 RESFlag --0X1--X 00D4 P0plh 11111111 00C5 RESOK XXXX---0 00D5 P0opd 0000---- 00C8 TM0 11111111 00D8 P2port 00000000 00CD TM1 11111111 00DD Address Content Default Address Content Default

6.2 Write Protect Function Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00F9H CWPR PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 -  Condition Write Protect flag register (CWPR) is used to protect IRQ_CLR.7 (WDT), PWR_CR.1 (CKC0), SCK_SEL, it must write “78H” to CWPR first. PT7~PT0: Write Protect Pattern. In MG65L513A write protect pattern is “78H” Note: 1. When CWPR is written by firmware, it would be au tomatically cleared by hardware after the “next write action” of firmware. Bit※ -manipulation instructions are not available on this register.

7 Interrupt

There are five kinds interrupt source is provided in MG65L513A. The flag IRQ_EN and IRQ_ST are used to control the interrupts. When flag IRQ_ST is set to ‘1’ by hardware and the corresponding bits of flag IRQ_EN has been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the CLI or STA IRQ_EN, # I instruction is invoked. Executing the SEI instruction can also disable the interrupts. Table 7-1 Interrupt Vector Table Vector Address Item Flag Properties Memo FFFEH, FFFFH P1 IRQ IRQ_ST.1 Ext. P1.0 ~ P1.4 interrupt vector P0 IRQ IRQ_ST.2 Ext. P0.0 ~ P0.7 interrupt vector TM0 IRQ IRQ_ST.3 Int. TM0 underflow interrupt TM1 IRQ IRQ_ST.4 Int. TM1 underflow interrupt DIV IRQ IRQ_ST.5 Int. Divider carry out interrupt FFFCH, FFFDH RESET None Ext. Initial reset WDT IRQ_ST.7 Int. Watch dog timer reset LVR None Int. Low voltage reset

7.1 Interrupt Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C2H IRQ_EN PDBOR - DIVx TM1 TM0 P0 P1 - -  Program can enable or disable the ability of triggering IRQ through this register. 0: Disable (default “0” at initialization) 1: Enable P0: Falling edge occurs at port 0 input mode P1: Falling edge occurs at port 1 TM0: Timer 0 underflow TM1: Timer 1 underflow DIVx: Divider selected interrupt frequency occurred PDBOR: Power down BOR (0: enable BOR IP 1: disable BOR IP) IRQ status flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C2H IRQ_ST WDT - DIVx TM1 TM0 P0 P1 -  - When IRQ occurs, program can read this register to know which source triggering IRQ. If the interrupt triggering is enabled and the interrupt event is accepted, the correspond IRQ status flag should be cleared by program after the interrupt vector is loaded into program counter. IRQ clear flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C3H IRQ_CLR WDT - DIVx TM1 TM0 P0 P1 - -  Program can clear the interrupt event by writing ‘1’ into the corresponding bit. The IRQ_CLR.7 (WDT) is protected by CWPR.

This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 13/30 MG65L513A Datasheet Version 0.04 Reset status flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C4H RESFlag - - IAR_F EXTR_F LVPOR LVD   IAR_F: Illegal address reset flag. (reset by POR and LVR) 1:An illegal address reset occurs. 0:This bit is set by hardware and clears by writing ‘1’. EXTR_F: External reset flag (reset by POR and LVR) 1: An external reset occurs. 0:This bit is set by hardware and clears by writing ‘1’. LVPOR: Low voltage reset and POR reset occur. (set by POR and LVR) 1:VDD is under 1.8V or power-on. 0: This bit is set by hardware and clears by writing ‘1’. LVD: Low voltage0 detected. (POR, LVR, BOR, illegal address reset and external reset) 1:VDD is under 2.1 or 2.3V. 0:This bit is set by hardware and clears by writing ‘1’.

7.2 Interrupt System

IRQ _ EN.3/4 Interrupt Vector Generator Logic Initial Reset STA IRQ_ EN , # I Enable Initial Reset STA IRQ _ CLR , # I SEI instructionDisable Timer 0/1 underflow signal S R Q CLI instruction IRQ _ EN .2 S R Q IRQ_ST.3/4 IRQ _ ST . 2 DIV 1_IST.4 Divider overflow signal IRQ _ EN .5 FFFEH, FFFFH P0/P 1 DIV 1_IST.13 DIV 1_IST.10 DIV 1_IST.7 Figure 7-1 Interrupt System Diagram

8 Reset

8.1 Low Voltage Reset (LVR)

The MG65L513A provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V ~ VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications 1. The low voltage (0.9V~VLVR) has to remain in their or iginal state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. 2. In the LVR mode, the clock source (INT./EXT. OSC) continuous oscillating and the IO status becomes default value.

8.2 Watchdog Timer (WDT)

(The example is base on 32.768KHz and SCK_SEL.1 = 1) Name Bit 8 R W WDT 1.9 (Hz) - - The watchdog timer time-out period is obtained by the equation: (FDIV /512)/512 or (FDIV /4096)/512 select by SCK_SEL.1 (CKS1). Before watchdog timer time-out occurs, the program must clear the 9-bit WDT timer by writing 1 to IRQ_CLR.7. WDT overflow will cause system reset and set IRQ_CLR.7 to high. Watchdog Block Diagram R Write EVTclr Data bus _bit7 = 0 Pulse generator Over flow detection SD C R Q Write EVTclr Hard _ rst WDTevt WDT reset 512 SEL SCK_SEL.1 FWDT F DIV / 512 F DIV / 4096 Data bus _bit 7 Figure 8-1 Watch Dog Diagram

8.3 Reset OK

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C5H RESOK RK7 RK6 RK5 RK4 - - - IO_RES -  RESOK (Reset OK): If the device reset OK and work well, must write #$90 into this register. For example: Program_start: LDA #10010000b STA $C5 IO_RES: IO reset selector. 0:IO status is reset by WDT, IA reset, LVR and POR, EXT_RESET (Default). 1:IO status is reset by LVR, EXT_RESET and POR.

9 Power Control

9.1 Power Control Register

System clock selector (※The Clock Control Register is protected by CWPR.) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00F0H SCK_SEL CKS7 - - - - CKS2 CKS1 CKS0 -  CKS0: FCPU clock source select. 0: FOSC, 1: FX32 CKS1: Watchdog clock source select. 0: FDIV/4096, 1: FDIV/512 CKS2: De-bounce (awakened from stop mode) time selector. 0: FOSC/16384, 1: FOSC/256 CKS7: Select the input clock source of divider. 0: FOSC, 1: FX32 Power saving control Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00FCH PWR_CR - - - - - CKC1 CKC0 HALT -  ※ CKC1 and CKC0 are protected by CWPR CKC1 CKC0 System clock control 0 0 FOSC enable, FX32 enable (Dual mode) 0 1 FOSC enable, FX32 disable (Single mode) 1 0 FOSC disable, FX32 enable (Slow mode) 1 1 FOSC disable, FX32 disable (Stop mode) Note: Dual mode and slow mode is inhibited when code option is selected to FX32 disable. HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line Program can switch the normal operation mode to the power-saving mode for saving power consumption through this register. There are three power saving modes in this system. Slow mode: (PWR_CR.CKC1 = 1, PWR_CR.CKC0 = 0) The main uC clock (FOSC) stops oscillating. Only very low power is needed for uC to keep running. Stop mode: (PWR_CR.CKC1 = 1, PWR_CR.CKC0 = 1) Both system clocks stop oscillating. The uC can be awakened from stop mode by 4-ways: port 0 falling edge, port 1 falling edge, hardware reset, or power-on reset. When the st op mode is released, only the oscillator, which is providing the uC clock, will be enabled again. If uC clock source is FX32 and system into STOP mode (set PWR_CR[2:1] = 11). The FX32 will be enabled and FOSC still keep same status, when uC waken up by port0 or port1. Halt mode: (PWR_CR.HALT = 1) The FCPU clock in off-line status. The oscillator(s) still k eep same status. The uC can be awakened from halt mode by 3-ways: the interrupt events, hardware reset, or power-on reset.

10 Divider

10.1 Divider

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00CCH DIV_SEL - - - - - - DIVS1 DIVS0 -  The divider clock source comes from FX32 (sub-main clock) or FOSC (main clock). Program can select divider interrupt frequency by DIV_SEL register. DIV _L ( 8 - b i t ) DIV_ H (8-bit) DIV FOSC DIVS1 DIVS0 FX32 FDIV SCK _SEL .7 DIVx FDIV /32, /256, /2048, /16384 DIVS1 DIVS0 DIV interrupt occurs status 0 0 F DIV / 16384 0 1 F DIV / 2048 1 0 F DIV / 256 1 1 F DIV / 32

11 Timer

11.1 Timer0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C8H TM0 T7 T6 T5 T4 T3 T2 T1 T0   00CAH TM0_CTL STC RL/S - - - TCS0 TKI1 TKI0  Timer 0 is an 8-bit down-count counter. STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload TCS0: select the input clock source of timer0. 0:FOSC, 1: FX32 FTM0_DIV FTM 0 _ DIV FOSC FX32 TM 0_ CTL .2 TKI1 TKI0 FTM0_DIV FTM0 TM0(R) TM0 re- load buffer (W) Control Logic MUX Reload _CTL.1 _CTL.0 FTM0 T M0 TM0 over- flow TM0 TM0 TM0_CTL.7 _ CTL.6TM0 FTM0/1 FTM0/4 FTM0/16 FTM0/64 FTM0_UV, can be calculated with the equation: FTM0_UV = FTM0 / (TM0+1), where the FTM0 is the timer input frequency set by TKI1 and TKI0. For example: (if FTM0 = 2.000MHz, TKI1=TKI0=0) TM0 Frequency 00H Reserved 01H 1.000MHz 02H 667kHz … … FFH 7.84kHz TKI1 TKI0 Selected TM0 input frequency (FTM0_DIV) 0 0 F TM0 / 1 0 1 F TM0 / 4 1 0 F TM0 / 16 1 1 F TM0 / 64

11.2 Timer1

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00CDH TM1 T7 T6 T5 T4 T3 T2 T1 T0   00CFH TM1_CTL STC RL/S - - - TCS1 TKI1 TKI0  Timer 1 is an 8-bit down-count counter. STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload TCS1: select the input clock source of timer1. 0: FOSC, 1: FX32 FTM1_DIV FTM 1 _ DIV FOSC FX32 TM 1_ CTL .2 TKI1 TKI0 FTM1_DIV FTM1 TM1(R) TM1 re- load buffer (W) Control Logic MUX Reload _CTL.1 _CTL.0 FTM1 T M1 TM1 over- flow TM1 TM1 TM1_CTL.7 _ CTL.6TM1 FTM1/1 FTM1/4 FTM1/16 FTM1/64 FTM1_UV, can be calculated with the equation: FTM1_UV = FTM1 / (TM1+1), where the FTM1 is the timer input frequency set by TKI1 and TKI0. For example: (if FTM1 = 2.000MHz,TKI1=TKI0=0) TM1 Frequency 00H Reserved 01H 1.000MHz 02H 667kHz … … FFH 7.84kHz TKI1 TKI0 Selected TM1 input frequency (FTM1_DIV) 0 0 F TM1 / 1 0 1 F TM1 / 4 1 0 F TM1 / 16 1 1 F TM1 / 64

12 Configurable I/O Ports

12.1 Port 0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D2H P0port P07 P06 P05 P04 P03 P02 P01 P00  - Port 0 is combined with 4-bit input port and 4-bit I/O port. P0.7~P0.4 can be programmed as input or output individually. When P0.n (n= 4~7) is configured as an output pin, the P0.n pin would output the logic content of internal P0obuf.n (P0 output buffer). The default value of P0obuf is 0000----b. When the P0.n is configured as output mode, reading P0.n would always read logic ‘0’. When the P0.n is configured as input mode, reading P0.n would always read the logic value from pad. Port 0 Output Buffer Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D2H P0port P07 P06 P05 P04 - - - - -  This register is used to buffer the output value of P0.7 ~ P0.4 in output mode and it is write-only. ※ Bit-manipulation instructions are not available on this register. Port 0 Direction Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D3H P0dir DR7 DR6 DR5 DR4 - - - - -  P0_DR (Port 0 Direction) P0_DR.n = 0: P0.n is configur ed as an input pin. (Default) 1: P0.n is configured as an output pin. ※ Bit-manipulation instructions are not available on this register. Port 0 Pull-high Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D4H P0plh PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 -  1: Enable internal pull-high (default); 0: Disable internal pull-high PHn: Control bit is used to enable the pull-high of P0.n pin. ※ Bit-manipulation instructions are not available on this register. Port 0 Open-Drain Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D5H P0opd OD7 OD6 OD5 OD4 - - - - -  0: Disable open-drain output (CMOS output); 1: Enable open-drain output ODn: Control bit is used to enable the open-drain of P0.n pin. ※ Bit-manipulation instructions not available on this register.

12.2 Port 1

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D6H P1port - - - P14 P13 P12 P11 P10   Port1 is a 5-bit quasi-bi-directional open drain output with internal pull-high resistors. This register is used to buffer resistors will be temporarily disable if the output value is low. ※ Bit-manipulation instructions are not available on this register. Port 1 Pull-high Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D7H P1plh - - - PH4 PH3 PH2 PH1 PH0 -  1: Enable internal pull-high (Default) 0: Disable internal pull-high PHn: Control bit is used to enable the pull-high of P1.n pin. ※ Bit-manipulation instructions are not available on this register.

12.3 Port 2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00D8H P2port P27 P26 P25 P24 P23 P22 P21 P20 -  Port2 is an open drain output port with internal pull-high resist ors. This register is used to buffer the output value of P2.0 ~ P2.7. The pull-high resistors will be temporarily disable if the output value is low. ※ Bit-manipulation instructions are not available on this register.

12.4 High sink output

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00DAH HSOB HSO - - - - - - PS0 -  HSO pad is a high sink current output pin. The HSO PAD output from HSOB or Tone is selected by PS0. HSOB. 7 can set up 1/3 or 2/3 duty cycle by using instruction, writer “1”, through HSO buffer to PAD output High, until writer “0”, and then the output status will change to Low. ※ Bit-manipulation instructions are not available on this register. PS0 (HSOB.0) can set the HSO pad output source as HSO buffer or tone generator. The HSO output waveform can be programmed to any duty cycle by software. MUX HSO PAD 1Tone HSO bufferTM 0 ( R) TM 0 re- load Control Logic Reload Carrier Generator En TM0 under - flow PS 0 PS 0 HSO PAD output source

1 Tone

HSO buffer (HSOB.7) TM 0_ CTL .6 TM 0_ CTL .7 (HSOB.7) (HSOB.0) PS0 If the tone path is selected (PS0=1), the duty cycle of the carrier output is fixed to 50%. . . .TT T = (TM0 + 1) / FOSC The counter underflow frequency of timer0 can be calculated with the equation: FTM0_UV = FTM0 / (TM0reg+1). The FTM0 is Timer0 clock input. For example: FTM0 = 455KHz,TM0reg = 0BH FTM0_UV = FTM0 / (TM0reg+1) = 455K/(0BH+1) = 37.92KHz.

13 LCD Controller/Driver

The MG65L513A can directly drive an LCD with 29 segment output pins and 4 common output pins for a total of 29  4 dots. LCD control register can be us ed to select LCD display configuratio n. LCD driving mode is 1/3 bias and 1/4 duty and frame frequency is about 81.38Hz. When CPU access the LCD RAM ar ea, the access path of the LCD RAM will be transferred from LCD driver to CPU automatically. LCD Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00DEH LCD_CR LCDON - - - - - CKS1 CKS0   LCDON: LCD on/off control bit. 0: off (default), 1:on LCD scan rate, FCOM, is derived from the clock source of divider. The relation between the CKS1, CKS0, F COM and FDIV is shown as below. CKS1 CKS0 Selected FCOM frequency 0 0 F DIV / 96 0 1 F DIV / 6144 1 0 F DIV / 12288 1 1 F DIV / 24576 The LCD frame rate can be calculated with the equation: FFRAME = FCOM / COM No. Typical selection combination for 1/4 duty are shown below: COM No. F DIV_IN Selected FCOM frequency FFRAME 4 6M F DIV / 24576 61.04 4 4M F DIV / 12288 81.38 4 2M F DIV / 6144 81.38 4 32K F DIV / 96 85.33 Segment / IO select Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00DBH SEG_SEL - - - - LVDSEL SSEL2 SSEL1 SSEL0 -  LVDSEL: 0: LVD voltage = 2.1V, 1: LVD voltage = 2.3V LCD Segment Output or IO Select: Function SSEL2 SSEL1 SSEL0 COM3~0 SEG15~0 SEG23~16 SEG 24 25 26 27 28 0 0 0 COM3~0 SEG15~0 SEG23~16 SEG24 SEG25 SEG26 SEG27 SEG28 0 0 1 COM3~0 0 1 0 COM3~0 0 1 1 COM3~0 SEG15~0 SEG23~16 SEG24 P1.1 P1.2 P1.3 P1.4 1 0 0 COM3~0 SEG15~0 SEG23~16 SEG24 SEG25 P1.2 P1.3 P1.4 1 0 1 COM3~0 SEG15~0 SEG23~16 SEG24 SEG25 SEG26 P1.3 P1.4 1 1 0 COM3~0 SEG15~0 SEG23~16 SEG24 SEG25 SEG26 SEG27 P1.4 1 1 1 COM3~0 SEG15~0 SEG23~16 SEG24 SEG25 SEG26 SEG27 SEG28

This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 24/30 MG65L513A Datasheet Version 0.04 There are 16 LCD data RAM in MG65L513A. When the bit valu e of LCD data RAM is “1”, the LCD is turned on. When the bit value of LCD data RAM is “0”, the LCD is turned off. The contents of the LCD data RAM are sent out through the SEG0 to SEG28 pins by a direct memory access. The relationship between the LCD data RAM and SEG/COM pins is shown as below. LCD Data COMX Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM SEG SEG SEG SEG SEG SEG SEG SEG 1000H COM 0 07 06 05 04 03 02 01 00 1001H 15 14 13 12 11 10 09 08 1002H 23 22 21 20 19 18 17 16 1003H RAM RAM RAM 28 27 26 25 24 1004H COM 1 07 06 05 04 03 02 01 00 1005H 15 14 13 12 11 10 09 08 1006H 23 22 21 20 19 18 17 16 1007H RAM RAM RAM 28 27 26 25 24 1008H COM 2 07 06 05 04 03 02 01 00 1009H 15 14 13 12 11 10 09 08 100AH 23 22 21 20 19 18 17 16 100BH RAM RAM RAM 28 27 26 25 24 100CH COM 3 07 06 05 04 03 02 01 00 100DH 15 14 13 12 11 10 09 08 100EH 23 22 21 20 19 18 17 16 100FH RAM RAM RAM 28 27 26 25 24

This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 25/30 MG65L513A Datasheet Version 0.04 1/4 duty 1/3 bias COM0 COM1 COM2 SEGn FRAME VDD VSS VSS VLCD VSS V LCD VLCD VSS COM3 VLCD VLCD VSS VSS VSS VSS VLCD VSS V LCD VSS VLCD 012 01 3012 012330123312

14 Mask Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Fm WDT Bit3: Fm 0 (Fm/2): FCPU clock / 2 1 (Fm): FCPU clock / 1 Bit2: WDT 0 (Disable): Disable watchdog timer function 1 (Enable): Enable watchdog function

This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 27/30 MG65L513A Datasheet Version 0.04 MG65 L513 GND VDD COM0~ COM3 X3 2I 32 kHz X3 2O 20pF 20pF P0.0~P0.7 / RESReset Key Key Pad VDD OSCI 10uF+

820 K ohm

@4 MHz @3V SEG0~ SEG28 LCD Panel 0.1uF 2 ohm VDD HSO High light LED 100 uF P1.0~P1.4 ( SEG24~ 28) 0.1 uF Figure 15-1 Application Circuit - LCD Remote Controller

16.1 Absolute Maximum Rating

Supply Voltage to Ground Potential -0.3 to +5.0 V Applied Input / Output Voltage -0.3 to +5.0 V Power Dissipation 60 mW Ambient Operating Temperature -10 to +50 C Storage Temperature -55 to +150 C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

16.2 DC Characteristics

(VDD-VSS = 3.0 V, FOSC = 4MHz, Ta = 25 C; unless otherwise specified) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Op. Voltage V DD - 1.8 - 3.6 V Op. Current 1 I OP Dual mode, No load, LCD on FCPU = 4MHz - 1.8 5.6 mA Halt Current 1 I STB2 Slow mode, HALT, No load, LCD on, FCPU = 32768Hz, DIVX INT on - 9 12 μA Halt Current 2 I STB3 Slow mode, HALT, No load, LCD off, FCPU = 32768Hz, DIVX INT off - 6 8 μA Stop Current I STB1 STOP mode, No load, LCD off - - 1 μA Input High Voltage V IH - 0.7 V DD - V DD V Input Low Voltage V IL - 0 - 0.3 V DD V Port 0 Drive Current I OH1 V OH = 2.4V, VDD = 3.0V 10 - - mA Port 0 Sink Current I OL1 V OL = 0.4V, VDD = 3.0V 16 - - mA IRO Drive Current I OH2 V OH = 2.4V, VDD = 3.0V 10 - - mA IRO Sink Current I OL2 V OL = 1.0V, VDD = 3.0V 250 - - mA COM, SEG Drive Current I OH3 V OH = 2.7V, VLCD = 3.0V 0.1 2 - mA COM, SEG Sink Current I OL3 V OL = 0.3V, VLCD = 3.0V 0.3 3 - mA P1.0 to P1.4 Sink Current I OL4 V OL = 0.4V, VDD = 3.0V 16 - - mA P2 Sink Current I OL5 V OL = 0.4V, VDD = 3.0V 10 mA P0 Internal Pull-high Resistor R PH1 V IL = 0V 25K 50K 75K  P1~2 Internal Pull-high Resistor R PH2 V IL = 0V 25K 50K 75K  /RES Pull-high Resistor R RES VIL = 0V - 30K -  Low Voltage Detector for LCD VLVD1 VDD > 2.3V 2.2 2.3 2.4 V Low Voltage Detector for uC V LVD0 VDD > 2.1V 2.0 2.1 2.2 V Low Voltage Reset V LVR - 1.7 1.8 1.9 V

16.3 AC Characteristics

PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Built-in CPU Op. Frequency F CPU RC, V DD = 3.0V 0.5 4 6 MHz Frequency Deviation by Voltage Drop for RC Oscillator f f(3.6V) - f(2.6) f(3.0V) - 3 10  POR Duration T POR F OSC = 4 MHz - 4 1 mS System Start-Up Time T SST Power-up, reset - 16384 - 1/F CPU System Wake-Up Time T SWT Wake-up from STOP mode 256 - 16384 1/F CPU

This document information is the intellectual property of Megawin Technology.  Megawin Technology Co., Ltd. 2011 All right reserved. QP-7300-03D 30/30 MG65L513A Datasheet Version 0.04 Revision Page Descriptions Date V0.01 Datasheet release 2012/02/01 V0.02 Modify halt mode current 2012/03/01

Product Information

MG65L513A specifications and overview.

Summary

Watchdog timer built-in

Description

Watchdog timer built-in

Source title MG65L513A Datasheet(PDF) - Megawin Technology Co., Ltd

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