MG20U201ASC1 MEGAWIN | Alldatasheet
Document overview
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- PDF pages: 10
Technical content
Datasheet sections
- 1 Description
- 2 Order Information
- 3 Application Field
- 4 Pin Description
- 4.1 Pin Definition
- 4.2 Pin Configuration
- 5 Block Diagram
- 6 Application Circuit
- 7 Application Information
- 8 Absolute Maximum Rating
- 9 Electrical Characteristics
- 10 Package Dimension
- 10.1 SOP8 Package Dimension
- 11 Revision History
(Preliminary) MG20U201 Switching Regulator LED Driver This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. © Megawin Technology Co., Ltd. 2013 All rights reserved. 2013/06 version 0.40 MG20U201 Data Sheet Version: V0.40
2 MG20U201 Data Sheet MEGAWIN
Features
z Operation voltage, 7.0V ~ 200V z PWM dimming control z Open loop current peak detector z Provide constant frequency or constant off-time control
4 MG20U201 Data Sheet MEGAWIN
1 Description
The MG20U201 is a current feedback control, buck type LED driver IC. It achieves good output current regulation without the need of external compensation components. The MG20U201 integrates a HV start-up circuit, 7.0V ~ 200V linear regulator, precision comparator, PWM control and ring oscillator into one chip. With those building circ uits, a precision current output buck mode converter with dimming control (PWM type) can be ea sily achieved with only few external components. The PWM dimming range is 0~100% duty at a frequency of up to 10KHz. The chip is available in 8-pin SOP package.
2 Order Information
3 Application Field
DC-DC LED driver application Backlighting LED driver General-purpose constant current source
MEGAWIN MG20U201 Data Sheet 5
4 Pin Description
4.1 Pin Definition
1 VIN 7.0V ~ 200V high voltage input. 2 CS Current sense input pin. 3 GND Ground pin. 4 GATE Driver for external power MOS. 5 PWM PWM dimming input. 6 VDD Regulated core supply. 7 NC No connection. 8 RT Ring oscillator bias input. When RT is connected to ground via a resistor, the MG20U201 operates in constant frequency mode. When the resistor is connected between RT & GATE, t he MG20U201 operates in constant off-time mode.
4.2 Pin Configuration
5 Block Diagram
R S Q RST CS GND GATE PWM RT 0.25V
6 MG20U201 Data Sheet MEGAWIN
6 Application Circuit
7 Application Information
The MG20U201 integrates one high voltage regulator to generate the power for internal core logic. The internal power is taken from the high voltage input direct ly. When a voltage (7~200V) is applied at the VIN pin, the regulator maintains a constant 5. 6V at the VDD pin. The VDD pin must be bypassed by a low ESR capacitor to provide a low impedance path for the high frequency current of the output date driver. Since the current driving capability of the regulator is limited to around 0.7mA. It’s not suitable for driving the external components. User must make sure the swit ching frequency should not be too high and the load at the GATE pin should not be too heavy. It’s recommended to add a pull-high resistor (R P) between V INDC and VDD pin to provide more driving current for large ILED application. Selection of the Switching Control Scheme The MG20U201 provides two control schemes, constant frequency and constant off time. For a buck converter, the duty of PWM control signal is determined as D = VO / VIN, where VO is the voltage drop on LED strings (V LED). For a heavy load application (large V LED drop, D>0.45), user should select the constant off time mode. Selection of the Switching Frequency (F Rule of thumb, the range of 20KHz ~ 100KHz is recommended. For detail frequency setting, please check design assistant file “MG20U201 DesignAssistantFileV1_0.xls”. GATE Output The GATE output of the MG20U201 is used to driv e an external MOSFET. It is recommended that the gate charge QG of the external MOSFET should satisfy the equation as below:
MEGAWIN MG20U201 Data Sheet 7 (VINDC - 5.6V)/RP + 0.7mA >= Fs*QG In the above equation, QG is the GATE charge of the external FET obtained from the manufacturer’s datasheet. Selection of the Sense Resistor (RCS) The MG20U201 is an open loop buck converter with pe ak current control. The peak current is decided by the equation IPEAK+ = VCSTH / RCS, where VCSTH is around 0.27V. The average current (ILED) is described as follow: The △ILED is determined by TOFF, L value and VLED load. ILED IPEAK+ IPEAK- TON TOFF △I LED
8 MG20U201 Data Sheet MEGAWIN
8 Absolute Maximum Rating
VIN to GND -0.5 to +225 V VDD to GND 7 V CS, PWM, GATE, RT to GND -0.3 to (VDD + 0.3) V Junction Temperature -40 to +125 °C Storage temperature -55 to +155 °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
9 Electrical Characteristics
All typical numbers are at Ta=25°C and VIN=12V, unless otherwise noted. Parameter Sym. Conditions Min. Typ. Max. Unit Input DC supply voltage range VINDC DC input voltage 7.0 - 200 V Shut down mode supply current IINSD PWM=0 - 0.5 - mA Operating Current IOP V IN > 7.5V, ROSC=226K and CGATE=500P - 0.8 1.2 mA Internal Regulator Internally regulated Voltage VDD V IN =7.5V ~ 200V, ROSC=226K, CGATE = 500pF, No load in pin VDD 5.0 5.6 6.0 V Maximal pin VDD voltage VDDMAX When an external voltage applied to pin VDD - - 7.0 V Output current of the regulator ISOURCE V DD = 5.6V - 0.7 - mA VDD under-voltage lockout threshold V UVLO V IN rising - 5.30 - V VDD under-voltage lockout hysteresis ΔUVLO V IN falling 100 300 500 mV PWM Dimming Pin PWM input high voltage VPWM (H) V IN =7.5V ~ 200V 2.0 - - V Pin PWM input low voltage VPWM (L) V IN =7.5V ~ 200V - - 0.8 V Pin PWM pull-down resistance RPWM V DD =5.5V 50 100 150 KΩ PWM signal duty DPWM 0 - 100 % Current Sense Input Ta= 0°C to +125°C, VDD = 5.6V 255 275 285 mV Current sense pull-in threshold voltage V CSTH Ta= -40°C, VDD = 5.6V 200 - - mV Offset voltage of comparator VOS -20 - 20 mV
MEGAWIN MG20U201 Data Sheet 9 Electrical Characteristics (continued) Current sense blanking interval tBLANK V CS=0.55 VDD 150 215 285 nS Delay from CS trip to GATE IO tDELAY V CS= VCSTH +50mV after tBLANK - - 300 nS Gate Driver GATE output high voltage VGATE (H) VDD -0.4 - - V GATE output low voltage VGATE (L) - - 0.4 V GATE output high driving current I GATE (H) V GATE= VDD-0.4V - 10 - mA GATE output low sinking current I GATE (L) V GATE= 0.4V - 25 - mA GATE output rise time tRISE C GATE = 500pF - 30 50 nS GATE output fall time tFALL C GATE = 500pF - 30 50 nS Oscillator ROSC= 1.0MΩ 22K 27K 32K Oscillator frequency FOSC ROSC= 226KΩ 90K 110K 120K Hz
10.1 SOP8 Package Dimension
V0.10 Initial release. 2012/03/07 V0.20 Modify the minimum operation voltage. 2012/10/01 V0.30 Modify the supply voltage range. 2013/03/05 V0.40 Modify the application circuit and add gate output notification. 2013/06/17