Power Management

MFS5600AVMA0EP

NXP Semiconductors

Automotive buck regulator and controller with voltage monitors and watchdog timer Rev. 4 - 29 April 2024

Manufacturer: NXP Semiconductors

Document: 118 Pages / 2Mb

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FS5600_V01 NXP | Alldatasheet

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PDF pages: 118

Technical content

Datasheet sections

1 General description
2 Features and benefits
2.1 Overview
3 Applications
4 Ordering information
5 FS5600 internal block diagram
6 Regulator input configurations
7 Pinout and pin description
8 ESD ratings
9 Thermal characteristics
10 Device level electrical parameters
11 SW1: 36 V integrated FET DC-DC
11.1 SW1 electrical specifications
11.2 SW1 external component selection
11.3 SW1 operation
11.3.1 Output voltage selection
11.3.2 PFM and pulse skipping operation
11.3.3 PFM operation
11.3.4 Soft-start
11.3.5 Current limit protection
11.3.6 Compensation selection
11.3.7 SW1 fault monitoring
12 SW2: 36 V DC-DC controller with
12.1 SW2 electrical characteristics
12.2 SW2 operation
12.2.1 SW2 external component selection
12.2.1.1 Compensation network
12.2.1.2 Inductor current sense selection
12.2.2 Output voltage selection
12.2.3 Pulse skipping operation
12.2.4 PFM operation
12.2.5 Soft-start
12.2.6 Current limit protection
12.2.7 Slope compensation
12.2.8 SW2 fault monitoring
13 BIAS_IN input
14 FS5600 clock management
14.1 FS5600 clock electrical characteristics
14.2 High frequency oscillator
14.3 Spread spectrum
14.4 SW1 and SW2 switching frequency
14.5 External clock synchronization
14.6 SYNCOUT function settings
15 I/O pins in FS5600
15.1 I/O pins electrical specifications
15.2 EN1 and EN2
15.2.1 Programming turn-off delay
15.3 PGOOD1 and PGOOD2
15.4 GPIO1/2/3
15.5 MODE pin
15.6 I2C communication
16 Thermal protection
17 Functional safety features in FS5600
17.1 GPIO1/2/3 feature selection
17.2 OV/UV monitors
17.2.1 VMON1-4 electrical specifications
17.3 Watchdog
17.3.1 Simple watchdog
17.3.2 Challenger watchdog
17.3.3 Watchdog error counter and error impact
17.3.4 Watchdog refresh counter
17.4 FCCU monitoring
17.4.1 BI_STABLE protocol with FCCU1 and
17.4.2 Single/independent FCCU monitoring
17.4.3 FCCU status reporting via interrupt register
17.5 External signal monitoring using ERRMON
17.6 PGOOD1/2 programmable reactions for
17.6.1 Watchdog impact on PGOOD1/2
17.7 FS0B pin
17.7.1 FS0B pin electrical specifications
17.8 PGOOD1, PGOOD2, FS0B stuck at fault
17.9 I2C robustness
17.9.1 I2C CRC verification
17.9.2 NOT logic registers
17.10 I2C write protection
17.11 Fault error counter
17.12 Latent failure detection
17.12.1 Analog built-in self-test (ABIST)
17.12.2 On-demand ABIST
17.12.3 Logical built-In self-test (LBIST)
17.12.4 VCC and VDIG monitoring
17.13 FS5600 operation states and state machine
17.13.1 Shutdown mode
17.13.2 Built-in self-test (BIST)
17.13.3 Power-up
17.13.4 Power-up in Debug mode
17.13.5 INIT_RUN
17.13.6 Normal state
17.13.7 Deep fail-safe state
17.13.8 Power-down
17.13.9 Low-power operation
17.13.9.1 Ultra low-power operation
17.13.10 State transition table
18 I2C register map
18.1 Register descriptions
18.1.1 SW1CTRL register
18.1.2 NOT_SW1CTRL register
18.1.3 SW2CTRL register
18.1.4 NOT_SW2CTRL register
18.1.5 GPIO_CTRL register
18.1.6 NOT_GPIO_CTRL register
18.1.7 CLOCK_CTRL register
18.1.8 NOT_CLOCK_CTRL register
18.1.9 WATCHDOG_CTRL1 register
18.1.10 NOT_WATCHDOG_CTRL1 register
18.1.11 WATCHDOG_CTRL2 register

Automotive buck regulator and controller with voltage monitors and watchdog timer Rev. 4 — 29 April 2024 Product data sheet

1 General description

The FS5600 integrates a battery connected DC-DC controller with external FETs and a battery connected DC- DC converter with internal FETs. It also offers functional safety features such as independent voltage monitors, windowed watchdog timer, I/O monitoring via ERRMON and FCCU, and built-in self-test.

2 Features and benefits

2 x high-voltage buck converters: – Buck controller - external FETs - 900 mA gate drive - up to 15 A load capability – Buck regulator - internal FETs - 3 A+ load capability – ±2 % output accuracy – 250 kHz to 3 MHz switching frequency
High-efficiency PFM mode
Safety features: – Available in enhanced ASIL B, ASIL B, and QM variations – Two internal and up to four high-accuracy external voltage monitors – Windowed watchdog timer – ERRMON and FCCU monitoring – 2 x PGOOD and 1 x FS0B outputs – ABIST and LBIST for latest failure check
GPIOs for seamless operation with PF PMICs
Rated from –40 °C to 150 °C TJ
32-Ld 5 mm x 5 mm QFN
AEC-Q100 Grade-1 Qualified

2.1 Overview

Automotive buck regulator and controller with voltage monitors and watchdog timer

3 Applications

QM to ASIL D automotive applications such as:

Infotainment / cluster / driver awareness
Telematics
V2X
Radar
Vision
ADAS
Sensor fusion Additional safety mechanisms may be needed for ASIL D compliance in the system level. FS5600 is developed to meet ASIL B requirements. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

4 Ordering information

system level. Additional safety mechanisms may be needed at the system level for ASIL D compliance.

4 External Voltage Monitors (VMON) No Yes Yes

Table 2. Ordering information...continued NXP’s latest graphical user interface and socketed evaluation board. third party are allowed to program the device for production purposes. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

5 FS5600 internal block diagram

20 MHz & 100 kHz

6 Regulator input configurations

7 Pinout and pin description

The FS5600 is offered in a 32-Ld 5 mm x 5 mm WF-QFN package. Figure 4. QM version pinout Figure 5. ASIL B, and enhanced ASIL B version pinout FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

6 SW2FB

internal resistor divider for SW2 outputs ≤ 5.5 V.

10 SW2LX

gate of external high side MOSFET. purpose output (GPO3) available in QM version. purpose output (GPO2) available in QM version. Table 3. Pin description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Fail-safe Output pin. Open drain.

25 SW1FB

internal resistor divider for SW1 outputs ≤ 5.5 V.

26 PGOOD1 PGOOD1 output from monitoring of selected

27 PGOOD2 PGOOD2 output from monitoring of selected

28 VDIG

Output of internal regulator for powering logic.

29 BIAS_IN

30 VCC

µF capacitor. No external loading permitted.

31 MODE/SYNCIN

8 ESD ratings

Table 4. ESD ratings This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. This is an ESD sensitive device, improper handling can cause permanent damage to the part. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

9 Thermal characteristics

Table 5. Temperature range Table 6. QFN32 thermal resistance and package dissipation ratings significant hot spots on the die. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

10 Device level electrical parameters

specified at 25 °C, unless otherwise noted. Quiescent Current (non-switching), SW1 & SW2 in PFM. BIAS_IN connected to 5 V. ULPM Mode. Quiescent Current (non-switching), SW1 in PFM. SW2 disabled. BIAS_IN connected to 5 V. ULPM Mode. Quiescent Current (non-switching), SW2 in PFM. SW1 disabled. BIAS_IN connected to 5 V. ULPM Mode. Table 7. Device level electrical parameters [1] In the absence of BIAS_IN, VIN falling below this voltage will cause FS5600 to power off. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11 SW1: 36 V integrated FET DC-DC converter

current limit. Figure 6 shows a high-level block diagram of SW1. Figure 6. SW1 high-level block diagram gates. EN1 controls the enable of the SW1 regulator.

11.1 SW1 electrical specifications

Table 8. SW1 electrical specifications...continued

11.2 SW1 external component selection

Table 9 provides the recommended external components for the SW1 regulator. Table 9. SW1 external component selection See Section 14.4 for switching frequency selection.

11.3 SW1 operation

for high efficiency and low solution cost.

11.3.1 Output voltage selection

The output voltage of SW1 may be set via OTP using the OTP_SW1_VOLT[7:0] bits. SW1FB pin directly to the output voltage in this case. calculated internally based on the output voltage. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 7. SW1 output voltage setting using an external resistor divider Table 10. OTP_SW1_VOLT[7:0] selection FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11.3.2 PFM and pulse skipping operation

regulation. The minimum on-time of the high side FET is programmable via the OTP_SW1_MIN_TON[1:0] bits. OTP_SW1_MIN_TON[1:0] = 0b01 is the recommended default value that is optimal for most applications. Table 11. OTP_SW1_MIN_TON[1:0] selection In addition, the controller starts to switch at half of the selected frequency when the VIN/VOUT ratio is above 6. This allows reduced ripple operation compared to pulse-skipping.

11.3.3 PFM operation

SW1_MODE[1:0] is loaded from OTP_SW1_MODE[1:0].

00 PFM

11 PWM

Table 12. SW1_MODE[1:0] selection. between the pin and register bits, do not use SW1_MODE[1:0] to change the operating mode. On-time of the pulses in PFM mode is configurable using the OTP_SW1_PFM_TON[1:0] bits. Table 13. OTP_SW1_PFM_TON[1:0] selection FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 13. OTP_SW1_PFM_TON[1:0] selection...continued

11.3.4 Soft-start

time is programmable via OTP using the OTP_SW1_SS[1:0] bits. See Table 8 for values.

11.3.5 Current limit protection

OTP using the OTP_SW1_ILIM_SEL[1:0] bits. See Table 8 for values.

11.3.6 Compensation selection

interpolation for values between the ones shown in Table 14. Table 14. SW1 compensation selection FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 15. OTP_SW1_SLOPECOMP[1:0] Value Table 16. OTP_SW1_GM_COMP[1:0] Value Table 17. OTP_SW1_PWM_R_COMP[2:0] Value

11.3.7 SW1 fault monitoring

in SW1. See Table 8 for monitoring thresholds. OTP_SW1_OV_PGOOD2 = 1, an overvoltage fault on SW1 asserts PGOOD2. OTP_SW1_UV_PGOOD2 = 1, an undervoltage fault on SW1 asserts PGOOD2. detected. The latch bits can be cleared by writing a 1 to them. SW1_UV_RT and SW1_OV_RT read-only bits indicate the real-time status of the faults. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12 SW2: 36 V DC-DC controller with external FETs

inductor and current sense circuitry, load currents of up to 15 A can be drawn without entering current limit. Figure 8. SW2 high-level block diagram

12.1 SW2 electrical characteristics

Table 18. SW2 electrical characteristics...continued

12.2 SW2 operation

Rds(on) N-channel high and low side MOSFETs for low cost and high efficiency.

12.2.1 SW2 external component selection

Table 19 provides the recommended external components for the SW2 regulator. Table 19. SW2 recommended external components of up to 15 A. Refer to the schematic of KITFS5600FRDMEVM for a design that can support 15 A. See Table 20 for guidance on the MOSFET selection. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

2.2 MHz < 5 A

Table 20. MOSFET selection See Section 14.4 for switching frequency selection.

12.2.1.1 Compensation network

frequency capacitor (Chf) placed from SW2COMP to Ground can be used in addition to the R-C network. Refer to the table below for recommended compensation values for typical use case conditions. Table 21. SW2 Compensation selection Select logical level NMOS (threshold voltage < 2.5 V). Use closest standard values for resistor and capacitors. The gate drive comes from VCC (5 V).

12.2.1.2 Inductor current sense selection

12.2.1.2.1 Using current sense resistor

Figure 9. SW2 application schematic with Rshunt current sensing OTP_SW2_ILIM = 80 mV and Rshunt = 0.01 Ω, the peak current limit is 8.0 A.

12.2.1.2.2 Inductor DCR current sense

and less accuracy means a wider current limitation range. Figure 10. DCR current sense with a single capacitor series resistance, the voltage across C1 is directly proportional to the inductor current. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Example: For an inductor L = 4.7 μH and RDCR = 7 mΩ, R1 = 6.7 kΩ and C1 = 100 nF. With OTP_SW2_ILIM = 0b11, the minimum SW2CSP-SW2CSN voltage where a current limit occurs is 150 mV. With 7 mΩ DCR, this is equivalent to a peak current limit of 150 mV / 7 mΩ = 21.4 A. To maintain a proper signal-to-noise ratio, choose an inductor with a DCR of at least 6 mΩ.

12.2.2 Output voltage selection

Output voltage of SW2 may be set via OTP using the OTP_SW2_VOLT[5:0] bits. voltage. Use the same equation for the external divider as for SW1. Table 22. OTP_SW2_VOLT[5:0] Selection FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

110111 Reserved. Do not use. 111001 Reserved. Do not use. 111010 Reserved. Do not use. 111011 Reserved. Do not use. 111100 Reserved. Do not use. 111101 Reserved. Do not use. 111110 Reserved. Do not use. Table 22. OTP_SW2_VOLT[5:0] Selection...continued FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

111111 Reserved. Do not use.

12.2.3 Pulse skipping operation

regulation. The minimum on-time of high side FET is programmable via the OTP_SW2_TON_MIN[1:0] bits. Table 23. OTP_SW2_TON_MIN[1:0] Selection

12.2.4 PFM operation

SW2_MODE[1:0] is loaded from OTP_SW2_MODE[1:0]. Table 24. SW2_MODE[2:0] selection SW2_MODE[1:0] to change the operating mode to avoid conflicts between the pin and the register bits. On-time of the pulses in PFM mode is configurable using the OTP_SW2_PFM_TON[1:0] bits. Table 25. OTP_SW2_PFM_TON[1:0] Selection FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12.2.5 Soft-start

programmable via OTP using the OTP_SW2_SS bit. See Table 18 for values.

12.2.6 Current limit protection

using the OTP_SW2_ILIM[1:0] bits. See Table 18 for values.

12.2.7 Slope compensation

Section 12.2.1 "SW2 external component selection" for values to use based on operating conditions. Table 26. OTP_SW2_SLOPECOMP[5:0] selection FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12.2.8 SW2 fault monitoring

SW2. See Table 18 for monitoring thresholds. OTP_SW2_OV_PGOOD2 = 1, an overvoltage fault on SW2 asserts PGOOD2. OTP_SW2_UV_PGOOD2 = 1, an undervoltage fault on SW2 asserts PGOOD2. detected. The latch bits can be cleared by writing a 1 to them. SW2_UV_RT and SW2_OV_RT read-only bits indicate the real-time status of the faults. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Automotive buck regulator and controller with voltage monitors and watchdog timer

13 BIAS_IN input

An external voltage between 3.7 V and 5.5 V can be applied at the BIAS_IN pin to reduce power consumption in the FS5600. When a valid voltage at BIAS_IN is detected, VCC is powered directly from the BIAS_IN path, eliminating the power dissipation in the high-voltage LDO from VIN to VCC. In the application, if either SW1 or SW2 is set to 5.0 V on the output, NXP recommends connecting that output to BIAS_IN. If an external 5 V is available in the system, that may be connected to BIAS_IN. Ensure that the BIAS_IN voltage does not exceed 5.5 V. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

14 FS5600 clock management

Low-power 100 kHz clock
Internal high frequency clock with programmable frequency
Phase-Locked Loop (PLL)
A digital clock management interface is in-charge of supporting interaction among these blocks. Figure 11 shows a high-level block diagram of the clock management system. aaa-037157 Internal Oscillator (Spread spectrum, Freq tuning) Divider /1 (OTP_FSYNC_RANGE = 1) /6 (OTP_FSYNC_RANGE = 0) Divider 2 /48 (OTP_CLK2_DIV = 0) /64 (OTP_CLK2_DIV = 1) SYNCIN Divider /48 OSC_MAIN/48 CLOCK monitoring SW1 PLL x 48 out in enable CLK CLK_FIN_DIV EXT_FIN_SEL Divider 1 /8 (OTP_CLK1_DIV = 0) /9 (OTP_CLK1_DIV = 1) CLK1 CLK1 CLK2 SYNCOUT 1CLK2 OTP_SW1_CLKSEL OTP_SW2_CLKSEL SW2 CLK1 0 1CLK2

Figure 11. Clock management system high-level block diagram

14.1 FS5600 clock electrical characteristics

parameters are specified at VIN = 12 V, Tj = 25 °C unless otherwise noted. Table 27. FS5600 clock electrical characteristics FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 27. FS5600 clock electrical characteristics...continued

14.2 High frequency oscillator

0101 Not used

0110 Not used

0111 Not used

1000 Not used

1101 Not used

1110 Not used

1111 Not used

14.3 Spread spectrum

OTP_FSS_EN and can be subsequently changed via I2C.

14.4 SW1 and SW2 switching frequency selection

The 20 MHz clock is divided internally to form CLK1 and CLK2 as shown in the block diagram. CLK1 uses a divide ratio of 8 if OTP_CLK1_DIV = 0 and a divide ratio of 9 if OTP_CLK1_DIV = 1. CLK2 uses a divide ratio of 48 if OTP_CLK2_DIV = 0 and a divide ratio of 64 if OTP_CLK2_DIV = 1. assigned to either CLK1 or CLK2. Refer to the table below for the available combinations. Table 29. SW1 and SW2 switching frequency selection

14.5 External clock synchronization

The MODE/SYNCIN pin can be configured as SYNCIN via OTP by setting OTP_MODE_SYNCINB = 0. internal high frequency oscillator or the SYNCIN pin as its source based on the validity of the external clock. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Automotive buck regulator and controller with voltage monitors and watchdog timer A frequency watchdog monitors the external clock at the SYNCIN pin. If the external clock is not present or invalid, the device automatically switches to the internal clock. The device switches back to the external clock if the frequency watchdog detects a valid input. When the external clock is selected, the switching regulators should be set in PWM mode at the application level to ensure clock synchronization.

14.6 SYNCOUT function settings

The GPIO2 pin may be configured as SYNCOUT via OTP by setting OTP_GPIO2_CFG[1:0] = 0b10. When configured as SYNCOUT, GPIO2 outputs the clock that the SW1 regulator uses (in terms of phasing and frequency) in a push-pull mode railing to VDDIO and ground. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

15 I/O pins in FS5600

through Section 15.6. Parametric requirements for all the IO's are summarized in Section 15.1.

15.1 I/O pins electrical specifications

otherwise noted. Typical values are specified at 25 °C, unless otherwise noted. Table 30. I/O pin electrical specifications

15.2 EN1 and EN2

SW1 and SW2 to be performed through their respective ENx pin, or via the respective I2C bit SWx_EN. SW1 regulator is disabled if (EN1 pin = LOW). SW1 regulator is disabled if (EN1 pin = HIGH AND SW1_EN = 0). SW1 regulator is enabled if (EN1 pin = HIGH AND SW1_EN = 1). SW2 regulator is disabled if (EN2 pin = LOW). SW2 regulator is disabled if (EN2 pin = HIGH AND SW2_EN = 0). SW2 regulator is enabled if (EN2 pin = HIGH AND SW2_EN = 1). SW1/2_EN are initialized to 1. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Automotive buck regulator and controller with voltage monitors and watchdog timer When OTP_SW1_PULLDN_B = 0, a pulldown resistor of 500 Ω is engaged on the output if SW1 is disabled. Similarly, when OTP_SW2_PULLDN_B = 0, a pulldown resistor of 500 ohm is engaged on the output if SW2 is disabled. The output is disabled in high-Z if OTP_SWx_PULLDN_B = 1.

15.2.1 Programming turn-off delay

When OTP_SW1_OFF_DELAY = 0, SW1 is turned off after EN1 goes low. When OTP_SW2_OFF_DELAY = 0, SW2 is turned off after EN2 goes low. When OTP_SW1_OFF_DELAY = 1, SW1 is turned off 32 ms after EN1 goes low. When OTP_SW2_OFF_DELAY = 1, SW2 is turned off 32 ms after EN2 goes low. The 32 ms setting is useful when other devices are to be powered down in the system prior to turning off the pre-regulators.

15.3 PGOOD1 and PGOOD2

For the QM variation of FS5600, PGOOD1 is used to indicate the voltage regulation status of SW1 and PGOOD2 is used to indicate the voltage regulation state of SW2. PGOOD1 is asserted low when the OV or UV monitor for SW1 indicates a faulty voltage. See Table 8 for OV/ UV thresholds. PGOOD2 is asserted low when the OV or UV monitor for SW2 indicates a faulty voltage. See Table 18 for OV/UV thresholds. The delay from SW1/2 reaching regulation to PGOOD1/2 being released high is programmable. See Section 15.4 for details. PGOOD1 and PGOOD2 are open-drain outputs and need an external pullup resistor. For the ASIL B, and Enhanced ASIL B variations, behavior of PGOOD1 and PGOOD2 can be programmed to indicate status of other safety functions. See Section 17.6 for details.

15.4 GPIO1/2/3

Pins 4, 14 and 13 are available as GPO1, GPO2, and GPO3 respectively in the QM variation. They can be sequenced as part of the device power up to control external devices. The pins can be configured to perform other functions in the ASIL B and Enhanced ASIL B versions. OTP_GPO1/2/3_DELAY[2:0] sets the delay from SW1 or SW2’s soft-start ramp start (which occurs first) to GPO1/2/3 being released high. GPIO1/2/3_OUTPUT bit is set high internally, if programmed as part of the start-up based on the OTP_GPIO1/2/3_DELAY[2:0] bits, and can be changed by the user via I2C after power-up. After power-up, the GPIO1/2/3 pins may be toggled via I2C using the bits GPIO1_OUTPUT, GPIO2_OUTPUT and GPIO3_OUTPUT respectively. When both EN1 and EN2 are brought low, the GPOs power down in the reverse sequence of their power-up delays. GPO1/2/3 pins are open-drain and need an external pullup resistor. GPIO2 pin can be configured as SYNCOUT in a push-pull mode. See Section 14.6 for details. PGOOD1/2 can also be delayed during start-up as shown in Table 31. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

000 GPO1/2/3 held low through power-up. No additional delay for PGOOD1/2 release. Table 31. PGOOD1/2, GPIO1/2/3 delay selection

15.5 MODE pin

The MODE/SYNCIN pin can be configured as a MODE input via OTP by setting OTP_MODE_SYNCINB = 1. The switching mode of SW1 and SW2 regulators can be changed by toggling with MODE pin. When MODE = 0, SW1 and SW2 operate in continuous PWM mode. and SW2 respectively in this condition.

15.6 I2C communication

500 Ω for 3.4 MHz operation. communication. The default I2C device address is set by the OTP_I2C_ADD[2:0]. Table 32. I2C address selection FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

16 Thermal protection

processor during subsequent power-up. the thermal shutdown state (no power down sequence). Table 33. Thermal protection characteristics FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

17 Functional safety features in FS5600

Four high precision voltage monitors (in addition to monitoring of SW1 and SW2 internally)
Challenger windowed watchdog timer
FCCU monitoring
2x ERRMON monitoring for external signal monitoring
Fail-safe Output (FS0B) with programmable fault reaction
PGOOD1 and PGOOD2 outputs with programmable fault reaction
Stuck-at-fault detection on PGOOD1, PGOOD2, and FS0B outputs
State machine with programmable fault reactions
Redundant band gap with band gap comparator for self-test
Internal oscillator self-test
Built-in self-test (ABIST and LBIST) of analog and digital monitoring functions for latent failure diagnostics
On-Demand ABIST
CRC on OTP bits in the device
I2C with CRC
NOT register functionality to prevent accidental writes to critical registers
Monitoring of internal voltages such as VCC and VDIG for over and under voltage faults

17.1 GPIO1/2/3 feature selection

Table 34, Table 35, and Table 36.

00 Output is high Z

01 GPO (output)

10 ERRMON1 (input)

11 Reserved (do not use)

Table 34. GPIO1 function selection

00 GPO (output)

01 FCCU1 (input)

10 SYNCOUT (output)

11 VMON3

01 FCCU2 (input)

10 ERRMON2 (input)

11 VMON4

Table 36. GPIO3 function selection

17.2 OV/UV monitors

voltage threshold for VMON1, VMON2, VMON3, and VMON4. using the OTP_VMONx_UV_DB[1:0] and OTP_VMONx_UV_DB[1:0] bits. An external resistor divider must be used to set the mid-point of the resistor divider to 0.6 V nominally. The OV and UV thresholds shown below are with respect to 0.6 V.

17.2.1 VMON1-4 electrical specifications

specified at 25 °C, unless otherwise noted. Table 37. VMON1-4 electrical specifications FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

17.3 Watchdog

available only in the Enhanced ASIL B version. The Watchdog timer is enabled by setting OTP_WD_DIS = 0. The Watchdog timer is disabled if OTP_WD_DIS = 1. Challenger scheme is selected. must occur during the OPEN window.

Wrong watchdog answer during the OPEN window
No watchdog refresh during the OPEN window
Good or bad watchdog answer during the CLOSED window. For a watchdog refresh to be considered valid (good), the refresh must occur with the right answer during the right time (OPEN window). This is represented on the figure below. aaa-037158 Bad data Good data None WD_failure WD_failure No issue WD_failure Closed Opened WD_Window Closed window Opened window WD window period with DC configurable WD_OK WD_failure Watchdog Answer (from MCU)

Figure 12. Windowed watchdog concept After a good or a bad watchdog refresh, a new window period starts immediately. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

The duration of the watchdog window is configurable from 1 ms to 1024 ms with the WD_WINDOW [3:0] bits.

0000 DISABLE (during INIT_FS only)

Table 38. Watchdog window period configuration The duty cycle of the watchdog window is configurable from 31.25 % to 68.75 % with the WDW_DC [2:0] bits. The new duty cycle is effective after the next watchdog refresh. Table 39. Watchdog window duty cycle configuration FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 39. Watchdog window duty cycle configuration...continued

17.3.1 Simple watchdog

WD_ANSWER register during the OPEN watchdog window. is incremented and the watchdog window is restarted. See Section 17.3.3 for watchdog error counter. communication error (I2C_REQ_ERR = 1) is reported if writes of 0x0000 and 0xFFFF are attempted.

17.3.2 Challenger watchdog

WD error counter is incremented, the watchdog window is restarted and the LFSR value is not changed. results in the WD_ANSWER register in the OPEN window for a valid watchdog refresh. Figure 13. Challenger watchdog formula

17.3.3 Watchdog error counter and error impact

counter is used to count the number of bad watchdog refreshes (data and temporal errors). behavior converges to a failure detection. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

WD_ERR_LIMIT[1:0] register as shown in the table below. Table 40. Watchdog error counter The watchdog error counter value can be read by the MCU for diagnostic with the WD_ERR_CNT[3:0] register. only if OTP_WD_PGOOD1/2 = 1.

00 Stay in NORMAL STATE

01 Transition to INIT_RUN state or Remain in INIT_RUN

10 Transition to deep fail-safe state

11 Stay in NORMAL STATE

Figure 14. Watchdog error counter configurations

17.3.4 Watchdog refresh counter

time there is a wrong refresh watchdog, the watchdog refresh counter is reset to ’0’. the WD_RFR_LIMIT[1:0] register. Table 42. Watchdog refresh counter configuration The watchdog refresh counter value can be read by the MCU for diagnostics with the WD_RFR_CNT[2:0] bits. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 15. Watchdog refresh counter configurations See Section 17.11 on Fault Error Counter for impact of watchdog refresh on the fault error counter value.

17.4 FCCU monitoring

= 0b01 configures GPIO2 as FCCU1. OTP_GPIO3_CFG[1:0] = 0b01 configures GPIO3 as FCCU2. output coming from other MCUs. FCCU can be configured by pair, or single independent inputs. thestate machine for reactions based on FCCU monitoring.

17.4.1 BI_STABLE protocol with FCCU1 and FCCU2

a bi-stable protocol used in the NXP MCUs for FCCU is enabled. The bi-stable protocol representation is shown in Figure 16. Figure 16. FCCU 1/2 bi-stable protocol example FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

When FCCU12_FLT_POL = 0, FCCU1 = 0 or FCCU2 = 1 is a fault
When FCCU12_FLT_POL = 1, FCCU1 = 1 or FCCU2 = 0 is a fault The FS0B is asserted when an FCCU fault is detected and the state machine returns to INIT_RUN state. It is possible to program the PGOOD1 and PGOOD2 pins to also toggle during an FCCU fault if they are programmed to do so via OTP. PGOOD1/2 may be used to assert RESET of the MCU in this case. See Section 17.6 on PGOOD for details.

17.4.2 Single/independent FCCU monitoring

When FCCU12_BISTABLE = 0, FCCU1 and FCCU2 may be used for independent signal monitoring. Either or both FCCU pins may be used in this configuration.

When FCCUx_FLT_POL = 0, LOW level on FCCUx is a fault
When FCCUx_FLT_POL = 1, HIGH-level on FCCUx is a fault The FS0B pin is asserted when an FCCU fault is detected and the state machine returns to INIT_RUN state. It is possible to program the PGOOD1 and PGOOD2 pins also to assert during an FCCU fault. PGOOD1/2 may be used to assert RESET of the MCU in this case.

17.4.3 FCCU status reporting via interrupt register

summarizes the error scenarios for FCCU1/2. Table 43. FCCU1/2 status reporting error scenarios

17.5 External signal monitoring using ERRMON

When OTP_ERRMON1/2_FLT_POL = 0, a low level on the ERRMON1/2 pin is detected as a fault. When OTP_ERRMON1/2_FLT_POL = 1, a high level on the ERRMON1/2 pin is detected as a fault. OTP_ERRMON1/2_ACK_TIME[1:0]) to allow the system microcontroller to acknowledge the ERRMON fault. The acknowledge is performed by writing 0b1 to the ERRMON1/2_I bit which in-turn clears the bit. If the ERRMON1/2_I bit is not cleared before the timer expires, the FS0B pin is asserted. The below diagram shows an example of the ERRMON function. Figure 17. Low-level ERRMONx detected as error Table 44. ERRMON acknowledge timer selection

17.6 PGOOD1/2 programmable reactions for ASIL B and Enhanced ASIL B versions

PGOODx to be pulsed low for 8 ms. Table 45. PGOOD1/2 programmable reactions...continued OTP_PGOODx_DELAY[2:0] bits. See Table 31 for details. After PGOODx is de-asserted and there is an OV or UV fault, the fault is de-bounced and PGOODx is asserted.

17.6.1 Watchdog impact on PGOOD1/2

watchdog is stopped when PGOODx is low and is reset at the end of the 10 ms. The FLT_ERR_CNT is incremented by 1 for every PGOODx toggle due to a watchdog failure. a Watchdog failure and the assigned PGOODx pin is toggled. After the initial 1024 ms window, a 'watchdog failure' when WD_ERR_CNT >= WD_ERR_LIMIT. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

17.7 FS0B pin

The FS0B pin indicates to the system status of the various safety mechanisms being handled by the FS5600. VMON2, VMON3, and VMON4, valid ERRMON, valid FCCU, and monitoring of PGOOD1/2. The FS0B pin is released high in the NORMAL state. It is asserted low in all other states. if the VIN pin has a disconnection, provided SW1IN pin is connected. FS0B is a global pin, and can be pulled up to VIN if required in the system.

17.7.1 FS0B pin electrical specifications

unless otherwise noted. Typical values are specified at 25 °C, unless otherwise noted. Table 46. FS0B pin electrical specifications

17.8 PGOOD1, PGOOD2, FS0B stuck at fault check

these pins is compared to the internal digital command in real time. PGOOD1_STUCK_AT_1 = 1 indicates that PGOOD1 pin is stuck at 1. PGOOD1_STUCK_AT_0 = 1 indicates that PGOOD1 pin is stuck at 0. PGOOD2_STUCK_AT_1 = 1 indicates that PGOOD2 pin is stuck at 1. PGOOD2_STUCK_AT_0 = 1 indicates that PGOOD2 pin is stuck at 0. FS0B_STUCK_AT_1 = 1 indicates that FS0B pin is stuck at 1. FS0B_STUCK_AT_0 = 1 indicates that FS0B pin is stuck at 0. them is not at logic low during ABIST, the corresponding 'STUCK_AT_1' bit is set. not, the corresponding 'STUCK_AT_0' bit is set set. corresponding I2C bits. System software should evaluate the status of these bits to control state transitions.

17.9 I2C robustness

17.9.1 I2C CRC verification

When this feature is enabled, a selectable CRC verification is performed on each I2C transaction. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled. When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled. command has not been corrupted. The CRC_I is cleared by writing a 1 to it. The FS5600 implements a CRC-8-SAE, per the SAE J1850 specification. Figure 18 shows the 8-bit CRC polynomial per SAE J1850. Figure 18. 8-bit CRC Polynomial

17.9.2 NOT logic registers

To prevent unintended writes to critical registers, a required two-step writing process must be followed.

Write the desired data in the REGISTER
Write the NOT value of Step 1 to the corresponding NOT_REGISTER

SWx regulator will be enabled if ((SWx_EN = 1 AND NOT_SWx_EN = 0) AND (ENx pin = HIGH)).
SWx regulator will be disabled if ((SWx_EN = 0 AND NOT_SWx_EN = 1) OR (ENx pin = LOW)). A real-time XOR is performed to ensure that only complimentary register values are accepted. Refer to Section 18 for list of registers where this feature is applicable.

17.10 I2C write protection

Table 47. List of registers modifiable only during INIT_RUN state...continued Table 48. INIT_RUN protected registers after first WD_OK if watchdog enabled.

17.11 Fault error counter

Note: “FLT_ERR_CNT_LIMIT[1:0]” should be initialized in the application once during system power-up. Changing it during normal operation may reset the FLT_ERR_CNT value.

00 Max value = 1

10 Max value = 6

11 Max value = 12

Table 49. FLT_ERR_CNT_LIMIT[1:0] description 0b0 to the NOT_CLR_FLT_ERR_CNT bit. counter reaches its maximum value. The fault error counter is incremented each time an assigned fault occurs. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 50. Fault counter source assignment the FLT_ERR_CNT is not incremented.

17.12 Latent failure detection

17.12.1 Analog built-in self-test (ABIST)

bypassed if OTP_ABIST_EN = 0. If enabled, the following actions are performed.

CRC check on mirror registers
Checking that internal oscillators are within 15% tolerance
Checking main band gap and monitoring band gap are within 12% of each other
ABIST on SW1, SW2, VMON1, VMON2, VMON3, VMON4 voltage monitors.
Check on PGOOD1, PGOOD2, and FS0B pins (check if PGOOD1, PGOOD2, and FS0B pins are low during ABIST) GPIO pins when used as inputs (FCCU/ERRMON) can be checked at the system level using real-time status registers (GPIO1/2/3_RT). Results from ABIST are stored in registers for evaluation by the processor. The system microcontroller shall be responsible to evaluate the ABIST results and determine if the FS5600 can proceed to the NORMAL STATE. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. operating in the expected range. Table 51. ABIST flag bits The above bits are all 0 if ABIST test is successful.

17.12.2 On-demand ABIST

FS0B is asserted low during on-demand ABIST if initiated in the INIT_RUN state. FS0B remains high during on-demand ABIST if initiated in the NORMAL state.

17.12.3 Logical built-In self-test (LBIST)

LBIST can be disabled by setting the OTP_LBIST_DIS[7:0] to 0b0011_0110.

No boot error (from OTP controller)
No CRC error (from OTP controller)
No ECC error (from OTP controller) If one of these conditions are not satisfied LBIST is enabled. LBIST_PASS bit in the I2C map is set when LBIST is completed successfully and passes.

17.12.4 VCC and VDIG monitoring

these faults is detected. See the state transition table for specific transitions. specified at 25 °C, unless otherwise noted. Table 52. POR Thresholds

17.13 FS5600 operation states and state machine

Figure 19 shows the high-level operation states of the FS5600 ASIL B, and Enhanced ASIL B versions. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 19. FS5600 state diagram

17.13.1 Shutdown mode

This is the state of the FS5600 when a valid VIN is applied, but EN1 and EN2 pins are held low. and EN2 = 0, the IC enters the shut-down mode through the 'Power Down' state.

When EN1 = EN2 = 0, GPO2 is asserted low immediately, 4 ms after which GPO1 is asserted low, 1 ms after which SW1 and SW2 regulators are disabled.
FS0B is asserted low immediately after NORMAL STATE is exited.

17.13.2 Built-in self-test (BIST)

state is bypassed if both are disabled.

17.13.3 Power-up

Automotive buck regulator and controller with voltage monitors and watchdog timer The OTP_PGOOD1_DELAY[2:0] and OTP_PGOOD2_DELAY[2:0] timers run in parallel to the GPO timers and do not need to expire to exit the power-up state. PGOOD1 and PGOOD2 may be released high even in the INIT_RUN state.

17.13.4 Power-up in Debug mode

The FS5600 offers a Debug mode of operation that is useful during system bring up and/or development. When in Debug mode, the following restrictions are in place:

deep fail-safe transition is disabled
Watchdog window duration is set to infinite To power up in Debug Mode, apply VDDOTP_GPIO1 = 8 V before EN1 or EN2 go high or before VIN is applied. In this condition, the FS5600 pauses power-up and waits for VDDOTP_GPIO1 < 1 V before continuing to power up in Debug Mode. Ensure that there is board-level isolation on the VDDOTP_GPIO1 bus if the GPIO1 function is used at a lower voltage level. While VDDOTP_GPIO1 is maintained at 8 V, the following I2C commands can be sent to open access to the OTP mirror registers: SET_REG:FS5600:Functional:TM_ENTRY:0xD5A7 SET_REG:FS5600:Functional:TM_ENTRY:0xB8EE SET_REG:FS5600:Functional:TM_ENTRY:0x0F37 The mirror registers modified in this fashion take effect during power-up when VDDOTP_GPIO < 1 V. Contact your NXP representative for commands needed to access the mirror registers.

17.13.5 INIT_RUN

The INIT_RUN state is entered after the power-up state. Either or both SW1 and SW2 may be enabled to enter the INIT_RUN state. The state machine can remain in the INIT_RUN state indefinitely. In this state, the state machine waits for conditions to transition to the normal state if enabled to do so. Alternatively, the state machine may proceed to power down to the deep fail-safe state if conditions enabling this are met. INIT_RUN state may also be entered from the normal state by setting the GOTO_INIT_RUN and clearing the NOT_GOTO_INIT_RUN bits.

17.13.6 Normal state

In the normal state, the FS0B pin is de-asserted to indicate to the system that essential parameters monitored by the FS5600 are in expected range. The normal state is entered from the INIT_RUN state, provided conditions for this transition are met. OTP_NORMAL_STATE_EN bit should be set to 1 to enable transition to the normal state. OTP_ERRMON1_SAFE = 1 is an enabling condition for a valid ERRMON1 signal to control transition to the normal state. OTP_ERRMON2_SAFE = 1 is an enabling condition for a valid ERRMON2 signal to control transition to the normal state. OTP_PGOOD1_SAFE = 1 is an enabling condition for a valid PGOOD1 output to control transition to the normal state. OTP_PGOOD2_SAFE = 1 is an enabling condition for a valid PGOOD2 output to control transition to the normal state. See Section 17.13.10 for conditions to transition to the normal state. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

17.13.7 Deep fail-safe state

and EN2 are pulled low in the application. fail-safe state. See Section 17.13.10 for detailed conditions.

17.13.8 Power-down

The FS56 enters a graceful power-down when both EN1 and EN2 are asserted low in the application. OTP_GPOx_DELAY[2:0] setting) followed by SW1 and/or SW2. enters shut-down mode after SW1, SW2, and GPIOs are asserted low (no power-down sequence).

17.13.9 Low-power operation

Turning off SW1 and SW2 (via I2C, or using EN1/2 pins)
Changing SW1 and SW2 operation mode from PWM to Auto Skip or PFM mode. The operation mode of SW1 and SW2 may be changed using I2C or by using the MODE pin.

17.13.9.1 Ultra low-power operation

17.13.10 State transition table

Automotive buck regulator and controller with voltage monitors and watchdog timer

18 I2C register map

18.1 Register descriptions

The following bit-types are used in the FS5600 register map. Table 55. FS5600 register map bit-types

18.1.1 SW1CTRL register

1b'1 — SW1 Enabled provided EN1 is high. MODE[1:0] = NOT(NOT_SW1_MODE[1:0]). Table 56. SW1CTRL register description

18.1.2 NOT_SW1CTRL register

1b'0 — See SW1_EN in SW1CTRL register. 1b'1 — See SW1_EN in SW1CTRL register. 2b'00 — See SW1_MODE[1:0] in SW1CTRL register. 2b'01 — See SW1_MODE[1:0] in SW1CTRL register. 2b'10 — See SW1_MODE[1:0] in SW1CTRL register. 2b'11 — See SW1_MODE[1:0] in SW1CTRL register. Table 57. NOT_SW1CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18.1.3 SW2CTRL register

1b'1 — SW2 Enabled provided EN2 is high. MODE[1:0] = NOT(NOT_SW2_MODE[1:0]). Table 58. SW2CTRL register description

18.1.4 NOT_SW2CTRL register

1b'0 — See SW2_EN in SW2CTRL register. 1b'1 — See SW2_EN in SW2CTRL register. MODE[1:0] = NOT(NOT_SW2_MODE[1:0]). 2b'00 — See SW2_MODE[1:0] in SW2CTRL register. 2b'01 — See SW2_MODE[1:0] in SW2CTRL register. 2b'10 — See SW2_MODE[1:0] in SW2CTRL register. 2b'11 — See SW2_MODE[1:0] in SW2CTRL register. Table 59. NOT_SW2CTRL register description

18.1.5 GPIO_CTRL register

8 MODE_RT SYNCIN_MODE input state (after deglitcher). 1b'0 — SYNCIN_MODE pin is low. 1b'1 — SYNCIN_MODE pin is high. 5 GPIO3_RT GPIO3 input state (after deglitcher). 4 GPIO2_RT GPIO2 input state (after deglitcher). Table 60. GPIO_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

3 GPIO1_RT GPIO1 input state (after deglitcher). 1b'0 — GPIO1_VDDOTP pin is low. 1b'1 — GPIO1_VDDOTP pin is high.

2 GPIO3_OUTPUT GPIO3 output control if programmed as output by OTP_GPIO3_

1b'0 — GPIO3 pin output driven low. 1b'1 — GPIO3 pin output HZ (pull-up).

1 GPIO2_OUTPUT GPIO2 output control if programmed as output by OTP_GPIO2_

1b'0 — GPIO2 pin output driven low. 1b'1 — GPIO2 pin output HZ (pull-up).

0 GPIO1_OUTPUT GPIO1 output control if programmed as output by OTP_GPIO1_

1b'0 — GPIO1_VDDOTP pin output driven low. Table 60. GPIO_CTRL register description...continued

18.1.6 NOT_GPIO_CTRL register

2 NOT_GPIO3_OUTPUT GPIO3 output control. 1b'0 — See GPIO3_OUTPUT in GPIO_CTRL register. 1b'1 — See GPIO3_OUTPUT in GPIO_CTRL register.

1 NOT_GPIO2_OUTPUT GPIO2 output control

1b'0 — See GPIO2_OUTPUT in GPIO_CTRL register. 1b'1 — See GPIO2_OUTPUT in GPIO_CTRL register.

0 NOT_GPIO1_OUTPUT GPIO1 output control

1b'0 — See GPIO1_OUTPUT in GPIO_CTRL register. 1b'1 — See GPIO1_OUTPUT in GPIO_CTRL register. Table 61. NOT_GPIO_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18.1.7 CLOCK_CTRL register

5 FSS_FMOD Frequency (triangular period) of internal 20 MHz oscillator frequency

4 FSS_EN Internal 20 MHz oscillator frequency spread spectrum control. 1b'0 — Frequency spread spectrum disabled. 1b'1 — Frequency spread spectrum enabled. 3 to 0 CLK_FREQ[3:0] Internal 20 MHz oscillator frequency selection (Unit MHz). Table 62. CLOCK_CTRL register description

18.1.8 NOT_CLOCK_CTRL register

3 to 0 NOT_CLK_FREQ[3:0] Internal 20 MHz oscillator frequency programming (Unit MHz). 4b'0000 - 4b’1111 — See CLK_FREQ[3:0] in CLK_CTRL register. Table 63. NOT_CLOCK_CTRL register description

18.1.9 WATCHDOG_CTRL1 register

15 to 14 WD_ERR_LIMIT[1:0] Watchdog error counter limit. Table 64. WATCHDOG_CTRL1 register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12 to 11 WD_RFR_LIMIT[1:0] Watchdog refresh counter limit. 9 to 8 WD_FAIL_IMPACT[1:0] Watchdog fail impact. 00 — No impact on FSM : stay in NORMAL state. 01 — Transition to INIT_RUN or remain in INIT_RUN state. 10 — Transition to DEEP_FS state. 11 — No impact on FSM : stay in NORMAL state. 6 to 4 WD_RFR_CNT[2:0] Watchdog refresh counter value. Resets on overflow. 4b'0000 — Counter Value = 0. 4b'0001 — Counter Value = 1. 4b'0010 — Counter Value = 2. 4b'0011 — Counter Value = 3. 4b'0100 — Counter Value = 4. 4b'0101 — Counter Value = 5. 4b'0110 — Counter Value = 6. 4b'0111 — Counter Value = 7. 4b'1000 — Counter Value = 8. 4b'1001 — Counter Value = 9. Table 64. WATCHDOG_CTRL1 register description...continued FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18.1.10 NOT_WATCHDOG_CTRL1 register

15 to 14 NOT_WD_ERR_LIMIT[1:0] Watchdog error counter limit. 2b'00 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'01 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'10 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'11 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register. 12 to 11 NOT_WD_RFR_LIMIT[1:0] Watchdog refresh counter limit. 2b'00 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'01 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'10 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'11 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register. 9 to 8 NOT_WD_FAIL_IMPACT[1:0] Watchdog fail impact. Table 65. NOT_WATCHDOG_CTRL1 register description

18.1.11 WATCHDOG_CTRL2 register

10 to 8 WDW_DC[2:0] Watchdog window duty cycle. Applied only when WDW_DC[2:0] = NOT(NOT_WDW_DC[2:0]). 3b'000 — Closed window 31.25 % Open window 68.75 %. 3b'001 — Closed window 37.5 % Open window 62.5 %. 3b'010 — Closed window 50 % Open window 50 %. 3b'011 — Closed window 62.5 % Open window 37.5 %. 3b'100 — Closed window 68.75 % Open window 31.25 %. 3b'101 — Closed window 50 % Open window 50 %. 3b'110 — Closed window 50 % Open window 50 %. 3b'111 — Closed window 50 % Open window 50 %. Table 66. WATCHDOG_CTRL2 register description...continued

18.1.12 NOT_WATCHDOG_CTRL2 register

15 to 12 NOT_WD_WINDOW[3:0] Watchdog window duration. 10 to 8 NOT_WDW_DC[2:0] Watchdog window duty cycle. Table 67. NOT_WATCHDOG_CTRL2 register description

18.1.13 WATCHDOG_SEED register

15 to 0 WD_SEED[15:0] Watchdog seed. It is impossible to write 16'hFFFF for challenger watchdog. It is impossible to write 16'h0000 or 16'hFFFF for simple watchdog. Table 68. WATCHDOG_SEED register description

18.1.14 WATCHDOG_ANSWER register

15 to 0 WD_ANSWER[15:0] Watchdog answer. Table 69. WATCHDOG_ANSWER register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

For simple watchdog WD_ANSWER = WD_SEED.
For challenger watchdog WD_ANSWER = ~WD_SEED. Reset Condition — POR

18.1.15 OD_ABIST_CTRL register

ABIST), self cleared when ABIST is finished. Table 70. OD_ABIST_CTRL register description

18.1.16 NOT_OD_ABIST register

0 NOT_OD_ABIST On-demand ABIST. 1b'0 — See OD_ABIST in OD_ABIST_CTRL register. 1b'1 — See OD_ABIST in OD_ABIST_CTRL register. Table 71. NOT_OD_ABIST register description

18.1.17 BIST_STATUS1 register

14 BG_ERR Bandgap monitor ABIST status.

13 ABIST_SW2_UV_ERR Switcher SW2 undervoltage monitor ABIST status,

12 ABIST_SW2_OV_ERR Switcher SW2 overvoltage monitor ABIST status. 11 ABIST_SW1_UV_ERR Switcher SW1 undervoltage monitor ABIST status. 10 ABIST_SW1_OV_ERR Switcher SW1 overvoltage monitor ABIST status. Table 72. BIST_STATUS1 register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

9 ABIST_VMON4_UV_ERR VMON4 undervoltage monitor ABIST status. 8 ABIST_VMON4_OV_ERR VMON4 overvoltage monitor ABIST status. 7 ABIST_VMON3_UV_ERR VMON3 undervoltage monitor ABIST status. 6 ABIST_VMON3_OV_ERR VMON3 overvoltage monitor ABIST status. 5 ABIST_VMON2_UV_ERR VMON2 undervoltage monitor ABIST status.

4 ABIST_VMON2_OV_ERR VMON2 overvoltage monitor ABIST status

3 ABIST_VMON1_UV_ERR VMON1 undervoltage monitor ABIST status. 2 ABIST_VMON1_OV_ERR VMON1 overvoltage monitor ABIST status. 1 ABIST_OSC_ERR Oscillators 20 MHz / 100 kHz monitor ABIST status. 0 ABIST_CRC_ERR OTP CRC status calculated during ABIST. Table 72. BIST_STATUS1 register description...continued FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18.1.18 BIST_STATUS2 register

13 FS0B_STUCK_AT_0 FS0B pin stuck at 0 flag. 1b'0 — No stuck at 0 detected. 12 FS0B_STUCK_AT_1 FS0B pin stuck at 1 flag. 11 PGOOD2_STUCK_AT_0 PGOOD2 pin stuck at 0 flag. 1b'0 — No stuck at 0 detected. 10 PGOOD2_STUCK_AT_1 PGOOD2 pin stuck at 1 flag. 9 PGOOD1_STUCK_AT_0 PGOOD1 pin stuck at 0 flag. 1b'0 — No stuck at 0 detected. 8 PGOOD1_STUCK_AT_1 PGOOD1 pin stuck at 1 flag. 1b'0 — No stuck at 1 detected. 1 LBIST_DONE LBIST completion status. 0 LBIST_PASS Logic BIST status. 1b'1 — Logic BIST done and pass. Table 73. BIST_STATUS2 register description

18.1.19 FAULT_CTRL register

6 CLR_FLT_ERR_CNT Clear fault error counter. 1b'1 — Clear fault error counter. Clear CLR_FLT_ERR_CNT bit. 5 to 2 FLT_ERR_CNT[3:0] Fault error counter value. 4b'0000 — Counter Value = 0. Table 74. FAULT_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

4b'0001 — Counter Value = 1. 4b'0010 — Counter Value = 2. 4b'0011 — Counter Value = 3. 4b'0100 — Counter Value = 4. 4b'0101 — Counter Value = 5. 4b'0110 — Counter Value = 6. 4b'0111 — Counter Value = 7. 4b'1000 — Counter Value = 8. 4b'1001 — Counter Value = 9. 1 to 0 FLT_ERR_CNT_LIMIT[1:0] Fault error counter limit. Table 74. FAULT_CTRL register description...continued

18.1.20 NOT_FAULT_CTRL register

6 NOT_CLR_FLT_ERR_CNT Clear fault error counter (NOT bit). 1b'0 — See CLR_FLT_ERR_CNT in FAULT_CTRL register. 1b'1 — See CLR_FLT_ERR_CNT in FAULT_CTRL register. 1 to 0 NOT_FLT_ERR_CNT_LIMIT[1:0] Fault error counter limit. 2b'00 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register. 2b'01 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register. 2b'10 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register. 2b'11 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register. Table 75. NOT_FAULT_CTRL register description

18.1.21 VMON_STS register

14 SW2_ILIM_I SW2 current limit fault. 1b'1 — Current limit detected. Table 76. VMON_STS register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13 SW1_ILIM_I SW1 current limit fault. 1b'1 — Current limit detected. 12 TSD_I Thermal shutdown indicator. 1b'0 — No thermal shutdown or cleared. 1b'1 — Thermal shutdown detected. 11 SW2_UV_I SW2 monitor undervoltage. 1b'1 — Undervoltage detected. 10 SW1_UV_I SW1 monitor undervoltage. 1b'1 —Undervoltage detected. 9 VMON4_UV_I VMON4 monitor undervoltage. 1b'1 — Undervoltage detected. 8 VMON3_UV_I VMON3 monitor undervoltage. 1b'1 — Undervoltage detected. 7 VMON2_UV_I VMON2 monitor undervoltage. 1b'1 — Undervoltage detected. 6 VMON1_UV_I VMON1 monitor undervoltage. 1b'1 — Undervoltage detected. 5 SW2_OV_I SW2 monitor overvoltage. 1b'1 — Overvoltage detected. 4 SW1_OV_I SW1 monitor overvoltage. 1b'1 — Overvoltage detected. 3 VMON4_OV_I VMON4 monitor overvoltage. 1b'1 — Overvoltage detected. Table 76. VMON_STS register description...continued FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

2 VMON3_OV_I VMON3 monitor overvoltage. 1b'1 — Overvoltage detected. 1 VMON2_OV_I VMON2 monitor overvoltage. 1b'1 — Overvoltage detected. 0 VMON1_OV_I VMON1 monitor overvoltage. 1b'1 — Overvoltage detected.

18.1.22 VMON_RT register

14 SW2_ILIM_RT SW2 current limit. 1b'0 — No current limit fault. 1b'1 — Current limit exists. 13 SW1_ILIM_RT SW1 current limit. 1b'0 — No current limit fault. 1b'1 — Current limit exists. 12 TSD_RT thermal shutdown indicator. 1b'0 — No thermal shutdown or cleared. 1b'1 — Thermal shutdown detected. 11 SW2_UV_RT SW2 monitor undervoltage. 1b'1 — Undervoltage detected. 10 SW1_UV_RT SW1 monitor undervoltage. 1b'1 — Undervoltage detected. 9 VMON4_UV_RT VMON4 monitor undervoltage. 1b'1 — Undervoltage detected. 8 VMON3_UV_RT VMON3 monitor undervoltage. 1b'1 — Undervoltage detected. Table 77. VMON_RT register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

7 VMON2_UV_RT VMON2 monitor undervoltage. 1b'1 — Undervoltage detected. 6 VMON1_UV_RT VMON1 monitor undervoltage. 1b'1 — Undervoltage detected. 5 SW2_OV_RT SW2 monitor overvoltage. 1b'1 — Overvoltage detected. 4 SW1_OV_RT SW1 monitor overvoltage. 1b'1 — Overvoltage detected. 3 VMON4_OV_RT VMON4 monitor overvoltage. 1b'1 — Overvoltage detected. 2 VMON3_OV_RT VMON3 monitor overvoltage. 1b'1 — Overvoltage detected. 1 VMON2_OV_RT VMON2 monitor overvoltage. 1b'1 — Overvoltage detected. 0 VMON1_OV_RT VMON1 monitor overvoltage. 1b'1 — Overvoltage detected. Table 77. VMON_RT register description...continued

18.1.23 GPIO_STS register

12 FCCU12_ERR FCCU12 error (bistable). 5 BAD_WD_TIMING Watchdog error bad timing. answer register in closed window or timeout). 4 BAD_WD_DATA Watchdog error bad answer. 1 I2C_CRC_ERR I2C CRC error. 1b'1 — CRC error detected in write operation. 0 I2C_REQ_ERR I2C request error. Table 78. GPIO_STS register description...continued

18.1.24 FCCU_CFG register

14 FCCU12_FLT_POL FCCU bistable fault polarity. 1b'0 — FCCU1 low or FCCU2 high is a fault. 1b'1 — FCCU1 high or FCCU2 low is a fault. 13 FCCU1_FLT_POL FCCU1 fault polarity. 1b'0 — FCCU1 low is a fault. 1b'1 — FCCU1 high is a fault. Table 79. FCCU_CFG register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12 FCCU2_FLT_POL FCCU2 fault polarity. 1b'0 — FCCU2 low is a fault. 1b'1 — FCCU2 high is a fault. 8 FCCU12_BISTABLE FCCU1/FCCU2 bistable control. 1b'0 — Independent FCCU1/FCCU2. 1b'1 — FCCU1/FCCU2 configured as bistable. Table 79. FCCU_CFG register description...continued

18.1.25 NOT_FCCU_CFG register

14 NOT_FCCU12_FLT_POL FCCU bistable fault polarity. See FCCU12_FLT_POL in FCCU_CFG register. 13 NOT_FCCU1_FLT_POL FCCU1 fault polarity. See FCCU1_FLT_POL in FCCU_CFG register. 12 NOT_FCCU2_FLT_POL FCCU2 fault polarity. See FCCU2_FLT_POL in FCCU_CFG register. 8 NOT_FCCU12_BISTABLE FCCU1/FCCU2 bistable control. See FCCU12_BISTABLE in FCCU_CFG register. Table 80. NOT_FCCU_CFG register description

18.1.26 STATE_CTRL register

15 DBG_EXIT Used to unlatch debug mode. 1 GOTO_INIT_RUN Go to INIT_RUN state command. cleared when in state INIT_RUN). Table 81. STATE_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 GOTO_NORMAL Go to NORMAL state command. Applied only when GOTO_NORMAL = NOT(NOT_GOTO_NORMAL). cleared when in state NORMAL). Table 81. STATE_CTRL register description...continued

18.1.27 NOT_STATE_CTRL register

1 NOT_GOTO_INIT_RUN Go to INIT_RUN state command. 1b'0 — See GOTO_INIT_RUN in STATE_CTRL register. 1b'1 — See GOTO_INIT_RUN in STATE_CTRL register. 0 NOT_GOTO_NORMAL Go to NORMAL state command. 1b'0 — See GOTO_NORMAL in STATE_CTRL register. 1b'1 — See GOTO_NORMAL in STATE_CTRL register. Table 82. NOT_STATE_CTRL register description

18.1.28 STATE register

4 to 0 PMIC_FSM[4:0] Indicates FSM State. Table 83. STATE register description

18.1.29 ID1 register

3 to 0 DEVICEID[3:0] Device variation identification. Defaulted to 0. Table 84. ID1 register description...continued FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

19 Typical application curves

20 Typical application block diagram

5.0 VBattery (< 40 V)

3.3 VSW2

20.1 Example power up and power down waveforms

21 Typical application schematic

32 VIN

31 SYNCIN/MODE

27 PGOOD2

26 PGOOD1

22.1 Package outline – ES version (wettable flank)

Figure 34. Package outline HVQFN32 (SOT617-24(SC)) – ES version (wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 35. Package outline detail HVQFN32 (SOT617-24(SC)) – ES version (wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 36. PCB design guidelines – solder mask opening pattern for HVQFN32 (SOT617-24(SC)) – ES version FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 37. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) – ES version (wettable FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 38. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) – ES version (wettable FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 39. Package outline note HVQFN32 (SOT617-24(SC)) – ES version (wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

22.2 Package outline – EP version (non-wettable flank)

Figure 40. Package outline HVQFN32 (SOT617-24(SC)) – EP version (non-wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 41. Package outline detail HVQFN32 (SOT617-24(SC)) – EP version (non-wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 42. PCB design guidelines – solder mask opening pattern for HVQFN32 (SOT617-24(SC)) – EP version (non- FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 43. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) – EP version (non- FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 44. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) – EP version (non-wettable FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 45. Package outline note HVQFN32 (SOT617-24(SC)) – EP version (non-wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Automotive buck regulator and controller with voltage monitors and watchdog timer Document ID Release date Modifications FS5600 v. 4 20240429 • CIN number 202402003I

In Table 2, added five part numbers (MFS5600AMBAFES, MFS5600AMMABES, MFS5600 AVMABEP, MFS5600AVMADEP, and MFS5600AVMAEEP)
In Section 4, added statement regarding OTP emulation and programming
In Table 32, added (Default) indication for device address 0x18
In Table 76, changed overvoltage to overcurrent for bits 14 and 13, and changed overvoltage to undervoltage for bits 11 - 6
In Table 77, changed overvoltage to undervoltage for bits 11-6
In Figure 11, changed /7 to /8 in the Divider 1 box and /44 to /48 in the Divider 2 box.
In Figure 33, changed value of L1 from 4.7 μH to 6.8 μH
Updated legal information FS5600 v. 3 20220802 • CIN number 202202008I
In Section 2, added up to 15 A load capability for Buck Controller - External FET
In Figure 1, under SW@ - Buck Controller, changed >10 A to up to 15 A
In Section 10, added this note below the table: In the absence of BIAS_IN, VIN falling below this voltage will cause FS5600 to power off
In Section 12.1, corrected the units of Error Amplifier Transconductance from ms to mS
In Section 12.2.1, added this to the end of the paragraph after the first table: When operating at 450 kHz or lower, by choosing low Rds(on) MOSFETs in separate packages, and with a low DCR inductor, SW2 can be designed to support loads of up to 15 A. Refer to the schematic of KITFS5600FRDMEVM for a design that can support 15 A.
Reorganized Section 12, adding Section 12.2.1.2 material
In Section 12.2.1.1, added Use closest standard values for resistor and capacitors to the end of the section
In Section 17.6.1, added PGOODx toggle due to a before watchdog failure
In Section 17.13.7, changed OTP_DFN_EN to OTP_DFS_EN
Added Section 19
In Figure 11, in the Divider 1 box, changed /8 to /7. In the Divider 2 box, changed /48 to /44.
In Figure 33, made these pin numbering changes at the lower left: Swap 5-6 Swap 4-2 Swap 3-1 FS5600 v. 2 20210601 Moved from Objective status to Product status FS5600 v. 1 20201029 Initial release of Objective data sheet Table 85. FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 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Automotive buck regulator and controller with voltage monitors and watchdog timer Tables Tab. 6. QFN32 thermal resistance and package Tab. 29. SW1 and SW2 switching frequency Tab. 47. List of registers modifiable only during Tab. 48. INIT_RUN protected registers after first Tab. 65. NOT_WATCHDOG_CTRL1 register Tab. 67. NOT_WATCHDOG_CTRL2 register Tab. 69. WATCHDOG_ANSWER register FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

Automotive buck regulator and controller with voltage monitors and watchdog timer Figures Fig. 5. ASIL B, and enhanced ASIL B version Fig. 7. SW1 output voltage setting using an Fig. 9. SW2 application schematic with Rshunt Fig. 11. Clock management system high-level block Fig. 32. Example power up and power down Fig. 34. Package outline HVQFN32 (SOT617-24(SC)) – ES version (wettable Fig. 35. Package outline detail HVQFN32 (SOT617-24(SC)) – ES version (wettable Fig. 36. PCB design guidelines – solder mask opening pattern for HVQFN32 (SOT617-24(SC)) – ES version (wettable Fig. 37. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) – ES Fig. 38. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) – Fig. 39. Package outline note HVQFN32 (SOT617-24(SC)) – ES version (wettable Fig. 40. Package outline HVQFN32 (SOT617-24(SC)) – EP version (non- Fig. 41. Package outline detail HVQFN32 (SOT617-24(SC)) – EP version (non- Fig. 42. PCB design guidelines – solder mask opening pattern for HVQFN32 (SOT617-24(SC)) – EP version (non- Fig. 43. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) – EP Fig. 44. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) – Fig. 45. Package outline note HVQFN32 (SOT617-24(SC)) – EP version (non- FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024

Automotive buck regulator and controller with voltage monitors and watchdog timer

20.1 Example power up and power down

22.1 Package outline – ES version (wettable

22.2 Package outline – EP version (non-wettable

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 29 April 2024 Document identifier: FS5600

Product Information

MFS5600AVMA0EP specifications and overview.

Summary

Automotive buck regulator and controller with voltage monitors and watchdog timer Rev. 4 - 29 April 2024

Description

Automotive buck regulator and controller with voltage monitors and watchdog timer Rev. 4 - 29 April 2024

Source title MFS5600AVMA0EP Datasheet(PDF) - NXP Semiconductors

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