Power Management

MFS5600AMBA0ES

NXP Semiconductors

Automotive buck regulator and controller with voltage monitors and watchdog timer Rev. 3 - 2 August 2022

Manufacturer: NXP Semiconductors

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PDF pages: 111

Technical content

Datasheet sections

1 General Description
2 Features and Benefits
2.1 Overview
3 Applications
4 Ordering Information
5 FS5600 Internal Block Diagram
6 Regulator Input Configurations
7 Pinout and Pin Description
8 ESD Ratings
9 Thermal Characteristics
10 Device Level Electrical Parameters
11 SW1: 36 V Integrated FET DC-DC
11.1 SW1 electrical specifications
11.2 SW1 external component selection
11.3 SW1 operation
11.3.1 Output voltage selection
11.3.2 PFM and pulse skipping operation
11.3.3 PFM operation
11.3.4 Soft-start
11.3.5 Current limit protection
11.3.6 Compensation selection
11.3.7 SW1 fault monitoring
12 SW2: 36 V DC-DC Controller with External
12.1 SW2 electrical characteristics
12.2 SW2 operation
12.2.1 SW2 external component selection
12.2.1.1 Compensation network
12.2.1.2 Inductor current sense selection
12.2.2 Output voltage selection
12.2.3 Pulse skipping operation
12.2.4 PFM operation
12.2.5 Soft-start
12.2.6 Current limit protection
12.2.7 Slope compensation
12.2.8 SW2 fault monitoring
13 BIAS_IN Input
14 FS5600 Clock Management
14.1 FS5600 clock electrical characteristics
14.2 High frequency oscillator
14.3 Spread spectrum
14.4 SW1 and SW2 switching frequency
14.5 External clock synchronization
14.6 SYNCOUT function settings
15 I/O Pins in FS5600
15.1 I/O pins electrical specifications
15.2 EN1 and EN2
15.2.1 Programming turn-off delay
15.3 PGOOD1 and PGOOD2
15.4 GPIO1/2/3
15.5 MODE pin
15.6 I2C communication
16 Thermal Protection
17 Functional safety features in FS5600
17.1 GPIO1/2/3 feature selection
17.2 OV/UV monitors
17.2.1 VMON1-4 electrical specifications
17.3 Watchdog
17.3.1 Simple watchdog
17.3.2 Challenger watchdog
17.3.3 Watchdog error counter and error impact
17.3.4 Watchdog refresh counter
17.4 FCCU monitoring
17.4.1 BI_STABLE protocol with FCCU1 and
17.4.2 Single/independent FCCU monitoring
17.4.3 FCCU status reporting via interrupt register
17.5 External signal monitoring using ERRMON
17.6 PGOOD1/2 programmable reactions for
17.6.1 Watchdog impact on PGOOD1/2
17.7 FS0B pin
17.7.1 FS0B pin electrical specifications
17.8 PGOOD1, PGOOD2, FS0B stuck at fault
17.9 I2C robustness
17.9.1 I2C CRC verification
17.9.2 NOT logic registers
17.10 I2C Write protection
17.11 Fault error counter
17.12 Latent failure detection
17.12.1 Analog built-in self-test (ABIST)
17.12.2 On-demand ABIST
17.12.3 Logical Built-In Self-Test (LBIST)
17.12.4 VCC and VDIG monitoring
17.13 FS5600 operation states and state machine
17.13.1 Shut-down mode
17.13.2 Built-in self-test (BIST)
17.13.3 Power-up
17.13.4 Power-up in Debug Mode
17.13.5 INIT_RUN
17.13.6 Normal state
17.13.7 Deep fail-safe state
17.13.8 Power-down
17.13.9 Low-power operation
17.13.9.1 Ultra low-power operation
17.13.10 State transition table
18 I2C Register Map
18.1 Register descriptions
18.1.1 SW1CTRL register
18.1.2 NOT_SW1CTRL register
18.1.3 SW2CTRL register
18.1.4 NOT_SW2CTRL register
18.1.5 GPIO_CTRL register
18.1.6 NOT_GPIO_CTRL register
18.1.7 CLOCK_CTRL register
18.1.8 NOT_CLOCK_CTRL register
18.1.9 WATCHDOG_CTRL1 register
18.1.10 NOT_WATCHDOG_CTRL1 register
18.1.11 WATCHDOG_CTRL2 register

Automotive buck regulator and controller with voltage monitors and watchdog timer Rev. 3 — 2 August 2022 Product data sheet

1 General Description

The FS5600 integrates a battery connected DC-DC controller with external FETs and a battery connected DC-DC converter with internal FETs. It also offers functional safety features such as independent voltage monitors, windowed watchdog timer, I/O monitoring via ERRMON and FCCU, and built-in self-test.

2 Features and Benefits

2 x High-Voltage Buck Converters: – Buck Controller - External FETs - 900 mA gate drive - up to 15 A load capability – Buck Regulator - Internal FETs - 3 A+ load capability – ±2 % Output Accuracy – 250 kHz to 3 MHz switching frequency
High-efficiency PFM mode
Safety Features: – Available in Enhanced ASIL B, ASIL B, and QM variations – 2 internal and up to 4 high-accuracy external voltage monitors – Windowed Watchdog Timer – ERRMON and FCCU monitoring – 2 x PGOOD and 1 x FS0B outputs – ABIST and LBIST for latest failure check
GPIOs for seamless operation with PF PMICs
Rated from –40 °C to 150 °C TJ
32-Ld 5 mm x 5 mm QFN
AEC-Q100 Grade-1 Qualified

2.1 Overview

Figure 1. FS5600 Functional block diagram

3 Applications

Infotainment / Cluster / Driver Awareness
Telematics
V2X
Radar
Vision
ADAS
Sensor fusion Additional safety mechanisms may be needed for ASIL D compliance in the system level. FS5600 is developed to meet ASIL B requirements.

4 Ordering Information

mechanisms may be needed at the system level for ASIL D compliance. Table 1. Device options FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

4 External Voltage Monitors (VMON) No Yes Yes

5 FS5600 Internal Block Diagram

20 MHz & 100 kHz

Figure 2. FS5600 internal block diagram

6 Regulator Input Configurations

the regulator goes high after its input is stable for proper soft-start operation. Figure 3. Regulator input options FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

7 Pinout and Pin Description

The FS5600 is offered in a 32-Ld 5 mm x 5 mm WF-QFN package. Figure 4. QM version pinout Figure 5. ASIL B, and enhanced ASIL B version pinout FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

6 SW2FB

internal resistor divider for SW2 outputs ≤ 5.5 V.

10 SW2LX

gate of external high side MOSFET. purpose output (GPO3) available in QM version. purpose output (GPO2) available in QM version. Table 3. Pin description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Fail-Safe Output pin. Open drain.

25 SW1FB

internal resistor divider for SW1 outputs ≤ 5.5 V.

26 PGOOD1 PGOOD1 output from monitoring of selected

27 PGOOD2 PGOOD2 output from monitoring of selected

28 VDIG

Output of internal regulator for powering logic.

29 BIAS_IN

30 VCC

µF capacitor. No external loading permitted.

31 MODE/SYNCIN

8 ESD Ratings

Table 4. ESD ratings This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. This is an ESD sensitive device, improper handling can cause permanent damage to the part.

9 Thermal Characteristics

Table 5. Temperature range Table 6. QFN32 thermal resistance and package dissipation ratings FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Table 6. QFN32 thermal resistance and package dissipation ratings...continued significant hot spots on the die.

10 Device Level Electrical Parameters

unless otherwise noted. Typical values are specified at 25 °C, unless otherwise noted. Quiescent Current (non-switching), SW1 & SW2 in PFM. BIAS_IN connected to 5 V. ULPM Mode. Quiescent Current (non-switching), SW1 in PFM. SW2 disabled. BIAS_IN connected to 5 V. ULPM Mode. Quiescent Current (non-switching), SW2 in PFM. SW1 disabled. BIAS_IN connected to 5 V. ULPM Mode. Table 7. Device level electrical parameters [1] In the absence of BIAS_IN, VIN falling below this voltage will cause FS5600 to power off. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

11 SW1: 36 V Integrated FET DC-DC Converter

drawn without entering current limit. Figure 6 shows a high-level block diagram of SW1. Figure 6. SW1 high-level block diagram to drive the MOSFET gates. EN1 controls the enable of the SW1 regulator.

11.1 SW1 electrical specifications

specified at VSW1IN = 12 V, Tj = 25 °C unless otherwise noted. Table 8. SW1 electrical specifications FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Table 8. SW1 electrical specifications...continued

11.2 SW1 external component selection

Table 9 provides the recommended external components for the SW1 regulator. Table 9. SW1 external component selection See Section 14.4 for switching frequency selection.

11.3 SW1 operation

low Rds(on) N-FETs for high efficiency and low solution cost.

11.3.1 Output voltage selection

The output voltage of SW1 may be set via OTP using the OTP_SW1_VOLT[7:0] bits. OTP. Connect the SW1FB pin directly to the output voltage in this case. divider. The gain of the resistor divider sets the output voltage as shown in Figure 7. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

compensation is calculated internally based on the output voltage. Figure 7. SW1 output voltage setting using an external resistor divider Table 10. OTP_SW1_VOLT[7:0] selection FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

11.3.2 PFM and pulse skipping operation

is the recommended default value that is optimal for most applications. Table 11. OTP_SW1_MIN_TON[1:0] selection VOUT ratio is above 6. This allows reduced ripple operation compared to pulse-skipping.

11.3.3 PFM operation

00 PFM

11 PWM

Table 12. SW1_MODE[1:0] selection. do not use SW1_MODE[1:0] to change the operating mode. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

current and the output ripple for most applications. Table 13. OTP_SW1_PFM_TON[1:0] selection

11.3.4 Soft-start

current. The soft-start time is programmable via OTP using the OTP_SW1_SS[1:0] bits.

11.3.5 Current limit protection

programmable to four different values via OTP using the OTP_SW1_ILIM_SEL[1:0] bits.

11.3.6 Compensation selection

Table 14. SW1 compensation selection...continued Table 15. OTP_SW1_SLOPECOMP[1:0] Value Table 16. OTP_SW1_GM_COMP[1:0] Value Table 17. OTP_SW1_PWM_R_COMP[2:0] Value

11.3.7 SW1 fault monitoring

Automotive buck regulator and controller with voltage monitors and watchdog timer When OTP_SW1_OV_PGOOD1 = 1, an overvoltage fault on SW1 asserts PGOOD1. Similarly, when OTP_SW1_OV_PGOOD2 = 1, an overvoltage fault on SW1 asserts PGOOD2. When OTP_SW1_UV_PGOOD1 = 1, an undervoltage fault on SW1 asserts PGOOD1. Similarly, when OTP_SW1_UV_PGOOD2 = 1, an undervoltage fault on SW1 asserts PGOOD2. The SW1_UV_I and SW1_OV_I bits are latched to 1 respectively if undervoltage and overvoltage faults are detected. The latch bits can be cleared by writing a 1 to them. SW1_UV_RT and SW1_OV_RT read-only bits indicate the real-time status of the faults. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

12 SW2: 36 V DC-DC Controller with External FETs

SW2. The rated load current of SW2 is dependent on the external components chosen. of up to 15 A can be drawn without entering current limit. Figure 8. SW2 high-level block diagram

12.1 SW2 electrical characteristics

are specified at VSW2IN = 12 V, Tj = 25 °C unless otherwise noted. Table 18. SW2 electrical characteristics FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Table 18. SW2 electrical characteristics...continued

12.2 SW2 operation

12.2.1 SW2 external component selection

Table 19 provides the recommended external components for the SW2 regulator. Table 19. SW2 recommended external components FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

See Table 20 for guidance on the MOSFET selection.

2.2 MHz < 5 A

Table 20. MOSFET selection See Section 14.4 for switching frequency selection.

12.2.1.1 Compensation network

in addition to the R-C network. Table 21. SW2 Compensation selection resistor and capacitors. The gate drive comes from VCC (5 V).

12.2.1.2 Inductor current sense selection

12.2.1.2.1 Using current sense resistor

resistor Rshunt in series with the SW2 inductor LSW2, as shown in Figure 9 below. Figure 9. SW2 application schematic with Rshunt current sensing and Rshunt = 0.01 Ω, PRSHUNT is 0.25 W.

12.2.1.2.2 Inductor DCR current sense

limitation, and less accuracy means a wider current limitation range. Figure 10. DCR current sense with a single capacitor FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

nF, and calculate the other components. Example: For an inductor L = 4.7 μH and RDCR = 7 mΩ, R1 = 6.7 kΩ and C1 = 100 nF.

12.2.2 Output voltage selection

Output voltage of SW2 may be set via OTP using the OTP_SW2_VOLT[5:0] bits. Table 22. OTP_SW2_VOLT[5:0] Selection FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

110111 Reserved. Do not use. Table 22. OTP_SW2_VOLT[5:0] Selection...continued FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

111001 Reserved. Do not use. 111010 Reserved. Do not use. 111011 Reserved. Do not use. 111100 Reserved. Do not use. 111101 Reserved. Do not use. 111110 Reserved. Do not use. 111111 Reserved. Do not use.

12.2.3 Pulse skipping operation

via the OTP_SW2_TON_MIN[1:0] bits. Table 23. OTP_SW2_TON_MIN[1:0] Selection

12.2.4 PFM operation

Table 24. SW2_MODE[2:0] selection operating mode to avoid conflicts between the pin and the register bits. current and the output ripple for most applications. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Table 25. OTP_SW2_PFM_TON[1:0] Selection

12.2.5 Soft-start

12.2.6 Current limit protection

12.2.7 Slope compensation

selection" for values to use based on operating conditions. Table 26. OTP_SW2_SLOPECOMP[5:0] selection FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

12.2.8 SW2 fault monitoring

undervoltage faults in SW2. See Table 18 for monitoring thresholds. When OTP_SW2_OV_PGOOD1 = 1, an overvoltage fault on SW2 asserts PGOOD1. When OTP_SW2_UV_PGOOD1 = 1, an undervoltage fault on SW2 asserts PGOOD1. overvoltage faults are detected. The latch bits can be cleared by writing a 1 to them. SW2_UV_RT and SW2_OV_RT read-only bits indicate the real-time status of the faults.

13 BIAS_IN Input

voltage LDO from VIN to VCC. be connected to BIAS_IN. Ensure that the BIAS_IN voltage does not exceed 5.5 V.

14 FS5600 Clock Management

Low-power 100 kHz clock
Internal high frequency clock with programmable frequency
Phase-Locked Loop (PLL)
A digital clock management interface is in-charge of supporting interaction among these blocks. Figure 11 shows a high-level block diagram of the clock management system. aaa-037157 Internal Oscillator (Spread spectrum, Freq tuning) Divider /1 (OTP_FSYNC_RANGE = 1) /6 (OTP_FSYNC_RANGE = 0) Divider 2 /44 (OTP_CLK2_DIV = 0) /64 (OTP_CLK2_DIV = 1) SYNCIN Divider /48 OSC_MAIN/48 CLOCK monitoring SW1 PLL x 48 out in enable CLK 1CLK_FIN_DIV EXT_FIN_SEL Divider 1 /7 (OTP_CLK1_DIV = 0) /9 (OTP_CLK1_DIV = 1) CLK1 CLK1 CLK2 SYNCOUT 1CLK2 OTP_SW1_CLKSEL OTP_SW2_CLKSEL SW2 CLK1 0 1CLK2

Figure 11. Clock management system high-level block diagram

14.1 FS5600 clock electrical characteristics

Table 27. FS5600 clock electrical characteristics...continued

14.2 High frequency oscillator

high frequency oscillator is referred to as the 20 MHz clock in this document for simplicity.

0101 Not used

0110 Not used

0111 Not used

1000 Not used

1101 Not used

1110 Not used

1111 Not used

Table 28. Internal oscillator frequency selection

14.3 Spread spectrum

14.4 SW1 and SW2 switching frequency selection

respect to each other to allow interleaving of the switching edges. Table 29. SW1 and SW2 switching frequency selection

14.5 External clock synchronization

clock is not present or invalid, the device automatically switches to the internal clock. at the application level to ensure clock synchronization.

14.6 SYNCOUT function settings

railing to VDDIO and ground.

15 I/O Pins in FS5600

15.1 I/O pins electrical specifications

Automotive buck regulator and controller with voltage monitors and watchdog timer

15.2 EN1 and EN2

EN1 and EN2 pins are used to enable SW1 and SW2 respectively. In addition to the EN1 and EN2 pins, the bits SW1_EN and SW2_EN ultimately determine if SW1 or SW2 are enabled. This allows enable and disable of SW1 and SW2 to be performed through their respective ENx pin, or via the respective I2C bit SWx_EN. SW1 regulator is disabled if (EN1 pin = LOW). SW1 regulator is disabled if (EN1 pin = HIGH AND SW1_EN = 0). SW1 regulator is enabled if (EN1 pin = HIGH AND SW1_EN = 1). SW2 regulator is disabled if (EN2 pin = LOW). SW2 regulator is disabled if (EN2 pin = HIGH AND SW2_EN = 0). SW2 regulator is enabled if (EN2 pin = HIGH AND SW2_EN = 1). SW1/2_EN are initialized to 1. When OTP_SW1_PULLDN_B = 0, a pulldown resistor of 500 Ω is engaged on the output if SW1 is disabled. Similarly, when OTP_SW2_PULLDN_B = 0, a pulldown resistor of 500 ohm is engaged on the output if SW2 is disabled. The output is disabled in high-Z if OTP_SWx_PULLDN_B = 1.

15.2.1 Programming turn-off delay

When OTP_SW1_OFF_DELAY = 0, SW1 is turned off after EN1 goes low. When OTP_SW2_OFF_DELAY = 0, SW2 is turned off after EN2 goes low. When OTP_SW1_OFF_DELAY = 1, SW1 is turned off 32 ms after EN1 goes low. When OTP_SW2_OFF_DELAY = 1, SW2 is turned off 32 ms after EN2 goes low. The 32 ms setting is useful when other devices are to be powered down in the system prior to turning off the pre-regulators.

15.3 PGOOD1 and PGOOD2

For the QM variation of FS5600, PGOOD1 is used to indicate the voltage regulation status of SW1 and PGOOD2 is used to indicate the voltage regulation state of SW2. PGOOD1 is asserted low when the OV or UV monitor for SW1 indicates a faulty voltage. See Table 8 for OV/UV thresholds. PGOOD2 is asserted low when the OV or UV monitor for SW2 indicates a faulty voltage. See Table 18 for OV/UV thresholds. The delay from SW1/2 reaching regulation to PGOOD1/2 being released high is programmable. See Section 15.4 for details. PGOOD1 and PGOOD2 are open-drain outputs and need an external pullup resistor. For the ASIL B, and Enhanced ASIL B variations, behavior of PGOOD1 and PGOOD2 can be programmed to indicate status of other safety functions. See Section 17.6 for details.

15.4 GPIO1/2/3

Pins 4, 14 and 13 are available as GPO1, GPO2, and GPO3 respectively in the QM variation. They can be sequenced as part of the device power up to control external FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

(which occurs first) to GPO1/2/3 being released high. configured as SYNCOUT in a push-pull mode. See Section 14.6 for details. PGOOD1/2 can also be delayed during start-up as shown in Table 31. 000 GPO1/2/3 held low through power-up. No additional delay for PGOOD1/2 release. Table 31. PGOOD1/2, GPIO1/2/3 delay selection

15.5 MODE pin

changed by toggling with MODE pin. When MODE = 0, SW1 and SW2 operate in continuous PWM mode. Note: OTP_ULPM_EN = 1 for all QM devices to achieve the low quiescent current. achieve different behavior. See Section 17.13.9 for details. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

15.6 I2C communication

typically with 2.2 kΩ resistors for 400 kHz operation, and 500 Ω for 3.4 MHz operation. Table 32. I2C address selection

16 Thermal Protection

entered, the TSD_I latch bit is set to notify the processor during subsequent power-up. immediately upon entering the thermal shutdown state (no power down sequence). otherwise noted. Typical values are specified at 25 °C, unless otherwise noted. Table 33. Thermal protection characteristics

17 Functional safety features in FS5600

Four high precision voltage monitors (in addition to monitoring of SW1 and SW2 internally)
Challenger windowed watchdog timer
FCCU monitoring
2x ERRMON monitoring for external signal monitoring
Fail-Safe Output (FS0B) with programmable fault reaction
PGOOD1 and PGOOD2 outputs with programmable fault reaction
Stuck-at-fault detection on PGOOD1, PGOOD2, and FS0B outputs
State machine with programmable fault reactions
Redundant band gap with band gap comparator for self-test
Internal oscillator self-test
Built-in self-test (ABIST and LBIST) of analog and digital monitoring functions for latent failure diagnostics
On-Demand ABIST
CRC on OTP bits in the device
I2C with CRC
NOT register functionality to prevent accidental writes to critical registers
Monitoring of internal voltages such as VCC and VDIG for over and under voltage faults

17.1 GPIO1/2/3 feature selection

OTP_GPIO3_CFG[1:0] bits as shown below in Table 34, Table 35, and Table 36.

00 Output is high Z

01 GPO (output)

10 ERRMON1 (input)

11 Reserved (do not use)

Table 34. GPIO1 function selection

00 GPO (output)

01 FCCU1 (input)

10 SYNCOUT (output)

11 VMON3

01 FCCU2 (input)

10 ERRMON2 (input)

11 VMON4

Table 36. GPIO3 function selection

17.2 OV/UV monitors

polled by I2C. See Section 17.6 for details on selecting desired PGOOD1/2 reactions. The OV and UV thresholds shown below are with respect to 0.6 V. VMONx_OV_RT and VMONx_UV_RT indicate real-time status of the faults.

17.2.1 VMON1-4 electrical specifications

17.3 Watchdog

OTP_WD_SELECTION = 1, the Challenger scheme is selected.

Wrong watchdog answer during the OPEN window
No watchdog refresh during the OPEN window
Good or bad watchdog answer during the CLOSED window. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

Figure 12. Windowed watchdog concept After a good or a bad watchdog refresh, a new window period starts immediately. "BAD_WD_TIMING" is set for diagnostics. "BAD_WD_DATA" is set for diagnostics. refresh. The watchdog window may be set to infinite. prevent erroneous communication from causing negative system impact. 1024 ms initial window is available every time the Watchdog starts.

0000 DISABLE (during INIT_FS only)

Table 38. Watchdog window period configuration...continued WDW_DC [2:0] bits. The new duty cycle is effective after the next watchdog refresh. Table 39. Watchdog window duty cycle configuration

17.3.1 Simple watchdog

MCU can send its own seed in WD_SEED register or use the default seed value 0x5AB2. Section 17.3.3 for watchdog error counter. window), the “WD_BAD_TIMING” bit is set to 1. 0x0000 and 0xFFFF are attempted.

17.3.2 Challenger watchdog

be sent through I2C during the OPEN watchdog window and is verified by the FS5600. When the result is right, the watchdog window is restarted and a new LFSR is generated. restarted and the LFSR value is not changed. window), the “WD_BAD_TIMING” bit is set to 1. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

the challenger mode. The I2C_REQ_ERR bit is set when writing a 0x0000 is attempted. Figure 13. Challenger watchdog formula

17.3.3 Watchdog error counter and error impact

refreshes (data and temporal errors). watchdog error counter decrements by 1 each time the watchdog is correctly refreshed. This principle ensures that a cyclic ’OK/NOK’ behavior converges to a failure detection. with the WD_ERR_LIMIT[1:0] register as shown in the table below. Table 40. Watchdog error counter

00 Stay in NORMAL STATE

01 Transition to INIT_RUN state or Remain in INIT_RUN

10 Transition to DEEP FAIL-SAFE state

11 Stay in NORMAL STATE

Figure 14. Watchdog error counter configurations

17.3.4 Watchdog refresh counter

is configurable with the WD_RFR_LIMIT[1:0] register. Table 42. Watchdog refresh counter configuration FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 15. Watchdog refresh counter configurations

17.4 FCCU monitoring

GPIO2 and GPIO3 pins can be configured as FCCU1 and FCCU2 respectively via OTP. 0b01 configures GPIO3 as FCCU2. pair, or single independent inputs. Monitoring of the FCCU pins is active when the state machine is in the NORMAL STATE. See Section 17.13 on thestate machine for reactions based on FCCU monitoring.

17.4.1 BI_STABLE protocol with FCCU1 and FCCU2

The bi-stable protocol representation is shown in Figure 16. Figure 16. FCCU 1/2 bi-stable protocol example FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

When FCCU12_FLT_POL = 0, FCCU1 = 0 or FCCU2 = 1 is a fault
When FCCU12_FLT_POL = 1, FCCU1 = 1 or FCCU2 = 0 is a fault The FS0B is asserted when an FCCU fault is detected and the state machine returns to INIT_RUN state. It is possible to program the PGOOD1 and PGOOD2 pins to also toggle during an FCCU fault if they are programmed to do so via OTP. PGOOD1/2 may be used to assert RESET of the MCU in this case. See Section 17.6 on PGOOD for details.

17.4.2 Single/independent FCCU monitoring

Either or both FCCU pins may be used in this configuration.

When FCCUx_FLT_POL = 0, LOW level on FCCUx is a fault
When FCCUx_FLT_POL = 1, HIGH-level on FCCUx is a fault The FS0B pin is asserted when an FCCU fault is detected and the state machine returns to INIT_RUN state. It is possible to program the PGOOD1 and PGOOD2 pins also to assert during an FCCU fault. PGOOD1/2 may be used to assert RESET of the MCU in this case.

17.4.3 FCCU status reporting via interrupt register

The FCCU12_ERR bit is set high when an error in FCCU12 (bi-stable) is detected. Table 43. FCCU1/2 status reporting error scenarios

17.5 External signal monitoring using ERRMON

The ERRMON1/2 input is activated on entering the INIT_RUN state. transition to the NORMAL STATE. used to assert the FS0B pin as described below. microcontroller to acknowledge the ERRMON fault. If the ERRMON1/2_I bit is not cleared before the timer expires, the FS0B pin is asserted. The below diagram shows an example of the ERRMON function. Figure 17. Low-level ERRMONx detected as error Table 44. ERRMON acknowledge timer selection FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

17.6 PGOOD1/2 programmable reactions for ASIL B and Enhanced ASIL B

ASIL B and Enhanced ASIL B versions. may be configured differently using OTP to provide varied functions at the system level. For simplicity, PGOODx is used in place of PGOOD1 and PGOOD2. causes PGOODx to be pulsed low for 8 ms. Table 45. PGOOD1/2 programmable reactions monitor has no impact on the PGOODx pin. using the OTP_PGOODx_DELAY[2:0] bits. See Table 31 for details. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

17.6.1 Watchdog impact on PGOOD1/2

1024ms) is considered a Watchdog failure and the assigned PGOODx pin is toggled. the watchdog fault impact settings (independent of PGOODx behavior).

17.7 FS0B pin

ERRMON, valid FCCU, and monitoring of PGOOD1/2. The FS0B pin is released high in the NORMAL state. It is asserted low in all other states. FS0B is a global pin, and can be pulled up to VIN if required in the system.

17.7.1 FS0B pin electrical specifications

Table 46. FS0B pin electrical specifications

17.8 PGOOD1, PGOOD2, FS0B stuck at fault check

PGOOD1_STUCK_AT_1 = 1 indicates that PGOOD1 pin is stuck at 1. PGOOD1_STUCK_AT_0 = 1 indicates that PGOOD1 pin is stuck at 0. PGOOD2_STUCK_AT_1 = 1 indicates that PGOOD2 pin is stuck at 1. PGOOD2_STUCK_AT_0 = 1 indicates that PGOOD2 pin is stuck at 0. FS0B_STUCK_AT_1 = 1 indicates that FS0B pin is stuck at 1. FS0B_STUCK_AT_0 = 1 indicates that FS0B pin is stuck at 0. it is at logic high. If not, the corresponding 'STUCK_AT_0' bit is set set. these bits to control state transitions.

17.9 I2C robustness

17.9.1 I2C CRC verification

When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled. When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled. the configuration command has not been corrupted. command and sets the CRC_I bit. The CRC_I is cleared by writing a 1 to it. The FS5600 implements a CRC-8-SAE, per the SAE J1850 specification. Figure 18 shows the 8-bit CRC polynomial per SAE J1850. Figure 18. 8-bit CRC Polynomial FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

17.9.2 NOT logic registers

Write the desired data in the REGISTER
Write the NOT value of Step 1 to the corresponding NOT_REGISTER

SWx regulator will be enabled if ((SWx_EN = 1 AND NOT_SWx_EN = 0) AND (ENx pin = HIGH)).
SWx regulator will be disabled if ((SWx_EN = 0 AND NOT_SWx_EN = 1) OR (ENx pin = LOW)). A real-time XOR is performed to ensure that only complimentary register values are accepted. Refer to Section 18 for list of registers where this feature is applicable.

17.10 I2C Write protection

Table 47. List of registers modifiable only during INIT_RUN state Table 48. INIT_RUN protected registers after first WD_OK if watchdog enabled. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

17.11 Fault error counter

programmable using the FLT_ERR_CNT_LIMIT[1:0] bits.

00 Max value = 1

10 Max value = 6

11 Max value = 12

Table 49. FLT_ERR_CNT_LIMIT[1:0] description 0b1 to the CLR_FLT_ERR_CNT bit and 0b0 to the NOT_CLR_FLT_ERR_CNT bit. the watchdog refresh counter reaches its maximum value. when watchdog is enabled is not recommended. The fault error counter is incremented each time an assigned fault occurs. assigned to either of the PGOODx pins. assigned to either of the PGOODx pins. assigned to either of the PGOODx pins. assigned to either of the PGOODx pins. assigned to either of the PGOODx pins. assigned to either of the PGOODx pins. Table 50. Fault counter source assignment FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Table 50. Fault counter source assignment...continued ERRMON1/2 in the INIT_RUN state, the FLT_ERR_CNT is not incremented.

17.12 Latent failure detection

17.12.1 Analog built-in self-test (ABIST)

CRC check on mirror registers
Checking that internal oscillators are within 15% tolerance
Checking main band gap and monitoring band gap are within 12% of each other
ABIST on SW1, SW2, VMON1, VMON2, VMON3, VMON4 voltage monitors.
Check on PGOOD1, PGOOD2, and FS0B pins (check if PGOOD1, PGOOD2, and FS0B pins are low during ABIST) GPIO pins when used as inputs (FCCU/ERRMON) can be checked at the system level using real-time status registers (GPIO1/2/3_RT). Results from ABIST are stored in registers for evaluation by the processor. The system microcontroller shall be responsible to evaluate the ABIST results and determine if the FS5600 can proceed to the NORMAL STATE. Flag name Description ABIST_CRC_ERR = 1 indicates that there was an error with the CRC values in the mirror register. ABIST_OSC_ERR = 1 indicates that the 20 MHz oscillator is not within 15 % of its nominal value. BG_ERR = 1 indicates that the main and monitoring band gaps are not within 12 % of each other. ABIST_VMON1_OV_ERR = 1 indicates that the VMON1's over voltage monitor is not operating in the expected range. ABIST_VMON1_UV_ERR = 1 indicates that the VMON1's under voltage monitor is not operating in the expected range. ABIST_VMON2_OV_ERR = 1 indicates that the VMON2's over voltage monitor is not operating in the expected range. ABIST_VMON2_UV_ERR = 1 indicates that the VMON2's under voltage monitor is not operating in the expected range.

monitor is not operating in the expected range. monitor is not operating in the expected range. monitor is not operating in the expected range. monitor is not operating in the expected range. not operating in the expected range. is not operating in the expected range. not operating in the expected range. is not operating in the expected range. Table 51. ABIST flag bits...continued The above bits are all 0 if ABIST test is successful.

17.12.2 On-demand ABIST

clearing after completing the on-demand ABIST. FS0B is asserted low during on-demand ABIST if initiated in the INIT_RUN state. FS0B remains high during on-demand ABIST if initiated in the NORMAL state.

17.12.3 Logical Built-In Self-Test (LBIST)

the logic block in the FS5600. LBIST can be disabled by setting the OTP_LBIST_DIS[7:0] to 0b0011_0110.

No boot error (from OTP controller)
No CRC error (from OTP controller)
No ECC error (from OTP controller) If one of these conditions are not satisfied LBIST is enabled. LBIST_PASS bit in the I2C map is set when LBIST is completed successfully and passes.

17.12.4 VCC and VDIG monitoring

otherwise noted. Typical values are specified at 25 °C, unless otherwise noted. Table 52. POR Thresholds

17.13 FS5600 operation states and state machine

Automotive buck regulator and controller with voltage monitors and watchdog timer

17.13.1 Shut-down mode

This is the state of the FS5600 when a valid VIN is applied, but EN1 and EN2 pins are held low. From one of the operation modes, (INIT_RUN/NORMAL STATE/On Demand ABIST, Deep Fail-Safe), when EN1 and EN2 = 0, the IC enters the shut-down mode through the 'Power Down' state. When entering the shut-down mode from INIT_RUN, NORMAL STATE or on-demand ABIST states, the FS5600 sequences the GPOs in the reverse order of the power-up at the appropriate time. See Section 17.13.8 for details. For example, if OTP_GPO1_DELAY is set to 1 ms, and OTP_GPO2_DELAY is set to 5 ms:

When EN1 = EN2 = 0, GPO2 is asserted low immediately, 4 ms after which GPO1 is asserted low, 1 ms after which SW1 and SW2 regulators are disabled.
FS0B is asserted low immediately after NORMAL STATE is exited.

17.13.2 Built-in self-test (BIST)

Analog Built-in self-test (ABIST) and logical built-in self-test (LBIST) are executed in this state if enabled. This state is bypassed if both are disabled.

17.13.3 Power-up

SW1, SW2, and the various GPOs in FS5600 are powered up in this state. SW1 and SW2 are enabled after exiting BIST or thermal shutdown and if their respective ENx pin is held high. The power-up state exits upon completion of the highest delay among OTP_GPO1_DELAY[2:0], OTP_GPO2_DELAY[2:0] and OTP_GPO3_DELAY[2:0]. The OTP_PGOOD1_DELAY[2:0] and OTP_PGOOD2_DELAY[2:0] timers run in parallel to the GPO timers and do not need to expire to exit the power-up state. PGOOD1 and PGOOD2 may be released high even in the INIT_RUN state.

17.13.4 Power-up in Debug Mode

The FS5600 offers a Debug Mode of operation that is useful during system bring up and/ or development. When in Debug Mode, the following restrictions are in place:

Deep Fail-Safe transition is disabled
Watchdog window duration is set to infinite To power up in Debug Mode, apply VDDOTP_GPIO1 = 8 V before EN1 or EN2 go high or before VIN is applied. In this condition, the FS5600 pauses power-up and waits for VDDOTP_GPIO1 < 1 V before continuing to power up in Debug Mode. Ensure that there is board-level isolation on the VDDOTP_GPIO1 bus if the GPIO1 function is used at a lower voltage level. While VDDOTP_GPIO1 is maintained at 8 V, the following I2C commands can be sent to open access to the OTP mirror registers: SET_REG:FS5600:Functional:TM_ENTRY:0xD5A7 SET_REG:FS5600:Functional:TM_ENTRY:0xB8EE SET_REG:FS5600:Functional:TM_ENTRY:0x0F37 FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

Automotive buck regulator and controller with voltage monitors and watchdog timer The mirror registers modified in this fashion take effect during power-up when VDDOTP_GPIO < 1 V. Contact your NXP representative for commands needed to access the mirror registers.

17.13.5 INIT_RUN

The INIT_RUN state is entered after the power-up state. Either or both SW1 and SW2 may be enabled to enter the INIT_RUN state. The state machine can remain in the INIT_RUN state indefinitely. In this state, the state machine waits for conditions to transition to the normal state if enabled to do so. Alternatively, the state machine may proceed to power down to the Deep Fail-Safe state if conditions enabling this are met. INIT_RUN state may also be entered from the normal state by setting the GOTO_INIT_RUN and clearing the NOT_GOTO_INIT_RUN bits.

17.13.6 Normal state

In the normal state, the FS0B pin is de-asserted to indicate to the system that essential parameters monitored by the FS5600 are in expected range. The normal state is entered from the INIT_RUN state, provided conditions for this transition are met. OTP_NORMAL_STATE_EN bit should be set to 1 to enable transition to the normal state. OTP_ERRMON1_SAFE = 1 is an enabling condition for a valid ERRMON1 signal to control transition to the normal state. OTP_ERRMON2_SAFE = 1 is an enabling condition for a valid ERRMON2 signal to control transition to the normal state. OTP_PGOOD1_SAFE = 1 is an enabling condition for a valid PGOOD1 output to control transition to the normal state. OTP_PGOOD2_SAFE = 1 is an enabling condition for a valid PGOOD2 output to control transition to the normal state. See Section 17.13.10 for conditions to transition to the normal state.

17.13.7 Deep fail-safe state

In the deep fail-safe state, the FS5600 is shut down. All the regulators are turned off and signal outputs are asserted low. The only way to exit deep fail-safe state is through a power cycle on the VIN input, or if both EN1 and EN2 are pulled low in the application. Deep fail-safe can be entered when the fault error counter reaches is maximum value, or when a watchdog failure is programmed to go to deep fail-safe. OTP_DFS_EN must be set to 1 to enable transition to the Deep Fail-Safe state. See Section 17.13.10 for detailed conditions.

17.13.8 Power-down

The FS56 enters a graceful power-down when both EN1 and EN2 are asserted low in the application. The power-down follows a reverse of the power-up sequence for the GPOs (each following the OTP_GPOx_DELAY[2:0] setting) followed by SW1 and/or SW2. If entering power-down from deep fail-safe, thermal shut-down, or power-up, the state machine immediately enters shut-down mode after SW1, SW2, and GPIOs are asserted low (no power-down sequence). FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

17.13.9 Low-power operation

There are several ways to reduce the quiescent current consumption of the FS5600.

Turning off SW1 and SW2 (via I2C, or using EN1/2 pins)
Changing SW1 and SW2 operation mode from PWM to Auto Skip or PFM mode. The operation mode of SW1 and SW2 may be changed using I2C or by using the MODE pin.

17.13.9.1 Ultra low-power operation

FS5600. The user may choose its value in ASIL B and Enhanced ASIL B versions.

17.13.10 State transition table

18 I2C Register Map

18.1 Register descriptions

The following bit-types are used in the FS5600 register map. Table 55. FS5600 register map bit-types

18.1.1 SW1CTRL register

1b'1 — SW1 Enabled provided EN1 is high. MODE[1:0] = NOT(NOT_SW1_MODE[1:0]). Table 56. SW1CTRL register description

18.1.2 NOT_SW1CTRL register

1b'0 — See SW1_EN in SW1CTRL register. 1b'1 — See SW1_EN in SW1CTRL register. 2b'00 — See SW1_MODE[1:0] in SW1CTRL register. 2b'01 — See SW1_MODE[1:0] in SW1CTRL register. 2b'10 — See SW1_MODE[1:0] in SW1CTRL register. 2b'11 — See SW1_MODE[1:0] in SW1CTRL register. Table 57. NOT_SW1CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

18.1.3 SW2CTRL register

1b'1 — SW2 Enabled provided EN2 is high. MODE[1:0] = NOT(NOT_SW2_MODE[1:0]). Table 58. SW2CTRL register description

18.1.4 NOT_SW2CTRL register

1b'0 — See SW2_EN in SW2CTRL register. 1b'1 — See SW2_EN in SW2CTRL register. MODE[1:0] = NOT(NOT_SW2_MODE[1:0]). 2b'00 — See SW2_MODE[1:0] in SW2CTRL register. 2b'01 — See SW2_MODE[1:0] in SW2CTRL register. 2b'10 — See SW2_MODE[1:0] in SW2CTRL register. 2b'11 — See SW2_MODE[1:0] in SW2CTRL register. Table 59. NOT_SW2CTRL register description

18.1.5 GPIO_CTRL register

8 MODE_RT SYNCIN_MODE input state (after deglitcher). 1b'0 — SYNCIN_MODE pin is low. 1b'1 — SYNCIN_MODE pin is high. 5 GPIO3_RT GPIO3 input state (after deglitcher). Table 60. GPIO_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

4 GPIO2_RT GPIO2 input state (after deglitcher). 3 GPIO1_RT GPIO1 input state (after deglitcher). 1b'0 — GPIO1_VDDOTP pin is low. 1b'1 — GPIO1_VDDOTP pin is high.

2 GPIO3_OUTPUT GPIO3 output control if programmed as output by OTP_GPIO3_

1b'0 — GPIO3 pin output driven low. 1b'1 — GPIO3 pin output HZ (pull-up).

1 GPIO2_OUTPUT GPIO2 output control if programmed as output by OTP_GPIO2_

1b'0 — GPIO2 pin output driven low. 1b'1 — GPIO2 pin output HZ (pull-up).

0 GPIO1_OUTPUT GPIO1 output control if programmed as output by OTP_GPIO1_

1b'0 — GPIO1_VDDOTP pin output driven low. Table 60. GPIO_CTRL register description...continued

18.1.6 NOT_GPIO_CTRL register

2 NOT_GPIO3_OUTPUT GPIO3 output control. 1b'0 — See GPIO3_OUTPUT in GPIO_CTRL register. 1b'1 — See GPIO3_OUTPUT in GPIO_CTRL register.

1 NOT_GPIO2_OUTPUT GPIO2 output control

1b'0 — See GPIO2_OUTPUT in GPIO_CTRL register. 1b'1 — See GPIO2_OUTPUT in GPIO_CTRL register.

0 NOT_GPIO1_OUTPUT GPIO1 output control

1b'0 — See GPIO1_OUTPUT in GPIO_CTRL register. 1b'1 — See GPIO1_OUTPUT in GPIO_CTRL register. Table 61. NOT_GPIO_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

18.1.7 CLOCK_CTRL register

5 FSS_FMOD Frequency (triangular period) of internal 20 MHz oscillator frequency

4 FSS_EN Internal 20 MHz oscillator frequency spread spectrum control. 1b'0 — Frequency spread spectrum disabled. 1b'1 — Frequency spread spectrum enabled. 3 to 0 CLK_FREQ[3:0] Internal 20 MHz oscillator frequency selection (Unit MHz). Table 62. CLOCK_CTRL register description

18.1.8 NOT_CLOCK_CTRL register

3 to 0 NOT_CLK_FREQ[3:0] Internal 20 MHz oscillator frequency programming (Unit MHz). 4b'0000 - 4b’1111 — See CLK_FREQ[3:0] in CLK_CTRL register. Table 63. NOT_CLOCK_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

18.1.9 WATCHDOG_CTRL1 register

15 to 14 WD_ERR_LIMIT[1:0] Watchdog error counter limit. 12 to 11 WD_RFR_LIMIT[1:0] Watchdog refresh counter limit. 9 to 8 WD_FAIL_IMPACT[1:0] Watchdog fail impact. 00 — No impact on FSM : stay in NORMAL state. 01 — Transition to INIT_RUN or remain in INIT_RUN state. 10 — Transition to DEEP_FAIL_SAFE state. 11 — No impact on FSM : stay in NORMAL state. 6 to 4 WD_RFR_CNT[2:0] Watchdog refresh counter value. Resets on overflow. Table 64. WATCHDOG_CTRL1 register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

4b'0000 — Counter Value = 0. 4b'0001 — Counter Value = 1. 4b'0010 — Counter Value = 2. 4b'0011 — Counter Value = 3. 4b'0100 — Counter Value = 4. 4b'0101 — Counter Value = 5. 4b'0110 — Counter Value = 6. 4b'0111 — Counter Value = 7. 4b'1000 — Counter Value = 8. 4b'1001 — Counter Value = 9. Table 64. WATCHDOG_CTRL1 register description...continued

18.1.10 NOT_WATCHDOG_CTRL1 register

15 to 14 NOT_WD_ERR_LIMIT[1:0] Watchdog error counter limit. 2b'00 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'01 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'10 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'11 — See WD_ERR_LIMIT[1:0] in WATCHDOG_CTRL1 register. 12 to 11 NOT_WD_RFR_LIMIT[1:0] Watchdog refresh counter limit. 2b'00 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'01 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'10 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register. 2b'11 — See WD_RFR_LIIMIT[1:0] in WATCHDOG_CTRL1 register. 9 to 8 NOT_WD_FAIL_IMPACT[1:0] Watchdog fail impact. Table 65. NOT_WATCHDOG_CTRL1 register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

18.1.11 WATCHDOG_CTRL2 register

10 to 8 WDW_DC[2:0] Watchdog window duty cycle. Applied only when WDW_DC[2:0] = NOT(NOT_WDW_DC[2:0]). 3b'000 — Closed window 31.25 % Open window 68.75 %. 3b'001 — Closed window 37.5 % Open window 62.5 %. 3b'010 — Closed window 50 % Open window 50 %. 3b'011 — Closed window 62.5 % Open window 37.5 %. 3b'100 — Closed window 68.75 % Open window 31.25 %. 3b'101 — Closed window 50 % Open window 50 %. 3b'110 — Closed window 50 % Open window 50 %. 3b'111 — Closed window 50 % Open window 50 %. Table 66. WATCHDOG_CTRL2 register description

18.1.12 NOT_WATCHDOG_CTRL2 register

15 to 12 NOT_WD_WINDOW[3:0] Watchdog window duration. 10 to 8 NOT_WDW_DC[2:0] Watchdog window duty cycle. Table 67. NOT_WATCHDOG_CTRL2 register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

18.1.13 WATCHDOG_SEED register

15 to 0 WD_SEED[15:0] Watchdog seed. It is impossible to write 16'hFFFF for challenger watchdog. It is impossible to write 16'h0000 or 16'hFFFF for simple watchdog. Table 68. WATCHDOG_SEED register description

18.1.14 WATCHDOG_ANSWER register

15 to 0 WD_ANSWER[15:0] Watchdog answer.

For simple watchdog WD_ANSWER = WD_SEED.
For challenger watchdog WD_ANSWER = ~WD_SEED. Reset Condition — POR

Table 69. WATCHDOG_ANSWER register description

18.1.15 OD_ABIST_CTRL register

ABIST), self cleared when ABIST is finished. Table 70. OD_ABIST_CTRL register description

18.1.16 NOT_OD_ABIST register

0 NOT_OD_ABIST On-demand ABIST. 1b'0 — See OD_ABIST in OD_ABIST_CTRL register. 1b'1 — See OD_ABIST in OD_ABIST_CTRL register. Table 71. NOT_OD_ABIST register description

18.1.17 BIST_STATUS1 register

14 BG_ERR Bandgap monitor ABIST status. Table 72. BIST_STATUS1 register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

13 ABIST_SW2_UV_ERR Switcher SW2 undervoltage monitor ABIST status,

12 ABIST_SW2_OV_ERR Switcher SW2 overvoltage monitor ABIST status. 11 ABIST_SW1_UV_ERR Switcher SW1 undervoltage monitor ABIST status. 10 ABIST_SW1_OV_ERR Switcher SW1 overvoltage monitor ABIST status. 9 ABIST_VMON4_UV_ERR VMON4 undervoltage monitor ABIST status. 8 ABIST_VMON4_OV_ERR VMON4 overvoltage monitor ABIST status. 7 ABIST_VMON3_UV_ERR VMON3 undervoltage monitor ABIST status. 6 ABIST_VMON3_OV_ERR VMON3 overvoltage monitor ABIST status. 5 ABIST_VMON2_UV_ERR VMON2 undervoltage monitor ABIST status.

4 ABIST_VMON2_OV_ERR VMON2 overvoltage monitor ABIST status

3 ABIST_VMON1_UV_ERR VMON1 undervoltage monitor ABIST status. Table 72. BIST_STATUS1 register description...continued FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

2 ABIST_VMON1_OV_ERR VMON1 overvoltage monitor ABIST status. 1 ABIST_OSC_ERR Oscillators 20 MHz / 100 kHz monitor ABIST status. 0 ABIST_CRC_ERR OTP CRC status calculated during ABIST.

18.1.18 BIST_STATUS2 register

13 FS0B_STUCK_AT_0 FS0B pin stuck at 0 flag. 1b'0 — No stuck at 0 detected. 12 FS0B_STUCK_AT_1 FS0B pin stuck at 1 flag. 11 PGOOD2_STUCK_AT_0 PGOOD2 pin stuck at 0 flag. 1b'0 — No stuck at 0 detected. 10 PGOOD2_STUCK_AT_1 PGOOD2 pin stuck at 1 flag. 9 PGOOD1_STUCK_AT_0 PGOOD1 pin stuck at 0 flag. 1b'0 — No stuck at 0 detected. 8 PGOOD1_STUCK_AT_1 PGOOD1 pin stuck at 1 flag. 1b'0 — No stuck at 1 detected. 1 LBIST_DONE LBIST completion status. Table 73. BIST_STATUS2 register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

0 LBIST_PASS Logic BIST status. 1b'1 — Logic BIST done and pass. Table 73. BIST_STATUS2 register description...continued

18.1.19 FAULT_CTRL register

6 CLR_FLT_ERR_CNT Clear fault error counter. 1b'1 — Clear fault error counter. Clear CLR_FLT_ERR_CNT bit. 5 to 2 FLT_ERR_CNT[3:0] Fault error counter value. 4b'0000 — Counter Value = 0. 4b'0001 — Counter Value = 1. 4b'0010 — Counter Value = 2. 4b'0011 — Counter Value = 3. 4b'0100 — Counter Value = 4. 4b'0101 — Counter Value = 5. 4b'0110 — Counter Value = 6. 4b'0111 — Counter Value = 7. 4b'1000 — Counter Value = 8. 4b'1001 — Counter Value = 9. 1 to 0 FLT_ERR_CNT_LIMIT[1:0] Fault error counter limit. Table 74. FAULT_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

18.1.20 NOT_FAULT_CTRL register

6 NOT_CLR_FLT_ERR_CNT Clear fault error counter (NOT bit). 1b'0 — See CLR_FLT_ERR_CNT in FAULT_CTRL register. 1b'1 — See CLR_FLT_ERR_CNT in FAULT_CTRL register. 1 to 0 NOT_FLT_ERR_CNT_LIMIT[1:0] Fault error counter limit. 2b'00 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register. 2b'01 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register. 2b'10 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register. 2b'11 — See FLT_ERR_CNT_LIMIT[1:0] in FAULT_CTRL register. Table 75. NOT_FAULT_CTRL register description

18.1.21 VMON_STS register

14 SW2_ILIM_I SW2 current limit fault. 1b'1 — Current limit detected. 13 SW1_ILIM_I SW1 current limit fault. 1b'1 — Current limit detected. 12 TSD_I Thermal shutdown indicator. 1b'0 — No thermal shutdown or cleared. 1b'1 — Thermal shutdown detected. 11 SW2_UV_I SW2 monitor undervoltage. 1b'1 — Overvoltage detected. 10 SW1_UV_I SW1 monitor undervoltage. 1b'1 — Overvoltage detected. 9 VMON4_UV_I VMON4 monitor undervoltage. 1b'1 — Overvoltage detected. 8 VMON3_UV_I VMON3 monitor undervoltage. 1b'1 — Overvoltage detected. Table 76. VMON_STS register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

7 VMON2_UV_I VMON2 monitor undervoltage. 1b'1 — Overvoltage detected. 6 VMON1_UV_I VMON1 monitor undervoltage. 1b'1 — Overvoltage detected. 5 SW2_OV_I SW2 monitor overvoltage. 1b'1 — Overvoltage detected. 4 SW1_OV_I SW1 monitor overvoltage. 1b'1 — Overvoltage detected. 3 VMON4_OV_I VMON4 monitor overvoltage. 1b'1 — Overvoltage detected. 2 VMON3_OV_I VMON3 monitor overvoltage. 1b'1 — Overvoltage detected. 1 VMON2_OV_I VMON2 monitor overvoltage. 1b'1 — Overvoltage detected. 0 VMON1_OV_I VMON1 monitor overvoltage. 1b'1 — Overvoltage detected. Table 76. VMON_STS register description...continued

18.1.22 VMON_RT register

14 SW2_ILIM_RT SW2 current limit. 1b'0 — No current limit fault. 1b'1 — Current limit exists. 13 SW1_ILIM_RT SW1 current limit. 1b'0 — No current limit fault. 1b'1 — Current limit exists. Table 77. VMON_RT register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

12 TSD_RT thermal shutdown indicator. 1b'0 — No thermal shutdown or cleared. 1b'1 — Thermal shutdown detected. 11 SW2_UV_RT SW2 monitor undervoltage. 1b'1 — Overvoltage detected. 10 SW1_UV_RT SW1 monitor undervoltage. 1b'1 — Overvoltage detected. 9 VMON4_UV_RT VMON4 monitor undervoltage. 1b'1 — Overvoltage detected. 8 VMON3_UV_RT VMON3 monitor undervoltage. 1b'1 — Overvoltage detected. 7 VMON2_UV_RT VMON2 monitor undervoltage. 1b'1 — Overvoltage detected. 6 VMON1_UV_RT VMON1 monitor undervoltage. 1b'1 — Overvoltage detected. 5 SW2_OV_RT SW2 monitor overvoltage. 1b'1 — Overvoltage detected. 4 SW1_OV_RT SW1 monitor overvoltage. 1b'1 — Overvoltage detected. 3 VMON4_OV_RT VMON4 monitor overvoltage. 1b'1 — Overvoltage detected. 2 VMON3_OV_RT VMON3 monitor overvoltage. 1b'1 — Overvoltage detected. Table 77. VMON_RT register description...continued FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

1 VMON2_OV_RT VMON2 monitor overvoltage. 1b'1 — Overvoltage detected. 0 VMON1_OV_RT VMON1 monitor overvoltage. 1b'1 — Overvoltage detected.

18.1.23 GPIO_STS register

12 FCCU12_ERR FCCU12 error (bistable). 5 BAD_WD_TIMING Watchdog error bad timing. answer register in closed window or timeout). 4 BAD_WD_DATA Watchdog error bad answer. Table 78. GPIO_STS register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

1 I2C_CRC_ERR I2C CRC error. 1b'1 — CRC error detected in write operation. 0 I2C_REQ_ERR I2C request error. Table 78. GPIO_STS register description...continued

18.1.24 FCCU_CFG register

14 FCCU12_FLT_POL FCCU bistable fault polarity. 1b'0 — FCCU1 low or FCCU2 high is a fault. 1b'1 — FCCU1 high or FCCU2 low is a fault. 13 FCCU1_FLT_POL FCCU1 fault polarity. 1b'0 — FCCU1 low is a fault. 1b'1 — FCCU1 high is a fault. 12 FCCU2_FLT_POL FCCU2 fault polarity. 1b'0 — FCCU2 low is a fault. 1b'1 — FCCU2 high is a fault. 8 FCCU12_BISTABLE FCCU1/FCCU2 bistable control. 1b'0 — Independent FCCU1/FCCU2. 1b'1 — FCCU1/FCCU2 configured as bistable. Table 79. FCCU_CFG register description

18.1.25 NOT_FCCU_CFG register

14 NOT_FCCU12_FLT_POL FCCU bistable fault polarity. See FCCU12_FLT_POL in FCCU_CFG register. Table 80. NOT_FCCU_CFG register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

13 NOT_FCCU1_FLT_POL FCCU1 fault polarity. See FCCU1_FLT_POL in FCCU_CFG register. 12 NOT_FCCU2_FLT_POL FCCU2 fault polarity. See FCCU2_FLT_POL in FCCU_CFG register. 8 NOT_FCCU12_BISTABLE FCCU1/FCCU2 bistable control. See FCCU12_BISTABLE in FCCU_CFG register. Table 80. NOT_FCCU_CFG register description...continued

18.1.26 STATE_CTRL register

15 DBG_EXIT Used to unlatch debug mode. 1 GOTO_INIT_RUN Go to INIT_RUN state command. cleared when in state INIT_RUN). 0 GOTO_NORMAL Go to NORMAL state command. Applied only when GOTO_NORMAL = NOT(NOT_GOTO_NORMAL). cleared when in state NORMAL). Table 81. STATE_CTRL register description

18.1.27 NOT_STATE_CTRL register

1 NOT_GOTO_INIT_RUN Go to INIT_RUN state command. 1b'0 — See GOTO_INIT_RUN in STATE_CTRL register. 1b'1 — See GOTO_INIT_RUN in STATE_CTRL register. 0 NOT_GOTO_NORMAL Go to NORMAL state command. 1b'0 — See GOTO_NORMAL in STATE_CTRL register. 1b'1 — See GOTO_NORMAL in STATE_CTRL register. Table 82. NOT_STATE_CTRL register description FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

18.1.28 STATE register

4 to 0 PMIC_FSM[4:0] Indicates FSM State. Table 83. STATE register description

18.1.29 ID1 register

3 to 0 DEVICEID[3:0] Device variation identification. Defaulted to 0. Table 84. ID1 register description

19 Typical application curves

20 Typical Application Block Diagram

5.0 VBattery (< 40 V)

3.3 VSW2

20.1 Example power up and power down waveforms

21 Typical Application Schematic

32 VIN

31 SYNCIN/MODE

27 PGOOD2

26 PGOOD1

22.1 Package outline – ES version (wettable flank)

Figure 34. Package outline HVQFN32 (SOT617-24(SC)) – ES version (wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 35. Package outline detail HVQFN32 (SOT617-24(SC)) – ES version (wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 37. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) – FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 38. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) – FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 39. Package outline note HVQFN32 (SOT617-24(SC)) – ES version (wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

22.2 Package outlines – EP version (non-wettable flank)

Figure 40. Package outline HVQFN32 (SOT617-24(SC)) – EP version (non-wettable flank) FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 41. Package outline detail HVQFN32 (SOT617-24(SC)) – EP version (non-wettable FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 43. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) – FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 44. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) – FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 45. Package outline note HVQFN32 (SOT617-24(SC)) – EP version (non-wettable FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

In Figure 1, under SW@ - Buck Controller, changed >10 A to up to 15 A
In Section 10, added this note below the table: In the absence of BIAS_IN, VIN falling below this voltage will cause FS5600 to power off
In Section 12.1, corrected the units of Error Amplifier Transconductance from ms to mS
In Section 12.2.1, added this to the end of the paragraph after the first table: When operating at 450 kHz or lower, by choosing low Rds(on) MOSFETs in separate packages, and with a low DCR inductor, SW2 can be designed to support loads of up to 15 A. Refer to the schematic of KITFS5600FRDMEVM for a design that can support 15 A.
Reorganized Section 12, adding Section 12.2.1.2 material
In Section 12.2.1.1, added Use closest standard values for resistor and capacitors to the end of the section
In Section 17.6.1, added PGOODx toggle due to a before watchdog failure
In Section 17.13.7, changed OTP_DFN_EN to OTP_DFS_EN
Added Section 19
In Figure 11, in the Divider 1 box, changed /8 to /7. In the Divider 2 box, changed /48 to /44.
In Figure 33, made these pin numbering changes at the lower left: Swap 5-6 Swap 4-2 Swap 3-1 FS5600 v.2 20210601 Product data sheet — v.1 Modifications Moved from Objective status to Product status FS5600 v.1 20201029 Objective data sheet — — Modifications Initial release

Automotive buck regulator and controller with voltage monitors and watchdog timer

24 Legal information

24.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

24.2 Definitions

Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

24.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

Automotive buck regulator and controller with voltage monitors and watchdog timer Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. Suitability for use in automotive applications (functional safety) — This NXP product has been qualified for use in automotive applications. It has been developed in accordance with ISO 26262, and has been ASIL classified accordingly. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application.

24.4 Trademarks

Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. SafeAssure — is a trademark of NXP B.V. FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

Automotive buck regulator and controller with voltage monitors and watchdog timer Tables Tab. 6. QFN32 thermal resistance and package Tab. 29. SW1 and SW2 switching frequency Tab. 47. List of registers modifiable only during Tab. 48. INIT_RUN protected registers after first Tab. 65. NOT_WATCHDOG_CTRL1 register Tab. 67. NOT_WATCHDOG_CTRL2 register Tab. 69. WATCHDOG_ANSWER register Figures Fig. 5. ASIL B, and enhanced ASIL B version Fig. 7. SW1 output voltage setting using an Fig. 9. SW2 application schematic with Rshunt FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

Automotive buck regulator and controller with voltage monitors and watchdog timer Fig. 11. Clock management system high-level block Fig. 32. Example power up and power down Fig. 34. Package outline HVQFN32 (SOT617-24(SC)) – ES version (wettable Fig. 35. Package outline detail HVQFN32 (SOT617-24(SC)) – ES version (wettable Fig. 36. PCB design guidelines – solder mask opening pattern for HVQFN32 (SOT617-24(SC)) – ES version (wettable Fig. 37. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) – ES Fig. 38. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) – Fig. 39. Package outline note HVQFN32 (SOT617-24(SC)) – ES version (wettable Fig. 40. Package outline HVQFN32 (SOT617-24(SC)) – EP version (non- Fig. 41. Package outline detail HVQFN32 (SOT617-24(SC)) – EP version (non- Fig. 42. PCB design guidelines – solder mask opening pattern for HVQFN32 (SOT617-24(SC)) – EP version (non- Fig. 43. PCB guidelines – I/O pads and solderable area for HVQFN32 (SOT617-24(SC)) – EP Fig. 44. PCB design guidelines – solder paste stencil for HVQFN32 (SOT617-24(SC)) – Fig. 45. Package outline note HVQFN32 (SOT617-24(SC)) – EP version (non- FS5600 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 August 2022

Automotive buck regulator and controller with voltage monitors and watchdog timer

20.1 Example power up and power down

22.1 Package outline – ES version (wettable

22.2 Package outlines – EP version (non-

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2022 NXP B.V. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 2 August 2022 Document identifier: FS5600

Product Information

MFS5600AMBA0ES specifications and overview.

Summary

Automotive buck regulator and controller with voltage monitors and watchdog timer Rev. 3 - 2 August 2022

Description

Automotive buck regulator and controller with voltage monitors and watchdog timer Rev. 3 - 2 August 2022

Source title MFS5600AMBA0ES Datasheet(PDF) - NXP Semiconductors

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