MF8 NSC | Alldatasheet
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Technical content
Features
Y Center frequency set by external clock Y Q set by five-bit digital word Y Uncommitted inverting op amp Y 4th-order all-pole filters using only three external resistors Y Cascadable for higher-order filters Y Bandwidth, response characteristic, and center frequency independently programmable Y Separate TTL and CMOS clock inputs Y 18 pin 0.3 × wide package Key Specifications Y Center frequency range 0.1 Hz to 20 kHz Y Q range 0.5 to 90 Y Supply voltage range 9V to 14V ( g4.5V to g7V) Y Center frequency accuracy 1% over full temperature range Typical Application & Connection Diagrams TL/H/8694–1 Fourth-Order Butterworth Bandpass Filter Dual-In-Line Package TL/H/8694–2 Top View Order Number MF8CCJ or MF8CCN See NS Package Number J18A or N18A C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V S e Va b Vb) b0.3V to a15V Voltage at any Input (Note 2) V b b0.3V to V a a0.3V Input Current at any Input Pin (Note 2) g1m A Output Short-Circuit Current (Note 7) g1m A Power Dissipation (Note 3) 500 mW Storage Temperature b65§Ct o a150§C Soldering Information: J Package: 10 sec. 260 §C N Package: 10 sec. 300 §C Infrared (15 sec.) 220 §C ESD rating is to be determined. See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering sur- face mount devices. Operating Ratings (Note 1) Temperature Range T MIN s TA s TMAX MF8CCN 0 §C s TA s a70§C MF8CCJ b40§C s TA s a85§C Supply Voltage (V S e Va b Vb) a9V to a14V fCLK c Q Range for 10 Hz s fCLK s 250 kHz any Q for 250 kHz s fCLK s 1 MHz f CLK c Q s 5 MHz Filter Electrical Characteristics The following specifications apply for V a ea 5V, V b eb 5V, C LOAD e 50 pF and R LOAD e 50 k X on filter output unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits TA e TJ e 25§C. MF8CCN MF8CCJ Symbol Parameter Conditions Typical Tested Design Typical Tested Design Units(Notes 4, 5) (Note 9) Limit Limit (Note 9) Limit Limit (Note 10) (Note 11) (Note 10) (Note 11) QQ 100:1 3.92 g2% 3.92 g10% 3.92 g2% 3.92 g10% Rf CLK/fo ABCDE e 11100 QQ 100:1 15.5 g3% 15.5 g12% 15.5 g3% 15.5 g12% Rf CLK/fo ABCDE e 10011 QQ 50:1 55 g5% 55 g14% 55 g5% 55 g14% Rf CLK/fo ABCDE e 00001 DQ/QTH Q Deviation from V S e g5V g5% Theoretical f CLK s 250 kHz, Q l 1 g5% g15% g5% g15% (See Table I) f CLK s 100 kHz, 1 k Q k 57 g2% g6% g2% g6% DR/RTH fCLK/fo Deviation V S e g5V g5% from Theoretical f CLK s 250 kHz g0.3% g1% g0.3% g1% (See Table I) QQ f CLK e 250 kHz, 50:1 10.6 g2% 10.6 10.6 g2% 10.6 g10%ABCDE e 00110 g10% Dynamic Range ABCDE e 11100 86 86 dB (Note 6) ABCDE e 10011 80 80 dB ABCDE e 00001 75 75 dB Clock Filter and Op Amp Feedthrough f CLK s 250 kHz Q s 18 0 8 0 m V Q l 14 0 4 0 m V IS Maximum Supply f CLK e 250 kHz, no 91 2 12 9 13 mACurrent loads on outputs VOS Maximum Filter f CLK e 250 kHz, Q e 4 Output Offset 50:1 g40 g120 g40 g120 mV Voltage 100:1 g80 g240 g80 g240 mV
Op Amp Electrical Characteristics The following specifications apply for V a ea 5V, V b eb 5V and no load on the Op Amp output unless otherwise specified. Boldface limits apply for T MIN to TMAX; all other limits T A e TJ e 25§C. MF8CCN MF8CCJ Symbol Parameter Conditions Typical Tested Design Typical Tested Design Units Limit Limit Limit Limit (Note 9) (Note 10) (Note 11) (Note 9) (Note 10) (Note 11) VOS Maximum Input Offset Voltage g8 g20 g8 g20 mV IB Maximum Input Bias Current 10 10 pA VOUT Minimum Output Voltage Swing R LOAD e 5k X g3.5 g3.5 V AVOL Open Loop Gain 80 80 dB GBW Gain Bandwidth 1.8 1.8 MHzProduct SR Slew Rate 10 10 V/ ms Logic Input and Output Characteristics The following specifications apply for V a ea 10V and V b e 0V unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A e TJ e 25§C. MF8CCN MF8CCJ Symbol Parameter Conditions Typical Tested Design Typical Tested Design Units Limit Limit Limit Limit (Note 9) (Note 10 (Note 11) (Note 9) (Note 10) (Note 11) VTa Positive Threshold Min V S e Vab Vb referred 0.7V S 0.58VS 0.7VS 0.58VS V Voltage on pin 8 Max to V b e 0V (Note 8) 0.7VS 0.89VS 0.7VS 0.89VS V VTb Negative Threshold Min V S e Va b Vb referred 0.35V S 0.11VS 0.35VS 0.11VS V Voltage on pin 8 Max to V b e 0V (Note 8) 0.35VS 0.47VS 0.35VS 0.47VS V VOH Output Voltage on Min High I O eb 10 mA 9.0 9.0 9.0 V VOL pin 9 (Note 12) Max Low I O ea 10 mA 1.0 1.0 1.0 V IOH Output Current on Min Source Pin 9 tied to V b 6.0 3.0 6.0 3.0 mA IOL pin 9 Min Sink Pin 9 tied to V a 5.0 2.5 5.0 2.5 mA VIH Input Voltage on Min High 7.0 9.0 7.0 9.0 V VIL pins: 1, 2, 3, 10, Max Low 3.0 1.0 3.0 1.0 V17, & 18 (Note 12) IIN Input Current on pins: 1, 2, 10 10 10 mA3, 7, 8, 10, 17, & 18 VIH Input Voltage on Min High V a ea 10V, V b e 0V or 2.0 2.0 2.0 V VIL pin 7 Max Low Va ea 5V, V b eb 5V 0.8 0.8 0.8 V Note 1: Absolute Maximum Raings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: When the applied voltage at any pin falls outside the power supply voltages (V IN k Vb or V IN l Va), the absolute value of current at that pin should be limited to 1 mA or less. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX, HJA, and the ambient temperature, T A. The maximum allowable power dissipation at any temperature is P D e (TJMAX b TA)/HJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T JMAX e 125§C, and the typical junction-to-ambient thermal resistance of the MF8CCN when board mounted is 50 §C/W. For the MF8CCJ, this number increases to 65 §C/W. Note 4: The center frequency of each 2nd-order filter section is defined as the frequency where the phase shift through the filter is zero. Note 5: Q is defined as the measured center frequency divided by the measured bandwidth, where the bandwidth is the difference between the two frequencies where the gain is 3 dB less than the gain measured at the center frequency. Note 6: Dynamic range is defined as the ratio of the tested minimum output swing of 2.69 Vrms ( g3.8V peak-to-peak) to the wideband noise over a 20 kHz bandwidth. For Qs of 1 or less the dynamic range and output swing will degrade because the gain at an internal node is 2/Q. Keeping the input signal level below 1.23xQ Vrms will avoid distortion in this case.
Note 7: If it is possible for a signal output (pin 6, 14, or 15) to be shorted to V a,V b or ground, add a series resistor to limit output current. Note 8: If V b is anything other than 0V then the value of V b should be added to the values given in the table. For example for V a ea 5V and V b eb 5V the typical V Ta e 0.7 (10V) a (b5V) ea 2V. Note 9: Typicals are at 25 §C and represent the most likely parametric norm. Note 10: Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: Design Limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 12: These logic levels have been referenced to V b. The logic levels will shift accordingly for split supplies. Pin Descriptions Q Logic Inputs These inputs program the Qs of the two A, B, C, D, E 2nd-order bandpass filter stages. Logic (3, 2, 1, 18, 17): ‘‘1’’ is V a and logic ‘‘0’’ is V b. AGND (4): This is the analog and digital ground pin and should be connected to the system ground for split supply operation or bi- ased to mid-supply for single supply op- eration. For best filter performance, the ground line should be ‘‘clean’’. V a (12), These are the positive and negative Vb (11): power supply inputs. Decoupling the power supply pins with 0.1 mF or larger capacitors is highly recommended. F1 IN (16), These are the inputs to the bandpass fil- F2 IN (5): ter stages. To minimize gain error the source impedance should be less than 2 kX. Input signals should be referenced to AGND. F1 OUT (15), These are the outputs of the bandpass F2 OUT (6): filter stages. A IN (13): This is the inverting input to the uncom- mitted operational amplifier. The non-in- verting input is internally connected to AGND. A OUT (14): This is the output of the uncommitted operational amplifier. 50/100 (10): This pin sets the ratio of the clock fre- quency to the bandpass center frequen- cy. Connecting this pin to V a sets the ratio to 100:1. Connecting it to V b sets the ratio to 50:1. TTL CLK (7): This is the TTL-level clock input pin. There are two logic threshold levels, so the MF8 can be operated on either sin- gle-ended or split supplies with the logic input referred to either V b or AGND. When this pin is not used (or when CMOS logic levels are used), it should be connected to either V a or V b. CMOS CLK (8): This pin is the input to a CMOS Schmitt inverter. Clock signals with CMOS logic levels may be applied to this input. If the TTL input is used this pin should be con- nected to V RC (9): This pin allows the MF8 to generate its own clock signal. To do this, connect an external resistor between the RC pin and the CMOS Clock input, and an external capacitor from the CMOS Clock input to AGND. The TTL Clock input should be connected to V b or V a. When the MF8 is driven from an external clock, the RC pin should be left open.
1.0 Application Information
1.1 INTRODUCTION
A simplified block diagram for the MF8 is shown in Figure 1 . The analog signal path components are two identical 2nd- order bandpass filters and an operational amplifier. Each filter has a fixed voltage gain of 2. The filters’ cutoff frequen- cy is proportional to the clock frequency, which may be ap- plied to the chip from an external source or generated inter- nally with the aid of an external resistor and capacitor. The proportionality constant f CLK/f0 can be set to either 50 or 100 depending on the logic level on pin 10. The ‘‘Q’’ of the two filters can have any of 31 values ranging from 0.5 to 90 and is set by the logic levels on pins 1, 2, 3, 17, and 18. Table I shows the available values of Q and the logic levels required to obtain them. The operational amplifier’s non-in- verting input is internally grounded, so it may be used only for inverting applications. The components in the analog signal path can be intercon- nected in several ways, three of which are illustrated in Fig- ures 2a, 2b and 2c. The two second-order filter sections can be used as separate filters whose center frequencies track very closely as in Figure 2a . Each filter section has a high input impedance and low output impedance. The op amp may be used for gain scaling or other inverting functions. If sharper cutoff slopes are desired, the two filter sections may be cascaded as in Figure 2b . Again, the op amp is uncommitted. The circuit in Figure 2c uses both filter sec- tions with the op amp and three resistors to build a ‘‘multiple feedback loop’’ filter. This configuration offers the greatest flexibility for fourth-order bandpass designs. Virtually any fourth-order all pole response shape (Butterworth, Cheby- shev) can be obtained with a wide range of bandwidths, simply by proper choice of resistor values and Q. The three connection schemes in Figure 2 will be discussed in more detail in Sections 1.4 and 1.5.
Typical Performance Characteristics FrequencyÐ50:1 Mode fCLK/fo Ratio vs Clock FrequencyÐ100:1 Mode fCLK/fo Ratio vs Clock 100:1 Mode VoltageÐ50:1 and f CLK/fo Ratio vs Supply TemperatureÐ100:1 Mode fCLK/fo Ratio vs TemperatureÐ50:1 Mode fCLK/fo Ratio vs 50:1 and 100:1 Q vs TemperatureÐ 50:1 and 100:1 Q vs Supply VoltageÐ 50:1 and 100:1 Q vs Clock FrequencyÐ 50:1 and 100:1 Q vs Clock FrequencyÐ Frequency Response Op AmpÐOpen Loop Supply Rejection Positive Power Supply Rejection Negative Power TL/H/8694–24
Typical Performance Characteristics (Continued) Load Resistance Positive Swing vs Load Resistance Negative Swing vs Supply Voltage Negative Swing vs Supply Voltage Positive Swing vs (Filter and Op Amp) Negative Swing vs Temperature (Filter and Op Amp) Positive Swing vs Temperature Temperature Supply Current vs Supply Voltage Supply Current vs vs Supply Voltage Filter Offset Voltage QÐ50:1 and 100:1 Filter Offset Voltage vs FrequencyÐ50:1 and 100:1 Filter Offset Voltage vs Clock TemperatureÐ50:1 and 100:1 Filter Offset Voltage vs TL/H/8694–25
1.0 Application Information (Continued)
FIGURE 1. Simplified Block Diagram of the MF8
1.2 CLOCKS
Clock input should be connected to either pin 11 or pin 12. FIGURE 3. Dual Supply Operation
1.3 POWER SUPPLIES AND ANALOG GROUND
AGND should be bypassed to system ground. FIGURE 4. Single supply operation. The AGND pin must be biased to mid-supply. The input signal should be dc biased to mid-supply or capacitor-coupled to the input pin.
1.4 MULTIPLE FEEDBACK LOOP CONFIGURATION
ly flexible and stable, yet uses few external components. FIGURE 7. Graphical representation of the amplitude filter’s response should fall within the shaded area. FIGURE 5. General fourth-order multiple-feedback bandpass filter circuit. MF8 pin numbers are shown. FIGURE 6. By adding more second-order filter stages and feedback resistors, higher order multiple-feedback filters may be built.
fC1 and f C2: The filter’s lower and upper cutoff frequencies. These define the filter’s passband. fS1 and f S2: The boundaries of the filter’s stopband. BW: The filter’s bandwidth. BW e fC2 b fC1. SBW: The width of the filter’s stopband. SBW e fS2 b fS1. f0: The center frequency of the filter. f 0 is equal to the geo- metric mean of f C1 and f C2:f 0 e 0fC1fC2.f 0 is also equal to the geometric mean of f S1 and f S2. H0BP: The nominal passband gain of the bandpass filter. This is normally taken to be the gain at f 0. f0/BW: The ratio of the center frequency to the bandwidth. For second-order filters, this quantity is also known as ‘‘Q’’. SBW/BW: The ratio of stopband width to bandwidth. This quantity is also called ‘‘Omega’’ and may be represented by the symbol ‘‘ X’’. A max: The maximum allowable gain variation within the filter passband. This will depend on the system requirements, but typically ranges from a fraction of a dB to 3 dB. A min: The minimum allowable attenuation in the stopband. Again, the required value will depend on system constraints. 2). Choose a Butterworth or Chebyshev response charac- teristic. Butterworth bandpass filters are monotonic on ei- ther side of the center frequency, while Chebyshev filters will have ‘‘ripple’’ in the passband, but generally faster at- tenuation outside the passband. Chebyshev filters are spec- ified according to the amount of ripple (in dB) within the passband. 3) Determine the filter order necessary to meet the re- sponse requirements defined above. This may be done with the aid of the nomographs in Figures 8 and 9 for Butter- worth and Chebyshev filters. To use the nomographs, draw a line through the desired values on the A MAX/AMIN scales to the left side of the graph. Draw a horizontal line to the right of this point and mark its intersection with the vertical line corresponding to the required ratio SBW/BW. The re- quired filter order will be equal to the number of the curve falling on or just above the intersection of the two lines. This is illustrated in Figure 10 for a Chebyshev filter with 1 dB ripple, 30 dB minimum attenuation in the stopband, and SBW/BW e 3. From the Figure, the required filter order is 4) The design tables in section 2.0 can now be used to find the component values that will yield the desired response for filters of order 4 through 12. The ‘‘K n’’ give the ratios of resistors ‘‘R n’’ to R F, and K Q is Q divided by f 0/BW. As an example of the Tables’ use, consider a fourth-order Chebyshev filter with 0.5 dB ripple and f 0/BW e 6. Begin by choosing a convenient value for R F, such as 100 k X. From the ‘‘0.5 dB Chebyshev’’ filter table, K 0 e R0/RF e 1.3405. This gives R 0 e RF c 1.345 e 134.05k. In a similar man- ner, R 2 is found to equal 201.61k. Q is found using the column labeled K Q. This gives Q e KQ c f0/BW e 8.4174. Table I shows the available Q values; the nearest value is 8.5, which is programmed by tying pins 1, 2, 3, and 18 to V a and pin 17 to V b. Note that the resistor values obtained from the tables are normalized for center frequency gain H OBP e 1. For differ- ent gains, simply divide R 0 by the desired gain. 5) Choose the clock-to-center-frequency ratio. This will nominally be 100:1 when pin 10 is connected to pin 12(V a) and 50:1 when pin 10 is connected to pin 11(V b). 100:1 generally gives a response curve nearer the ideal and fewer (if any) problems with aliasing, while 50:1 allows operation over the highest octave of center frequencies (10 kHz to 20 kHz). Supply the MF8 with a clock signal of the appropriate frequency to either the TTL or CMOS input, depending on the available clock logic levels. TABLE I. Q and Clock-to-Center-Frequency Ratio Versus Logic Levels on ‘‘Q-set’’ Pins 50:1 mode 100:1 mode ABCDE F CLK/Fo QF CLK/Fo Q 10000 43.7 0.45 94.0 0.47 11000 45.8 0.71 95.8 0.73 01000 46.8 0.96 96.8 0.98 10100 48.4 2.0 98.4 2.0 00100 48.7 2.5 98.7 2.5 01100 48.9 3.0 98.9 3.0 11100 49.2 4.0 99.2 4.0 01010 49.3 5.0 99.3 5.0 10010 49.4 5.7 99.4 5.7 10110 49.4 6.4 99.4 6.4 00010 49.5 7.6 99.5 7.6 11110 49.6 8.5 99.6 8.5 00110 49.6 10.6 99.6 10.6 11001 49.6 11.7 99.6 11.7 11010 49.7 12.5 99.7 12.5 11101 49.7 13.6 99.7 13.6 01001 49.7 14.7 99.7 14.7 10011 49.7 15.8 99.7 15.8 10101 49.7 16.5 99.7 16.5 01110 49.7 17 99.7 17 10001 49.8 19 99.8 19 10111 49.8 22 99.8 22 11011 49.8 27 99.8 27 11111 49.8 30 99.8 30 00101 49.8 33 99.8 33 01011 49.8 40 99.8 40 00111 49.8 44 99.8 44 00001 49.9 57 99.9 57 01101 49.9 68 99.9 68 00011 49.9 79 99.9 79 01111 49.9 90 99.9 90
Higher-order filters are designed in a similar manner. An eighth-order Chebyshev with 0.1 dB ripple, center frequency equal to 1 kHz, and 100 Hz bandwidth, for example, could be built as in Figure 11 with the following component values: R0 e 79.86k RF e 100k R2 e 57.82k R3 e 188.08k R4 e 203.42k Pins 1, 3, 17 and 18 high, pin 2 low. For 100:1 clock-to-cen- ter-frequency ratio, pin 10 is tied to V a and the clock fre- quency is 100 kHz. For 50:1 clock-to-center-frequency ratio, pin 10 is tied to V b and the clock frequency is 50 kHz. When building filters of order 4 or higher, best performance will always be realized when the filter blocks are cascaded in numerical order: Filter 1 (pins 16 and 15) should always precede Filter 2 (pins 5 and 6). If a second MF8 is used, Filter 2 of the first MF8 should precede Filter 1 of the sec- ond MF8, and so on. Dynamic Considerations Some filter response characteristics will result in high gain at certain internal nodes, particularly at the op amp output. This can cause clipping in intermediate stages even when no clipping is evident at the filter output. The consequences are significant distortion and degradation of the overall transfer function. The likelihood of clipping at the op amp output becomes greater as R F/R0 increases. As the design tables show, R F/R0 increases with increasing filter order and increasing ripple. It is good practice to keep out-of-band input signal levels small enough that the first stage can’t overload.
FIGURE 8. Butterworth Bandpass Filter Design Nomograph
FIGURE 9. Chebyshev Bandpass Filter Design Nomograph
FIGURE 10. Example of Chebyshev Bandpass Nomograph Use.
FIGURE 11. Eighth-Order multiple-feedback bandpass filter using two MF8s. The circuit shown accepts a TTL-level clock signal and has a clock-to-center-frequency ratio of 100:1.
1.5 TRACKING AND CASCADED SECOND-ORDER
FIGURE 12. H(s) For second-order bandpass filters with various values of Q. H o normalized in each case to 0 dB. FIGURE 13. Design Nomograph for Cascaded
1.6 INPUT IMPEDANCE
FIGURE 14. Simplified MF8 Input Stage the input impedance should never be less than this number.
1.7 OUTPUT DRIVE
1.8 SAMPLED-DATA SYSTEM CONSIDERATIONS
a frequency less than one-half the sampling frequency. frequency, this will usually not be necessary. 100:1 than when the ratio is 50:1. stronger at elevated operating temperatures. FIGURE 15. Output Waveform of
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters
Order K 0 K2 K3 K4 K5 K6 KQ 4 2.0000 4.0000 1.4142 6 2.3704 2.6667 9.1429 1.5000 CHEBYSHEV RIPPLE 0.01 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.9041 3.6339 0.4489 6 1.8277 1.8450 6.6170 0.9438 CHEBYSHEV RIPPLE 0.02 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.8644 3.4922 0.5393 6 1.7024 1.6787 6.0772 1.0849 CHEBYSHEV RIPPLE 0.03 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.8341 3.3871 0.6016 6 1.6183 1.5713 5.7231 1.1808 CHEBYSHEV RIPPLE 0.04 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.8085 3.3009 0.6508 6 1.5535 1.4908 5.4548 1.2560 CHEBYSHEV RIPPLE 0.05 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.7860 3.2268 0.6923 6 1.5002 1.4260 5.2373 1.3191 CHEBYSHEV RIPPLE 0.06 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.7657 3.1612 0.7285 6 1.4548 1.3717 5.0536 1.3741
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV RIPPLE .07 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.7471 3.1020 0.7609 6 1.4150 1.3249 4.8943 1.4232 CHEBYSHEV RIPPLE .08 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.7298 3.0478 0.7905 6 1.3795 1.2837 4.7534 1.4679 CHEBYSHEV RIPPLE .09 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.7136 2.9978 0.8177 6 1.3475 1.2469 4.6271 1.5090 CHEBYSHEV RIPPLE 0.1 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.6983 2.9512 0.8430 6 1.3183 1.2137 4.5125 1.5473 CHEBYSHEV RIPPLE 0.2 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.5757 2.5998 1.0378 6 1.1128 0.9894 3.7271 1.8413 CHEBYSHEV RIPPLE 0.3 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.4833 2.3575 1.1804 6 0.9835 0.8560 3.2501 2.0568 CHEBYSHEV RIPPLE 0.4 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.4067 2.1698 1.2988 6 0.8888 0.7618 2.9088 2.2363 CHEBYSHEV RIPPLE 0.5 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.3405 2.0161 1.4029 6 0.8143 0.6897 2.6447 2.3944
CHEBYSHEV RIPPLE 0.6 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.2816 1.8857 1.4975 6 0.7530 0.6316 2.4305 2.5385 CHEBYSHEV RIPPLE 0.7 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.2283 1.7727 1.5852 6 0.7012 0.5834 2.2515 2.6724 CHEBYSHEV RIPPLE 0.8 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.1797 1.6731 1.6678 6 0.6564 0.5424 2.0983 2.7989 CHEBYSHEV RIPPLE 0.9 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.1347 1.5841 1.7464 6 0.6171 0.5068 1.9650 2.9194 CHEBYSHEV RIPPLE 1.0 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.0930 1.5039 1.8219 6 0.5822 0.4756 1.8475 3.0354 CHEBYSHEV RIPPLE 1.1 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.0539 1.4310 1.8949 6 0.5509 0.4479 1.7428 3.1476 CHEBYSHEV RIPPLE 1.2 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 1.0173 1.3643 1.9657 6 0.5226 0.4231 1.6487 3.2567 CHEBYSHEV RIPPLE 1.3 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.9828 1.3029 2.0348 6 0.4969 0.4006 1.5634 3.3633
CHEBYSHEV RIPPLE 1.4 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.9501 1.2461 2.1024 6 0.4733 0.3803 1.4857 3.4678 CHEBYSHEV RIPPLE 1.5 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.9192 1.1934 2.1688 6 0.4515 0.3616 1.4145 3.5705 CHEBYSHEV RIPPLE 1.6 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.8897 1.1443 2.2341 6 0.4315 0.3445 1.3490 3.6717 CHEBYSHEV RIPPLE 1.7 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.8617 1.0983 2.2986 6 0.4128 0.3287 1.2883 3.7717 CHEBYSHEV RIPPLE 1.8 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.8350 1.0553 2.3624 6 0.3955 0.3141 1.2321 3.8706 CHEBYSHEV RIPPLE 1.9 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.8095 1.0148 2.4255 6 0.3793 0.3005 1.1797 3.9687 CHEBYSHEV RIPPLE 2.0 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.7850 0.9767 2.4881 6 0.3641 0.2878 1.1308 4.0660 CHEBYSHEV RIPPLE 2.1 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.7616 0.9407 2.5503 6 0.3498 0.2759 1.0850 4.1628 CHEBYSHEV RIPPLE 2.2 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.7391 0.9067 2.6122 6 0.3364 0.2648 1.0420 4.2591
CHEBYSHEV RIPPLE 2.3 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.7176 0.8744 2.6737 6 0.3237 0.2544 1.0016 4.3550 CHEBYSHEV RIPPLE 2.4 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.6968 0.8438 2.7350 6 0.3118 0.2446 0.9635 4.4507 CHEBYSHEV RIPPLE 2.5 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.6769 0.8148 2.7962 6 0.3005 0.2353 0.9275 4.5462 CHEBYSHEV RIPPLE 2.6 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.6577 0.7871 2.8573 6 0.2897 0.2265 0.8935 4.6415 CHEBYSHEV RIPPLE 2.7 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.6392 0.7607 2.9183 6 0.2796 0.2182 0.8612 4.7368 CHEBYSHEV RIPPLE 2.8 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.6213 0.7356 2.9792 6 0.2699 0.2104 0.8306 4.8322 CHEBYSHEV RIPPLE 2.9 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.6041 0.7116 3.0402 6 0.2607 0.2029 0.8016 4.9276 CHEBYSHEV RIPPLE 3.0 dB Order K 0 K2 K3 K4 K5 K6 KQ 4 0.5875 0.6886 3.1013 6 0.2519 0.1959 0.7739 5.0231 Note: Multiple feedback loop filters of higher order than those specified in the tables will oscillate due to phase shift at the output of the summing amplifier. This phase shift is not the fault of the MF8; it is inherent in this type of multiple feedback loop topology. In addition, all filters marked with an asterisk ( *) will be unstable for Q s 1, due to phase shifts caused by the MF8’s switched-capacitor design approach.
Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MF8CCJ
MF8 4th-Order Switched Capacitor Bandpass Filter Physical Dimensions inches (millimeters) (Continued) Lit. Ý 108778 Molded Dual-In-Line Package (N) Order Number MF8CCN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
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