MF6C

MF6C NSC | Alldatasheet

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o wo = - A National MF6 6th Order Switched Capacitor Butterworth Lowpass Filter General Description Features The MF6 is a versatile easy to use, precision 6th order But- = No external components terworth lowpass active filter. Switched capacitor tech- m 14-pin DIP or 14-pin wide-body S.O. package niques eliminate external component requirements and al- wm Cutoff frequency accuracy of +0.3% typical low a clock tunable cutoff frequency. The ratio of the clock Cutoff frequency range of 0.1 Hz to 20 kHz frequency to the lowpass cutoff frequency is intemally set to - 50 to 1 (MF6-50) or 100 to 1 (MF6-100). A Schmitt trigger we — mited op amr avaiable clock input stage allows two clocking options, either self 5V to 14V total supply voltage clocking (via an external resistor and capacitor) for stand- ™ Cutoff frequency set by external or internal clock alone applications, or an external TTL or CMOS logic com- patible clock can be used for tighter cutoff frequency con- trol. The maximally flat passband frequency response to- gether with a DC gain of 1 V/V allows cascading MF6 sec- tions for higher order filtering. In addition to the filter, two independent CMOS op amps are included on the die and are useful for any general signal conditioning applications. Block and Connection Diagrams yd owt All Packages U] L] C) ) a 13 a 4. v2, wie [mm] | UL ns a wml | eee, E> 7m um ™ | LOWPASS FLTER ‘er axe =O ST nano La) v CLOCK GENERATOR ves fa TRISTATE? BUFFER LEVEL ‘SHIFT a Lave curs > 5 > <H : TL/H/5085-2 w et> Top View ] LJ nvere Order Number MF6CWM-50 or MF6CWM-100 W g YJ ie See NS Package Number M14B. (} ane Order Number MF6CN-50 on te vor or MF6CN-100 TU/H/5085-1 See NS Package Number N14A. Order Number MF6CJ-50 or MF6CJ-100 See NS Package Number J14A 1-134

. . n Absolute Maximum Ratings (note 11) o If Military/Aerospace specified devices are required, See AN-450 “Surface Mounting Methods and Their Effect Please contact the National Semiconductor Sales on Product Reliability” (Appendix D) for other methods of Office/Distributors for availability and specifications. soldering surface mount devices. Supply Voltage 14V Voltage at Any Pin V- ~ 0.2V,V+ + 0.2V Operating Ratings (ote 11) Input Current at Any Pin (Note 13) 5mA Temperature Range TmIn $ Ta S TMAX Power Dissipation (Note 14) 500 mW MF6CWM-50, MF6CWM-100 OC < Tas +70°C Storage Temperature 65°C to +150°C MF6CJ-50, MF6CJ-100 40°C < Ta < +85°C ESD Susceptibility (Note 12) 800Vv ‘Supply Voltage (Vs = V+—V—) SV to 14V Soldering Information N Package (10 sec.) 260°C J Package (10 sec.) 300°C Vapor Phase (60 sec.) 215°C Infrared (15 sec.) 220°C Filter Electrical Characteristics the following specifications apply for fox < 250 kHz (see Note 3) unless otherwise specified. Boldface limits apply for Tyin to Twax; all other limits Ta = Ty = 25°C. MF6CWM-50, MFECWM-100, MF6CN-50, MF6CN-100 MF6CI-50, MF6CJ-100 Parameter Conditions Tested Design Tested | Design | Units Typical Typical (Notes) | Limit Limit (note 8) Limit Limit (Note 9) | (Note 10) (Note 9) | (Note 10) V+ = +8V,V~ = -5V fo Cutoff MF6-50 Min] 0.4 O41 Frequency Max 20k 20k He Range MF6-100 Min 0.1 O41 (Note 1) Max| 10k 10k Total Supply Curent feax=25000e] 40 | oo | es | 40 | 5 | | m Maximum Clock Filter Output} mv Feedthrough Op Amp 1 Out (peak-to- Op Amp 2 Out} Peak) ter Peouce DC Gain s2kn oo | *00 #030 | oo | £0.80 | | ia Frequency Ratio oc MF6-50| —200 ~200 v Offset Voltage MF6-100| —400 = 400 m Minimum Output FL= 10k +4.0 +35 +35 +4.0 +35 V Voltage Swing -44 -38 -3.5 -44 -3.5 Maximum Output Short Circuit Sour) bee mA Current (Note 6) “ Dynamic Range MF6-50] 83 83 oe (Note 2) MF6-100) 81 81 Additional MF6-50] foi = 250 kHz| Points (Note 4) MF6-100| foi x= 250 kHz! 1-135

=| Filter Electrical Characteristics (continued) The following specifications apply for fox < 250 kHz (see Note 3) unless otherwise specified. Boldface limits apply for Twin to Tax; all other limits Ta = Ty = 25°C. MF8CWM-50, MF6CWM-100 MF6CN-50, MFECN-100 MFOCJ-£0, MF6CJ-100 Parameter Conditions Tested Design Tested | Design | Unite Typical Typical (votes) | unt Limit (nates) Umit Limit (Note 9) | (Note 10) (Note 9) _|(Note 10) vt = +5V,V- = —5¥ (Continued) Attenuation Rate = MF6-B0|fc1 x= 250 KH <B/ if; = 6000 Hz octave p= 8000 Hz MF6-100 lfc = 250 kHz| if, =3000 Hz ce lte= 4000 Hz fo Cutoff MF6-50 Min] O41 Frequency Ma 1% | Range = MF6-100 Mii O41 (Note 1) Maxq sk Total Supply Curent fux=280Kre] 25 | 40 | 40 [| 25 [40 || ma Maximum Clock Filter Output 20 mv Feedthrough Op Amp 1 Out! 18 (peak-to- Op Amp 2 Out 10 peak) Hp DO Gain [Frowces2ka] oo | s0a0 | s0a0 | oo | z0a0 | | as foux/te, Clock to oc MF6-50] 200 200 mv Offset Voltage MFE6-100 400 —400 Minimum Output RL=10k2 +15 +10 +1.0 +15 +1.0 Vv Voltage Swing -22 =17 -1.8 =22 -1.85 Maximum Output Short Circuit Sous mA Current (Note 6) DynamicRange ota) || Te Additional MF6-50tc1 x= 250 kHz] Magnitude lt=6000 Hz -954 |-964+05| -9.84:0.68| -954 | -9.s4+0.65 3B Points (Note 4) MF6-100lfo1 x= 250 kHz| Attenuation MF6-50fcx x= 250 kHz! 48/ Rato It; = 6000 Hz octave p= 8000 Hz MF6-100lfc «= 250 kHz If; = 9000 Hz cene itp= 4000 Hz 1-136

Op Amp Electrical Characteristics a Boldface limits apply for Twin to Tax; all other limits T, = Ty = 25°C. MF6CN-50, MF6CN-100, MF6CWM-50, MF6CWM-100 MF6CJ-60, MF6CJ-100 Parameter Tested Design Tested Design Units Typical Typical (Note 8) Limit Limit (Note 8) Limit Umit (Note 9) | (Note 10) (Note 9) | (Note 10) Vt = +5V,V- = —5V CMRR (Op Amp #2 Only) Vom1 = 1.8V, 3B Vome = —2.2V Output Voltage Swing AL=10 ka +40 +3.8 +3.6 +40 +3.6 Vv Maximum Output Short Source 65 mA Circuit Current (Note 6) Sink 4.0 input bias Gent [oo ft MRR (Op-Amp #2 Only) Vom1 = +0.5V, 4B Vome = —0.9V Output Voltage Swing RL = 10kn +15 +13 +41 +15 +44 v Maximum Output Short Source 24 24 mA Circuit Current (Note 6) Sink 1.0 1.0 1-137

=| Logic Input-Output Electrical Characteristics the foiowing specifications apply for V~ = OV (gee Note 5) unless otherwise specified, Boldface limits apply for Twin to Tmax; all other limits Ta = Ty = 25°C. MF6CN-50, MF6CN-100 MF6CWM-50, MFecwM-100 | _ MF8C¥-50, MFECJ-100 Parameter Typical Teoted Design Typical Tested Design Units (Note a) |, Limtt mit | (ote e) | Limit | | Limit (Note 9) | (Note 10) (Note 9) | (Note 10) TTL CLOCK INPUT, CLK R PIN (Note 7) Maximum Vi, Logical “0” Vv input Voltage Minimum Vj}, Logical 1" Vv Input Voltage Maximum Leakage Current LSh Pin at BA at CLK R Pin Mid- Supply SCHMITT TRIGGER Vr +, Positive Going V+ = 10V 7.0 64 6.1 7.0 v Threshold Voltage 8.9 8.9 + = were Papas tay dy Vr~, Negative Going V+ = 10V Vv Threshold Voltage v+ = 5V 15 06 wel Ls ist ly Hysteresis (Vt4 — Vr-) v+ = 10V 23 Vv 7.6 vt = 5V 12 Fa a OD Minimum Logical "1" Output |) _ _ soa | Vt = 10V 9.0 v Voltage (Pin 11) ° BAT vt = 8V 45 Maximum Logical "0" Output = V+ = 10V Voltage (Pin 11) lo=10HA ly = By v Minimum Output Source CLKRTied | V+ = 10V 3.0 mA Current (Pin 11) to Ground vt =5V 0.75 Maximum Output Sink CLKATied | V+ = 10V 2.5 2.8 5.0 mA Current (Pin 11) tov+ vt = 5V 065 | 0.68 1.3 Note 1: The cutott frequency of the filter is defined as the frequency where the magnitude response is 9.01 dB less than the OC gain of the filter. Note 2: For +5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 » Vrms for the MF6-50 and 250 Vrms for the MF6-100. For + 2.5V supplies the dynamic range is referenced to 1.06 Vrms (1.5V peak) where the wideband noise over a 20 kHz bandwidth is typically 140 4Vrms for both the MF6-50 and the MF6-100. Note 3: The specifications for the MF6 have been given for a clock frequency (fox) of 250 kHz and less. Above this clock frequency the | cutolt frequency begins to deviate from the specified error band of + 4.0% but the filter still maintains its magnitude characteristics. See Application Hints, Section 1.5. Note 4: Besides checking the cutoff frequency (1c) and the stopband attenuation at 2 fo, two additional frequencies are used to check the magnitude response of the filter, The magnitudes are referenced to a DC gain of 0.0 dB. Note &: For simplicity all the logic levels have been referenced to V- = OV and will scale ‘accordingly for +5V and +2.5V supplies (except for the TTL input logic levels). Note 8: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage ewing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst-case conditions. Note 7: The MF6 is operating with symmetrical split supplies and L.Sh is tied to ground. Note 8: Typicals are at 25°C and represent most likely parametric norm. Note 9: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level. Note 10: Design limits are guaranteed, but not 100% tested. These limits are not used to calculate ‘outgoing quality levels. Note 11: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when ‘operating the device beyond its specified conditions. Note 12: Human body model, 100 pF discharged through a 1.5k 11 resistor. Note 13: When the input voltage (Vin) at any pin exceeds the power supply rails (Vin < V~ of Vin > V+) the absolute value of current at that pin should be limited to 5 mA or leas. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. Note 14: The maximum power dissipation must be derated at elevated temperatures and is dictated by Tywax, @ja, and the ambient temperature, Ta. The maximum allowable power dissipation at any temperature is Pp = (Tymax ~ Ta)/@ya or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, Tyywax = 125°C, and the typical junction-to-ambient thermal resistance | of the MF6CN when boasd mounted is 67°C/W. For the MF6CJ this number decreases to 62°C/W. For MF6CWM, @jq = 78°C/W. 1-138

Typical Performance Characteristics o Schmitt Trigger Threshold Voltage Crosstalk from Filter Crosstalk from Elther Op-Amp = 1% Power Supply Voltage 82 OP-Amps (MFE-100) wg 0 Filter Output (MF6-50) y ike tttad if, Tos] ge SUT Tse atta fe “rr iteeries] BS eta Pps’ 2s5220 Sees | ee ne eee fee ; iro oe oe ll ee Wim ieee os Tet “Ta iNT ; oscommerce eT 5 7 9 10 1 12 14 0 0 ve oe sv “mec "mca . Crosstalk from Filter Crosstalk from Elther Op-Amp Equivalent Input Noise . Sn anne wg 6? Filter Output (MF6-100) @ enn Te) is Tez) § Bs HIM arse] 8S Ne ae NEL Sessa iy Lill i SCNT 3 eee a TTT og SCN ze “EIN 6s 7 ‘i = SCN STEN aa es nn St

2 Seer | EP UM 3 “oT

10 100 « 11K 10K 10 10 « 11 100K Hy J 100 a 10K wo FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) 1-139

o au =| Typical Performance Characteristics (continues) Positive Voltage Swing vs Positive Votage owing ve Tonneentore tes oat Power Supply Voltage Power Supply Voltage ‘emperature (Filter gq (OP Amp Output) 1s Fier Output) __ 1g OP Amp Outputs) - = at a oe a =tonn Tt a fesse | | eo Bott A “COT eg a a 7 | ee | LTT TAT EI g 8 5 a a | 5 a a | = 4 7 Feed 7 A es 7 2 FAT SrTtTATrr ey ee 2 | tPCT 26 tr ai JA st, abe S=aaae Hey er crrrry | i a wf LTT tity] $0 GD 7D 8D 90 100 110 120 130 SD 60 70 8 90 100 110 H-B-55 BS SG iGIS POWER SUPPLY VOLTAGE (V) POWER SUPPLY VOLTAGE (V) TEMPERATURE °C Negative Voltage Swing vs Negative Voltage Swing vs Power Supply Voltage Temperature (Filter and Power fant Current vs (Fliter and Op Amp Outputs) Op Amp Outputs) Clock Frequency SNCCL “ew TTTITILIA peed a s SEXO em Ss facto | eed = rf a wufroal TTP) Eerie BeceNtctth gO i eset H PSE Petco, BE oy NY 3 4 3 0 y CTT Pry rr ery ee-ttHHN pawl DA Sse CCoee a“-eeeee NO CRETE coor SCCCETCCTN LOOT TTT x Hess t+} 50 6D 70 80 90 100 110 120 130 B-SB-155 BSS SiGIS 0 100200 300 400 500 600 700 800 900 1000 POWER SUPPLY VOLTAGE (V) TEMPERATURE (°C) (CLOCK FREQUENCY (KHZ) Power Supply Current Power Supply Current vs Temperature vs Power Supply Voltage PROC es eee q 20S sg were e at tt Newt Te oe COoaee ECCS Sea i SLC OES i sR EAH = Sree > sire a ee | Bereoeooor]—§ ws ES a i > se ee ee a SNe TT oe E PT yy AAT TTT E Sy SCLLLT Seed SD a S-B-55 5S GHGS 5 6 7 8 8 1 1 12 13 ‘TEMPERATURE (°C) POWER SUPPLY VOLTAGE (V) TU/H/5005-95 1-140

Typical Performance Characteristics (continued) a Foun/te Deviation feik/te Deviation foLk/fe Deviation vs Cl ‘requency vs Temperature vs Power Supply Voltage » os 4D ee me-50 T TT 1714 ers er) a ee we Oe ffeux= 2500 4 we _ ftax= 250.02 H+ S CGI IAs tao Suet te 5! M44

3 SM OMANCT Tt 3 OLS ca 3 [|

s SLOT s wf LDR s wot ttt Prey j sof Pee j = FERRE EH | PPP rr rrr SEC Pe eeeee ee ee PS) PSESEEAGA oP PES od dS, A SCOOT SS A ao LETTE 100 200 300 400 S00 600 700 800 $00 1000 B-B-5 5 BH GH S 105125 5.6 7 8 8 0 mM 2 13 (CLOCK FREQUENCY (KHZ) ‘TEMPERATURE (°C) POWER SUPPLY VOLTAGE (V) - foik/fe Deviation foik/fe Deviation foLK/fe Deviation vs Clock Frequency vs Temperature vs Power Supply Voltage 10 7 1» 0 + ob hen os [iegetowe || TT TY wee ae Sd 2 a Rd ane Ly faeces TT

3 Efe pepe 3 Pee

pt) a er ee ee s ttt Tey ima s of LTA TT Sw ee ir wry se od oo oo oL 7 NA TA ee a | LT 10 eee ad ae 02 La | Seen SN | | Arse | | a ee uty oes Ty oe cast] TPT TTT Pt Terr oo HEE EEN vat LETT TT TT ao - LL TT Tr 100 200 300 400 500 600 700 800 900 1000 BH-B-15 5 4S SG 10515 5 6 7 8 $ W 1 12 13 CLOCK FREQUENCY (kHZ) ‘TEMPERATURE (°C) POWER SUPPLY VOLTAGE (¥) TUH/5088-36 DC Gain Deviation DC Gain Deviation DC Gain Deviation an vs Temperature om vs Power Supply Voltage 2 vs Clock Frequency ow fea sowd || TTA oo (Gono of Pe eee g om [Mss 4g e SCAR & os! ON yaa & oma |R=10K0 A = err anne COONS Lt te | m ys 4 (oe a et AHH 00s | tee LYIATTT ee any An Cee eZ 0m SH | 3 nf | No) atime we cond ane on | A] COCA 8 0 ccs FA a SCC can} LTT TTT TT I ree a a da asLLLT TTT anL LTT ETT) So LETT Tre B-S-155 5 HS SiGiS 5.6 7 8 9 0 1 12 13 © 100.200 300 400 500 600 700 800 900 1000 TEMPERATURE (°C) POWER SUPPLY VOLTAGE (V) CLOCK FREQUENCY (KHZ) DC Gain Deviation DC Gain Deviation DC Gain Deviation vs Temperature vs Power Supply Voltage vs Clock Frequency 002 2 of ASST | aa of oT ete gg eee Som s = 1040 vd Cry yon oe = EEE ab oe BB oper see NA 3 aol HT eesoeol | TTY 2 os POLE EEE gaff fr Tf ean) oe eee se ou do a CCC CCeeeee cw LEE TT TT aan COCO} 2 COCCCCCEY 55-BHW15 5 25 45 65 85 105125 5.6 7 8 8 10 12:15 © 100 200.300 400 S00 800 700 600 900 1000 TEMPERATURE (°C) POWER SUPPLY VOLTAGE (V) (CLOCK FREQUENCY (it1Z) TUH/8086~30 1-141

=| Crosstalk Test Circuits From Filter to Opamps ann Wels 250. Yee Cp-ae 72 = TL/H/5085-10 From Either Opamp to Filter Output R 7! Sr 1 ee a 20Hr~ 20% ‘ = ans was” to = psowie ee ‘OPAMP #2 = = TU 5065—11 Pin Descriptions (in numbers) Pin Description Pin Description FILTER OUT (3) —_—_The output of the lowpass filter. Voe (2), Voz is the output, INV2 is the It will typically sink 0.9 mA and INV2 (14), inverting input, and NINV2 is the source 3 mA and swing to within NINV2 (1) non-inverting input of Op-Amp 1V of each supply rail. #2. FILTER IN (8) The input to the lowpass filter. V+(6), V~(10) The positive and negative To minimize gain errors the ‘supply pins. The total power ‘source impedance that drives supply range is 5V to 14V. this input should be less than 2k Decoupling these pins with (see section 1.4). For single 0.1. pF capacitors is highly supply operation the input signal recommended. must be biased to mid-supply or CLK IN (9) ACMOS Schmitt-trigger input to AC coupled. be used with an external CMOS VogADu (7) This pin is used to adjust the DC logic level clock. Also used for offset of the filter output; if not self-clocking Schmitt-trigger used it must be tied to the oscillator (see section 1.1). AGND potential. (See section CLK R (11) ATTL logic level clock input 1.3) when in split supply operation AGND (5) The analog ground pin. This pin (+2.5V to £7V) and L. Sh tied sets the DC bias level for the to system ground. This pin filter section and the non- becomes a low impedance inverting input of Op-Amp #1 output when L. Sh is tied to V~. and must be tied to the system Also used in conjunction with ground for split supply operation the CLK IN pin for a self or to mid-supply for single clocking Schmitt-trigger supply operation (see section oscillator (see section 1.1). 1.2). When tied to mid-supply L. Sh (12) Level shift pin, selects the logic this pin should be well threshold levels for the desired bypassed. clock. When tied to V- it Vos (4), Vo is the output and INV1 is enables an internal tri-state INV4 (13) the inverting input of Op-Amp buffer stage between the #1. The non-inverting input of ‘Schmitt trigger and the internal this Op-Amp is internally clock level shift stage thus connected to the AGND pin. enabling the CLK IN Schmitt- trigger input and making the CLK R pin a low impedance output. 1-142

7 CLKR

FIGURE 4. Single Supply Operation

FIGURE 5. Vos Adjust Schemes

1.2 POWER SUPPLY BIASING

1.3 OFFSET ADJUST Reel

This pin sets the zero reference for the output of the filter.

1.4 INPUT IMPEDANCE lia = Q/T

the input to the filter can be seen in Figure 6. The input - | .

=) Application Hints (continued MF6-100, so for the MF6-100 Since the maximum overall gain error for the MF6 is +£0.3 dB with a Rs < 2 k® the actual gain error for this case Rin = L107 _ 1x 1082 _ 1 x 1010 would be +0.21 dB to —0.39 dB. 4 fax fex100 te 4.5 CUTOFF FREQUENCY RANGE an The filter’s cutoff fraquency (f,) has a lower limit caused by 6§x1011 §x 1011 1 1010 leakage currents through the internal switches discharging Bin = Tax x80 the stored charge on the capacitors. At lower clock frequen- for the MF6-50. As shown in the above equations for a given bnmiined leakage currents can cause millvolts of error, for cutoff frequency (f.) the input impedance remains the same a for the MF6-50 and the MF6-100. The higher the clock to fouk = 100 Hz, lieakage = 1pA,C = 1 pF center frequency ratio, the greater equivalent input resist- ance for a given clock frequency. As the cutoff frequency ve 1paA = 10mv increases the equivalent input impedance decreases. This 1 pF (100 Hz) input resistance will form a voltage divider with the source The propagation delay in the logic and the settling time re- impedance (Reource). Since Rin is inversely proportional to quired to acquire a new voltage level on the capacitors in- the cutoff frequency, operation at higher cutoff frequencies creases as the MF6 power supply voltage decreases. This will be more likely to load the input signal which would ap- causes a shift in the foLk/fe ratio which will become notice- Pear as an overall decrease in gain to the output of the filter. able when the clock frequency exceeds 250 kHz. The ampli- Since the filter's ideal gain is unity its overall gain is given tude characteristic will stay within tolerance until fo.x ex- by: ceeds 500 kHz and will peak at about 0.5 dB at the corner Ri frequency with a 1 MHz clock. The response of the MF6 is A= —o still a reasonable approximation of the ideal Butterworth Fin + Reource lowpass characteristic as can be seen in Figure 7. If the MF6-50 or the MF6-100 were set up for a cutoff fre- quency of 10 kHz the input impedance would be: 2.0 Designing with the MF6 1X 1010 Given any lowpass filter specification two equations will Rin = loKHe = 1Ma come in handy in trying to determine whether the MF6 will . do the job. The first equation determines the order of the In this example with a source impedance of 10k the overall lowpass filter required: gain, if the MF6 had an ideal gain of 1 or 0 dB, would be: +Ma py = 09,(10% Amin— 1) — tog (10% Amex—1) w Av ToRae Twn 7 9.98009 oF —88.4 maB 2 log (fe/fp) oo js ee | os wo LL A =e oleh Vleet a wleu AM ell = wheels Vel: 5 wo lel ele wo ELLE LT wo LTT et ey aw ATTA a _-U TT aw AUT A eg a WY at AAT VY ot MT TI aw WT TY ot WT WT a a a? a a a oo he x 0 KM ox FREQUENCY (Va) FREQUENCY (He) TL/H/5085-20 TUH/5065-21 FIGURE 7a. MF6-100 + 5V Supplies FIGURE 7b. MF6-50 + 5V Supplies Ampiltude Response Amplitude Response oe a

2 Wo 1 DWAA WED UE pael

a= lll 37 LALLA NS 5 a» HHI 5 wo LIA ~«t \\ oy a ao LOT ae i a wo LTT AAT oe SW ” LAAT aM AT i « ~o MW WT a a a ag 10 0 Kx yx ox 0 0 eax “ox FREQUENCY (Hz) FREQUENCY (ie) ‘TL/H/S085~22 TLH/5085-23 Amplitude Response Amplitude Response 1-146

be] Designing with the MF6 (continued) o where nis the order of the filter, Amin is the minimum stop- To implement this example for the MF6-50 the clock fre- band attenuation (in dB) desired at frequency f,, and Amax is quency will have to be set to fo. = 50(1.116 kHz) = 55.8 the passband ripple or attenuation (in dB) at frequency fp. If kHz or for the MF6-100 fc_k = 100(1.116 kHz) = 111.6 the result of this equation is greater than 6, then more than kHz. & single MF i roared we found by the fo 2.2 CASCADING MF6s lowi Aepalsel at any frequency can be found by the fol- In the case where a steeper stopband attenuation rate is 1g equation: required two MF6’s can be cascaded (Figure 9) yielding a Attn(f) = 10 log [1 + (100-TAmax—4) (f/f,)2"1 dB (2) 12th order slope of 72 dB per octave. Because the MF6 is a = i Butterworth filter and therefore has no ripple in its pass- where n = 6 (the order of the filter. band, when MF6s are cascaded the resulting filter also has 2.1 ALOWPASS DESIGN EXAMPLE no ripple in its passband. Likewise the DC and passband ‘Suppose the amplitude response specification in Figure 8 is gains will remain at 1V/V. The resulting response is shown given. Can the MF6 be used? The order of the Butterworth in Figure 10. approximation will have to be determined using eq. 1: In determining whether the cascaded MF6s will yield a filter Amin = 30 dB, Amax = 1.0 0B, fg = 2 kHz, and fy = 1 kHz that will meet a particular amplitude response specification, 03 oo. as above, equations 3 and 4 can be used, shown below. n= oe) 8B n= 199 (102-08 Amin — 1) — log (10°08 Amax— 1) @) Since n can only take on integer values, n = 6. Therefore 2 log (fe/fo) the MF6 can be used. In general, if n is 6 or less a single Attn(f) = 10 log [1 + (100-05 Amax—1) (f/f,)20] dB (4) MF6 stage can be uti ized. t t . where n = 6 (the order of each filter). pikewise, the artonuation 3 s;can be found using equation Equation 3 will determine whether the order of the fitter is b ng: - adequate (n < 6) while equation 4 can determine if the Atten (2 kHz) = 10 log [1 + (100-1 — 1) (2 kHz/1 kHz)12] required stopband attenuation is met and what actual cutoff = 30.26 dB frequency (fc) is required to obtain the particular frequency This result also meets the design specification given in Fig- response desired. The design procedure would be identical ure 8 again verifying that a single MF6 section will be ade- to the one shown in section 2.1. quate. 2.3 IMPLEMENTING A “NOTCH” FILTER WITH THE MF6. A “notch” filter with 60 dB of attenuation can be obtained by using one of the Op-Amps, available in the MF6, and three -9 oC TT J external resistors. The circuit and amplitude response are Auax= \\) shown in Figure 11. Ss The frequency where the “notch” will occur is equal to the e frequency at which the output signal of the MF6 will have e the same magnitude but be 180 degrees out of phase with a its input signal. For a sixth order Butterworth filter 180° z phase shift occurs where f = fy, = 0.742 fo. The attenuation Aym= 750 at this frequency is 0.12 dB which must be compensated for IC XX, by making Ry = 1.014 x Ro.

0 Since R; does not equal R2 there will be a gain inequality

fyetk f= 2k above and below the notch frequency. At frequencies below FREQUENCY (Hz) the notch frequency (f << fy), the signal through the filter UW/s08s-24 has a gain of one and is non-inverting. Summing this with the input signal through the Op-Amp yields an overail gain specifietion vasion the Reopens of the Piter Design of two or +6 dB. For f >> fp, the signal at the output of the Must Fail Within the Shaded Area of the Specification filter is greatly attenuated thus only the input signal will ap- . pear at the output of the Op-Amp. With Rg = Ry = 1.014 Since the MF6's cutoff frequency f,, which corresponds to a Rp the overall gain is 0.986 or —0.12 dB at frequencies gain attenuation of —3.01 dB, was not specified in this ex- above the notch, ample it needs to be calculated. Solving equation 2 where f = fe as follows: tat [coonee dB) — aver oT L101 Amax — 4) 100.301 — ay = 1H [ rr] = 1.119 kHz where fe = foLk/50 or foLK/100. 1-147

Designing with the MF6 (continued a [1] Vos AD a BUTTERWORTH 5 a FILTER FILTER our a AGND 5 = Oh wasn ell Yor E Lsh Oy =X mae iNv2. > /N TL ov lak

0 Ss CLAR

nme! Kus /\\ PND O

13 CLK IN

[J L jw Cj (C)vy . ‘SIGNAL ‘NPUT “NOTCH™ FILTER OUTPUT FIGURE 11a. “Notch” Filter +10 ee a ow on € ot * SE ECT Til oo) 10 50 «100 500 1K FREQUENCY (Hz) runeaes-20 FIGURE 11b. MF6-50 “Notch” Filter Amplitude Response 1-149

2.4 CHANGING CLOCK FREQUENCY

quency changes to 50 kHz yielding 1 kHz fo. dependent on the f, and thus the fo. applied to the filter. FIGURE 12. MF6-50 Abrupt Clock Frequency Change Figure 15 using one of the uncommitted Op-Amps available 2.5 ALIASING CONSIDERATIONS in the MF6. f,/2 + { causes an output signal to appear at f/2 — f. half the sampling frequency will cause an output to appear at a frequency lower than one-half the sampling frequency.

Ho = R4/R3 (Ho = 1 when Rg and Ry are omitted and V2 is directly tied to INV2).

2 Barta GCy

Note: The parallel combination of Fi, (i used), Ry and Re should be > 10 kN in order not to load Op-Amp #2. FIGURE 15. Second Order Butterworth AntiAliasing Fitter Using Uncommitted Op-Amp #2