MF6

MF6 NSC | Alldatasheet

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n Cutoff frequency accuracy of±0.3% typical n Cutoff frequency range of 0.1 Hz to 20 kHz n Two uncommitted op amps available n 5V to 14V total supply voltage n Cutoff frequency set by external or internal clock Block and Connection Diagrams TRI-STATE® is a registered trademark of National Semiconductor Corporation. All Packages DS005065-2 Top View Order Number MF6CWM-50 or MF6CWM-100 See NS Package Number M14B DS005065-1 June 1999 MF6 6th Order Switched Capacitor Butterworth Lowpass Filter © 1999 National Semiconductor Corporation DS005065 www.national.com

Absolute Maximum Ratings(Note 11) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 14V Voltage at Any Pin V Input Current at Any Pin (Note 13) 5 mA Package Input Current (Note 13) 20 mA Power Dissipation (Note 14) 500 mW Storage Temperature −65˚C to +150˚C ESD Susceptibility (Note 12) 800V Soldering Information Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” (Appendix D) for other methods of soldering surface mount devices. Operating Ratings(Note 11) Temperature Range T MIN ≤ TA ≤ TMAX MF6CWM-50, MF6CWM-100 0˚C ≤ TA ≤ +70˚C Supply Voltage (VS = V+−V −) 5 Vt o1 4 V Filter Electrical Characteristics The following specifications apply for fCLK ≤ 250 kHz (Note 3) unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Parameter Conditions Typical Tested Design Units (Note 8) Limit Limit (Note 9) (Note 10) V+ = +5V, V− = −5V fc, Cutoff MF6-50 Min 0.1 Frequency Max 20k Hz Range MF6-100 Min 0.1 (Note 1) Max 10k Total Supply Current f CLK =250 kHz 4.0 6.0 8.5 mA Maximum Clock Filter Output 30 mV Feedthrough Op Amp 1 Out 25 (peak-to- Op Amp 2 Out 20 peak) H o,R source 0.0 ±0.30 ±0.30 dB DC Gain ≤ 2k Ω Clock to Cutoff MF6-100 98.97 ±0.3% 98.97±1% 98.97±1% Frequency Ratio DC MF6-50 −200 mV Offset Voltage MF6-100 −400 Minimum Output R Voltage Swing −4.1 −3.8 −3.5 Maximum Output Source 50 Short Circuit Sink 1.5 mA Current (Note 6) Dynamic Range MF6-50 83 dB (Note 2) MF6-100 81 Additional MF6-50 f CLK =250 kHz Points (Note MF6-100 f CLK =250 kHz Attenuation Rate MF6-50 f CLK =250 kHz dB/ f1=6000 Hz −36 −36 octave f2=8000 Hz MF6-100 f CLK =250 kHz dB/ f1=3000 Hz −36 −36 octave f2=4000 Hz fc, Cutoff MF6-50 Min 0.1 Frequency Max 10k Hz Range MF6-100 Min 0.1 (Note 1) Max 5k www.national.com 2

Filter Electrical Characteristics(Continued) The following specifications apply for fCLK ≤ 250 kHz (Note 3) unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Parameter Conditions Typical Tested Design Units (Note 8) Limit Limit (Note 9) (Note 10) Total Supply Current f CLK =250 kHz 2.5 4.0 4.0 mA Maximum Clock Filter Output 20 mV Feedthrough Op Amp 1 Out 15 (peak-to- Op Amp 2 Out 10 peak) H o, DC Gain R source≤2k Ω 0.0 ±0.30 ±0.30 dB fCLK /fc, Clock to Cutoff Frequency DC MF6-50 −200 mV Offset Voltage MF6-100 −400 Minimum Output R Voltage Swing −2.2 −1.7 −1.5 Maximum Output Source 28 Short Circuit Sink 0.5 mA Current (Note 6) Dynamic Range (Note 2) 77 dB Additional MF6-50 f CLK =250 kHz Points (Note MF6-100 f CLK =250 kHz Attenuation MF6-50 f CLK =250 kHz dB/ Rate f 1=6000 Hz −36 −36 octave f2=8000 Hz MF6-100 f CLK =250 kHz dB/ f1=3000 Hz −36 −36 octave f2=4000 Hz Op Amp Electrical Characteristics Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Parameter Conditions Typical Tested Design Units (Note 8) Limit Limit (Note 9) (Note 10) V+ = +5V, V− = −5V Input Offset Voltage ±8.0 ±20 ±20 mV Input Bias Current 10 pA CMRR (Op Amp #2 Only) V CM1 = 1.8V, 60 55 dB VCM2 = −2.2V Output Voltage Swing R L=10 kΩ +4.0 +3.8 +3.6 V −4.5 −4.0 −4.0 Maximum Output Short Source 54 65 80 mA Circuit Current (Note 6) Sink 2.0 4.0 6.0 Slew Rate 7.0 V/µs DC Open Loop Gain 72 dB Gain Bandwidth Product 1.2 MHz V Input Offset Voltage ±8.0 ±20 ±20 mV www.national.com3

Op Amp Electrical Characteristics(Continued) Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Parameter Conditions Typical Tested Design Units (Note 8) Limit Limit (Note 9) (Note 10) Input Bias Current 10 pA CMRR (Op-Amp #2 Only) V CM1 = +0.5V, 60 55 dB VCM2 = −0.9V Output Voltage Swing R L = 10 kΩ +1.5 +1.3 +1.1 V −2.2 −1.7 −1.7 Maximum Output Short Source 24 mA Circuit Current (Note 6) Sink 1.0 Slew Rate 6.0 V/µs DC Open Loop Gain 67 dB Gain Bandwidth Product 1.2 MHz Logic Input-Output Electrical Characteristics (Note 5) The following specifications apply for V− = 0V unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Parameter Conditions Typical Tested Design Units (Note 8) Limit Limit (Note 9) (Note 10) TTL CLOCK INPUT, CLK R PIN (Note 7) Maximum V IL, Logical “0” 0.8 0.8 V Input Voltage Minimum V IH, Logical “1” 2.0 2.0 V Input Voltage Maximum Leakage Current L Sh Pin at 2.0 2.0 µA at CLK R Pin Mid- Supply SCHMITT TRIGGER V T+, Positive Going Min V + = 10V 7.0 6.1 6.1 V Threshold Voltage Max 8.9 8.9 Min V + = 5V 3.5 3.1 3.1 V Max 4.4 4.4 VT−, Negative Going Min V + = 10V 3.0 1.3 1.3 V Threshold Voltage Max 3.8 3.8 Min V + = 5V 1.5 0.6 0.6 V Max 1.9 1.9 Hysteresis (VT+ −V T−) Min V + = 10V 4.0 2.3 2.3 V Max 7.6 7.6 Min V + = 5V 2.0 1.2 1.2 V Max 3.8 3.8 Minimum Logical “1” Output Io = −10µA V+ = 10V 9.0 9.0 V Voltage (Pin 11) V + = 5V 4.5 4.5 Maximum Logical “0” Output Io = 10µA V+ = 10V 1.0 1.0 V Voltage (Pin 11) V + = 5V 0.5 0.5 Minimum Output Source CLK R Tied V + = 10V 6.0 3.0 3.0 mA Current (Pin 11) to Ground V + = 5V 1.5 0.75 0.75 Maximum Output Sink CLK R Tied V + = 10V 5.0 2.5 2.5 mA Current (Pin 11) to V + V+ = 5V 1.3 0.65 0.65 Note 1:The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter. Note 2:For ±5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 µVrms for the MF6-50 and 250 µVrms for the MF6-100. For±2.5V supplies the dynamic range is referenced to 1.06 Vrms (1.5V peak) where the wideband noise over a 20 kHz bandwidth is typically 140 µVrms for both the MF6-50 and the MF6-100. Note 3:The specifications for the MF6 have been given for a clock frequency (fCLK ) of 250 kHz and less. Above this clock frequency the cutoff frequency begins to deviate from the specified error band of±1.0% but the filter still maintains its magnitude characteristics. See Application Hints, Section 1.5. www.national.com 4

Logic Input-Output Electrical Characteristics(Continued) Note 4:Besides checking the cutoff frequency (fc) and the stopband attenuation at 2 fc, two additional frequencies are used to check the magnitude response of the filter. The magnitudes are referenced to a DC gain of 0.0 dB. Note 5:For simplicity all the logic levels have been referenced to V− = 0V and will scale accordingly for±5V and ±2.5V supplies (except for the TTL input logic lev- els). Note 6:The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst-case conditions. Note 7:The MF6 is operating with symmetrical split supplies and L.Sh is tied to ground. Note 8:Typicals are at 25˚C and represent most likely parametric norm. Note 9:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10:Design limits are guaranteed, but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 11:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified conditions. Note 12:Human body model, 100 pF discharged through a 1.5kΩ resistor. Note 13:When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5m A current limit to four. Note 14:The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX −T A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125˚C, and the typical junction-to-ambient thermal resistance is 78˚C/W. For the MF6CJ this number decreases to 62˚C/W. For MF6CWM,θJA = 78˚C/W. Typical Performance Characteristics Schmitt Trigger Threshold Voltage vs Power Supply Voltage DS005065-40 Crosstalk from Filter to Op-Amps (MF6-100) DS005065-41 Crosstalk from Either Op-Amp to Filter Output (MF6-50) DS005065-42 Crosstalk from Filter to Op-Amps (MF6-50) DS005065-43 Crosstalk from Either Op-Amp to Filter Output (MF6-100) DS005065-44 Equivalent Input Noise Voltage of Op-Amps DS005065-45 www.national.com5

Typical Performance Characteristics(Continued) Positive Voltage Swing vs Power Supply Voltage (Op Amp Output) DS005065-46 Positive Voltage Swing vs Power Supply Voltage (Filter Output) DS005065-47 Positive Voltage Swing vs Temperature (Filter and Op Amp Outputs) DS005065-48 Negative Voltage Swing vs Power Supply Voltage (Filter and Op Amp Outputs) DS005065-49 Negative Voltage Swing vs Temperature (Filter and Op Amp Outputs) DS005065-50 Power Supply Current vs Clock Frequency DS005065-51 Power Supply Current vs Temperature DS005065-52 Power Supply Current vs Power Supply Voltage DS005065-53 fCLK /fc Deviation vs Clock Frequency DS005065-54 www.national.com 6

Typical Performance Characteristics(Continued) fCLK /fc Deviation vs Temperature DS005065-55 fCLK /fc Deviation vs Power Supply Voltage DS005065-56 fCLK /fc Deviation vs Clock Frequency DS005065-57 fCLK /fc Deviation vs Temperature DS005065-58 fCLK /fc Deviation vs Power Supply Voltage DS005065-59 DC Gain Deviation vs Temperature DS005065-60 DC Gain Deviation vs Power Supply Voltage DS005065-61 DC Gain Deviation vs Clock Frequency DS005065-62 DC Gain Deviation vs Temperature DS005065-63 www.national.com7

Typical Performance Characteristics(Continued) Crosstalk Test Circuits Pin Descriptions(Pin Numbers) Pin Description FILTER OUT (3) The output of the lowpass filter. It will typically sink 0.9 mA and source 3 mA and swing to within 1V of each supply rail. FILTER IN (8) The input to the lowpass filter. To minimize gain errors the source impedance that drives this input should be less than 2k (see section 1.4). For single supply operation the input signal must be biased to mid-supply or AC coupled. Pin Description V OS ADJ (7) This pin is used to adjust the DC offset of the filter output; if not used it must be tied to the AGND potential. (See section 1.3) DC Gain Deviation vs Power Supply Voltage DS005065-64 DC Gain Deviation vs Clock Frequency DS005065-65 From Filter to Op Amps DS005065-10 From Either Op Amp to Filter Output DS005065-11 www.national.com 8

Pin Descriptions(Pin Numbers) (Continued) Pin Description AGND (5) The analog ground pin. This pin sets the DC bias level for the filter section and the non-inverting input of Op-Amp #1 and must be tied to the system ground for split supply operation or to mid-supply for single supply operation (see section 1.2). When tied to mid-supply this pin should be well bypassed. V O1 (4), INV1 (13) VO1 is the output and INV1 is the inverting input of Op-Amp#1. The non-inverting input of this Op-Amp is internally connected to the AGND pin. V O2 (2), INV2 (14), NINV2 (1) V O2 is the output, INV2 is the inverting input, and NINV2 is the non-inverting input of Op-Amp #2. V+(6), V−(10) The positive and negative supply pins. The total power supply range is 5V to 14V. Decoupling these pins with 0.1 µF capacitors is highly recommended. CLK IN (9) A CMOS Schmitt-trigger input to be used with an external CMOS logic level clock. Also used for self-clocking Schmitt-trigger oscillator (see section 1.1). CLK R (11) A TTL logic level clock input when in split supply operation ( ±2.5V to ±7V) and L. Sh tied to system ground. This pin becomes a low impedance output when L. Sh is tied to V −. Also used in conjunction with the CLK IN pin for a self clocking Schmitt-trigger oscillator (see section 1.1). L. Sh (12) Level shift pin, selects the logic threshold levels for the desired clock. When tied to V − it enables an internal tri-state® buffer stage between the Schmitt trigger and the internal clock level shift stage thus enabling the CLK IN Schmitt-trigger input and making the CLK R pin a low impedance output. When the voltage level at this input exceeds [25% (V + −V −)+V −] the internal tri-state buffer is disabled allowing the CLK R pin to become the clock input for the internal clock level shift stage. The CLK R threshold level is now 2V above the voltage applied to the L. Sh pin. Driving the CLK R pin with TTL logic levels can be accomplished through the use of split supplies and by tying the L. Sh pin to system ground. www.national.com9

1.0 MF6 Application Hints

approximation is to the theoretical Butterworth response.

1.1 CLOCK INPUTS

FIGURE 1. Schmitt Trigger R/C Oscillator

1.0 MF6 Application Hints(Continued)

FIGURE 2. Dual Supply Operation FIGURE 3. Dual Supply Operation

FIGURE 4. Single Supply Operation

1.2 POWER SUPPLY BIASING

clock logic levels can be used.

1.3 OFFSET ADJUST

ended supply operation or ground for split supply operation. This pin sets the zero reference for the output of the filter.

1.4 INPUT IMPEDANCE

Figure 6. The input ca- FIGURE 5. VOS Adjust Schemes FIGURE 6. MF6 Filter Input

pear as an overall decrease in gain to the output of the filter.

1.5 CUTOFF FREQUENCY RANGE

FIGURE 7. MF6-100 ±5V Supplies FIGURE 8. MF6-50 ±5V Supplies FIGURE 9. MF6-100 ±2.5V Supplies

2.0 Designing with the MF6

where n= 6 (the order of the filter).

2.1 A LOWPASS DESIGN EXAMPLE

2.2 CASCADING MF6s

as above, equations 3 and 4 can be used, shown below. where n= 6 (the order of each filter). FIGURE 10. MF6-50 ±2.5V Supplies FIGURE 11. Design Example Magnitude Response

2.0 Designing with the MF6(Continued)

2.3 IMPLEMENTING A “NOTCH” FILTER WITH THE MF6

all gain is 0.986 or −0.12 dB at frequencies above the notch. FIGURE 12. Cascading Two MF6s FIGURE 13. One MF6-50 vs. Two MF6-50s Cascaded FIGURE 14. Phase Response of

2.4 CHANGING CLOCK FREQUENCY

changes to 50 kHz yielding 1 kHz fc. dependent on the fc and thus the fCLK applied to the filter. FIGURE 15. “Notch” Filter FIGURE 16. MF6-50 “Notch” Filter Amplitude Response

2.5 ALIASING CONSIDERATIONS

the uncommitted Op-Amps available in the MF6. FIGURE 17. MF6-50 Abrupt Clock Frequency Change FIGURE 18. MF6-50 Step Input Response, Vertical= at fs/2 + f causes an output signal to appear at fs/ 2−f . FIGURE 19. The phenomenon of aliasing in sampled-data systems. An input signal whose frequecy is greater than frequency. In the MF6, fsfCLK .

Note:The parallel combination of R4 (if used), R1 and R2 should be≥ 10 kΩ in order not to load Op-Amp#2. FIGURE 20. Second Order Butterworth Anti-Aliasing Filter Using Uncommitted Op-Amp#2

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Small Outline Wide Body (M) Order Number MF6CWM-50 or MF6CWM-100 MF6 6th Order Switched Capacitor Butterworth Lowpass Filter National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.