MF5CN

MF5CN NSC | Alldatasheet

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Features

Y 14-pin DIP or 14-pin Surface Mount (SO) wide-body package Y Easy to use Y Clock to center frequency ratio accuracy g0.6% Y Filter cutoff frequency stability directly dependent on external clock quality Y Low sensitivity to external component variations Y Separate highpass (or notch or allpass), bandpass, low- pass outputs Y focQ range up to 200 kHz Y Operation up to 30 kHz (typical) Y Additional uncommitted op-amp Block and Connection Diagrams TL/H/5066–1 All Packages TL/H/5066–2 Top View Order Number MF5CN See NS Package Number N14A Order Number MF5CWM See NS Package Number M14B C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V a b Vb) 14V Power Dissipation T A e 25§C (note 1) 500 mW Storage Temp. 150 §C Soldering Information: N Package: 10 sec. 260 §C Infrared (15 sec.) 220 §C See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering sur- face mount devices. Input Voltage (any pin) V b s Vin s Va Operating Temp. Range T MIN s TA s TMAX MF5CN, MF5CWM 0 §C s TA s 70§C Electrical Characteristics Va e 5V g 0.5%, V b eb 5V g 0.5% unless otherwise noted. Boldface limits apply over temperature, T MIN s TA s TMAX. For all other limits T A e 25§C. Typical Tested Design Parameter Conditions (Note 6) Limit Limit Units (Note 7) (Note 8) Supply Voltage Min 8 V (Va b Vb) Max 14 V Maximum Supply Current Clock applied to Pin 8 4.5 6.0 mA No Input Signal Clock Filter Output 10 mV Feedthrough Op-amp Output 10 mV Filter Electrical Characteristics Va e 5Vg 0.5%, V b eb 5Vg 0.5% unless otherwise noted. Boldface limits apply over temperature, T MIN s TA s TMAX. For all other limits T A e 25§C. Typical Tested Design Parameter Conditions (Note 6) Limit Limit Units (Note 7) (Note 8) Center Frequency Max 30 20 kHz Range (f o) Min 0.1 0.2 Hz Clock Frequency Max 1.5 1.0 MHz Range (f CLK) Min 5.0 10 Hz Clock to Center Ideal Vpin9 ea 5V 50.11 g 0.2% 50.11 g 1.5%Frequency Ratio Qe10 FCLKe250 kHz (fCLK/fo) Mode 1 Vpin9 eb 5V 100.04 g 0.2% 100.04 g 1.5%FCLKe500 kHz fCLK/fo Temp. V pin9 ea 5V g10 ppm/ §CCoefficient (50:1 CLK ratio) Vpin9 eb 5V g20 ppm/ §C(100:1 CLK ratio) Q Accuracy (Max) Ideal Vpin9 ea 5V g10 %(Note 2) Qe10 FCLKe250 kHz Mode 1 Vpin9 eb 5V g10 %FCLKe500 kHz Q Temperature V pin9 ea 5V b200 ppm/ §CCoefficient (50:1 CLK ratio) Vpin9 eb 5V b70 ppm/ §C(100:1 CLK ratio) DC Lowpass Gain Mode 1 g0.2 dBAccuracy (Max) R1 e R2 e 10 k X DC Offset V os1 g5.0 mV Voltage (Max) Vos2 Vpin9 ea 5V b185 mV Vos3 (50:1 CLK ratio) a115 mV (Note 3) V os2 Vpin9 eb 5V b310 mV Vos3 (100:1 CLK ratio) a240 mV

Filter Electrical Characteristics Va e 5Vg 0.5%, V b eb 5Vg 0.5% unless otherwise noted. Boldface limits apply over temperature, T MIN s TA s TMAX. For all other limits T A e 25§C. (Continued) Typical Tested Design Parameter Conditions (Note 6) Limit Limit Units (Note 7) (Note 8) Output BP, LP pins RL e 5k X g4.0 g3.8 V Swing (Min) N/AP/HP pin RL e 3.5 k X g4.2 g3.8 V Vpin9ea 5V 83 dB Dynamic Range (50:1 CLK ratio) (Note 4) Vpin9eb 5V 80 dB (100:1 CLK ratio) Maximum Output Short Circuit Source 20 mA Current (Note 5) Sink 3.0 mA face limits apply over temperature, T MIN s TA s TMAX. For all other limits T A e 25§C. Typical Tested Design Parameter Conditions (Note 6) Limit Limit Units (Note 7) (Note 8) Gain Bandwidth Product 2.5 MHz Output Voltage Swing (Min) RL e 3.5 k X g4.2 g3.8 V Slew Rate 7.0 V/ ms DC Open-Loop Gain 80 db Input Offset Voltage (Max) g5.0 g20 mV Input Bias Current 10 pA Maximum Output Source 20 mA Short Circuit Current (Note 5) Sink 3.0 mA Logic Input Characteristics Boldface limits apply over temperature, T MIN s TA s TMAX. All other limits T A e 25§C. Typical Tested Design Parameter Conditions (Note 6) Limit Limit Units (Note 7) (Note 8) CMOS Clock Min Logical ‘‘1’’ 3.0 V Input Input Voltage V a ea 5V, V b eb 5V, Max Logical ‘‘0’’ V L.Sh. e0V b3.0 V Input Voltage Min Logical ‘‘1’’ 8.0 V Input Voltage V a ea 10V, V b e 0V, Max Logical ‘‘0’’ V L.Sh. ea 5V 2.0 V Input Voltage TTL Clock Min Logical ‘‘1’’ 2.0 V Input Input Voltage V a ea 5V, V b eb 5V, Max Logical ‘‘0’’ V L.Sh. e 0V 0.8 V Input Voltage Note 1: The typical junction-to-ambient thermal resistance ( iJA) of the 14 pin N package is 160 §C/W, and 82 §C/W for the M package. Note 2: The accuracy of the Q value is a function of the center frequency (f o). This is illustrated in the curves under the heading ‘‘Typical Performance Characteristics’’. Note 3: Vos1,V os2, and V os3 refer to the internal offsets as discussed in the Application Information section 3.4. Note 4: For g5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 mV rms for the MF5 with a 50:1 CLK ratio and 280 mV rms for the MF5 with a 100:1 CLK ratio. Note 5: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Note 6: Typicals are at 25 §C and represent most likely parametric norm. Note 7: Guaranteed and 100% tested. Note 8: Guaranteed, but not 100% tested. These limits are not used to calculate outgoing quality levels.

LP(14), BP(1), The second order lowpass, bandpass, N/AP/HP(2): and notch/allpass/highpass outputs. The LP and BP outputs can typically sink 1 mA and source 3 mA. The N/AP/HP output can typically sink 1.5 mA and source 3 mA. Each output typically swings to within 1V of each supply. INV1(3): The inverting input of the summing op amp of the filter. This is a high impedance input, but the non-inverting input is internally tied to AGND, making INV1 behave like a summing junction (low impedance current input). S1(4): S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5). The pin should be driven with a source impedance of less than 1 k X.I fS 1i sn o t driven with a signal it should be tied to AGND (mid-supply). SA(5): This pin activates a switch that connects one of the inputs of the filter’s second summer to either AGND (SA tied to V or to the lowpass (LP) output (SA tied to V a). This offers the flexibility needed for configuring the filter in its various modes of operation. 50/100(9): This pin is used to set the internal clock to center frequency ratio (f CLK/fo)o ft h e filter. By tying the pin to V a an f CLK/fo ratio of about 50:1 (typically 50.11 g 0.2%) is obtained. Tying the 50/100 pin to either AGND or V b will set the f CLK/fo ratio to about 100:1 (typically 100.04 g 0.2%). AGND(11): This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a ‘‘clean’’ ground must be provided. V a(6), V b(10): These are the positive and negative supply pins. The MF5 will operate over a total supply range of 8V to 14V. Decoupling the supply pins with 0.1 mF capacitors is highly recommended. CLK(8): This is the clock input for the filter. CMOS or TTL logic level clocks can be accomodated by setting the L. Sh pin to the levels described in the L. Sh pin description. For optimum filter performance a 50% duty cycle clock is recommended for clock frequencies greater than 200 kHz. This gives each op amp the maximum amount of time to settle to a new sampled input. L. Sh(7): This pin allows the MF5 to accommodate either CMOS or TTL logic level clocks. For dual supply operation (i.e., g5V), a CMOS or TTL logic level clock can be accepted if the L. Sh pin is tied to mid-supply (AGND), which should be the system ground. For single supply operation the L. Sh pin should be tied to mid-supply (AGND) for a CMOS logic level clock. The mid-supply bias should be a very low impedance node. See Applications Information for biasing techniques. For a TTL logic level clock the L. Sh pin should be tied to V b which should be the system ground. INV2(12): This is the inverting input of the uncommitted op amp. This is a very high impedance input, but the non-inverting input is internally tied to AGND, making INV2 behave like a summing junction (low-impedance current input). Vo2(13): This is the output of the uncommitted op amp. It will typically sink 1.5 mA and source 3.0 mA. It will typically swing to within 1V of each supply. Typical Performance Characteristics Deviation of FCLK Fo vs Nominal Q Deviation of FCLK Fo vs Nominal Q OPAMP Output Voltage Swing vs Temperature TL/H/5066–3

1.0 Definitions of Terms

and is the frequency of maximum bandpass gain. ( Figure 1 ). observed as the frequency of a notch at the allpass output. order filter responses as shown in Figure 6 . where Q z e Q for an all-pass response. HOBP: the gain (in V/V) of the bandpass output at f e fo. low are used in place of H ON. HON1: the gain (in V/V) of the notch output as f x0 Hz. HON2: the gain (in V/V) of the notch output as f xfclk/2. FIGURE 1. 2nd-Order Bandpass Response FIGURE 2. 2nd-Order Low-Pass Response FIGURE 3. 2nd-Order High-Pass Response

1.0 Definition of Terms (Continued)

FIGURE 4. 2nd-Order Notch Response FIGURE 5. 2nd-Order All-Pass Response FIGURE 6. Responses of various 2nd-order filters

2.0 Modes of Operation

discussion is based on the well known frequency domain. 1 for a summary of the characteristics of the various modes. fnotch e center frequency of the imaginary zero pair e fo. BW e the b3 dB bandwidth of the bandpass output. Q or H OBP e HOLP c Q e HON c Q. FIGURE 7. MODE 1 FIGURE 8. MODE 1a

2.0 Modes of Operation (Continued)

FIGURE 9. MODE 2 FIGURE 10. MODE 3

able, Mode 5 is recommended. FIGURE 11. MODE 3a FIGURE 12. MODE 4

FIGURE 13. MODE 5 FIGURE 14. MODE 6a FIGURE 15. MODE 6b

gains of various filter outputs are inverting and adjustable by resistor ratios. Mode BP LP HP N AP Number of Adjustable Notesresistors f CLK/fo ** * 3N o (2) May need input buf- 1a H OBP1eb Q HOLPea 1 2 No fer. Poor dynamics HOBP2ea 1 for high Q. Yes (above ** * 3f CLK/50 or fCLK/100) Universal State- ** * 4 Yes Variable Filter. Best general-purpose mode. As above, but also ** * *

7 Yes includes resistor-

tuneable notch. Gives Allpass res- ** *

3 No ponse with H OAPeb1

and H OLPeb2. Gives flatter allpass ** * 4 response than above if R 1eR2e0.02R4. 3 Single pole. (2) 6b H OLPea 1 2 Single pole HOLP2ebR3

3.0 Applications Information

The MF5 is a general-purpose second-order state variable filter whose center frequency is proportional to the frequen- cy of the square wave applied to the clock input (f CLK). By connecting pin 9 to the appropriate DC voltage, the filter center frequency f o can be made equal to either f CLK/100 or f CLK/50. f o can be very accurately set (within g0.6%) by using a crystal clock oscillator, or can be easily varied over a wide frequency range by adjusting the clock frequency. If desired, the f CLK/fo ratio can be altered by external resis- tors as in Figures 9, 10, 11, 13, 14 , and 15 . The filter Q and gain are determined by external resistors. All of the five second-order filter types can be built using the MF5. These are illustrated in Figures 1 through 5 along with their transfer functions and some related equations. Figure 6 shows the effect of Q on the shapes of these curves. When filter orders greater than two are desired, two or more MF5s can be cascaded. The MF5 also includes an uncom- mitted CMOS operational amplifier for additional signal pro- cessing applications.

3.1 DESIGN EXAMPLE

An example will help illustrate the MF5 design procedure. For the example, we will design a 2nd order Butterworth low-pass filter with a cutoff frequency of 200 Hz, and a pass- band gain of b2. The circuit will operate from a g5V power supply, and the clock amplitude will be g5v (CMOS) levels). From the specifications, the filter parameters are: foe200 Hz, H OLPeb2, and, for Butterworth response, Qe0.707. In section 2.0 are several modes of operation for the MF5, each having different characteristics. Some allow adjust- ment of f CLK/fo, others produce different combinations of filter types, some are inverting while others are non-invert- ing, etc. These characteristics are summarized in Table I. To keep the example simple, we will use mode 1, which has notch, bandpass, and lowpass outputs, and inverts the sig- nal polarity. Three external resistors determine the filter’s Q and gain. From the equations accompanying Figure 7 , QeR3/R2 and the passband gain H OLP eb R2/R1. Since the input signal is driving a summing junction through R 1, the input impedance will be equal to R 1. Start by choosing a value for R 1. 10k is convenient and gives a reasonable input impedance. For H OLP eb 2, we have: R2 eb R1HOLP e 10k c 2 e 20k. For Q e 0.707 we have: R3 e R2Q e 20k c 0.707 e 14.14k. Use 15k. For operation on g5V supplies, V a is connected to a5V, Vb to b5V, and AGND to ground. The power supplies should be ‘‘clean’’ (regulated supplies are preferred) and 0.1 mF bypass capacitors are recommended.

3.0 Applications Information (Continued)

FIGURE 16. 2nd-Order Butterworth Low-Pass Filter of Design Change Clock Frequency to 10 kHz. FIGURE 17. Butterworth Low-Pass Circuit of Example, but Designed for Single-Supply Operation

FIGURE 18. Three Ways of Generating Va pedance (less than 1000 X) voltage source.

3.2 SINGLE SUPPLY OPERATION

AGND pin must be tied to V a/2 for single supply operation. be clean (preferably regulated) and bypassed with 0.1 mF.

3.3 DYNAMIC CONSIDERATIONS

ics’’, which relate the Q and the gains at the various outputs. and maximum allowable signals for a given application.

3.4 OFFSET VOLTAGE

typical continuous-time active filter integrator. tios, as described in the following expressions.

FIGURE 19. Block Diagram Showing MF5 FIGURE 20. Method for Trimming V OS,

os(BP) in modes 1a and 3, for example).

3.5 SAMPLED DATA SYSTEM CONSIDERATIONS

a frequency less than one-half the sampling frequency. voltages, as discussed in 3.4. of the ratio with external resistors. FIGURE 21. The Sampled-Data Output Waveform

MF5 Universal Monolithic Switched Capacitor Filter Physical Dimensions inches (millimeters) Order Number MF5CWM Molded Dual-In-Line Package (N) Order Number MF5CN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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