Microcontroller

MF5438AMEP

Texas Instruments

MIXED SIGNAL MICROCONTROLLER REVISED JANUARY 2014

Manufacturer: Texas Instruments

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 MIXEDSIGNALMICROCONTROLLER 1FEATURES 2• Low Supply Voltage Range: – Low-Frequency Trimmed Internal Reference 3.6 V Down to 1.8 V Source (REFO)

Ultralow Power Consumption – 32-kHz Crystals – Active Mode (AM): – High-Frequency Crystals up to 32 MHz (1) All System Clocks Active • 16-Bit Timer TA0, Timer_A With Five 230 µA/MHz at 8 MHz, 3.0 V, Flash Program Capture/Compare Registers Execution (Typical) • 16-Bit Timer TA1, Timer_A With Three110 µA/MHz at 8 MHz, 3.0 V, RAM Program Capture/Compare RegistersExecution (Typical) • 16-Bit Timer TB0, Timer_B With Seven– Standby Mode (LPM3): Capture/Compare Shadow RegistersReal-Time Clock With Crystal, Watchdog, • Up to Four Universal Serial Communicationand Supply Supervisor Operational, Full InterfacesRAM Retention, Fast Wake-Up: – USCI_A0, USCI_A1, USCI_A2, and USCI_A31.7 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) Each SupportingLow-Power Oscillator (VLO), General- Purpose Counter, Watchdog, and Supply – Enhanced UART supporting Auto- Supervisor Operational, Full RAM Baudrate Detection Retention, Fast Wake-Up: – IrDA Encoder and Decoder 1.2 µA at 3.0 V (Typical) – Synchronous SPI – Off Mode (LPM4): – USCI_B0, USCI_B1, USCI_B2, and USCI_B3Full RAM Retention, Supply Supervisor Each SupportingOperational, Fast Wake-Up: – I2CTM 1.2 µA at 3.0 V (Typical) – Synchronous SPI– Shutdown Mode (LPM4.5):
12-Bit Analog-to-Digital (A/D) Converter0.1 µA at 3.0 V (Typical) – Internal Reference• Wake-Up From Standby Mode in 3.5 µs (Typical) – Sample-and-Hold
16-Bit RISC Architecture – Autoscan Feature – Extended Memory – 14 External Channels, 2 Internal Channels – Up to 25-MHz System Clock • Hardware Multiplier Supporting 32-Bit Operations• Flexible Power Management System
Serial Onboard Programming, No External– Fully Integrated LDO With Programmable Programming Voltage NeededRegulated Core Supply Voltage
Three Channel Internal DMA– Supply Voltage Supervision, Monitoring, and Brownout • Basic Timer With Real-Time Clock Feature
Unified Clock System • For Complete Module Descriptions, See the MSP430x5xx and MSP430x6xx Family User's– FLL Control Loop for Frequency Guide (SLAU208)Stabilization
Wide Operational Range: -40°C to 125°C (Q– Low-Power/Low-Frequency Internal Clock Temp), -55°C to 125°C (M Temp) (Some NotedSource (VLO) Parameters Specified for –40°C to 85°C Only) (1) Use of crystals is not ensured above 85°C for both 32-kHz and high frequency crystals. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2014, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Extended (–55°C to 125°C) Temperature Range
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability

DESCRIPTION

The MSP430F5438A-EP is an ultralow-power microcontroller. The architecture, combined with extensive low- power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3.5 µs (typical). The MSP430F5438A-EP is a microcontroller configuration with three 16-bit timers, a high performance 12-bit analog-to-digital (A/D) converter, up to four universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, and up to 87 I/O pins. Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, and hand-held meters. Table 1. Summary

113 GQW,MSP430F5438A-EP 256 16 5, 3 7 4 4 14 ext, 2 int 87 100 PZ

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

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A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A1 1 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B1 1 B12 C1 C2 C3 C1 1 C12 D1 D2 D4 D5 D6 D7 D8 D9 D1 1 D12 E1 E2 E4 E5 E6 E7 E8 E9 E1 1 E12 F1 F2 F4 F5 F8 F9 F1 1 F12 G1 G2 G4 G5 G8 G9 G1 1 G12 J1 J2 J4 J5 J6 J7 J8 J9 J1 1 J12 H1 H2 H4 H5 H6 H7 H8 H9 H1 1 H12 K1 K2 K1 1 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L1 1 L12 M1 M2 M3 M5 M6 M7 M8 M9 M10 M1 1 M12M4 GQW PACKAGE (TOP VIEW) P7.5 P6.7 P9.4 P9.2 P5.0 P7.6 P9.0 P8.7 P5.1 AVCC P6.5 P9.3 P8.6 DVCC2 P7.0 AVSS P7.4 P9.1 P8.5 DVSS2 P7.1 DVSS1 P7.7 P8.3 P8.4 VCORE P1.5 P1.6 P5.6 P5.7 MSP430F5438A-EP www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Pin Designations Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3

(TOP VIEW) 1 1 767778798081828384858687888990919293949596979899100 50494847464544434241403938373635343332313029282726 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 P7.4/A12 P7.5/A13 P7.6/A14 P7.7/A15 P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF−/VeREF− A VCC A VSS P7.0/XIN P7.1/XOUT P1.0/T A0CLK/ACLK P1.1/T A0.0 P1.2/T A0.1 P1.3/T A0.2 P1.4/T A0.3 P1.5/T A0.4 P1.6/SMCLK P1.7 P2.0/T A1CLK/MCLK P9.7 P9.6 P9.5/UCA2RXDUCA2SOMI P9.4/UCA2TXD/UCA2SIMO P9.3/UCB2CLK/UCA2STE P9.2/UCB2SOMI/UCB2SCL P9.1/UCB2SIMO/UCB2SDA P9.0/UCB2STE/UCA2CLK P8.7 P8.6/T A1.1 P8.5/T A1.0 DVCC2 DVSS2 VCORE P8.4/T A0.4 P8.3/T A0.3 P8.2/T A0.2 P8.1/T A0.1 P8.0/T A0.0 P7.3/T A1.2 P7.2/TB0OUTH/SVMOUT P5.7/UCA1RXD/UCA1SOMI P5.6/UCA1TXD/UCA1SIMO P5.5/UCB1CLK/UCA1STE P5.4/UCB1SOMI/UCB1SCL MSP430F5438AMPZ P2.4/RTCCLK P2.5 P2.6/ACLK DVSS3DVCC3 P3.4/UCA0TXD/UCA0SIMOP3.5/UCA0RXD/UCA0SOMIP3.6/UCB1STE/UCA1CLKP3.7/UCB1SIMO/UCB1SDA P4.7/TB0CLK/SMCLK DVSS1 DVCC1 MSP430F5438A-EP SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com

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I/O□Ports P1/P2 2×8□I/Os Interrupt Capability PA 1×16□I/Os CPUXV2 and Working Registers EEM (L:□8+2) XIN XOUT JTAG/ Interface SBW PA PB PC PD DMA 3□Channel XT2IN XT OUT 2 PE Power Management LDO SVM/ Brownout SVS SYS Watchdog PF I/O□Ports P3/P4 2×8□I/Os PB 1×16□I/Os I/O□Ports P5/P6 2×8□I/Os PC 1×16□I/Os I/O□Ports P7/P8 2×8□I/Os PD 1×16□I/Os I/O□Ports P9/P10 2×8□I/Os PE 1×16□I/Os I/O□Ports P11 1×3□I/Os PF 1×3□I/Os MPY32 TA0 Timer_A 5□CC Registers TA1 Timer_A 3□CC Registers TB0 Timer_B 7□CC Registers RTC_A CRC16 USCI0,1,2,3 USCI_Ax: UART, IrDA,□SPI UCSI_Bx: SPI,□I2C ADC12_A 200□KSPS 16□Channels (14□ext/2□int) Autoscan 12□Bit DVCC DVSS AVCC AVSS RST/NMI MAB MDB REF MSP430F5438A-EP www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Functional Block Diagram Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5

Table 2. Terminal Functions

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Table 2. Terminal Functions (continued)

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(3) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions, respectively. (4) See JTAG Operation for use with JTAG function.

Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated. (5) C3, E5, E6, E7, E8, F5, F8, G5, G8, H5, H6, H7, H8 are reserved and should be connected to ground.

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General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R15 General-Purpose Register R14 MSP430F5438A-EP www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 SHORT-FORM DESCRIPTION CPU (Link to User's Guide) The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Operating Modes The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low- power mode on return from the interrupt program. The following seven operating modes can be configured by software:

Active mode (AM) – All clocks are active
Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – FLL loop control remains active
Low-power mode 1 (LPM1) – CPU is disabled – FLL loop control is disabled – ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2) – CPU is disabled – MCLK and FLL loop control and DCOCLK are disabled – DCO's dc-generator remains enabled – ACLK remains active
Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc generator is disabled – ACLK remains active
Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc generator is disabled – Crystal oscillator is stopped – Complete data retention
Low-power mode 4.5 (LPM4.5) – Internal regulator disabled – No data retention – Wakeup from RST, digital I/O

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vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3. Interrupt Sources, Flags, and Vectors (2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (3) Interrupt flags are located in the module. compatibility with other devices, it is recommended to reserve these locations.

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Memory Organization MSP430F5438A Memory (flash) Total Size 256 KB Main: interrupt vector Flash 00FFFFh–00FF80h Main: code memory Flash 045BFFh–005C00h Bank D 64 KB 03FFFFh–030000h Bank C 64 KB 02FFFFh–020000h Main: code memory Bank B 64 KB 01FFFFh–010000h Bank A 64 KB 045BFFh–040000h 00FFFFh–005C00h Size 16 KB Sector 3 4 KB 005BFFh–004C00h Sector 2 4 KB RAM 004BFFh–003C00h Sector 1 4 KB 003BFFh–002C00h Sector 0 4 KB 002BFFh–001C00h Info A 128 B 0019FFh–001980h Info B 128 B 00197Fh–001900h Information memory (flash) Info C 128 B 0018FFh–001880h Info D 128 B 00187Fh–001800h BSL 3 512 B 0017FFh–001600h BSL 2 512 B 0015FFh–001400h Bootstrap loader (BSL) memory (Flash) BSL 1 512 B 0013FFh–001200h BSL 0 512 B 0011FFh–001000h Size 4KBPeripherals 000FFFh–000000h

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Programming via the Bootstrap Loader User's Guide (SLAU319). Table 4. BSL Pin Requirements and Functions MSP430 Memory Programming via the JTAG Interface User's Guide (SLAU320). Table 5. JTAG Pin Requirements and Functions Table 6. Spy-Bi-Wire Pin Requirements and Functions

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Flash Memory (Link to User's Guide) The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include:

Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually. Segments A to D are also called information memory.
Segment A can be locked separately. RAM Memory (Link to User's Guide) The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage, however all data is lost. Features of the RAM memory include:
RAM memory has n sectors. The size of a sector can be found in Memory Organization.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low-power retention mode when possible.
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Digital I/O (Link to User's Guide) There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains three individual I/O ports. For 80-pin options, P1 through P7 are complete. P8 contains seven individual I/O ports. P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.

All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Drive strength on all ports is programmable.
Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF). Oscillator and System Clock (Link to User's Guide) The clock system in the MSP430x5xx family of devices is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode), an internal very-low-power low- frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT1 HF mode or XT2). The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals:
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal low- frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled oscillator DCO.
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32. Power Management Module (PMM) (Link to User's Guide) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply. Hardware Multiplier (MPY) (Link to User's Guide) The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Real-Time Clock (RTC_A) (Link to User's Guide) The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real- time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware. Watchdog Timer (WDT_A) (Link to User's Guide) The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

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exchange mechanism via JTAG called a JTAG mailbox that can be used in the application. Table 7. System Module Interrupt Vector Registers

Table 8. DMA Trigger Assignments (1)

0 DMAREQ DMAREQ DMAREQ

1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG

2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG

3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG

4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG

5 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG

6 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG

7 Reserved Reserved Reserved

8 Reserved Reserved Reserved

9 Reserved Reserved Reserved

10 Reserved Reserved Reserved

11 Reserved Reserved Reserved

12 Reserved Reserved Reserved

13 Reserved Reserved Reserved

14 Reserved Reserved Reserved

15 Reserved Reserved Reserved

16 UCA0RXIFG UCA0RXIFG UCA0RXIFG

17 UCA0TXIFG UCA0TXIFG UCA0TXIFG

18 UCB0RXIFG UCB0RXIFG UCB0RXIFG

19 UCB0TXIFG UCB0TXIFG UCB0TXIFG

20 UCA1RXIFG UCA1RXIFG UCA1RXIFG

21 UCA1TXIFG UCA1TXIFG UCA1TXIFG

22 UCB1RXIFG UCB1RXIFG UCB1RXIFG

23 UCB1TXIFG UCB1TXIFG UCB1TXIFG

24 ADC12IFGx ADC12IFGx ADC12IFGx

25 Reserved Reserved Reserved

26 Reserved Reserved Reserved

27 Reserved Reserved Reserved

28 Reserved Reserved Reserved

29 MPY ready MPY ready MPY ready

30 DMA2IFG DMA0IFG DMA1IFG

31 DMAE0 DMAE0 DMAE0

cause any DMA trigger event when selected.

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The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C. The MSP430F5438A, MSP430F5436A, and MSP430F5419A include four complete USCI modules (n = 0 to 3). The MSP430F5437A, MSP430F5435A, and MSP430F5418A include two complete USCI modules (n = 0 to 1). be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 9. TA0 Signal Connections

be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 10. TA1 Signal Connections

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be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 11. TB0 Signal Connections

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com ADC12_A (Link to User's Guide) The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion- and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. CRC16 (Link to User's Guide) The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. REF Voltage Reference (Link to User's Guide) The reference module (REF) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. Embedded Emulation Module (EEM) (L Version) (Link to User's Guide) The EEM supports real-time in-system debugging. The L version of the EEM implemented on all devices has the following features:

Eight hardware triggers or breakpoints on memory access
Two hardware trigger or breakpoint on CPU register write access
Up to ten hardware triggers can be combined to form complex triggers or breakpoints
Two cycle counters
Sequencer
State storage
Clock control on module level

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Table 12. Peripherals

Table 13. Special Function Registers (Base Address: 0100h) Table 14. PMM Registers (Base Address: 0120h) Table 15. Flash Control Registers (Base Address: 0140h) Table 16. CRC16 Registers (Base Address: 0150h) Table 17. RAM Control Registers (Base Address: 0158h) Table 18. Watchdog Registers (Base Address: 015Ch) Table 19. UCS Registers (Base Address: 0160h)

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Table 20. SYS Registers (Base Address: 0180h) Table 21. Shared Reference Registers (Base Address: 01B0h) Table 22. Port P1, P2 Registers (Base Address: 0200h)

Table 23. Port P3, P4 Registers (Base Address: 0220h) Table 24. Port P5, P6 Registers (Base Address: 0240h) Table 25. Port P7, P8 Registers (Base Address: 0260h)

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Table 26. Port P9, P10 Registers (Base Address: 0280h) Table 27. Port P11 Registers (Base Address: 02A0h) Table 28. Port J Registers (Base Address: 0320h)

Table 29. TA0 Registers (Base Address: 0340h) Table 30. TA1 Registers (Base Address: 0380h)

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Table 31. TB0 Registers (Base Address: 03C0h) Table 32. Real Time Clock Registers (Base Address: 04A0h)

Table 33. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)

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Table 34. DMA Registers (Base Address DMA General Control: 0500h, Table 35. USCI_A0 Registers (Base Address: 05C0h)

Table 36. USCI_B0 Registers (Base Address: 05E0h) Table 37. USCI_A1 Registers (Base Address: 0600h)

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Table 38. USCI_B1 Registers (Base Address: 0620h) Table 39. USCI_A2 Registers (Base Address: 0640h) Table 40. USCI_B2 Registers (Base Address: 0660h)

Table 41. USCI_A3 Registers (Base Address: 0680h) Table 42. USCI_B3 Registers (Base Address: 06A0h)

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Table 43. ADC12_A Registers (Base Address: 0700h)

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied. temperatures not higher than classified on the device label on the shipping boxes or reels. (1) See datasheet for absolute maximum and minimum recommended operating conditions. dominant failure mechanism affecting device wearout for the specific device process and design characteristics. Figure 1. Electromigration Fail Mode Derating Chart

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Thermal Information MSP430F5438A-EP THERMAL METRIC(1) GQW PZ UNITS

113 PINS 100 PINS

θJA Junction-to-ambient thermal resistance(2) 43.6 49 θJCtop Junction-to-case (top) thermal resistance(3) 16.6 9.3 θJB Junction-to-board thermal resistance(4) 17.8 25 °C/W ψJT Junction-to-top characterization parameter(5) 0.3 0.2 ψJB Junction-to-board characterization parameter(6) 15.1 24.7 θJCbot Junction-to-case (bottom) thermal resistance(7) N/A N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 39

The□numbers□within□the□fields□denote□the□supported□PMMCOREVx□settings. tolerated during power up and operation. parameters for the exact values and further details. specified maximum frequency. (4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. Figure 2. Frequency vs Supply Voltage

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014

Electrical Characteristics

Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3) FREQUENCY (fDCO = fMCLK = fSMCLK) EXECUTIONPARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz 25 MHz UNITMEMORY TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX 0 0.29 0.45 2.08 2.30 1 0.32 2.08 3.10 IAM, Flash Flash 3.0 V mA 2 0.33 2.24 3.50 6.37 0 0.17 0.30 0.90 1.10 1 0.18 1.00 1.47 IAM, RAM RAM 3.0 V mA 2 0.19 1.13 1.68 2.82 (1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. (3) Characterized with program executing typical data processing. fACLK = 32768 Hz, fDCO = fMCLK = fSMCLK at specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 41

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2) PARAMETER VCC PMMCOREVx UNIT TYP MAX TYP MAX TYP MAX TYP MAX

2.2 V 0 69 93 69 93 69 93 85 150

ILPM0,1MHz Low-power mode 0(3)(4) µA

3.0 V 3 73 100 73 100 73 100 90 150

ILPM2 Low-power mode 2(5)(4) µA 0 1.4 1.4 1.7 8.5 2 1.5 1.5 2.0 10.1 1 1.8 1.8 2.3 10.5 3.0 V 2 1.9 1.9 2.4 10.6 1 1.0 1.0 1.3 8Low-power mode 3,ILPM3,VLO 3.0 V µAVLO mode(7)(4) 2 1.1 1.1 1.4 8.5 1 1.2 1.2 1.2 8 ILPM4 Low-power mode 4(8)(4) 3.0 V µA 2 1.3 1.3 1.3 8.5 (1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. (3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz (4) Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML). High side monitor disabled (SVMH). RAM retention enabled. (5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled. (6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz (7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz (8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz (9) Internal regulator disabled. No data retention. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Schmitt-Trigger Inputs – General Purpose I/O(1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 1.8 V 0.75 1.45 VIT+ Positive-going input threshold voltage V 3 V 1.45 2.15 1.8 V 0.40 1.05 VIT– Negative-going input threshold voltage V 3 V 0.70 1.7 1.8 V 0.25 0.9 Vhys Input voltage hysteresis (VIT+ – VIT–) V 3 V 0.35 1.05 For pullup: VIN = VSSRPull Pullup or pulldown resistor(2) 21 35 51 kΩFor pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC 5 pF (1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). (2) Also applies to the RST pin when the pullup or pulldown resistor is enabled. Inputs – Ports P1 and P2(1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Port P1, P2: P1.x to P2.x, External trigger pulset(int) External interrupt timing(2) 2.2 V, 3 V 20 nsduration to set interrupt flag (1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. (2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). Leakage Current – General Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Ilkg(Px.y) High-impedance leakage current (1) (2) 1.8 V, 3 V ±50 nA (1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 43

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Outputs – General Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT I(OHmax) = –3 mA(1) VCC – 0.35 VCC 1.8 V I(OHmax) = –10 mA(2) VCC – 0.70 VCC VOH High-level output voltage V I(OHmax) = –5 mA(1) VCC – 0.35 VCC 3 V I(OHmax) = –15 mA(2) VCC – 0.70 VCC I(OLmax) = 3 mA(1) VSS VSS + 0.35 1.8 V I(OLmax) = 10 mA(2) VSS VSS + 0.70 VOL Low-level output voltage V I(OLmax) = 5 mA(1) VSS VSS + 0.35 3 V I(OLmax) = 15 mA(2) VSS VSS + 0.70 (1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. (2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. Outputs – General Purpose I/O (Reduced Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT I(OHmax) = –1 mA(2) VCC – 0.35 VCC 1.8 V I(OHmax) = –3 mA(3) VCC – 0.70 VCC VOH High-level output voltage V I(OHmax) = –2 mA(2) VCC – 0.35 VCC 3.0 V I(OHmax) = –6 mA(3) VCC – 0.70 VCC I(OLmax) = 1 mA(2) VSS VSS + 0.35 1.8 V I(OLmax) = 3 mA(3) VSS VSS + 0.70 VOL Low-level output voltage V I(OLmax) = 2 mA(2) VSS VSS + 0.35 3.0 V I(OLmax) = 6 mA(3) VSS VSS + 0.70 (1) Selecting reduced drive strength may reduce EMI. (2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. (3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified. Output Frequency – General Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VCC = 1.8 V, 16PMMCOREVx = 0Port output frequencyfPx.y P1.6/SMCLK (1) (2) MHz(with load) VCC = 3 V, 25PMMCOREVx = 3 VCC = 1.8 V,P1.0/TA0CLK/ACLK 16PMMCOREVx = 0P1.6/SMCLKfPort_CLK Clock output frequency MHzP2.0/TA1CLK/MCLK VCC = 3 V, 25CL = 20 pF(2) PMMCOREVx = 3 (1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS. (2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

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Figure 7. Figure 8. Figure 9. Figure 10.

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Crystal Oscillator, XT1, Low-Frequency Mode(1)(2) over recommended ranges of supply voltage and TJ = -40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, 0.075 TA = 25°C Differential XT1 oscillator crystal fOSC = 32768 Hz, XTS = 0, ΔIDVCC.LF current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2, 3.0 V 0.170 µA drive setting, LF mode TA = 25°C fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, 0.290 TA = 25°C XT1 oscillator crystal frequency,fXT1,LF0 XTS = 0, XT1BYPASS = 0 32768 HzLF mode XT1 oscillator logic-level square-fXT1,LF,SW XTS = 0, XT1BYPASS = 1(3) (4) 10 32.768 50 kHzwave input frequency, LF mode XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, 210 fXT1,LF = 32768 Hz, CL,eff = 6 pFOscillation allowance forOALF kΩLF crystals(5) XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, 300 fXT1,LF = 32768 Hz, CL,eff = 12 pF XTS = 0, XCAPx = 0(7) 2 XTS = 0, XCAPx = 1 5.5Integrated effective loadCL,eff pFcapacitance, LF mode(6) XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 12.0 XTS = 0, Measured at ACLK,Duty cycle, LF mode 30 70 %fXT1,LF = 32768 Hz Oscillator fault frequency,fFault,LF XTS = 0(9) 10 10000 HzLF mode(8) fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, 1000 TA = 25°C, CL,eff = 6 pF tSTART,LF Startup time, LF mode 3.0 V ms fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, 500 TA = 25°C, CL,eff = 12 pF (1) To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (2) Use of crystal oscillator is not ensured above 85°C. It is recommended that an external digital clock source or other internally generated clock source. (3) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. (4) Maximum frequency of operation of the entire device cannot be exceeded. (5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: (a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF. (b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF. (c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF. (d) For XT1DRIVEx = 3, CL,eff ≥ 6 pF. (6) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. (7) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. (8) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (9) Measured with logic-level input frequency but also applies to operation with crystals. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 47

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Crystal Oscillator, XT1, High-Frequency Mode(1)(2) over recommended ranges of supply voltage and TJ = -40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fOSC = 4 MHz, XTS = 1, XOSCOFF = 0, 200XT1BYPASS = 0, XT1DRIVEx = 0, TA = 25°C fOSC = 12 MHz, XTS = 1, XOSCOFF = 0, 260XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°CXT1 oscillator crystal current,IDVCC.HF 3.0 V µAHF mode fOSC = 20 MHz, XTS = 1, XOSCOFF = 0, 325XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C fOSC = 32 MHz, XTS = 1, XOSCOFF = 0, 450XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C XT1 oscillator crystal frequency, XTS = 1,fXT1,HF0 4 8 MHzHF mode 0 XT1BYPASS = 0, XT1DRIVEx = 0(3) XT1 oscillator crystal frequency, XTS = 1,fXT1,HF1 8 16 MHzHF mode 1 XT1BYPASS = 0, XT1DRIVEx = 1(3) XT1 oscillator crystal frequency, XTS = 1,fXT1,HF2 16 24 MHzHF mode 2 XT1BYPASS = 0, XT1DRIVEx = 2(3) XT1 oscillator crystal frequency, XTS = 1,fXT1,HF3 24 32 MHzHF mode 3 XT1BYPASS = 0, XT1DRIVEx = 3(3) XT1 oscillator logic-level square- XTS = 1,fXT1,HF,SW wave input frequency, HF mode, 0.7 32 MHzXT1BYPASS = 1(4)(3) bypass mode XTS = 1, XT1BYPASS = 0, XT1DRIVEx = 0, 450 fXT1,HF = 6 MHz, CL,eff = 15 pF XTS = 1, XT1BYPASS = 0, XT1DRIVEx = 1, 320 fXT1,HF = 12 MHz, CL,eff = 15 pFOscillation allowance forOAHF ΩHF crystals(5) XTS = 1, XT1BYPASS = 0, XT1DRIVEx = 2, 200 fXT1,HF = 20 MHz, CL,eff = 15 pF XTS = 1, XT1BYPASS = 0, XT1DRIVEx = 3, 200 fXT1,HF = 32 MHz, CL,eff = 15 pF fOSC = 6 MHz, XTS = 1, XT1BYPASS = 0, XT1DRIVEx = 0, 0.5 TA = 25°C, CL,eff = 15 pF tSTART,HF Startup time, HF mode 3.0 V ms fOSC = 20 MHz, XTS = 1, XT1BYPASS = 0, XT1DRIVEx = 2, 0.3 TA = 25°C, CL,eff = 15 pF (1) To improve EMI on the XT1 oscillator the following guidelines should be observed. (a) Keep the traces between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (2) Use of crystal oscillator is not ensured above 85°C. It is recommended that an external digital clock source or other internally generated clock source. (3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation. (4) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. (5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Crystal Oscillator, XT1, High-Frequency Mode(1)(2) (continued) over recommended ranges of supply voltage and TJ = -40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Integrated effective loadCL,eff XTS = 1 1 pFcapacitance, HF mode(6)(7) XTS = 1, Measured at ACLK,Duty cycle, HF mode 40 50 60 %fXT1,HF2 = 20 MHz Oscillator fault frequency,fFault,HF XTS = 1(9) 30 300 kHzHF mode(8) (6) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. (7) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance of up to 18 pF can be supported. (8) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (9) Measured with logic-level input frequency but also applies to operation with crystals. Crystal Oscillator, XT2(1) over recommended ranges of supply voltage and TJ = -40°C to 85°C (unless otherwise noted)(2) (3) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 0, 200 TA = 25°C fOSC = 12 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 1, 260 TA = 25°CXT2 oscillator crystal currentIDVCC.XT2 3.0 V µAconsumption fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 2, 325 TA = 25°C fOSC = 32 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 3, 450 TA = 25°C XT2 oscillator crystal frequency,fXT2,HF0 XT2DRIVEx = 0, XT2BYPASS = 0(4) 4 8 MHzmode 0 XT2 oscillator crystal frequency,fXT2,HF1 XT2DRIVEx = 1, XT2BYPASS = 0(4) 8 16 MHzmode 1 XT2 oscillator crystal frequency,fXT2,HF2 XT2DRIVEx = 2, XT2BYPASS = 0(4) 16 24 MHzmode 2 XT2 oscillator crystal frequency,fXT2,HF3 XT2DRIVEx = 3, XT2BYPASS = 0(4) 24 32 MHzmode 3 XT2 oscillator logic-level square- fXT2,HF,SW wave input frequency, bypass XT2BYPASS = 1(5) (4) 0.7 32 MHz mode (1) Use of crystal oscillator is not ensured above 85°C. It is recommended that an external digital clock source or other internally generated clock source. (2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance of up to 18 pF can be supported. (3) To improve EMI on the XT2 oscillator the following guidelines should be observed. (a) Keep the traces between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT. (d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (4) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation. (5) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 49

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Crystal Oscillator, XT2(1) (continued) over recommended ranges of supply voltage and TJ = -40°C to 85°C (unless otherwise noted)(2) (3) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT XT2DRIVEx = 0, XT2BYPASS = 0, 450fXT2,HF0 = 6 MHz, CL,eff = 15 pF XT2DRIVEx = 1, XT2BYPASS = 0, 320fXT2,HF1 = 12 MHz, CL,eff = 15 pFOscillation allowance forOAHF ΩHF crystals(6) XT2DRIVEx = 2, XT2BYPASS = 0, 200fXT2,HF2 = 20 MHz, CL,eff = 15 pF XT2DRIVEx = 3, XT2BYPASS = 0, 200fXT2,HF3 = 32 MHz, CL,eff = 15 pF fOSC = 6 MHz XT2BYPASS = 0, XT2DRIVEx = 0, 0.5 TA = 25°C, CL,eff = 15 pF tSTART,HF Startup time 3.0 V ms fOSC = 20 MHz XT2BYPASS = 0, XT2DRIVEx = 2, 0.3 TA = 25°C, CL,eff = 15 pF Integrated effective loadCL,eff 1 pFcapacitance, HF mode(7)(2) Duty cycle Measured at ACLK, fXT2,HF2 = 20 MHz 40 50 60 % fFault,HF Oscillator fault frequency(8) XT2BYPASS = 1(9) 30 300 kHz (6) Oscillation allowance is based on a safety factor of 5 for recommended crystals. (7) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. (8) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (9) Measured with logic-level input frequency but also applies to operation with crystals. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 5 9.4 14 kHz dfVLO/dT VLO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.5 %/°C dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 4 %/V Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 % (1) Calculated using the box method: Q temperature: (MAX(-40 to 125°C) – MIN(-40 to 125°C)) / MIN(-40 to 125°C) / (125°C – (-40°C)) M temperature: (MAX(-55 to 125°C) – MIN(-55 to 125°C)) / MIN(-55 to 125°C) / (125°C – (-55°C)) Internal Reference, Low-Frequency Oscillator (REFO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT IREFO REFO oscillator current consumption TA = 25°C 1.8 V to 3.6 V 3 µA REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz fREFO Full temperature range 1.8 V to 3.6 V ±3.5 REFO absolute tolerance calibrated % TA = 25°C 3 V ±1.5 dfREFO/dT REFO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.01 %/°C dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 1.0 %/V Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 % tSTART REFO startup time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs (1) Calculated using the box method: Q temperature: (MAX(-40 to 125°C) – MIN(-40 to 125°C)) / MIN(-40 to 125°C) / (125°C – (-40°C)) M temperature: (MAX(-55 to 125°C) – MIN(-55 to 125°C)) / MIN(-55 to 125°C) / (125°C – (-55°C))

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fDCO(0,0) DCO frequency (0, 0)(1) DCORSELx = 0, DCOx = 0, MODx = 0 0.065 0.25 MHz fDCO(0,31) DCO frequency (0, 31)(1) DCORSELx = 0, DCOx = 31, MODx = 0 0.65 1.75 MHz fDCO(1,0) DCO frequency (1, 0)(1) DCORSELx = 1, DCOx = 0, MODx = 0 0.10 0.41 MHz fDCO(1,31) DCO frequency (1, 31)(1) DCORSELx = 1, DCOx = 31, MODx = 0 1.42 3.5 MHz fDCO(2,0) DCO frequency (2, 0)(1) DCORSELx = 2, DCOx = 0, MODx = 0 0.27 0.8 MHz fDCO(2,31) DCO frequency (2, 31)(1) DCORSELx = 2, DCOx = 31, MODx = 0 3.12 7.43 MHz fDCO(3,0) DCO frequency (3, 0)(1) DCORSELx = 3, DCOx = 0, MODx = 0 0.59 1.56 MHz fDCO(3,31) DCO frequency (3, 31)(1) DCORSELx = 3, DCOx = 31, MODx = 0 6.02 14.05 MHz fDCO(4,0) DCO frequency (4, 0)(1) DCORSELx = 4, DCOx = 0, MODx = 0 1.25 3.25 MHz fDCO(4,31) DCO frequency (4, 31)(1) DCORSELx = 4, DCOx = 31, MODx = 0 12.25 28.25 MHz fDCO(5,0) DCO frequency (5, 0)(1) DCORSELx = 5, DCOx = 0, MODx = 0 2.45 6.05 MHz fDCO(5,31) DCO frequency (5, 31)(1) DCORSELx = 5, DCOx = 31, MODx = 0 23.65 54.15 MHz fDCO(6,0) DCO frequency (6, 0)(1) DCORSELx = 6, DCOx = 0, MODx = 0 4.55 10.75 MHz fDCO(6,31) DCO frequency (6, 31)(1) DCORSELx = 6, DCOx = 31, MODx = 0 38.95 88.05 MHz fDCO(7,0) DCO frequency (7, 0)(1) DCORSELx = 7, DCOx = 0, MODx = 0 8.45 19.65 MHz 135.0fDCO(7,31) DCO frequency (7, 31)(1) DCORSELx = 7, DCOx = 31, MODx = 0 59.95 MHz5 Frequency step between rangeSDCORSEL SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratioDCORSEL and DCORSEL + 1 Frequency step between tapSDCO SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratioDCO and DCO + 1 Duty cycle Measured at SMCLK 40 50 60 % DCO frequency temperaturedfDCO/dT fDCO = 1 MHz 0.1 %/°Cdrift(2) dfDCO/dVCC DCO frequency voltage drift(3) fDCO = 1 MHz 1.9 %/V (1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum or maximum tap setting. (2) Calculated using the box method: Q temperature: (MAX(-40 to 125°C) – MIN(-40 to 125°C)) / MIN(-40 to 125°C) / (125°C – (-40°C)) M temperature: (MAX(-55 to 125°C) – MIN(-55 to 125°C)) / MIN(-55 to 125°C) / (125°C – (-55°C)) Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 51

Figure 11. Typical DCO frequency

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 PMM, Brown-Out Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BORH on voltage,V(DVCC_BOR_IT–) | dDVCC/dt | < 3 V/s 1.47 VDVCC falling level BORH off voltage,V(DVCC_BOR_IT+) | dDVCC/dt | < 3 V/s 0.78 1.30 1.52 VDVCC rising level V(DVCC_BOR_hys) BORH hysteresis 58 275 mV Pulse length required at RST/NMItRESET 2 µspin to accept a reset PMM, Core Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Core voltage, active mode,VCORE3(AM) 2.4 V ≤ DVCC ≤ 3.6 V 1.90 VPMMCOREV = 3 Core voltage, active mode,VCORE2(AM) 2.2 V ≤ DVCC ≤ 3.6 V 1.80 VPMMCOREV = 2 Core voltage, active mode,VCORE1(AM) 2.0 V ≤ DVCC ≤ 3.6 V 1.60 VPMMCOREV = 1 Core voltage, active mode,VCORE0(AM) 1.8 V ≤ DVCC ≤ 3.6 V 1.40 VPMMCOREV = 0 Core voltage, low-currentVCORE3(LPM) 2.4 V ≤ DVCC ≤ 3.6 V 1.94 Vmode, PMMCOREV = 3 Core voltage, low-currentVCORE2(LPM) 2.2 V ≤ DVCC ≤ 3.6 V 1.84 Vmode, PMMCOREV = 2 Core voltage, low-currentVCORE1(LPM) 2.0 V ≤ DVCC ≤ 3.6 V 1.64 Vmode, PMMCOREV = 1 Core voltage, low-currentVCORE0(LPM) 1.8 V ≤ DVCC ≤ 3.6 V 1.44 Vmode, PMMCOREV = 0 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 53

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVSHE = 0, DVCC = 3.6 V 0 nA I(SVSH) SVS current consumption SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200 nA SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 1.5 µA SVSHE = 1, SVSHRVL = 0 1.55 1.68 1.8 SVSHE = 1, SVSHRVL = 1 1.77 1.88 2 V(SVSH_IT–) SVSH on voltage level(1) V SVSHE = 1, SVSHRVL = 2 1.96 2.08 2.23 SVSHE = 1, SVSHRVL = 3 2.07 2.18 2.33 SVSHE = 1, SVSMHRRL = 0 1.60 1.74 1.87 SVSHE = 1, SVSMHRRL = 1 1.86 1.94 2.09 SVSHE = 1, SVSMHRRL = 2 2.05 2.14 2.3 SVSHE = 1, SVSMHRRL = 3 2.18 2.30 2.44 V(SVSH_IT+) SVSH off voltage level(1) V SVSHE = 1, SVSMHRRL = 4 2.30 2.40 2.57 SVSHE = 1, SVSMHRRL = 5 2.50 2.70 2.9 SVSHE = 1, SVSMHRRL = 6 2.85 3.10 3.25 SVSHE = 1, SVSMHRRL = 7 2.85 3.10 3.25 SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5 tpd(SVSH) SVSH propagation delay µs SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20 SVSHE = 0 → 1, SVSHFP = 1 12.5 t(SVSH) SVSH on or off delay time µs SVSHE = 0 → 1, SVSHFP = 0 100 dVDVCC/dt DVCC rise time 0 1000 V/s (1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use. PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVMHE = 0, DVCC = 3.6 V 0 nA I(SVMH) SVMH current consumption SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0 200 nA SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.5 µA SVMHE = 1, SVSMHRRL = 0 1.61 1.74 1.87 SVMHE = 1, SVSMHRRL = 1 1.86 1.94 2.09 SVMHE = 1, SVSMHRRL = 2 2.05 2.14 2.30 SVMHE = 1, SVSMHRRL = 3 2.18 2.30 2.44 V(SVMH) SVMH on or off voltage level(1) SVMHE = 1, SVSMHRRL = 4 2.30 2.40 2.58 V SVMHE = 1, SVSMHRRL = 5 2.50 2.70 2.93 SVMHE = 1, SVSMHRRL = 6 2.85 3.10 3.25 SVMHE = 1, SVSMHRRL = 7 2.85 3.10 3.25 SVMHE = 1, SVMHOVPE = 1 3.75 SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5 tpd(SVMH) SVMH propagation delay µs SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20 SVMHE = 0 → 1, SVMHFP = 1 12.5 t(SVMH) SVMH on or off delay time µs SVMHE = 0 → 1, SVMHFP = 0 100 (1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 PMM, SVS Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVSLE = 0, PMMCOREV = 2 0 nA I(SVSL) SVSL current consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 nA SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 µA SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5 tpd(SVSL) SVSL propagation delay µs SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20 SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 12.5 t(SVSL) SVSL on or off delay time µs SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 100 PMM, SVM Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVMLE = 0, PMMCOREV = 2 0 nA I(SVML) SVML current consumption SVMLE= 1, PMMCOREV = 2, SVMLFP = 0 200 nA SVMLE= 1, PMMCOREV = 2, SVMLFP = 1 1.5 µA SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5 tpd(SVML) SVML propagation delay µs SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20 SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 12.5 t(SVML) SVML on or off delay time µs SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 100 Wake-Up From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMCLK ≥ 4.0 MHz 3.5 7.5Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n tWAKE-UP-FAST LPM3, or LPM4 to active (where n = 0, 1, 2, or 3), µs1.0 MHz < fMCLK 4.5 9.5mode(1)(2) SVSLFP = 1 < 4.0 MHz Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n tWAKE-UP-SLOW LPM3 or LPM4 to active (where n = 0, 1, 2, or 3), 150 170 µs mode(3) SVSLFP = 0 Wake-up time from LPM4.5 totWAKE-UP-LPM5 2 3.5 msactive mode(4) Wake-up time from RST ortWAKE-UP-RESET 2 3.5 msBOR event to active mode(4) (1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (2) Ensured only until TJ = 85°C. (3) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (4) This value represents the time from the wakeup event to the reset vector execution. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 55

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLK, 1.8 V/fTA Timer_A input clock frequency External: TACLK, 25 MHz3.0 VDuty cycle = 50% ± 10% All capture inputs, 1.8 V/tTA,cap Timer_A capture timing 20 nsMinimum pulse duration required for capture 3.0 V Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLK, 1.8 V/fTB Timer_B input clock frequency External: TBCLK, 25 MHz3.0 VDuty cycle = 50% ± 10% All capture inputs, 1.8 V/tTB,cap Timer_B capture timing 20 nsMinimum pulse duration required for capture 3.0 V USCI (UART Mode) Recommended Operating Conditions PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLK, fUSCI USCI input clock frequency External: UCLK, fSYSTEM MHz Duty cycle = 50% ± 10% BITCLK clock frequencyfBITCLK 1 MHz(equals baud rate in MBaud) USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT

2.2 V 50 600

tτ UART receive deglitch time(1) ns

3 V 48 620

(1) Pulses on the UART receive input (UCxRX) that are shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 USCI (SPI Master Mode) Recommended Operating Conditions PARAMETER CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLKfUSCI USCI input clock frequency fSYSTEM MHzDuty cycle = 50% ± 10% USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note (1), Figure 12 and Figure 13) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT SMCLK, ACLK,fUSCI USCI input clock frequency fSYSTEM MHzDuty cycle = 50% ± 10%

1.8 V 55

PMMCOREV = 0 ns

3.0 V 38

tSU,MI SOMI input data setup time

2.4 V 30

PMMCOREV = 3 ns

3.0 V 25

1.8 V 0

PMMCOREV = 0 ns

3.0 V 0

tHD,MI SOMI input data hold time

2.4 V 0

PMMCOREV = 3 ns 1.8 V 20UCLK edge to SIMO valid, nsCL = 20 pF, PMMCOREV = 0 3.0 V 18 tVALID,MO SIMO output data valid time(2) 2.4 V 16UCLK edge to SIMO valid, nsCL = 20 pF, PMMCOREV = 3 3.0 V 15

1.8 V -10

CL = 20 pF, PMMCOREV = 0 ns

3.0 V -8

tHD,MO SIMO output data hold time(3)

2.4 V -10

CL = 20 pF, PMMCOREV = 3 ns (1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. (2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 12 and Figure 13. (3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 12 and Figure 13. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 57

Figure 12. SPI Master Mode, CKPH = 0 Figure 13. SPI Master Mode, CKPH = 1

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www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note (1), Figure 14 and Figure 15) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

1.8 V 11

PMMCOREV = 0 ns

3.0 V 8

tSTE,LEAD STE lead time, STE low to clock

2.4 V 7

PMMCOREV = 3 ns

3.0 V 6

1.8 V 3

PMMCOREV = 0 ns

3.0 V 3

tSTE,LAG STE lag time, Last clock to STE high

2.4 V 3

PMMCOREV = 3 ns

1.8 V 66

PMMCOREV = 0 ns 3.0 V 50STE access time, STE low to SOMI datatSTE,ACC out 2.4 V 36 PMMCOREV = 3 ns

3.0 V 30

1.8 V 30

PMMCOREV = 0 ns 3.0 V 23STE disable time, STE high to SOMI hightSTE,DIS impedance 2.4 V 16 PMMCOREV = 3 ns

3.0 V 13

1.8 V 5

PMMCOREV = 0 ns

3.0 V 5

tSU,SI SIMO input data setup time

2.4 V 2

PMMCOREV = 3 ns

3.0 V 2

PMMCOREV = 0 ns tHD,SI SIMO input data hold time

2.4 V 5

PMMCOREV = 3 ns 1.8 V 76UCLK edge to SOMI valid, nsCL = 20 pF, PMMCOREV = 0 3.0 V 60 tVALID,SO SOMI output data valid time(2) 2.4 V 44UCLK edge to SOMI valid, nsCL = 20 pF, PMMCOREV = 3 3.0 V 40

1.8 V 18

CL = 20 pF, PMMCOREV = 0 ns

3.0 V 12

tHD,SO SOMI output data hold time(3)

2.4 V 10

CL = 20 pF, PMMCOREV = 3 ns (1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)). For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave. (2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 12 and Figure 13. (3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 12 and Figure 13. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 59

Figure 14. SPI Slave Mode, CKPH = 0 Figure 15. SPI Slave Mode, CKPH = 1

2.2 V 50 600Pulse duration of spikes suppressed by inputtSP nsfilter 3 V 50 600

Figure 16. I2C Mode Timing

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com 12-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT AVCC and DVCC are connected together, AVCC Analog supply voltage AVSS and DVSS are connected together, 2.2 3.6 V V(AVSS) = V(DVSS) = 0 V V(Ax) Analog input voltage range(2) All ADC12 analog input pins Ax 0 AVCC V 2.2 V 125 200Operating supply current intoIADC12_A fADC12CLK = 5.0 MHz(4) µAAVCC terminal(3)

3 V 150 270

Only one terminal Ax can be selected at oneCI Input capacitance 2.2 V 20 pFtime RI Input MUX ON resistance 0 V ≤ VAx ≤ AVCC 200 Ω (1) The leakage current is specified by the digital I/O input leakage. (2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling capacitors are required. See REF, External Reference andREF, Built-In Reference. (3) The internal reference supply current is not included in current consumption parameter IADC12_A. (4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0. 12-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT For specified performance of ADC12 linearity parameters using an external reference voltage or 0.45 4.8 5.0 AVCC as reference.(1) For specified performance of ADC12 linearity 0.45 2.4 2.7parameters using the internal reference.(3) Internal ADC12fADC12OSC ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHzoscillator(4) REFON = 0, Internal oscillator, 2.2 V, 3 V 2.4 3.1ADC12OSC used for ADC conversion clock tCONVERT Conversion time µs External fADC12CLK from ACLK, MCLK, or SMCLK, (5) ADC12SSEL ≠ 0 RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,tSample Sampling time 2.2 V, 3 V 1000 nsτ = [RS + RI] × CI (6) (1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0, SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz. (2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1 (3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC divided by 2. (4) The ADC12OSC is sourced directly from MODOSC inside the UCS. (5) 13 × ADC12DIV × 1/fADC12CLK (6) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance

www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI Integral linearity error(1) 2.2 V, 3 V LSB 1.6 V < dVREF(2) ±1.7 ED Differential linearity error(1) (2) 2.2 V, 3 V ±1.0 LSB dVREF ≤ 2.2 V(2) 2.2 V, 3 V ±2.0 EO Offset error(3) LSB dVREF > 2.2 V(2) 2.2 V, 3 V ±2.0 EG Gain error(3) (2) 2.2 V, 3 V ±2.0 LSB dVREF ≤ 2.2 V(2) 2.2 V, 3 V ±3.5 ET Total unadjusted error LSB dVREF > 2.2 V(2) 2.2 V, 3 V ±3.5 (1) Parameters are derived using the histogram method. (2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-, VR+ < AVCC, VR- > AVSS. Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (3) Parameters are derived using a best fit curve. 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS(1) VCC MIN TYP MAX UNIT ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz ±1.7Integral linearityEI 2.2 V, 3 V LSBerror(2) ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±2.5 ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz +1.5 DifferentialED ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 2.7 MHz 2.2 V, 3 V +1.0 LSBlinearity error(2) ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz +2.5 ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz ±4.0 EO Offset error(3) 2.2 V, 3 V LSB ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±4.0 ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz ±2.5 LSB EG Gain error(3) 2.2 V, 3 V ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±1.5%(4) VREF ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz ±5 LSBTotal unadjustedET 2.2 V, 3 Verror ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±1.5%(4) VREF (1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ - VR-. (2) Parameters are derived using the histogram method. (3) Parameters are derived using a best fit curve. (4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this mode the reference voltage used by the ADC12_A is not available on a pin. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 63

2.2 V 680ADC12ON = 1, INCH = 0Ah,VSENSOR See (2) mVTA = 0°C 3 V 680

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on). (4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. Figure 17. Typical Temperature Sensor Voltage

www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Positive external referenceVeREF+ VeREF+ > VREF–/VeREF– (2) 1.4 AVCC Vvoltage input Negative external referenceVREF–/VeREF– VeREF+ > VREF–/VeREF– (3) 0 1.2 Vvoltage input (VeREF+ – Differential external reference VeREF+ > VREF–/VeREF– (4) 1.4 AVCC VVREF–/VeREF–) voltage input

1.4 V ≤ VeREF+ ≤ VAVCC,

VeREF– = 0 V, fADC12CLK = 5 MHz, TJ = 25°C 2.2 V, 3 V ±26 µA ADC12SHTx = 1h, IVeREF+, Conversion rate 200 kspsStatic input currentIVREF–/VeREF– VeREF– = 0 V, fADC12CLK = 5 MHz, 2.2 V, 3 V -2.5 2.5 µAADC12SHTx = 8h, Conversion rate 20 ksps Capacitance at VREF+ and VREF-CVREF+/- See (5) 10 µFterminals (1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. (2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. (3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. (4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. (5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT REFVSEL = {2} for 2.5 V, 3 V 2.50 ±2.5%REFON = REFOUT = 1, IVREF+= 0 A Positive built-in reference REFVSEL = {1} for 2.0 V,VREF+ 3 V 1.98 ±2.5% Vvoltage output REFON = REFOUT = 1, IVREF+= 0 A REFVSEL = {0} for 1.5 V, 2.2 V, 3 V 1.49 ±2.5%REFON = REFOUT = 1, IVREF+= 0 A REFVSEL = {0} for 1.5 V 2.2AVCC minimum voltage, AVCC(min) Positive built-in reference REFVSEL = {1} for 2.0 V 2.3 V active REFVSEL = {2} for 2.5 V 2.8 ADC12SR = 1, REFON = 1, REFOUT = 0, 3 V 70 µAREFBURST = 0 ADC12SR = 1, REFON = 1, REFOUT = 1, 3 V 0.45 mAREFBURST = 0Operating supply current intoIREF+ AVCC terminal(2) (3) ADC12SR = 0, REFON = 1, REFOUT = 0, 3 V 210 350 µAREFBURST = 0 ADC12SR = 0, REFON = 1, REFOUT = 1, 3 V 0.95 2 mAREFBURST = 0 (1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as, used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference for the conversion and utilizes the smaller buffer. (2) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without external load. (3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with REFON =1 and REFOUT = 0. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 65

SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com REF, Built-In Reference (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT REFVSEL = (0, 1, 2} Load-current regulation, IVREF+ = +10 µA/–1000 µAIL(VREF+) 2500 µV/mAVREF+ terminal(4) AVCC = AVCC (min) for each reference level, REFVSEL = (0, 1, 2}, REFON = REFOUT = 1 Capacitance at VREF+CVREF+ REFON = REFOUT = 1 20 100 pFterminals IVREF+ = 0 A,Temperature coefficient of ppm/TCREF+ REFVSEL = (0, 1, 2}, REFON = 1, 30built-in reference(5) °CREFOUT = 0 or 1 AVCC = AVCC (min) - AVCC(max), TJ = 25°C,Power supply rejection ratioPSRR_DC REFVSEL = (0, 1, 2}, REFON = 1, 120 µV/V(DC) REFOUT = 0 or 1 AVCC = AVCC (min) - AVCC(max), TJ = 25°C, Power supply rejection ratio f = 1 kHz, ΔVpp = 100 mV,PSRR_AC 6.4 mV/V(AC) REFVSEL = (0, 1, 2}, REFON = 1, REFOUT = 0 or 1 AVCC = AVCC (min) - AVCC(max), REFVSEL = (0, 1, 2}, REFOUT = 0, 75 REFON = 0 → 1 Settling time of referencetSETTLE µsAVCC = AVCC (min) - AVCC(max),voltage(6) CVREF = CVREF(max), 75REFVSEL = (0, 1, 2}, REFOUT = 1, REFON = 0 → 1 (4) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc. (5) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)). (6) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load when REFOUT = 1. Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DVCC(PGM/ERASE) Program and erase supply voltage 1.8 3.6 V IPGM Average supply current from DVCC during program 3 7 mA IERASE Average supply current from DVCC during erase 7 mA Average supply current from DVCC during mass erase orIMERASE, IBANK 7 mAbank erase tCPT Cumulative program time See (1) 16 ms Program and erase endurance TJ = -40°C to 105°C 104 105 cycles tRetention Data retention duration(2) TJ = 25°C 100 years tWord Word or byte program time See (3) 64 85 µs tBlock, 0 Block program time for first byte or word See (3) 49 65 µs Block program time for each additional byte or word, excepttBlock, 1–(N–1) See (3) 37 49 µsfor last byte or word tBlock, N Block program time for last byte or word See (3) 55 73 µs Erase time for segment, mass erase, and bank erase whentErase See (3) 23 32 msavailable. MCLK frequency in marginal read modefMCLK,MGR 0 1 MHz(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1) (1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. (2) The data retention specification is based on qualification stress testing at 170°C for 420 hours with temperature derating based on an Arrhenius model with activation energy of 0.6 eV. Additional flash retention documentation is provided in application report SLAA392. (3) These values are hardwired into the flash controller's state machine.

www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1) 2.2 V, 3 V 1 µs tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs

2.2 V 0 5 MHz

fTCK TCK input frequency, 4-wire JTAG(2)

3 V 0 10 MHz

Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ (1) Tools accessing the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. (2) fTCK may be restricted to meet the timing requirements of the module selected. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 67

P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/SMCLK P1.7 Direction 0: Input 1: Output P1SEL.x 0P1DIR.x P1IN.x P1IRQ.x EN Module X IN Module X OUT P1OUT.x Interrupt Edge Select Q EN Set P1SEL.x P1IES.x P1IFG.x P1IE.x 0DVSS DVCC P1REN.x Pad Logic P1DS.x 0: Low drive 1: High drive D MSP430F5438A-EP SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

Table 44. Port P1 (P1.0 to P1.7) Pin Functions

P2.0/TA1CLK/MCLK P2.1/TA1.0 P2.2/TA1.1 P2.3/TA1.2 P2.4/RTCCLK P2.5 P2.6/ACLK P2.7/ADC12CLK/DMAE0 Direction 0: Input 1: Output P2SEL.x 0P2DIR.x P2IN.x P2IRQ.x EN Module X IN Module X OUT P2OUT.x Interrupt Edge Select Q EN Set P2SEL.x P2IES.x P2IFG.x P2IE.x 0DVSS DVCC P2REN.x Pad Logic P2DS.x 0: Low drive 1: High drive D MSP430F5438A-EP SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

Table 45. Port P2 (P2.0 to P2.7) Pin Functions

Table 46. Port P3 (P3.0 to P3.7) Pin Functions (2) The pin direction is controlled by the USCI module. 3-wire SPI mode if 4-wire SPI mode is selected. (4) If the I2C functionality is selected, the output drives only the logical 0 to VSS level. 3-wire SPI mode if 4-wire SPI mode is selected. 3-wire SPI mode if 4-wire SPI mode is selected.

P4.0/TB0.0 P4.1/TB0.1 P4.2/TB0.2 P4.3/TB0.3 P4.4/TB0.4 P4.5/TB0.5 P4.6/TB0.6 P4.7/TB0CLK/SMCLK Direction 0: Input 1: Output P4SEL.x 0P4DIR.x P4IN.x EN Module X IN Module X OUT P4OUT.x 0DVSS DVCC P4REN.x Pad Logic P4DS.x 0: Low drive 1: High drive D MSP430F5438A-EP www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 73

Table 47. Port P4 (P4.0 to P4.7) Pin Functions (1) Setting TBOUTH causes all Timer_B configured outputs to be set to high impedance.

P5.0/A8/VREF+/VeREF+ P5.1/A9/VREF–/VeREF– P5SEL.x 0P5DIR.x P5IN.x EN Module□X□IN Module□X□OUT P5OUT.x 0DVSS DVCC P5REN.x P5DS.x 0:□Low□drive 1:□High□drive D Bus Keeper To/From ADC12□Reference Pad□Logic To ADC12 INCHx□=□y MSP430F5438A-EP www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 75

Table 48. Port P5 (P5.0 and P5.1) Pin Functions with the INCHx bits, is connected to the VREF+/VeREF+ pin. with the INCHx bits, is connected to the VREF-/VeREF- pin.

P5.2/XT2IN P5SEL.2 0P5DIR.2 P5IN.2 EN Module□X□IN Module□X□OUT P5OUT.2 0DVSS DVCC P5REN.2 Pad□Logic P5DS.2 0:□Low□drive 1:□High□drive D Bus Keeper To□XT2 MSP430F5438A-EP www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014 Port P5, P5.2, Input/Output With Schmitt Trigger Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 77

Table 49. Port P5 (P5.2) Pin Functions

Table 50. Port P5 (P5.4 to P5.7) Pin Functions (2) The pin direction is controlled by the USCI module. (3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level. 3-wire SPI mode if 4-wire SPI mode is selected.

P6SEL.x 0P6DIR.x P6IN.x EN Module X IN Module X OUT P6OUT.x 0DVSS DVCC P6REN.x Pad Logic P6DS.x 0: Low drive 1: High drive D Bus Keeper To ADC12 P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 INCHx = y MSP430F5438A-EP SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

Table 51. Port P6 (P6.0 to P6.7) Pin Functions (3) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.

P7.0/XIN P7SEL.0 0P7DIR.0 P7IN.0 EN Module X IN Module X OUT P7OUT.0 0DVSS DVCC P7REN.0 Pad Logic P7DS.0 0: Low drive 1: High drive D Bus Keeper To XT1 MSP430F5438A-EP SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Port P7, P7.0, Input/Output With Schmitt Trigger

Table 52. Port P7 (P7.0 and P7.1) Pin Functions

Table 53. Port P7 (P7.2 and P7.3) Pin Functions

Table 54. Port P7 (P7.4 to P7.7) Pin Functions (3) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits. (5) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.

Table 55. Port P8 (P8.0 to P8.7) Pin Functions

Table 56. Port P9 (P9.0 to P9.7) Pin Functions (2) The pin direction is controlled by the USCI module. 3-wire SPI mode if 4-wire SPI mode is selected. (4) If the I2C functionality is selected, the output drives only the logical 0 to VSS level. 3-wire SPI mode if 4-wire SPI mode is selected.

Table 57. Port P10 (P10.0 to P10.7) Pin Functions (2) The pin direction is controlled by the USCI module. 3-wire SPI mode if 4-wire SPI mode is selected. (4) If the I2C functionality is selected, the output drives only the logical 0 to VSS level. 3-wire SPI mode if 4-wire SPI mode is selected. cleared to prevent potential conflicts with the application.

Table 58. Port P11 (P11.0 to P11.2) Pin Functions

PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK From JTAG 0PJDIR.x PJIN.x EN From JTAG PJOUT.x 0DVSS DVCC PJREN.x Pad Logic PJDS.x 0: Low drive 1: High drive D DVSS To JTAG PJ.0/TDO From JTAG 0PJDIR.0 PJIN.0 EN From JTAG PJOUT.0 0DVSS DVCC PJREN.0 Pad Logic PJDS.0 0: Low drive 1: High drive D DVCC MSP430F5438A-EP SLAS967A – JANUARY 2014– REVISED JANUARY 2014 www.ti.com Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

Table 59. Port PJ (PJ.0 to PJ.3) Pin Functions (3) The pin direction is controlled by the JTAG module. (4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

Table 60. Device Descriptor Table(1)

Table 60. Device Descriptor Table(1) (continued)

www.ti.com SLAS967A – JANUARY 2014– REVISED JANUARY 2014

REVISION HISTORY

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) MSP430F5438AMPZREP Active Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -55 to 125 MF5438AMEP MSP430F5438AMPZREP.A Active Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -55 to 125 MF5438AMEP V62/14608-02YE Active Production LQFP (PZ) | 100 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -55 to 125 MF5438AMEP (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF MSP430F5438A-EP :

Catalog : MSP430F5438A Addendum-Page 1

www.ti.com 23-May-2025 NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product Addendum-Page 2

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149/B 11/96 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 12,00 TYP 0,17 100 SQ SQ15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0°–7° Seating Plane 0,08 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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Product Information

MF5438AMEP specifications and overview.

Summary

MIXED SIGNAL MICROCONTROLLER REVISED JANUARY 2014

Description

MIXED SIGNAL MICROCONTROLLER REVISED JANUARY 2014

Source title MF5438AMEP Datasheet(PDF) - Texas Instruments

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