MF4CN-100

MF4CN-100 NSC | Alldatasheet

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MF4 4th Order Switched Capacitor Butterworth Lowpass Filter General Description Features The MF4 is a versatile, easy to use, precision 4th order ™ Low Cost Butterworth low-pass filter. Switched-capacitor techniques ™@ Easy to use eliminate external component requirements and allow @ m 8-pin mini-DIP or 14-pin wide-body S.O. clock-tunable cutoff frequency. The ratio of the clock fre- —_m No external components quency to the low-pass cutoff frequency is internally setto g sy to 14V ita 50 to 1 (MF4-50) or 100 to 1 (MF4-100). A Schmitt trigger supply voltage , § Cutoff frequency range of 0.1 Hz to 20 kHz clock input stage allows two clocking options, either seif- Cutott fr f + 0.3% typical clocking (via an external resistor and capacitor) for stand- § Cutoff frequency accuracy of 3% typical alone applications, or for tighter cutoff frequency control an Cutott frequency set by external clock external TTL or CMOS logic compatible clock can be ap- Separate TTL and CMOS/Schmitt-trigger clock inputs plied. The maximally flat passband frequency response to- gether with a DC gain of 1 V/V allows cascading MF4 sec- tions together for higher order filtering. el Rein eed Block and Connection Diagrams Dual-In-Line Package cxwedy JL aoe ‘FILTER cu 2 7 vw ouT Ld 48h 3 6 ano - AUER ¥ 4 5 our FILTER ' ‘4TH ORDER LJ TL/H/5064-2 wO] BUTTERWORTH ‘ Order Number MF4CN-50 LOWPASS FLTER Ov or MF4CN-100 See NS Package Number NOSE soca Small-Outiine ‘TRISTATE? LEVEL ox pt [>> ) SHIFT Wide-Body Package “ an ve a, CuKIN—A 14 FILTER IN NC—2 13, NC CLKR=43 12ev 2 3 Noms 11 Nc oo LsH45 10 GND CLKR sh NC 16 OF NC TUM/S064~1 vo 8 FILTER OUT TUH/s064-25 Top View Order Number MF4CWM-50 or MF4CWM-100 See NS Package Number M14B 1-106

i Soldering Information: a Absolute Maximum Ratings (notes 1, 2) ° N Package. 10 s00. 260°C If Military/Aerospace specified devices are required, © SO Package: Vapor Phase (60 sec.) 215°C please contact the National Semiconductor Sales Infrared (15 sec.) 220°C Offloe/ Distributors for availability and specifications. See AN-450 “Surface Mounting Methods and Their Effect Supply Voltage (V*+-V—) tv ‘on Product Reliability” for other methods of soldering sur- Voltage At Any Pin V+ +0.2V face mount devices. V~ -0.2V Input Current at Any Pin (Note 14) 5mA Operating Ratings (note 2) Package Input Current (Note 14) 20 mA Temperature Range Tmin < TA < Tmax Power Dissipation (Note 15) 500 mw MFA4CN-50, MF4CN-100 Orc <Ta < 70°C Storage Temperature 150°C MF4CWN-50, MFACWM-100 oc <Ta < 70°C ESD Susceptibility (Note 13) 800V Supply Voltage (V+-V—) SV to 14V Filter Electrical Characteristics the following specifications apply for tox < 250 kHz (see Note 5) unless otherwise specified. Boldface limits apply for Tin to Tmax; all other limits Ta = Ty = 25°C. ec ee Parameter Conditions Typical Tested | Design Typical Tested Design Unit (Note 10) | Limit Limit (Note 10) | Limit Limit (Note 11) | (Note 12) (Note 11) | (Note 12) Vt = +5V,V- = —5V fg Cutoff Frequency oA fy Range (Note 3) 410k Supply Current lrox= 250K | 26 | 3s | as | 2s | 3s | ss | ma Maximum Clock | Filter Output | Vi, = OV Feedthrough mV (Peak-to-Peak) fotk/fe Temperature + 1 Coefficient #15 #90 ppm/*C StopbandAttenuation (Min) [at2te | -250 | -240 | 20.0 [ -250 | -240 | -200| a8 1 | DC Ofset Voltage P| 200 P00 Pn Minimum Output Swing Ri = 10k +4.0 +35 +3.5 +40 +3.5 +3.5 v Output Short Circuit | Source 50 mA Current (Note 8) Sink 15 mA DynamicRange notes) | | ao TTT oe PT Additional Magnitude f = 6000 Hz -7.57 -7.57 Response Test Points +0.27 +0.27 Note 6 08 (Note 6) f= 4500 Hz -1.44 | —1.44 fork = 250 kHz +012 | +012 +0. +0.2 +0.2 4B f = 2250 Hz —1.39 —1.39 £04 £04 1-107

=| Filter Electrical Characteristics the toliowing specifications apply for fo.x < 250 kHz (see Note 5) unless otherwise specified. Boldface limits apply for Tyan to Tax; all other limits Ta = Ty = 25°C. (Continued) Parameter Ty Tested Design Typical Tested Design Unit wi yen) Limit | Limit | ayete 10] Limit | Lit (ote 11) | (ote 12) | 8 9) ote 41) | (Note 12) fc Cutoff Frequency He Range (Note 3) sama Ouert lan aowe [is [ex | eas | ve | a0 | eae | ma Maximum Clock Feedthrough | Fitter Output | Vin = 0V mv (Peak-to-Peak) He 00 Gn Ioana Zena] oo | sare | seas | oo | vois | sone | a fotk/fe, Clock to Cutoff 50.07 | 5007 | 80.07 | 9916 | 99.16 | 99.16 fouk/fc Temperature . ‘ent +25 +60 ppm/*C_ StopbandAttenuation(Miny [atte ‘| -250 | -240 | -2a0 | -250 | -240 | -240 | op DC Offset Vottage [to T= a00 Pv Minimum Output Swing Ry = 10k +15 | +10 | +40 | +15 | +10 | +40 / Vv Output Short Circuit Source mA Current (Note 8) Sink mA DynamicRangoinotea) | | ve [| | S| es TT Additional Magnitude fok = 250 kHz Response Test Points (fe = 5 kHz) f = 6000 Hz +0.27 | £0.27 Magnitude at f = 4500 Hz -146 | -1.46 +012 | +042 3B Magnitude +0.2 +0.2 4B -1.39 | -4.39 +01 | +04 Logic Input-Output Characteristics the following specifications apply for V- = OV (see Note 7) unless otherwise specified. Boldface limits apply for Twin to Twax; all other limits Ta = Ty = 25°C. typical | Tested Parameter Conditions (ete 0) Limit Unit (Note 11) SCHMITT TRIGGER aap Te Te Voltage V+ = 5V 34 fiefs te | ee le 4-108

. wv" Logic Input-Output Characteristics the totiowing specifications apply for V— = OV (see Note 7) unless ry otherwise specified. Boldface limits apply for Twin to Tax; all other limits Ta = ty = 25°C. (Continued) Tested Design Parameter « te 10) Umit Limit Unit (Note 11) | (Note 12) SCHMITT TRIGGER (Continued) Vy-+ Negative Going Threshold V+ = 10V 1.3 v Voltage 38 vt = 5V 0.6 Hysteresis (V;+—V;_) V+ = 10V 23 V += 5V Minimum Logical “1” Output Vottage lo=-10na [ve=rv[ [| 90 ~| =o S| sv Maximum Logical “0” Output Voltage lo = 10 pA ve=tv{[ | to S| oto | Minimum Output Source Current CLKRShorted | v+=10v | 60 | 30 | 30 | ma Maximum Output Sink Current cukRShorted | v+=10v | 50 | 25 | 28 | ma TTL CLOCK INPUT, CLK R PIN (Note 9) Maximum Vy, Logical"O" Inputvotage [|| TCV Minimum Vpi.togicalt” nputvotage | | eo | Td Maximum Leakage Current at CLK R Pin L.ShPinatMidSuppy | 20 | | ssw Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. AC and DC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: Alt voltages are with respect to GND. Note 3: The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter. Note 4: For +5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 280 »Vrms for 1 kHz bandwidth is typically 190 Vrms for both the MF4-50 and the MF4-100. ‘Note &: The specifications for the MF4 have been given for a clock frequency (tc.x) of 250 kHz or less. Above ths clock frequency the cutoff frequency begins to deviate from the specified error band of +0.6% but the filter still maintains its magnitude characteristics. See Application Hints. Note 6: Besides checking the cutoff frequency (f.) and the stopband attenuation at 2 fo, two additional frequencies are used to check the magnitude response of the fitter. The magnitudes are referenced to a DC gain of 0.0 dB. Note 7: For simplicity all the logic levels have been referenced to V- = OV (except for the TTL input logic levels). The logic levels will scale accordingly for + 5V and +2.5V supplies. Note 8: The short circuit source current is measured by forcing the output that is being tested to its maximum positive ‘voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage and then shorting that ‘output to the positive supply. These are worst case conditions. Note 9: The MF4 is operating with symmetrical split supplies and L. Sh is tied to ground. Note 10: Typicals are at 25°C and represent most likely parametric norm. Note 11: Guaranteed to National's Average Outgoing Quality Level {AOOL). Note 12: Guaranteed, but not 100% production tested. These limits are not used to determine outgoing quality levels. Note 13: Human body model; 100 pF discharged through a 1.5 kf resistor. Note 14: When the input voltage (Vin) at any pin exceeds the power supply rails (Vy < V~ or Vin > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. Note 15: Thermal Resistance 1-109

. ly Curren ristics . ice Characte: —_ rforman _ = = = Typical Pe Power Supply ¢ ee _ = y t vs Clock ee . anes et ly Current “CTT TTY sean as sseieens =H Power er uot Voltage 2 Seeeees tt ; Fi berssscoss att a ' aH PT 3 oo rT = Pan Coo E 2 ee “ HO ee a Es Hoe ene Br SneEe = SNe Zs N| | y 38 aA SCN ne | : lene i eo i aC TET 28 ia yA 1B SSeeeurcae i a eo A || g a Ebr | Area “ee 7 = : : l re ; . CLOCK FREQUENCY (kHz) _ vie wo 65 70 — wl 35 40 45 50 ween —_ - — POWER SUPPLY VOLT Negative voltage Swing ee: a ing vs Power ae =" 2 ae a vero rn Vote 2 caeenue é o ea 0! Suppl S : : cs ee i’ ANH rT] 2 oft Cee HH LENSE eae. =H ‘tee aan z NE pai a foun = 250 tt A ‘ tN : StH =. Rona = 2 {| CON - : Ly coe

3 Z| 7 2 Coo KH ra i

as : 5 T= 2s <H : : Hoy tH 5 feu eNe iss = : . E en : ‘ 40 45 50 55 60 65 70 : AAAHHH seuoowews = ! | : ~ . er er ‘Supply vere . a TTT In ae ve Bower Supply Voltage “ FEE rigs row : : vs Power — . af = Th Te Nae Neg: rature Fy ae : . E i # ee 1 . hoo 3 [C= M Coe Ht ii Vv | fe eee | ot] a of i MAt : aie zg Ll = : | E10 SEGGGnE 3 PePEEr “EES i * TAGE Sus | | [| ro « EEE = I: | tH “susessaee - = nen sie -~ g [ : : 415 25 125, - 7 : . fiation . jation TEMPERATURE 20) veiock Prewueney “ ess as vs Cl —— 5. B = = “ ae = Sopa Neeser anes _ Sitti ass ane aL ‘4 ary CON, 4G ‘0 Ee meaerel 2s i th lapeanrd 7 : ae ay isecfcceee o{EBEEESEEE| TONG fine i : ps8 | ~ aft =etcg : Ett | i 2 — * (ec) - i. a i TN + ieee SN ee - L HEH 2 EEE - — ° FREQUENCY (kHz) “oo al = ™ ox reer) 1-110

Typical Performance Characteristles (continues) = foik/fc Deviation DC Gain Deviation DC Gain Deviation as vs Temperature cos vs Power Supply Voltage om vs Power Supply Voltage co Hee Bed +4 a os [TT TT Tae _ ov| yw oot > re

2 He iceta 4% EEE yo

*CETTET Nenad ent LTT TTT ne a «02 COCCEEE NH re on “03 8 -os|_ YT TT TT I or i ~ Ss 8 SB S 1B “OH 1530 55 40 45 8D 85 00 65 70 “M5 1530 35 40 45 50 85 80 85 70 TEMPERATURE (°C) POWER SUPPLY VOLTAGE (8) POWER SUPPLY VOLTAGE (£) DC Gain Deviation DC Gain Deviation vs Temperature vs Temperature [TTT VAL TTT) os FLT TFT ETT rn > ARC ee HEE EEE EE I 3s HA WC S aoe ure- 10 -t H on LT YS 008 T teax = 250k TT PeeCe eee ow PSR oo LTT TT TAR oo

3 TTT 3 OS eee

EEECCerrer (PEERS -aai as _-LLOLT TTT TT om CEE EPs} 3-15 2S 8 125 5-15 8 18 TEMPERATURE (°C) ‘TEMPERATURE (°C) TUH/s064—10 4-111

w : inti 50:1) of the clock frequency supplied to the filter. Internal =| Pin Descriptions ; integrator time constants set the filter's cutoff frequency. (Numbers in ( ) are for 14-pin package.) The resistive element of these integrators is actually a ca- Pin Pin Function pacitor which is “switched” at the clock frequency (for a # Name detailed discussion see Input Impedance Section). Varying 1 CLKIN ACMOS Schmnitt-trigger input to be used the clock frequency changes the value of this resistive ele- (1) with an external CMOS logic level clock. ment and thus the time constant of the integrators. The Also used for self clocking Schmitt-trigger clock-to-cutoff-frequency ratio (fcikfc) is set by the ratio of oscillator (see section 1.1). the input and feedback capacitors in the integrators. The 2. CLKA ATTL logic level clock input when in split higher the clock-to-cutoff-frequency ratio the closer this ap- @) supply operation (+ 2.5V to +7V) with L. Sh proximation is to the theoretical Butterworth response. The tied to system ground. This pin becomes a MF4 is available in fcLk/fe ratios of 50:1 (MF4-50) or 100:1 low impedance output when L. Shis tied to (MF4-100). V—. Also used in conjunction with the CLK 4.1 CLOCK INPUTS meiner feet clocking One rut The MF4 has a Schmitt-trigger inverting buffer which can be si used to construct a simple R/C oscillator. Pin 3 is connect- ignal must nat exceed the supply voltages: aad “ by more than 0.2V. ed i M wen makes Pin 2 3 ow impedance output. The 3 L.Sh Level shift pin; selects the logic threshold oscillator’ frequency Is nominal 6) levels for the clock. When tied to V~ it fe.k = —— oOo (1) enables an internal tri-state buffer stage ACIn [(s2 = v=) ()| between the Schmitt trigger and the internal Voc — Vr+/ \\Wy- clock level shift stage thus enabling the which, is typically CLK IN Schmitt-trigger input and making the 1 CLK R pin a low impedance output. When tok = ——— (1a) the voltage level at this input exceeds 25% 1.69 RC (V+ —V-) + V- the internal tri-state for Voc = 10V. buffer is disabled allowing the CLK R pin to Note that fox is dependent on the buffer’s threshold levels become the clock input for the internal as well as the resistor/capacitor tolerance (see Figure 1). clock level-shift stage. The CLK R threshold Schmitt-trigger threshold voltage levels can change signifi- level is now 2V above the voltage on the L. cantly causing the R/C oscillator’s frequency to vary greatly ‘Sh pin. The CLK R pin will be compatible from part to part. with TTL logic levels when the MF4 is Where accurate cutoff frequency is required, an external operated on split supplies with the L. Sh pin clock can be used to drive the CLK R input of the MF4. This Connected to system ground. input is TTL logic level compatible and also presents a very 5 FILTER The output of the low-pass filter. It will light load to the external clock source (~2 yA). With split (8) OUT typically sink 0.9 mA and source 3 mA and supplies and the level shift (L. Sh) tied to system ground, ‘swing to within 1V of each supply rail. the logic level is about 2V. (See the Pin Description for L. 6 — AGND The analog ground pin. This pin sets the DC Sh). (10) bias level for the filter section and must be tied to the system ground for split supply 1.2 POWER SUPPLY ; operation or to mid-supply for single supply The MF4 can be powered from a single supply or split sup- ‘operation (see section 1.2). When tied to plies. The split supply mode shown in Figure 2 is the most mid-supply this pin should be well flexible and easiest to implement. Supply voltages of +5V bypassed. ‘© + 7 enable the use of mr or eos stock logic levels - se - A ‘igure S resistor-biased to jor single C1) tol nonoranpyecageissviaay. supply operation. In this mode only CMOS clock logic lavels . Power range . can be used, and input signals should be capacitor-coupled Decoupling these pins with 0.1 pF or biased near mid-supply capacitors is highly recommended. ° 8 FILTER The input to the low-pass filter. To minimize 1.3 INPUT IMPEDANCE (14) IN gain errors the source impedance that The MF4 low-pass filter input (FILTER IN) is not a high im- drives this input should be less than 2K (see pedance buffer input. This input is a switched-capacitor re- ‘section 1.3 of the Application Hints). For sistor equivalent, and its effective impedance is inversely single supply operation the input signal proportional to the clock frequency. The equivalent circuit of must be biased to mid-supply or AC coupled the filter's input can be seen in Figure 4. The input capacitor through a capacitor. charges to Vin during the first half of the clock period; during the second half the charge is transferred to the feedback 1.0 MF4 Application Hints capacitor. The total transfer of charge in one clock cycle is The MF4 is a non-inverting unity gain low-pass fourth-order therefore Q = CpVin, and since current is defined as the Butterworth switched-capacitor filter. The switched-capaci- flow of charge per unit time, the average input current be- tor topology makes the cutoff frequency (where the gain comes drops 3.01 dB below the DC gain) a direct ratio (100:1 or lin = Q/T 1-112

1.0 MF4 Application Hints (continuea) =

(where T equals one clock period) or which will become noticeable when the clock frequency ex- CinVin ceeds 250 kHz. The response of the MF4 is still a good lin = > = CinVinfouk approximation of the ideal Butterworth low-pass characteris- \\ T - - tic shown in Figure 5. The equivalent input resistor (Rj,) then can be expressed as Rin = Min = —1 2.0 Designing With The MF4 lin CinfoLk Given any low-pass filter specification, two equations will The input capacitor is 2 pF for the MF4-50 and 1 pF for the come in handy in trying to determine whether the MF4 will MF4-100, so for the MF4-100 do the job. The first equation determines the order of the 1X 1012 4x 1012 1x 1010 low-pass filter requirad to meet a given response specifica- Rin= Ext tion: IcLK fc X 100 fe 0.1mm A and n= 9 [(100-1Amin — 1)/(100.1Amax — 1)] @ Sx 1011 5x 1011 1x 1010 2 log (Fs/fy) Fin = “Tak = Tx 50° = — where n is the order of the filter, Amin is the minimum stop- . . band attenuation (in dB) desired at frequency f,, and Amax is for the MF4-50. The above equation shows that for a given the pasaband ripple or attenuation (in dB) at cutoff frequen- cutoff frequency (f,), the input resistance of the MF4-50 is cy fp. If the result of this equation is greater than 4, more the same as that of the MF4-100. The higher the clock-to- than a single MF4 is required. cutoff-frequency ratio, the greater equivalent input resist- ‘ ance for a given clock frequency. loa entation at any frequency can be found by the fol- This input resistance will form a voltage divider with the — ‘Amex — ot source impedance (Rgource)- Since Rin is inversely propor- Attn (f) = 10 log [1 + (100.1Amax — 1) (f/fp)?"1 dB (3) tional to the cutoff frequency, operation at higher cutoff fre- where n = 4 for the MF4. quencies will be more likely to load the input signal which 2.1 ALOW-PASS DESIGN EXAMPLE would appear as an overall decrease in gain to the output of Suppose the amplitude response specification in Figure 6 is the filter. Since the filter's ideal gain is unity, the overall gain given. Can the MF4 be used? The order of the Bul orth is given by: R approximation will have to be determined using (1): Ay= ATR Amin = 18 dB, Amax = 1.0 dB, fg = 2 kHz, and fy = 1 KHz in * Msource log {(101.8 — 1)/(400.1 — 1)] If the MF4-50 or the MF-100 were set up for a cutoff fre- 1S ee = 8.988 quency of 10 kHz the input impedance would be: 2log(2) 4x 1910 Since n can only take on integer values, n = 4. Therefore Rin = ——— = 1 M2 the MF4 can be used. In general, if n is 4 or less a single 10 kHz MF4 stage can be utilized. In this example with a source impedance of 10K the overall Likewise, the attenuation at f, can be found using (3) with gain, if the MF4 had an ideal gain of 1 or 0 dB, would be: the above values andn = 4: 1Mo2 AY Tok + 1MO 0.99009 or —0.086 dB 18.28 dB Since the maximum overall gain error for the MF4 is This result also meets the design specification given in Fig- | £0.15 dB with Rg < 2k the actual gain error for this case ure 6 again verifying that a single MF4 section will be ade- would be +0.06 dB to —0.24 dB. quate.

1.4 CUTOFF FREQUENCY RANGE Since the MF4's cutoff frequency (f,), which corresponds to

The filter's cutoff frequency (f.) has a lower limit due to Oe nee be calncietet Solve eects leakage currents through the internal switches draining the hare t= tae follows: : 9 eq charge stored on the capacitors. At lower clock frequencies where t = fe as follows: these leakage currents can cause millivolts of error, for ex- k= or 38) — yen ample: e [(100-1Amax = 1) fouk = 100 Hz, lieakage = 1 PA,C = 1 pF = tte [2002 = ye v=—1PA__ tomy torr 4 1 pF (100 Hz) = 1.184 kHz The propagation delay in the logic and the settling time re- where fe = foik/50 or fo. k/100. To implement this exam- quired to acquire a new voltage level on the capacitors limit ple for the MF4-50 the clock frequency will have to be set to the filter's accuracy at high clock frequencies. The ampli- foLk = 50(1.184 kHz) = 59.2 kHz, or for the MF4-100, fcLk tude characteristic on +5V supplies will typically stay flat = 100 (1.184 kHz) = 118.4 kHz. until foLk exceeds 750 kHz and then peak at about 0.5 dB age drops to + 2.5V, a shift in the foik/fe ratio occurs When a steeper stopband attenuation rate is required, two MF4s can be cascaded (Figure 7) yielding an 8th order 1-113

main at 1V/V. The resulting response Is shown in Figure 9. den change in clock frequency. as above, equations 3 and 4 can be used, shown below. worth low-pass filter. obtain the desired frequency response. The design proce- J f the fitter f i.

2 Is '*TeeRc

FIGURE 1. Schmitt Trigger R/C Oscillator

FIGURE 2. Split Supply Operation with CMOS Level Clock (a) and TTL Level Clock (b) FIGURE 3. Single Supply Operation. ANGD Resistor Biased to V+ /2

1 AGND Rye

FIGURE 4. MF4 Filter input

fe/2 + f causes an output signal to appear at f,/2 — f. FIGURE 11. The phenomenon of aliasing in sampied-data systems. An input signal whose