MF4

MF4 NSC | Alldatasheet

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Features

n 8-pin mini-DIP or 14-pin wide-body S.O. n No external components n 5V to 14V supply voltage n Cutoff frequency range of 0.1 Hz to 20 kHz n Cutoff frequency accuracy of± 0.3% typical n Cutoff frequency set by external clock n Separate TTL and CMOS/Schmitt-trigger clock inputs Connection Diagram Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corp. Dual-In-Line Package DS005064-2 Order Number MF4CN-50 See NS Package Number N08E DS005064-1 July 1999 MF4 4th Order Switched Capacitor Butterworth Lowpass Filter © 1999 National Semiconductor Corporation DS005064 www.national.com

Block Diagram (Continued) Pin Descriptions Pin Pin Function # Name

1 CLK IN A CMOS Schmitt-trigger input to be

used with an external CMOS logic level clock. Also used for self clocking Schmitt-trigger oscillator (see section 1.1).

2 CLK R A TTL logic level clock input when in

split supply operation ( ±2.5V to±7V) with L. Sh tied to system ground. This pin becomes a low impedance output when L. Sh is tied to V −. Also used in conjunction with the CLK IN pin for a self clocking Schmitt-trigger oscillator (see section 1.1). The TTL input signal must not exceed the supply voltages by more than 0.2V. 3 L. Sh Level shift pin; selects the logic threshold levels for the clock. When tied to V − it enables an internal tri-state buffer stage between the Schmitt trigger and the internal clock level shift stage thus enabling the CLK IN Schmitt-trigger input and making the CLK R pin a low impedance output. When the voltage level at this input exceeds 25% (V + −V −)+V − the internal tri-state buffer is disabled allowing the CLK R pin to become the clock input for the internal clock level-shift stage. The CLK R threshold level is now 2V above the voltage on the L. Sh pin. The CLK R pin will be compatible with TTL logic levels when the MF4 is operated on split supplies with the L. Sh pin connected to system ground.

5 FILTER

The output of the low-pass filter. It will typically sink 0.9 mA and source 3 mA and swing to within 1V of each supply rail. 6 AGND The analog ground pin. This pin sets the DC bias level for the filter section and must be tied to the system ground for split supply operation or to mid-supply for single supply operation (see section 1.2). When tied to mid-supply this pin should be well bypassed. V +,V − The positive and negative supply pins. The total power supply range is 5V to 14V. Decoupling these pins with 0.1 µF capacitors is highly recommended. Pin Pin Function # Name

8 FILTER

The input to the low-pass filter. To minimize gain errors the source impedance that drives this input should be less than 2K (see section 1.3 of the Application Hints). For single supply operation the input signal must be biased to mid-supply or AC coupled through a capacitor. www.national.com 2

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V +–V −) 14V Voltage At Any Pin V + + 0.2V V− − 0.2V Input Current at Any Pin (Note 14) 5 mA Package Input Current (Note 14) 20 mA Power Dissipation (Note 15) 500 mW Storage Temperature 150˚C ESD Susceptibility (Note 13) 800 V Soldering Information (10 sec.) 260˚C Operating Ratings(Note 2) Temperature Range T min ≤ TA ≤ Tmax MF4CN-50 0˚C ≤ TA≤ 70˚C Supply Voltage (V+–V −) 5 Vt o1 4 V Filter Electrical Characteristics The following specifications apply for fCLK ≤ 250 kHz (Note 5) unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Parameter Conditions Typical Tested Design Unit (Note 10) Limit Limit (Note 11) (Note 12) V+ = +5V, V− = −5V fc, Cutoff Frequency Min 0.1 Hz Range (Note 3) Max 20k Supply Current f clk= 250 kHz 2.5 3.5 3.5 mA Maximum Clock Filter Output V in = 0V Feedthrough 25 mV (Peak-to-Peak) H o, DC Gain R source≤ 2k Ω 0.0 ±0.15 ±0.15 dB fclk/fc, Clock to Cutoff 49.96 49.96 Frequency Ratio ±0.3% ±1% fclk/fc Temperature ±15 ppm/˚C Coefficient Stopband Attenuation (Min) at 2 f DC Offset Voltage −200 mV Minimum Output Swing R −4.5 −4.0 −4.0 V Output Short Circuit Source 50 mA Current (Note 8) Sink 1.5 mA Dynamic Range (Note 4) 80 dB Additional Magnitude f = 6000 Hz −7.57 −7.57 Response Test Points ±0.47 ±0.47 dB (Note 6) f = 4500 Hz −1.44 −1.44 fclk= 250 kHz ±0.12 ±0.12 f= 3000 Hz dB f= 2250 Hz fc Cutoff Frequency min 0.1 Hz Range (Note 3) max 10k Supply Current f clk= 250 kHz 1.5 2.25 2.25 mA Maximum Clock Feedthrough Filter Output V in = 0V 15 mV (Peak-to-Peak) H o, DC Gain R source≤ 2k Ω 0.0 ±0.15 ±0.15 dB fclk/fc, Clock to Cutoff 50.07 50.07 Frequency Ratio ±0.3% ±1.0% fCLK /fC Temperature ±25 ppm/˚C Coefficient www.national.com3

Filter Electrical Characteristics(Continued) The following specifications apply for fCLK ≤ 250 kHz (Note 5) unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Parameter Conditions Typical Tested Design Unit (Note 10) Limit Limit (Note 11) (Note 12) Stopband Attenuation (Min) at 2 f c −25.0 −24.0 −24.0 dB DC Offset Voltage −150 mV Minimum Output Swing R −2.2 −1.7 −1.7 V Output Short Circuit Source 28 mA Current (Note 8) Sink 0.5 mA Dynamic Range (Note 4) 78 dB Additional Magnitude f clk= 250 kHz Response Test Points (Note 6) −7.57 −7.57 dB c = 5 kHz) f = 6000 Hz ±0.47 ±0.47 Magnitude at f = 4500 Hz −1.46 −1.46 dB ±0.12 ±0.12 (fc = 2.5 kHz) f = 3000 Hz Magnitude dB f= 2250 Hz Logic Input-Output Characteristics The following specifications apply for V− = 0V (Note 7) unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Typical Tested Design Parameter Conditions (Note 10) Limit Limit Unit (Note 11) (Note 12) SCHMITT TRIGGER V T+, Positive Going Threshold Min V + = 10V 7.0 6.1 6.1 V Voltage Max 8.9 Min V + = 5V 3.5 3.1 3.1 V Max 4.4 4.4 VT−, Negative Going Threshold Min V + = 10V 3.0 1.3 1.3 V Voltage Max 3.8 3.8 Min V + = 5V 1.5 0.6 0.6 V Max 1.9 1.9 Hysteresis (VT+–V T−) Min V + = 10V 4.0 2.3 2.3 V Max 7.6 7.6 Min V + = 5V 2.0 1.2 1.2 V Max 3.8 3.8 Minimum Logical “1” Output Voltage I 0 = −10 µA V + = 10V 9.0 9.0 V (pin 2) V + = 5V 4.5 4.5 V Maximum Logical “0” Output Voltage I 0 = 10 µA V + = 10V 1.0 1.0 V (pin 2) V + = 5V 0.5 0.5 V Minimum Output Source Current CLK R Shorted V + = 10V 6.0 3.0 3.0 mA (pin 2) to Ground V + = 5V 1.5 0.75 0.75 mA Maximum Output Sink Current CLK R Shorted V + = 10V 5.0 2.5 2.5 mA (pin 2) to V + V+ = 5V 1.3 0.65 0.65 mA www.national.com 4

Logic Input-Output Characteristics(Continued) The following specifications apply for V− = 0V (Note 7) unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA = TJ = 25˚C. Typical Tested Design Parameter Conditions (Note 10) Limit Limit Unit (Note 11) (Note 12) TTL CLOCK INPUT, CLK R PIN (Note 9) Maximum V IL, Logical “0” Input Voltage 0.8 V Minimum VIH, Logical “1” Input Voltage 2.0 V Maximum Leakage Current at CLK R Pin L. Sh Pin at Mid-Supply 2.0 µA Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. AC and DC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2:All voltages are with respect to GND. Note 3:The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter. Note 4:For ±5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 280 µVrms for Note 5:The specifications for the MF4 have been given for a clock frequency (fCLK ) of 250 kHz or less. Above the clock frequency the cutoff frequency begins to deviate from the specified error band of±0.6% but the filter still maintains its magnitude characteristics. See Application Hints. Note 6:Besides checking the cutoff frequency (fc) and the stopband attenuation at 2 fc, two additional frequencies are used to check the magnitude response of the filter. The magnitudes are referenced to a DC gain of 0.0 dB. Note 7:For simplicity all the logic levels have been referenced to V− = 0V (except for the TTL input logic levels). The logic levels will scale accordingly for±5V and ±2.5V supplies. Note 8:The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage and then shorting that output to the positive supply. These are worst case conditions. Note 9:The MF4 is operating with symmetrical split supplies and L. Sh is tied to ground. Note 10:Typicals are at 25˚C and represent most likely parametric norm. Note 11:Guaranteed to National’s Average Outgoing Quality Level (AOQL). Note 12:Guaranteed, but not 100% production tested. These limits are not used to determine outgoing quality levels. Note 13:Human body model; 100 pF discharged through a 1.5 kΩ resistor. Note 14:When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V−or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5m A current limit to four. Note 15:Thermal Resistance θJA (Junction to Ambient) N Package: 105˚C/W. www.national.com5

Typical Performance Characteristics Power Supply Current vs Power Supply Voltage DS005064-26 Power Supply Current vs Clock Frequency DS005064-27 Power Supply Current vs Temperature DS005064-28 Positive Voltage Swing vs Power Supply Voltage DS005064-29 Negative Voltage Swing vs Power Supply Voltage DS005064-30 Positive Voltage Swing vs Temperature DS005064-31 Negative Voltage Swing vs Temperature DS005064-32 fCLK /fc Deviation vs Power Supply Voltage DS005064-34 fCLK /fc Deviation vs Clock Frequency DS005064-36 www.national.com 6

1.0 MF4 Application Hints

CLK /fc ratios of 50:1 (MF4-50).

1.1 CLOCK INPUTS

as well as the resistor/capacitor tolerance (seeFigure 1). logic level is about 2V. (See the Pin Description for L. Sh).

1.2 POWER SUPPLY

1.3 INPUT IMPEDANCE

Figure 5. The input capacitor equivalent input resistance for a given clock frequency.

1.0 MF4 Application Hints(Continued)

If the MF were set up for a cutoff frequency of 10 kHz the in- put impedance would be: In this example with a source impedance of 10K the overall gain, if the MF4 had an ideal gain of 1 or 0 dB, would be: Since the maximum overall gain error for the MF4 is ±0.15 dB with Rs ≤ 2k Ω the actual gain error for this case would be +0.06 dB to −0.24 dB.

1.4 CUTOFF FREQUENCY RANGE

The filter’s cutoff frequency (fc) has a lower limit due to leak- age currents through the internal switches draining the charge stored on the capacitors. At lower clock frequencies these leakage currents can cause millivolts of error, for ex- ample: The propagation delay in the logic and the settling time re- quired to acquire a new voltage level on the capacitors limit the filter’s accuracy at high clock frequencies. The amplitude characteristic on ±5V supplies will typically stay flat until fCLK exceeds 750 kHz and then peak at about 0.5 dB at the cor- ner frequency with a 1 MHz clock. As supply voltage drops to ± 2.5V, a shift in the fCLK /fc ratio occurs which will become noticeable when the clock frequency exceeds 250 kHz. The response of the MF4 is still a good approximation of the ideal Butterworth low-pass characteristic shown in Figures 6, 7.

2.0 Designing With The MF4

Given any low-pass filter specification, two equations will come in handy in trying to determine whether the MF4 will do the job. The first equation determines the order of the low-pass filter required to meet a given response specifica- tion: (3) where n is the order of the filter, Amin is the minimum stop- band attenuation (in dB) desired at frequency fs, and Amax is the passband ripple or attenuation (in dB) at cutoff frequency f b. If the result of this equation is greater than 4, more than a single MF4 is required. The attenuation at any frequency can be found by the follow- ing equation: Attn (f) = 10 log [1 + (100.1Amax − 1) (f/fb)2n] dB (4) where n= 4 for the MF4.

2.1 A LOW-PASS DESIGN EXAMPLE

Suppose the amplitude response specification inFigure 8is given. Can the MF4 be used? The order of the Butterworth approximation will have to be determined using Equation (1): Since n can only take on integer values, n= 4. Therefore the MF4 can be used. In general, if n is 4 or less a single MF4 stage can be utilized. Likewise, the attenuation at f s can be found usingEquation (4)with the above values and n= 4: Attn (2 kHz)= 10 log [1 + 100.1 − 1) (2 kHz/1 kHz)8]= 18.28 dB This result also meets the design specification given inFig- ure 8again verifying that a single MF4 section will be ad- equate. Since the MF4’s cutoff frequency (fc), which corresponds to a gain attenuation of −3.01 dB, was not specified in this ex- ample, it needs to be calculated. Solving Equation (4)where f= fc as follows: where fc = fCLK /50. To implement this example for the MF4-50 the clock frequency will have to be set to fCLK = 50(1.184 kHz)= 59.2 kHz, or for the MF4-100, fCLK = 100 (1.184 kHz)= 118.4 kHz.

2.2 CASCADING MF4s

When a steeper stopband attenuation rate is required, two MF4s can be cascaded (Figure 9) yielding an 8th order slope of 48 dB per octave. Because the MF4 is a Butterworth filter and therefore has no ripple in its passband when MF4s are cascaded, the resulting filter also has no ripple in its pass- band. Likewise the DC and passband gains will remain at 1V/V. The resulting response is shown in Figure 10,Figure 11. In determining whether the cascaded MF4s will yield a filter that will meet a particular amplitude response specification, as above, Equations (5), (6)can be used, shown below. (5) (6) where n= 4 (the order of each filter). Equation (5)will determine whether the order of the filter is adequate (n≤ 4) whileEquation (6)can determine the actual stopband attenuation and cutoff frequency (fc) necessary to obtain the desired frequency response. The design proce- dure would be identical to the one shown in section 2.0. www.national.com 8

2.3 CHANGING CLOCK FREQUENCY

2.4 ALIASING CONSIDERATIONS

be attenuated at least to the filter’s residual noise level. FIGURE 1. Schmitt Trigger R/C Oscillator FIGURE 2. Split Supply Operation with CMOS Level Clock

2.0 Designing With The MF4(Continued)

FIGURE 3. Split Supply Operation with TTL Level Clock FIGURE 4. Single Supply Operation. ANGD Resistor Biased to V+/2 FIGURE 5. MF4 Filter Input

FIGURE 6. MF4-50 Amplitude Response with±5V FIGURE 7. MF4-50 Amplitude Response with±2.5V FIGURE 8. Design Example Magnitude Response Specification where the Response of

FIGURE 9. Cascading Two MF4s FIGURE 10. One MF4-50 FIGURE 11. Phase Response FIGURE 12. MF4-50 Abrupt Clock Frequency Change FIGURE 13. MF4-50 Input Step Response

at fc/2 + f causes an output signal to appear at fc/ 2−f . FIGURE 14. The phenomenon of aliasing in sampled-data systems. An input signal whose at a frequency lower than one-half the sampling frequency. In the MF4, fs = fCLK .

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