MF201

SN65MLVD201_07 TI | Alldatasheet

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D RE R A B LOGIC DIAGRAM (POSITIVE LOGIC) DE D RE R A B 9 Y Z SN65ML VD203, SN65ML VD207SN65ML VD201, SN65MLVD206 SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 www.ti.com MULTIPOINT-LVDS LINE DRIVER AND RECEIVER Low-Power High-Speed Short-Reach Low-Voltage Differential 30- Ω to 55- Ω Line Alternative to TIA/EIA-485 Drivers and Receivers for Signaling Rates (1) Backplane or Cabled Multipoint Data and Up to 200 Mbps Clock Transmission Type-1 Receivers Incorporate mV of Cellular Base Stations Hysteresis Central-Office Switches Type-2 Receivers Provide an Offset (100 mV) Network Switches and Routers Threshold to Detect Open-Circuit and Idle-Bus Conditions Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange The SN65MLVD201, 203, 206, and 207 are multipoint-low-voltage differential (M-LVDS) line Controlled Driver Output Voltage Transition drivers and receivers, which are optimized to operate Times for Improved Signal Quality at signaling rates up to 200 Mbps. All parts comply V to 3.4 V Common-Mode Voltage Range with the multipoint low-voltage differential signaling Allows Data Transfer With V of Ground Noise (M-LVDS) standard TIA/EIA-899. These circuits are similar to their TIA/EIA-644 standard compliant LVDS Bus Pins High Impedance When Disabled or counterparts, with added V CC 1.5 V multipoint applications. The driver output has been 100-Mbps Devices Available (SN65MLVD200A, designed to support multipoint buses presenting 202A, 204A, 205A) loads as low as Ω and incorporates controlled M-LVDS Bus Power Up/Down Glitch Free transition times to allow for stubs off of the backbone transmission line. The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per These devices have Type-1 and Type-2 receivers second). that detect the bus state with as little as mV of differential input voltage over a common-mode voltage range of V to 3.4 The Type-1 receivers exhibit mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other faults conditions. The devices are characterized for operation from C to Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2002 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com PACKAGE DISSIPATION RATINGS ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER (1) FOOTPRINT RECEIVER TYPE PACKAGE MARKING SN65MLVD201D SN75176 Type MF201 SM65MLVD203D SN75ALS180 Type MLVD203 SN65MLVD206D SN75176 Type MF206 SM65MLVD207D SN75ALS180 Type MLVD207 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com T A C DERATING FACTOR T A C PACKAGE POWER RATING ABOVE T A C POWER RATING D(8) 725 mW 5.8 mW/ C 377 mW D(14) 950 mW 7.6 mW/ C 494 mw over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Supply voltage range (2) V CC 0.5 V to V DE, RE 0.5 V to V Input voltage range B (201, 206) 1.8 V to V B (203, 207) V to V R 0.3 V to V Output voltage range or B 1.8 V to V and Z kV Human Body Model (3) Electrostatic discharge All pins kV Charged-Device Model (4) All pins 1500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range C to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. MIN NOM MAX UNIT V CC Supply voltage 3.3 3.6 V V IH High-level input voltage V CC V V IL Low-level input voltage GND 0.8 V Voltage at any bus terminal V A V V Y or V Z 1.4 3.8 V ID Magnitude of differential input voltage 0.05 V CC V T A Operating free-air temperature C Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com DEVICE ELECTRICAL CHARACTERISTICS DRIVER ELECTRICAL CHARACTERISTICS SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Driver only RE and DE at V CC R L Ω All others open Both disabled RE at V CC DE at R L No Load, All others open I CC Supply current mA Both enabled RE at DE at V CC R L Ω All others open Receiver only RE at DE at R L Ω All others open (1) All typical values are at C and with a 3.3-V supply voltage. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX UNIT AB or Differential output voltage magnitude 480 650 mV YZ See Figure Δ AB or Change in differential output voltage magnitude mV Δ YZ between logic states V OS(SS) Steady-state common-mode output voltage 0.8 1.2 V Change in steady-state common-mode output Δ V OS(SS) See Figure mV voltage between logic states V OS(PP) Peak-to-peak common-mode output voltage 150 mV V Y(OC) or Maximum steady-state open-circuit output 2.4 V V A(OC) voltage See Figure V Z(OC) or Maximum steady-state open-circuit output 2.4 V V B(OC) voltage V P(H) Voltage overshoot, low-to-high level output 1.2 V SS V See Figure V P(L) Voltage overshoot, high-to-low level output 0.2 V SS V I IH High-level input current (D, DE) V IH V µ A I IL Low-level input current (D, DE) V IL 0.8 V µ A JI OS J Differential short-circuit output current magnitude See Figure mA 1.4 V V Y or V Z 3.8 I OZ High-impedance state output current (driver only) µ A Other output 1.2 V 1.4 V V Y or V Z 3.8 I O(OFF) Power-off output current Other output 1.2 µ A V V CC 1.5 V V I 0.4 sin(30E6 π 0.5 (3) C Y or C Z Output capacitance pF Other input at 1.2 Driver disabled V AB 0.4 sin(30E6 π (3) C YZ Differential output capacitance 2.5 pF Driver disabled C Y/Z Output capacitance balance, Y Z 0.99 1.01 (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) All typical values are at C and with a 3.3-V supply voltage. (3) HP4194A impedance analyzer (or equivalent) Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 over recommended operating conditions unless otherwise noted (1) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Type V IT+ Positive-going differential input voltage threshold mV Type 150 Type See Figure and Table and V IT- Negative-going differential input voltage threshold mV Table Type Type V HYS Differential input voltage hysteresis, IT+ V IT mV Type V OH High-level output voltage I OH mA 2.4 V V OL Low-level output voltage I OL mA 0.4 V I IH High-level input current RE V IH V µ A I IL Low-level input current RE V IL 0.8 V µ A I OZ High-impedance output current V O V or 3.6 V µ A V I 0.4 sin(30E6 π 0.5 (2) C A or C B Input capacitance pF Other input at 1.2 V C AB Differential input capacitance V AB 0.4 sin(30E6 π V (2) 2.5 pF C A/B Input capacitance balance, C B 0.99 1.01 (1) All typical values are at C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS DRIVER SWITCHING CHARACTERISTICS SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT V A 3.8 V B 1.2 Receiver or transceiver with driver I A V A V or 2.4 V B 1.2 V µ A disabled input current V A 1.4 V B 1.2 V V B 3.8 V A 1.2 V Receiver or transceiver with driver I B V B V or 2.4 V A 1.2 V µ A disabled input current V B 1.4 V A 1.2 V Receiver or transceiver with driver I AB disabled differential input current V A V B 1.4 V A 3.8 V µ A A I B V A 3.8 V B 1.2 V V CC 1.5 V Receiver or transceiver power-off I A(OFF) V A V or 2.4 V B 1.2 V V CC 1.5 V µ A input current V A 1.4 V B 1.2 V V CC 1.5 V V B 3.8 V A 1.2 V V CC 1.5 V Receiver or transceiver power-off I B(OFF) V B V or 2.4 V A 1.2 V V CC 1.5 V µ A input current V B 1.4 V A 1.2 V V CC 1.5 V Receiver input or transceiver I AB(OFF) power-off differential input current V A V B V V CC 1.5 1.4 V A 3.8 V µ A A I B Transceiver with driver disabled input C A V A 0.4 sin (30E6 π 0.5V (2) V B 1.2 V pF capacitance Transceiver with driver disabled input C B V B 0.4 sin (30E6 π 0.5 V (2) V A 1.2 V pF capacitance Transceiver with driver disabled C AB V AB 0.4 sin (30E6 π t)V (2) pF differential input capacitance Transceiver with driver disabled input C A/B 0.99 1.01 capacitance balance, A B (1) All typical values are at C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT t PLH Propagation delay time, low-to-high-level output 1.5 2.4 ns t PHL Propagation delay time, high-to-low-level output 1.5 2.4 ns t r Differential output signal rise time 1.6 ns See Figure t f Differential output signal fall time 1.6 ns t sk(p) Pulse skew (|t PHL t PLH 100 ps t sk(pp) Part-to-part skew (2) ns t jit(per) Period jitter, rms standard deviation) (3) 100 MHz clock input (4) ps t jit(pp) Peak-to-peak jitter (3) (5) 200 Mbps PRBS input (6) 130 ps t PHZ Disable time, high-level-to-high-impedance output ns t PLZ Disable time, low-level-to-high-impedance output ns See Figure t PZH Enable time, high-impedance-to-high-level output ns t PZL Enable time, high-impedance-to-low-level output ns (1) All typical values are at C and with a 3.3-V supply voltage. (2) t sk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (4) t r t f 0.5 ns (10% to 90%), measured over k samples. (5) Peak-to-peak jitter includes jitter due to pulse skew sk(p) (6) t r t f 0.5 ns (10% to 90%), measured over 100 k samples. Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com RECEIVER SWITCHING CHARACTERISTICS SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT t pLH Propagation delay time, low-to-high-level output ns t pHL Propagation delay time, high-to-low-level output ns t r Output signal rise time 2.3 ns t f Output signal fall time C L pF, See Figure 2.3 ns Type 100 300 ps t sk(p) Pulse skew (|t pHL t pLH Type 300 500 ps t sk(pp) Part-to-part skew (2) ns t jit(per) Period jitter, rms standard deviation) (3) 100 MHz clock input (4) ps Type 300 700 ps t jit(pp) Peak-to-peak jitter (3) (5) 200 Mbps PRBS input (6) Type 450 800 ps t pHZ Disable time, high-level-to-high-impedance output ns t pLZ Disable time, low-level-to-high-impedance output ns See Figure t pZH Enable time, high-impedance-to-high-level output ns t pZL Enable time, high-impedance-to-low-level output ns (1) All typical values are at C and with a 3.3-V supply voltage. (2) t sk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (4) V ID 200 mV pp (LVD201, 203), V ID 400 mV pp (LVD206, 207), V cm t r t f 0.5 ns (10% to 90%), measured over k samples. (5) Peak-to-peak jitter includes jitter due to pulse skew sk(p) (6) V ID 200 mV pp (LVD201, 203), V ID 400 mV pp (LVD206, 207), V cm t r t f 0.5 ns (10% to 90%), measured over 100 k samples. Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com PARAMETER MEASUREMENT INFORMATION VAB or VYZ A/Y B/Z IA or IY VB or VZ VA or VY VOS VA + VB VI D VCC VY + VZ 2or IB or IZ II VAB or VYZ 49.9 W 3.32 kW 3.32 kW + -1 V ≤ Vtest ≤ 3.4 V A/Y B/Z D VOS 24.9 W A/Y 2.5 pF VOS(PP) VOS(SS) VOS ≈/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr1.3 V B/Z A/Y ≈/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr0.7 V B/Z D 24.9 W 1 pF 1 pF VTest A/Y B/Z IOS

0 V or VCC

-1 V or 3.4 V SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 Figure Driver Voltage and Current Definitions All resistors are tolerance. Figure Differential Output Voltage Test Circuit All input pulses are supplied by a generator having the following characteristics: t r or t f ns, pulse frequency 500 kHz, duty cycle 5%. C1, and include instrumentation and fixture capacitance within cm of the D.U.T. and are 20%. and are metal film, surface mount, 1%, and located within cm of the D.U.T. The measurement of V OS(PP) is made on test equipment with a dB bandwidth of at least GHz. Figure Test Circuit and Definitions for the Driver Common-Mode Output Voltage Figure Driver Short-Circuit Test Circuit Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com Output A/Y Output tpLH tpHL Input 0.5 pF B/Z D 0 V 0.9V V 0 V tf tr VCC VCC /2 0 V SS SS0 V 0.1VSS SS 1 pF 1 pF VP(H) VP(L) 50 Ω A/Y B/Z 24.9 Ω tpZH tpHZ tpZL tpLZ VCC VCC /2 0 V ∼ 0.6 V 0.1 V 0 V ∼ -0.6 V 0 V -0.1 V DE Output With D at VCC Output0 V or VCC DE Output With D at 0 V 1 pF 24.9 Ω 0.5 pF 1 pF D 2.5 pF SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) All input pulses are supplied by a generator having the following characteristics: t r or t f ns, frequency 500 kHz, duty cycle 5%. C1, C2, and include instrumentation and fixture capacitance within cm of the D.U.T. and are 20%. is a metal film, surface mount, and tolerance and located within cm of the D.U.T. The measurement is made on test equipment with a dB bandwidth of at least GHz. Figure Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal All input pulses are supplied by a generator having the following characteristics: t r or t f ns, frequency 500 kHz, duty cycle 5%. C1, C2, C3, and includes instrumentation and fixture capacitance within cm of the D.U.T. and are 20%. and are metal film, surface mount, and tolerance and located within cm of the D.U.T. The measurement is made on test equipment with a dB bandwidth of at least GHz. Figure Driver Enable and Disable Time Circuit and Definitions Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com A/Y B/Z 1.62 kW , ±1%VA , VB , VY or VZ tc(n) 1/f0 0 V 0 V Period Jitter

0 V Diff

tjit(per) =  tc(n) -1/f0 tjit(pp) 0 V VCC VCC /2 0 V VA -VB or VY -VZ VA -VB or VY -VZ (VA + VB )/2 IO R VCM VO VID VA IA A B IB VB SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure Maximum Steady State Output Voltage All input pulses are supplied by an Agilent 8304A Stimulus System. The measurement is made on a TEK TDS6604 running TDSJIT3 application software Period jitter is measured using a 100 MHz duty cycle clock input. Peak-to-peak jitter is measured using a 200Mbps PRBS input. Figure Driver Jitter Measurement Waveforms Figure Receiver Voltage and Current Definitions Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com 1.2 V 1.0 V tpLH 0.2 V -0.2 V VA VB VID 90% VOH VOL tpHL 10% tf tr VO VCC /2 VO VID VB VA C L 0 V 15 pF SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 Table Type-1 Receiver Input Threshold Test Voltages APPLIED RESULTING DIFFERENTIAL RESULTING COMMON- RECEIVER VOLTAGES INPUT VOLTAGE MODE INPUT VOLTAGE OUTPUT (1) V IA V IB V ID V IC 2.400 0.000 2.400 1.200 H 0.000 2.400 2.400 1.200 L 3.800 3.750 0.050 3.775 H 3.750 3.800 0.050 3.775 L 1.350 1.400 0.050 1.375 H 1.400 1.350 0.050 1.375 L (1) H high level, L low level, output state assumes receiver is enabled RE Table Type-2 Receiver Input Threshold Test Voltages APPLIED RESULTING DIFFERENTIAL RESULTING COMMON- RECEIVER VOLTAGES INPUT VOLTAGE MODE INPUT VOLTAGE OUTPUT (1) V IA V IB V ID V IC 2.400 0.000 2.400 1.200 H 0.000 2.400 2.400 1.200 L 3.800 3.650 0.150 3.725 H 3.800 3.750 0.050 3.775 L 1.250 1.400 0.150 1.325 H 1.350 1.400 0.050 1.375 L (1) H high level, L low level, output state assumes receiver is enabled RE All input pulses are supplied by a generator having the following characteristics: t r or t f ns, frequency MHz, duty cycle 5%. C L is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within cm of the D.U.T. The measurement is made on test equipment with a dB bandwidth of at least GHz. Figure 10. Receiver Timing Test Circuit and Waveforms Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com 15 pF tpZL tpLZ VOL VOL +0.5 V VO R L 499 Ω + VTEST B A RE 1.2 V Inputs VCC 1 V VCC VCC /2 0 V VCC VCC /2 VTEST A RE R 0 V 1.4 VA tpZH tpHZ 0 V VOH -0.5 V VCC VCC /2 0 V VOH VCC /2 RE VO R Output VTEST C L SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 All input pulses are supplied by a generator having the following characteristics: t r or t f ns, frequency 500 kHz, duty cycle 5%. R L is tolerance, metal film, surface mount, and located within cm of the D.U.T. R L is tolerance, metal film, surface mount, and located within cm of the D.U.T. C L is the instrumentation and fixture capacitance within cm of the DUT and 20%. Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com tc(n) 1/f0 Period Jitter Peak to Peak Jitter 1/f0 PRBS INPUT OUTPUT CLOCK INPUT IDEAL OUTPUT ACTUAL OUTPUT tjit(per) =  tc(n) -1/f0 tjit(pp) VA -VB INPUTS VA -VB

0.2 V - Type 1

0.4 V - Type 2

SN65ML VD203D (Marked as MLVD203) SN65ML VD207D (Marked as MLVD207) (TOP VIEW) NC R RE DE D GND GND V CC VCC A B Z Y NC NC - No internal connection R RE DE D VCC B A GND SN65ML VD201D (Marked as MF201) SN65ML VD206D (Marked as MF206) (TOP VIEW) SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 All input pulses are supplied by an Agilent 8304A Stimulus System. The measurement is made on a TEK TDS6604 running TDSJIT3 application software Period jitter is measured using a 100 MHz duty cycle clock input. Peak-to-peak jitter is measured using a 200 Mbps PRBS input. Figure 12. Receiver Jitter Measurement Waveforms Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com DEVICE FUNCTION TABLES INPUTS OUTPUT VID = VA - VB L H -50 mV < VID < 50 mV L ? VID ≤ -50 mV L L X H Z TYPE-1 RECEIVER (201, 203) VID ≥ 50 mV Open Circuit L RE R TYPE-2 RECEIVER (206, 207) H = high level, L = low level, Z = high impedance, X = Don't care, ? = indeterminate INPUT OUTPUTS L H OPEN X X DRIVER D DE A OR Y H H H OPEN L L H L Z Z H L H Z Z ENABLE B OR Z X Open Z INPUTS OUTPUT VID = VA - VB L H 50 mV < VID < 150 mV L ? VID ≤ 50 mV L L X H Z VID ≥ 150 mV Open Circuit L RE L R X Open Z EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS 360 kΩ 400 Ω VCC DRIVER INPUT AND DRIVER ENABLE D or DE 7 V 400 Ω VCC RE 7 V RECEIVER ENABLE VCC 7 V 10 Ω 10 Ω RECEIVER OUTPUT 360 kΩ DRIVER OUTPUT A/Y or B/Z R VCC 200 kΩ 250 kΩ 200 kΩ 250 kΩ 100 kΩ100 kΩ VCC RECEIVER INPUT BA SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com TYPICAL CHARACTERISTICS −50 10 70 90 I − Supply Current − mACC −30 30 TA − Free-Air Temperature −/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr°C −10 50 Receiver VID = 250 mV VIC = 1 V Receiver Driver VCC = 3.3 V TA = 25°C f = 100 MHz 10 50 90 110 I f − Frequency − MHz − Supply Current − mACC 30 70 VCC = 3.3 V TA = 25°C Receiver VID = 250 mV VIC = 1 V Receiver Driver 0 1 2 4 − Receiver Low Level Output Current − mA VOL − Low Level Output Voltage −/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrV IOL VCC = 3.6 V VCC = 3.3 V VCC = 3.0 V TA = 25°C −90 −60 −50 −40 −30 −20 0 1 2 4 − Receiver High Level Output Current − mA VOH − High Level Output Voltage −/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrV IOH −80 −70 VCC = 3.0 V −10 VCC = 3.6 V VCC = 3.3 V TA = 25°C SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 SUPPLY CURRENT SUPPLY CURRENT vs vs FREQUENCY FREE-AIR TEMPERATURE Figure 13. Figure 14. RECEIVER LOW-LEVEL OUTPUT CURRENT RECEIVER HIGH-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE Figure 15. Figure 16. Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com 1.2 1.4 1.6 1.8 −50 10 50 90 Driver Propagation Delay − ns TA − Free-Air Temperature −/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr°C −30 −10 30 70 VCC = 3.3 V f = 1 MHz tpHL tpLH 0.4 0.8 1.2 1.6 0 4 6 12 Differential Output Voltage − V IO − Output Current −/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrmA 2 8 VCC = 3.3 V TA = 25°C 10 50 90 110 f − Frequency − MHz Added Driver Cycle-To-Cycle Jitter − pa 30 70 VCC = 3.3 V TA = 25°C Input = Clock −50 10 50 90 Receiver Propagation Delay − ns TA − Free-Air Temperature −/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr°C −30 −10 30 70 tpLH VCC = 3.3 V VID = 250 mV VIC = 1 V f = 1 MHz tpHL SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL OUTPUT VOLTAGE DRIVER PROPAGATION DELAY vs vs OUTPUT CURRENT FREE-AIR TEMPERATURE Figure 17. Figure 18. ADDED DRIVER CYCLE-TO-CYCLE RECEIVER PROPAGATION DELAY JITTER (PEAK) vs vs FREE-AIR TEMPERATURE FREQUENCY Figure 19. Figure 20. Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com 25 105 185 225 Data Rate − Mbps Added Driver Peak-To-Peak Jitter − ps 65 145 VCC = 3.3 V TA = 25°C Input = PRBS 215−1 −50 −10 30 50 Added Driver Peak-To-Peak Jitter − ps −30 10 TA − Free-Air Temperature −/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr°C 70 90 VCC = 3.3 V TA = 25°C Input = PRBS 215−1 f = 200 Mbps 160 240 320 0 60 120 150 Added Receiver Peak-To-Peak Jitter − ps 30 90 400 180 210 VCC = 3.3 V VID = 250 mV TA = 25°C Pattern = 215−1 Data Rate − Mbps 10 50 90 110 f − Frequency − MHz Added Receiver Cycle-To-Cycle Jitter − ps 30 70 VCC = 3.3 V VID = 250 mV TA = 25°C VIC = 3.0 V VIC = 1 V VIC = −0.5 V SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) ADDED DRIVER PEAK-TO-PEAK JITTER ADDED DRIVER PEAK-TO-PEAK JITTER vs vs DATA RATE FREE-AIR TEMPERATURE Figure 21. Figure 22. ADDED RECEIVER CYCLE-TO-CYCLE JITTER ADDED RERCEIVER PEAK-TO-PEAK JITTER vs vs FREQUENCY FREE-AIR TEMPERATURE Figure 23. Figure 24. Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com Horizontal Scale = 1 ns/div Vertical Scale = 175 mV/div 160 240 320 400 −50 10 50 90 Added Receiver Peak-To-Peak Jitter − ps TA − Free-Air Temperature −/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr°C −30 −10 30 70 VCC = 3.3 V VID = 250 mV VIC =1 V f =200 Mbps Pattern = 215−1 Horizontal Scale = 1 ns/div Vertical Scale = 400 mV/div SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) SN65MLVD201 DRIVER OUTPUT ADDED RECEIVER PEAK-TO-PEAK JITTER EYE PATTERN vs FREE-AIR TEMPERATURE 200 Mbps, PRBS, R L Ω Figure 25. Figure 26. SN65MLVD201 RECEIVER OUTPUT EYE PATTERN 200 Mbps, PRBS, R L Ω Figure 27. Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com APPLICATION INFORMATION Receiver Input Threshold (Failsafe) -100 -50 100 150

200 Type 1

Differential Input Voltage - mVVID SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 The MLVD standard defines a type and type receiver. Type receivers include no provisions for failsafe and have their differential input voltage thresholds near zero volts. Type receivers have their differential input voltage thresholds offset from zero volts to detect the absence of a voltage difference. The impact to receiver output by the offset input can be seen in Table and Figure Table Receiver Input Voltage Threshold Requirements RECEIVER TYPE OUTPUT LOW OUTPUT HIGH Type 2.4 V V ID 0.05 V 0.05 V V ID 2.4 V Type 2.4 V V ID 0.05 V 0.15 V V ID 2.4 V Figure 28. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region Submit Documentation Feedback Copyright 2002 2007, Texas Instruments Incorporated Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

www.ti.com LIVE INSERTION/GLITCH-FREE POWER UP/DOWN SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207 SLLS558C DECEMBER 2002 REVISED JANUARY 2007 The SN65MLVD201/203/206/207 family of products offered by Texas Instruments provides a glitch-free powerup/down feature that prevents the M-LVDS outputs of the device from turning on during a powerup or powerdown event. This is especially important in live insertion applications, when a device is physically connected to an M-LVDS multipoint bus and VCC is ramping. While the M-LVDS interface for these devices is glitch free on powerup/down, the receiver output structure is not. Figure shows the performance of the receiver output pin, R (CHANNEL 2), as Vcc (CHANNEL is ramped. Figure 29. M-LVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL The glitch on the R pin is independent of the RE voltage. Any complications or issues from this glitch are easily resolved in power sequencing or system requirements that suspend operation until VCC has reached a steady state value. Copyright 2002 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65MLVD201 SN65MLVD203 SN65MLVD206 SN65MLVD207

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN65MLVD201D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD201DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD201DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD201DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD203D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD203DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD203DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD203DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD206D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD206DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD206DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD206DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD207D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD207DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD207DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65MLVD207DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) PACKAGE OPTION ADDENDUM www.ti.com 7-Jan-2008 Addendum-Page 1

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 7-Jan-2008 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65MLVD201DR SOIC D 8 2500 340.5 338.1 20.6 SN65MLVD203DR SOIC D 14 2500 333.2 345.9 28.6 SN65MLVD206DR SOIC D 8 2500 340.5 338.1 20.6 SN65MLVD207DR SOIC D 14 2500 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 2

(TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for design. Customers are responsible for their products and components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony RF/IF and ZigBee Solutions www.ti.com/lprf Video Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2008, Texas Instruments Incorporated

Summary

MULTIPOINT-LVDS LINE DRIVER AND RECEIVER

Description