MF10CCWM/NOPB

MF10-N_17 TI1 | Alldatasheet

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 MF10-NUniversalMonolithicDualSwitchedCapacitorFilter Check forSamples: MF10-N 1FEATURES DESCRIPTION The MF10-N consistsof2 independentand extremely• Easy toUse easy to use, generalpurpose CMOS activefilter• Clock toCenterFrequency RatioAccuracy buildingblocks.Each block,togetherwithan external±0.6% clockand 3 to 4 resistors,can produce various2nd

• FilterCutoffFrequency StabilityDirectly order functions.Each buildingblock has 3 output pins.One oftheoutputscan be configuredtoperformDependent on ExternalClock Quality eitheran allpass,highpassor a notch function;the• Low SensitivitytoExternalComponent remaining 2 output pins perform lowpass andVariation bandpass functions.The center frequencyof the
• SeparateHighpass (orNotch or Allpass), lowpass and bandpass 2nd orderfunctionscan be Bandpass, Lowpass Outputs eitherdirectlydependent on the clockfrequency,or they can depend on both clock frequency and• fO × Q Range up to200 kHz externalresistorratios.The centerfrequencyof the• Operationup to30 kHz notchand allpassfunctionsisdirectlydependent on
• 20-pin0.3″ Wide PDIP Package the clock frequency,while the highpass center frequencydepends on both resistorratioand clock.• 20-pinSurfaceMount (SOIC)Wide-Body Up to 4th order functionscan be performed byPackage cascadingthe two 2nd orderbuildingblocksof the MF10-N; higher than 4th order functionscan be obtainedby cascadingMF10-N packages.Any ofthe classicalfilterconfigurations(such as Butterworth, Bessel,Cauer and Chebyshev)can be formed. For pin-compatibledevicewithimprovedperformance refertoLMF100 datasheet. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com System Block Diagram Package in20 pinmolded widebody SOIC and 20 pinPDIP. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage(V+ − V−) 14V V+ + 0.3V VoltageatAny Pin V− − 0.3V InputCurrentatAny Pin(3) 5 mA Package InputCurrent(3) 20 mA Power Dissipation(4) 500 mW StorageTemperature 150°C ESD Susceptability(5) 2000V SolderingInformation N Package:10 sec 260°C Vapor Phase (60Sec.) 215°C Infrared(15Sec.) 220°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.DC and AC electricalspecificationsdo not applywhen operatingthedevicebeyond itsspecifiedoperatingconditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) When theinputvoltage(VIN)atany pinexceedsthepower supplyrails(VIN < V− orVIN > V+)theabsolutevalueofcurrentatthatpin shouldbe limitedto5 mA orless.The 20 mA package inputcurrentlimitsthenumber ofpinsthatcan exceed thepower supply boundarieswitha 5 mA currentlimittofour. (4) The maximum power dissipationmust be deratedatelevatedtemperaturesand isdictatedby TJMAX ,θJA,and theambienttemperature, TA.The maximum allowablepower dissipationatany temperatureisPD = (TJMAX − TA)/θJA orthenumber givenintheAbsolute Maximum Ratings,whicheverislower.Forthisdevice,TJMAX = 125°C, and thetypicaljunction-to-ambientthermalresistanceofthe MF10ACN/CCN when boardmounted is55°C/W. FortheMF10AJ/CCJ, thisnumber increasesto95°C/W and forthe MF10ACWM/CCWM thisnumber is66°C/W. (5) Human body model,100 pF dischargedthrougha 1.5kΩ resistor.

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 OperatingRatings(1) TemperatureRange (TMIN ≤ TA ≤ TMAX ) MF10ACN, MF10CCN, MF10CCWM 0°C ≤ TA ≤ 70°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.DC and AC electricalspecificationsdo not applywhen operatingthedevicebeyond itsspecifiedoperatingconditions. ElectricalCharacteristics V+ = +5.00V and V− = −5.00Vunlessotherwisespecified.BoldfacelimitsapplyforTMIN toTMAX ;allotherlimitsTA = TJ = 25°C. MF10ACN, MF10CCN, MF10CCWM Symbol Parameter Conditions Units Tested DesignTypical(1) Limit(2) Limit(3) V+ − V− Min 9 V SupplyVoltage Max 14 IS ClockAppliedtoPins10 & 11Maximum SupplyCurrent 8 12 12 mANo InputSignal fO Min fO × Q < 200 kHz 0.1 0.2 Hz CenterFrequencyRange Max 30 20 kHz fCLK Min 5.0 10 Hz ClockFrequencyRange Max 1.5 1.0 MHz ClockFeedthrough Q = 10,Mode 1 10 mV Vpin12= 5V ±2 ±6 ±6fCLK = 250 kHz Q Error(MAX) (4) Q = 10,Mode 1 % Vpin12= 0V ±2 ±6 ±6fCLK = 500 kHz H OLP DC Lowpass Gain Mode 1 R1 = R2 = 10k 0 ±0.2 ±0.2 dB VOS1 DC OffsetVoltage(5) ±5.0 ±20 ±20 mV VOS2 Min Vpin12= +5V SA/B = V+ −150 −185 −185 mV(fCLK /fO = 50)Max −85 −85 DC OffsetVoltage(5) Min Vpin12= +5V SA/B = V− −70 mV(fCLK /fO = 50)Max VOS3 Min Vpin12= +5V AllModes −70 −100 −100 DC OffsetVoltage(5) mV(fCLK /fO = 50)Max −20 −20 VOS2 Vpin12= 0V SA/B = V+ −300 mV(fCLK /fO = 100) DC OffsetVoltage(5) Vpin12= 0V SA/B = V− −140 mV(fCLK /fO = 100) VOS3 Vpin12= 0V AllModesDC OffsetVoltage(5) −140 mV(fCLK /fO = 100) VOUT Minimum Output BP, LP Pins R L = 5k ±4.25 ±3.8 ±3.8 V VoltageSwing N/AP/HP Pin R L = 3.5k ±4.25 ±3.8 ±3.8 V GBW Op Amp Gain BW Product 2.5 MHz SR Op Amp Slew Rate 7 V/μs (1) Typicalsareat25°C and representmost likelyparametricnorm. (2) TestedlimitsareensuredtoAOQL (AverageOutgoingQualityLevel). (3) Designlimitsarespecifiedbutnot100% tested.These limitsarenotused tocalculateoutgoingqualitylevels. (4) The accuracyoftheQ valueisa functionofthecenterfrequency(fO ).Thisisillustratedinthecurvesundertheheading“Typical PerformanceCharacteristics”. (5) VOS1 ,VOS2 ,and VOS3 refertotheinternaloffsetsas discussedinOFFSET VOLTAGE . Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) V+ = +5.00V and V− = −5.00Vunlessotherwisespecified.BoldfacelimitsapplyforTMIN toTMAX ;allotherlimitsTA = TJ = 25°C. MF10ACN, MF10CCN, MF10CCWM Symbol Parameter Conditions Units Tested DesignTypical(1) Limit(2) Limit(3) Vpin12= +5V, (fCLK /fO = 50) 83 dB Dynamic Range (6) Vpin12= 0V,(fCLK /fO = 100) 80 dB ISC Source 20 mAMaximum OutputShortCircuit Current(7) Sink 3.0 mA (6) For±5V suppliesthedynamicrangeisreferencedto2.82Vrms (4V peak)where thewidebandnoiseovera 20 kHz bandwidthis typically200 μV rms fortheMF10-N witha 50:1CLK ratioand 280 μV rms fortheMF10-N witha 100:1CLK ratio. (7) The shortcircuitsourcecurrentismeasured by forcingtheoutputthatisbeingtestedtoitsmaximum positivevoltageswingand then shortingthatoutputtothenegativesupply.The shortcircuitsinkcurrentismeasured by forcingtheoutputthatisbeingtestedtoits maximum negativevoltageswingand thenshortingthatoutputtothepositivesupply.These aretheworstcase conditions. Logic InputCharacteristics BoldfacelimitsapplyforTMIN toTMAX ;allotherlimitsTA = TJ = 25°C MF10ACN, MF10CCN, MF10CCWM Parameter Conditions UnitsTested DesignTypical(1) Limit(2) Limit(3) Min Logical“1” +3.0 +3.0 V V+ = +5V, V− = −5V,VLSh = 0V Max Logical“0” −3.0 −3.0 VCMOS ClockInput Voltage Min Logical“1” +8.0 +8.0 V V+ = +10V, V− = 0V,VLSh = +5V Max Logical“0” +2.0 +2.0 V Min Logical“1” +2.0 +2.0 V V+ = +5V, V− = −5V,VLSh = 0V Max Logical“0” +0.8 +0.8 VTTL ClockInput Voltage Min Logical“1” +2.0 +2.0 V V+ = +10V, V− = 0V,VLSh = 0V Max Logical“0” +0.8 +0.8 V (1) Typicalsareat25°C and representmost likelyparametricnorm. (2) TestedlimitsareensuredtoAOQL (AverageOutgoingQualityLevel). (3) Designlimitsarespecifiedbutnot100% tested.These limitsarenotused tocalculateoutgoingqualitylevels.

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 TypicalPerformance Characteristics Power Supply Currentvs. PositiveOutput VoltageSwing vs. Power Supply Voltage Load Resistance(N/AP/HP Output) Figure1. Figure2. NegativeOutput VoltageSwing vs. Load Resistance(N/AP/HP Output) NegativeOutput Swing vs.Temperature Figure3. Figure4. PositiveOutput Swing vs.Temperature Crosstalkvs.Clock Frequency Figure5. Figure6. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) Q Deviationvs.Temperature Q Deviationvs.Temperature Figure7. Figure8. Q Deviationvs.Clock Frequency Q Deviationvs.Clock Frequency Figure9. Figure10. fCLK /fO Deviationvs.Temperature fCLK /fO Deviationvs.Temperature Figure11. Figure12.

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 TypicalPerformance Characteristics(continued) fCLK /fO Deviationvs.lockFrequency fCLK /fO Deviationvs.Clock Frequency Figure13. Figure14. DeviationoffCLK /fO vs.Nominal Q DeviationoffCLK /fO vs.Nominal Q Figure15. Figure16. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS LP(1,20),BP(2,19),N/AP/HP(3,18)The second orderlowpass,bandpass and notch/allpass/highpassoutputs. These outputscan typicallysink1.5mA and source3 mA. Each outputtypicallyswingstowithin1V of each supply. INV(4,17)The invertinginputofthesumming op-amp ofeach filter.These arehighimpedance inputs,butthe non-invertinginputisinternallytiedtoAGND, making INVA and INVB behave likesumming junctions(low impedance,currentinputs). S1(5,16)S1 isa signalinputpinused intheallpassfilterconfigurations(seemodes 4 and 5).The pinshouldbe drivenwitha sourceimpedance oflessthan1 kΩ.IfS1 isnotdrivenwitha signalitshouldbe tiedto AGND (mid-supply). SA/B(6)Thispinactivatesa switchthatconnectsone oftheinputsofeach filter'ssecond summer toeitherAGND (SA/B tiedtoV−)ortothelowpass(LP)output(SA/B tiedtoV+).Thisofferstheflexibilityneeded for configuringthefilterinitsvariousmodes ofoperation. VA +(7),VD +(8)Analogpositivesupplyand digitalpositivesupply.These pinsareinternallyconnectedthroughthe IC substrateand thereforeVA + and VD + shouldbe derivedfromthesame power supplysource.They have been broughtoutseparatelyso theycan be bypassedby separatecapacitors,ifdesired.They can be externallytiedtogetherand bypassedby a singlecapacitor. VA −(14),VD −(13)Analogand digitalnegativesupplies.The same comments as forVA + and VD + applyhere. LSh(9) Levelshiftpin;itaccommodates variousclocklevelswithdualorsinglesupplyoperation.Withdual±5V supplies,theMF10-N can be drivenwithCMOS clocklevels(±5V) and theLSh pinshouldbe tiedtothe systemground.Ifthesame suppliesas above areused butonlyTTL clocklevels,derivedfrom0V to+5V supply,areavailable,theLSh pinshouldbe tiedtothesystemground.Forsinglesupplyoperation(0V and +10V) theVA −,VD −pinsshouldbe connectedtothesystemground,theAGND pinshouldbe biasedat +5V and theLSh pinshouldalsobe tiedtothesystemgroundforTTL clocklevels.LSh shouldbe biased at+5V forCMOS clocklevelsin10V single-supplyapplications. CLKA(10),CLKB(11) Clockinputsforeach switchedcapacitorfilterbuildingblock.They shouldbothbe ofthe same level(TTL orCMOS). The levelshift(LSh)pindescriptiondiscusseshow toaccommodate their levels.The dutycycleoftheclockshouldbe closeto50% especiallywhen clockfrequenciesabove 200 kHz areused.Thisallowsthemaximum timefortheinternalop-amps tosettle,whichyieldsoptimum filter operation. 50/100/CL(12)By tyingthispinhigha 50:1clock-to-filter-center-frequencyratioisobtained.Tyingthispinatmid- supplies(i.e.analoggroundwithdualsupplies)allowsthefiltertooperateata 100:1clock-to-center- frequencyratio.When thepinistiedlow(i.e.,negativesupplywithdualsupplies),a simplecurrentlimiting circuitistriggeredtolimittheoverallsupplycurrentdown toabout2.5mA. The filteringactionisthen aborted. AGND(15) Thisistheanaloggroundpin.Thispinshouldbe connectedtothesystemgroundfordualsupply operationorbiasedtomid-supplyforsinglesupplyoperation.Fora furtherdiscussionofmid-supply biasingtechniquessee theApplicationsInformation.Foroptimum filterperformancea “clean”groundmust be provided. DefinitionofTerms fCLK :thefrequencyoftheexternalclocksignalappliedtopin10 or11. fO :centerfrequencyofthesecond orderfunctioncomplex polepair.fO ismeasured atthebandpass outputsof theMF10-N, and isthefrequencyofmaximum bandpass gain(Figure17). fnotch:thefrequencyofminimum (ideallyzero)gainatthenotchoutputs. fz:thecenterfrequencyofthesecond ordercomplex zeropair,ifany.Iffz isdifferentfromfO and ifQ Z ishigh,it can be observedas thefrequencyofa notchattheallpassoutput(Figure26). Q: “qualityfactor”ofthe2nd orderfilter.Q ismeasured atthebandpass outputsoftheMF10-N and isequaltofO dividedby the −3 dB bandwidthof the 2nd orderbandpass filter(Figure17).The valueof Q determinesthe shape ofthe2nd orderfilterresponsesas shown inFigure22.

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 Q Z: thequalityfactorofthesecond ordercomplex zeropair,ifany.Q Z isrelatedtotheallpasscharacteristic, whichiswritten: (1) where Q Z = Q foran all-passresponse. H OBP :thegain(inV/V)ofthebandpass outputatf= fO . H OLP :thegain(inV/V)ofthelowpassoutputas f→ 0 Hz (Figure18). H OHP :thegain(inV/V)ofthehighpassoutputas f→ fCLK /2(Figure19). H ON : thegain(inV/V)ofthenotchoutputas f→ 0 Hz and as f→ fCLK /2,when thenotchfilterhas equalgain above and below thecenterfrequency(Figure20).When thelow-frequencygaindiffersfromthehigh-frequency gain,as inmodes 2 and 3a (Figure27 and Figure24),thetwo quantitiesbelowareused inplaceofH ON . H ON1 :thegain(inV/V)ofthenotchoutputas f→ 0 Hz. H ON2 :thegain(inV/V)ofthenotchoutputas f→ fCLK /2. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com (a) (b) Figure17. 2nd-OrderBandpass Response

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 (a) (b) Figure18. 2nd-OrderLow-Pass Response Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com (a) (b) Figure19. 2nd-OrderHigh-Pass Response

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 (a) (b) Figure20. 2nd-OrderNotch Response Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com (a) (b) Figure21. 2nd-OrderAll-PassResponse (a)Bandpass (b)Low Pass (c)High-Pass (d)Notch (e)All-Pass Figure22. Response ofvarious2nd-orderfiltersas a functionofQ. Gains and centerfrequenciesarenormalizedtounity.

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 Modes ofOperation The MF10-N isa switchedcapacitor(sampleddata)filter.To fullydescribeitstransferfunctions,a timedomain approach isappropriate.Since thisiscumbersome, and sincethe MF10-N closelyapproximatescontinuous filters,thefollowingdiscussionisbased on thewellknown frequencydomain.Each MF10-N can producea full 2nd orderfunction.See Table1 fora summary ofthecharacteristicsofthevariousmodes. MODE 1:Notch 1,Bandpass, Lowpass Outputs: fnotch = fO (See Figure23) (2) fO = centerfrequencyofthecomplexpolepair (3) fnotch= centerfrequencyoftheimaginaryzeropair= fO . (4) (5) = qualityfactorofthecomplexpolepair BW = the−3 dB bandwidthofthebandpass output. Circuitdynamics: (6) MODE 1a:Non-InvertingBP, LP (See Figure24) (7) Figure23. MODE 1 Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com VIN shouldbe drivenfroma lowimpedance (<1 kΩ)source. Figure24. MODE 1a MODE 2:Notch 2,Bandpass, Lowpass: fnotch < fO (See Figure25) (8) MODE 3:Highpass,Bandpass, Lowpass Outputs (See Figure26) (9)

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 Figure25. MODE 2 *InMode 3,thefeedbackloopisclosedaroundtheinputsumming amplifier;thefiniteGBW productofthisop amp causesa slightQ enhancement.Ifthisisa problem,connecta smallcapacitor(10pF − 100 pF)acrossR4 toprovide some phase lead. Figure26. MODE 3 Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com MODE 3a:HP, BP, LP and Notch withExternalOp Amp (See Figure27) (10) MODE 4:Allpass,Bandpass, Lowpass Outputs (See Figure28) (11) *Due tothesampled datanatureof the filter,a slightmismatch of fz and fO occurscausinga 0.4 dB peaking around fO of the allpassfilteramplituderesponse (whichtheoreticallyshould be a straightline).Ifthisis unacceptable,Mode 5 isrecommended.

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 Figure27. MODE 3a Figure28. MODE 4 MODE 5:Numerator Complex Zeros,BP, LP (See Figure29) (12) Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com MODE 6a:SinglePole,HP, LP Filter(See Figure30) (13) MODE 6b:SinglePole LP Filter(Invertingand Non-Inverting)(See Figure31) (14) Figure29. MODE 5 Figure30. MODE 6a Figure31. MODE 6b

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 Unless otherwisenoted,gainsofvariousfilteroutputsareinvertingand adjustableby resistorratios. Number ofMode BP LP HP N AP AdjustablefCLK /fO NotesResistors 1 * * * 3 No 1a H OBP1 = −Q May need inputbuffer.PoorH OLP + 1 2 NoH OBP2 = +1 dynamicsforhighQ. Yes (abovefCLK /50or2 * * * 3 fCLK /100) UniversalState-VariableFilter.Best3 * * * 4 Yes general-purposemode. As above,butalsoincludesresistor-3a * * * * 7 Yes tuneablenotch. 4 GivesAllpassresponsewithH OAP =* * * 3 No −1 and H OLP = −2. Givesflatterallpassresponsethan5 * * * 4 above ifR 1 = R 2 = 0.02R4. 6a * * 3 Singlepole. 6b HOLP1 = +1 2 Singlepole.HOLP2 = -R3/R2 Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION The MF10-N isa general-purposedualsecond-orderstatevariablefilterwhose centerfrequencyisproportional tothefrequencyofthesquarewave appliedtotheclockinput(fCLK ).By connectingpin12 totheappropriateDC voltage,thefiltercenterfrequencyfO can be made equaltoeitherfCLK /100orfCLK /50.fO can be veryaccurately set(within±6%) by usinga crystalclockoscillator,or can be easilyvariedover a wide frequencyrange by adjustingthe clockfrequency.Ifdesired,the fCLK /fO ratiocan be alteredby externalresistorsas inFigure25, Figure26, Figure27, Figure29, Figure30, and Figure31. The filterQ and gainare determinedby external resistors. Allofthefivesecond-orderfiltertypescan be builtusingeithersectionoftheMF10-N. These are illustratedin Figure17 throughFigure21 alongwiththeirtransferfunctionsand some relatedequations.Figure22 shows the effectofQ on theshapes ofthesecurves.When filterordersgreaterthantwo aredesired,two ormore MF10-N sectionscan be cascaded. DESIGN EXAMPLE Inordertodesigna second-orderfiltersectionusingtheMF10-N, we must definethenecessaryvaluesofthree parameters:f0, the filtersection'scenterfrequency;H 0, the passband gain;and the filter'sQ. These are determinedby thecharacteristicsrequiredofthefilterbeingdesigned. As an example,let'sassume thata system requiresa fourth-orderChebyshev low-passfilterwith1 dB ripple, unitygainatDC, and 1000 Hz cutofffrequency.As thesystem orderisfour,itisrealizableusingbothsecond- ordersectionsofan MF10-N. Many filterdesigntextsincludetablesthatlistthecharacteristics(fO and Q) ofeach of the second-orderfiltersectionsneeded to synthesizea givenhigher-orderfilter.For the Chebyshev filter definedabove,such a tableyieldsthefollowingcharacteristics: f0A = 529 Hz Q A = 0.785 f0B = 993 Hz Q B = 3.559 ForunitygainatDC, we alsospecify: H 0A = 1 H 0B = 1 The desiredclock-to-cutoff-frequencyratiofortheoverallfilterofthisexample is100 and a 100 kHz clocksignal isavailable.Note thattherequiredcenterfrequenciesforthetwo second-ordersectionswillnotbe obtainable withclock-to-center-frequencyratiosof50 or100.Itwillbe necessarytoadjust (15) externally.From Table1,we see thatMode 3 can be used toproducea low-passfilterwithresistor-adjustable centerfrequency. Inmost filterdesignsinvolvingmultiplesecond-orderstages,itisbesttoplacethestageswithlowerQ values ahead of stageswithhigherQ, especiallywhen the higherQ isgreaterthan 0.707.Thisisdue to the higher relativegainatthecenterfrequencyofa higher-Qstage.Placinga stagewithlowerQ ahead ofa higher-Qstage willprovidesome attenuationatthecenterfrequencyand thushelpavoidclippingofsignalsnearthisfrequency. Forthisexample,stageA has thelowerQ (0.785)so itwillbe placedahead oftheotherstage. For thefirstsection,we beginthedesignby choosinga convenientvaluefortheinputresistance:R 1A = 20k.The absolutevalueofthepassband gainH OLPA ismade equalto1 by choosingR 4A such that:R 4A = −H OLPA R 1A = R 1A = 20k.Ifthe50/100/CLpinisconnectedtomid-supplyfornominal100:1clock-to-center-frequencyratio,we find R 2A by: (16) The resistorsforthesecond sectionarefoundina similarfashion:

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 (17) The completecircuitisshown inFigure32 forsplit±5V power supplies.Supply bypass capacitorsare highly recommended. Figure32. Fourth-OrderChebyshev Low-Pass Filterfrom Example in3.1. ±5V Power Supply.0V–5V TTL or −5V ±5V CMOS Logic Levels. Figure33. Fourth-OrderChebyshev Low-Pass Filterfrom Example in3.1. Single+10V Power Supply.0V–5V TTL Logic Levels.InputSignals Should be ReferredtoHalf-Supplyor Appliedthrough a Coupling Capacitor. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com ResistiveDividerwith OperationalAmplifier Decoupling Capacitor VoltageRegulator withDivider Figure34. Three Ways ofGeneratingV+/2forSingle-SupplyOperation SINGLE SUPPLY OPERATION The MF10-N can alsooperatewitha single-endedpower supply.Figure33 shows the example filterwitha single-endedpower supply.VA + and VD + areagainconnectedtothepositivepower supply(8V to14V),and VA and VD − areconnectedtoground.The AGND pinmust be tiedtoV+/2forsinglesupplyoperation.Thishalf-supply pointshouldbe very“clean”,as any noiseappearingon itwillbe treatedas an inputtothefilter.Itcan be derived fromthesupplyvoltagewitha pairofresistorsand a bypass capacitor(See Figure34),ora low-impedancehalf- supplyvoltagecan be made usinga three-terminalvoltageregulatoror an operationalamplifier(See Figure34 and Figure34).The passiveresistordividerwitha bypass capacitorissufficientformany applications,provided thatthetimeconstantislongenough torejectany power supplynoise.Itisalsoimportantthatthehalf-supply referencepresenta low impedance totheclockfrequency,so atverylow clockfrequenciestheregulatororop- amp approachesmay be preferablebecause theywillrequiresmallercapacitorstofiltertheclockfrequency.The main power supplyvoltageshouldbe clean(preferablyregulated)and bypassedwith0.1μF. DYNAMIC CONSIDERATIONS The maximum signalhandlingcapabilityof the MF10-N, likethatof any activefilter,islimitedby the power supplyvoltagesused.The amplifiersintheMF10-N areabletoswingtowithinabout1V ofthesupplies,so the inputsignalsmust be keptsmallenough thatnone of the outputswillexceed theselimits.Ifthe MF10-N is operatingon ±5V, forexample,theoutputswillclipatabout8 Vp–p.The maximum inputvoltagemultipliedby the filtergainshouldthereforebe lessthan8 Vp–p. Note thatifthefilterQ ishigh,thegainatthelowpassorhighpassoutputswillbe much greaterthanthenominal filtergain(Figure22).As an example,a lowpassfilterwitha Q of10 willhave a 20 dB peak initsamplitude responseatfO .IfthenominalgainofthefilterH OLP isequalto1,thegainatfO willbe 10.The maximum input signalatfO must thereforebe lessthan800 mV p–p when thecircuitisoperatedon ±5V supplies. Alsonotethatone outputcan have a reasonablesmallvoltageon itwhileanotherissaturated.Thisismost likely fora circuitsuch as thenotchinMode 1 (Figure23).The notchoutputwillbe verysmallatfO ,so itmightappear safetoapplya largesignaltotheinput.However,thebandpass willhave itsmaximum gainatfO and can clipif overdriven.Ifone outputclips,theperformanceattheotheroutputswillbe degraded,so avoidoverdrivingany filtersection,even ones whose outputsarenotbeingdirectlyused.Accompanying Figure23 throughFigure31 areequationslabeled“circuitdynamics”,whichrelatetheQ and thegainsatthevariousoutputs.These should be consultedtodeterminepeak circuitgainsand maximum allowablesignalsfora givenapplication. OFFSET VOLTAGE The MF10-N's switchedcapacitorintegratorshave a higherequivalentinputoffsetvoltagethanwouldbe foundin a typicalcontinuous-timeactivefilterintegrator.Figure35 shows an equivalentcircuitoftheMF10-N fromwhich theoutputDC offsetscan be calculated.TypicalvaluesfortheseoffsetswithSA/B tiedtoV+ are: Vos1 = opamp offset= ±5 mV Vos2 = −150 mV @ 50:1 −300 mV @ 100:1 Vos3 = −70 mV @ 50:1 −140 mV @ 100:1

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 When SA/B istiedtoV−,Vos2 willapproximatelyhalve.The DC offsetattheBP outputisequaltotheinputoffset of the lowpass integrator(Vos3).The offsetsat the otheroutputsdepend on the mode of operationand the resistorratios,as describedinthefollowingexpressions. (18) (19) Figure35. MF10-N OffsetVoltageSources Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com Figure36. Method forTrimming VOS For most applications,theoutputsare AC coupledand DC offsetsare notbothersomeunlesslargesignalsare appliedtothefilterinput.However, largeroffsetvoltageswillcause clippingtooccuratlowerAC signallevels, and clippingat any of the outputswillcause gainnonlinearitiesand willchange fO and Q. When operatingin Mode 3,offsetscan become excessivelylargeifR2 and R4 areused tomake fCLK /fO significantlyhigherthanthe nominalvalue,especiallyifQ isalsohigh.An extremeexample isa bandpass filterhavingunitygain,a Q of20, and fCLK /fO = 250 withpin12 tiedtoground(100:1nominal).R4/R2 willthereforebe equalto6.25and theoffset voltageatthelowpassoutputwillbe about+1V. Where necessary,theoffsetvoltagecan be adjustedby using thecircuitofFigure36.ThisallowsadjustmentofVOS1 ,whichwillhave varyingeffectson thedifferentoutputsas describedintheabove equations.Some outputscannotbe adjustedthisway insome modes, however (VOS(BP) inmodes 1a and 3,forexample). SAMPLED DATA SYSTEM CONSIDERATIONS The MF10-N isa sampled datafilter,and as such,differsinmany ways fromconventionalcontinuous-timefilters. An importantcharacteristicofsampled-datasystems istheireffecton signalsatfrequenciesgreaterthanone- halfthesamplingfrequency.(The MF10-N's samplingfrequencyisthesame as itsclockfrequency.)Ifa signal witha frequencygreaterthanone-halfthesamplingfrequencyisappliedtotheinputofa sampled datasystem,it willbe “reflected” to a frequencylessthan one-halfthe samplingfrequency.Thus, an inputsignalwhose frequencyisfs/2+ 100 Hz willcause thesystem torespondas thoughtheinputfrequencywas fs/2− 100 Hz. Thisphenomenon isknown as “aliasing”,and can be reducedoreliminatedby limitingtheinputsignalspectrum tolessthanfs/2.Thismay insome cases requiretheuse ofa bandwidth-limitingfilterahead oftheMF10-N to limittheinputspectrum.However, sincetheclockfrequencyismuch higherthanthecenterfrequency,thiswill oftennotbe necessary. Anothercharacteristicofsampled-datacircuitsisthattheoutputsignalchanges amplitudeonce everysampling period,resultingin“steps”intheoutputvoltagewhichoccurattheclockrate(Figure37).Ifnecessary,thesecan be “smoothed”witha simpleR –C low-passfilterattheMF10-N output. The ratiooffCLK tofC (normallyeither50:1or100:1)willalsoaffectperformance.A ratioof100:1willreduceany aliasingproblems and is usuallyrecommended forwideband inputsignals.In noise sensitiveapplications, however,a ratioof50:1may be betteras itwillresultin3 dB loweroutputnoise.The 50:1ratioalsoresultsin lowerDC offsetvoltages,as discussedinOFFSET VOLTAGE . The accuracyof the fCLK /fO ratioisdependent on the valueof Q. This isillustratedin TypicalPerformance Characteristics.As Q ischanged,thetruevalueoftheratiochanges as well.UnlesstheQ islow,theerrorin fCLK /fO willbe small.Iftheerroristoolargefora specificapplication,use a mode thatallowsadjustmentofthe ratiowithexternalresistors. Itshouldalsobe notedthattheproductofQ and fO shouldbe limitedto300 kHz when fO < 5 kHz, and to200 kHz forfO > 5 kHz.

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www.ti.com SNOS547C –JUNE 1999–REVISED APRIL 2013 Figure37. The Sampled-Data Output Waveform Connection Diagram Figure38. SOIC and PDIP Packages (Top View) See Package Numbers DW and NFH0020A Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:MF10-N

SNOS547C –JUNE 1999–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page

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www.ti.com 12-Nov-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples MF10CCWM/NOPB ACTIVE SOIC DW 20 36 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 MF10CCWM MF10CCWMX/NOPB ACTIVE SOIC DW 20 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 MF10CCWM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 12-Nov-2017 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Oct-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MF10CCWMX/NOPB SOIC DW 20 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Oct-2017 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP10.63 9.97

2.65 MAX

18X 1.27 20X 0.51 0.31 11.43 TYP0.33 0.10 0 - 8 0.3 0.1 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 13.0 12.6 B 7.6 7.4 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. 1 20

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.200

www.ti.com EXAMPLE BOARD LAYOUT (9.3)

0.07 MAX

0.07 MIN

20X (2) 20X (0.6) 18X (1.27) (R ) TYP 0.05 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 10 11 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (9.3) 18X (1.27) 20X (0.6) 20X (2) 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 10 11 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X

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