MF10CCWM

MF10 NSC | Alldatasheet

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Features

Y Clock to center frequency ratio accuracy g0.6% Y Filter cutoff frequency stability directly dependent on external clock quality Y Low sensitivity to external component variation Y Separate highpass (or notch or allpass), bandpass, low- pass outputs Y fO c Q range up to 200 kHz Y Operation up to 30 kHz Y 20-pin 0.3 × wide Dual-In-Line package Y 20-pin Surface Mount (SO) wide-body package System Block Diagram TL/H/10399–1 Connection Diagram Surface Mount and Dual-In-Line Package TL/H/10399–4 Top View Order Number MF10AJ or MF10CCJ See NS Package Number J20A Order Number MF10ACWM or MF10CCWM See NS Package Number M20B Order Number MF10ACN or MF10CCN See NS Package Number N20A C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V a b Vb) 14V Voltage at Any Pin V a a 0.3V Vb b 0.3V Input Current at Any Pin (Note 2) 5 mA Package Input Current (Note 2) 20 mA Power Dissipation (Note 3) 500 mW Storage Temperature 150 ESD Susceptability (Note 11) 2000V Soldering Information N Package: 10 sec. 260 §C J Package: 10 sec. 300 §C Infrared (15 Sec.) 220 §C See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ (Appendix D) for other methods of soldering surface mount devices. Operating Ratings (Note 1) Temperature Range T MIN s TA s TMAX MF10ACN, MF10CCN 0 §C s TA s 70§C MF10CCWM, MF10ACWM 0 §C s TA s 70§C MF10CCJ b40§C s TA s 85§C MF10AJ b55§C s TA s 125§C Electrical Characteristics Va ea 5.00V and V b eb 5.00V unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A e TJ e 25§C. MF10ACN, MF10CCN, MF10CCJ, MF10AJMF10ACWM, MF10CCWM Symbol Parameter Conditions Typical Tested Design Typical Tested Design Units (Note 8) Limit Limit (Note 8) Limit Limit (Note 9) (Note 10) (Note 9) (Note 10) Va b Vb Supply Voltage Min 99 V Max 14 14 V IS Maximum Supply Clock Applied to Pins 10 & 11 81 2 12 8 12 mACurrent No Input Signal fO Center Frequency Min f O c Q k 200 kHz 0.1 0.2 0.1 0.2 Hz Range Max 30 20 30 20 kHz fCLK Clock Frequency Min 5.0 10 5.0 10 Hz Range Max 1.5 1.0 1.5 1.0 MHz Center Frequency MF10C Mode 1 f CLK e 250 kHz Center Frequency MF10C Mode 1 f CLK e 500 kHz Clock Feedthrough Q e 10 10 10 mVMode 1 Q Error (MAX) Q e 10 V pin12 e 5V g2 g6 g6 g2 g10 %(Note 4) Mode 1 f CLK e 250 kHz Vpin12 e 0V g2 g6 g6 g2 g10 %fCLK e 500 kHz HOLP DC Lowpass Gain Mode 1 R1 e R2 e 10k 0 g0.2 g0.2 0 g0.2 dB VOS1 DC Offset Voltage (Note 5) g5.0 g20 g20 g5.0 g20 mV VOS2 DC Offset Voltage Min V pin12 ea 5V S A/B e Va b150 b185 b185 b150 b185 mV(Note 5) Max (fCLK/fO e 50) b85 b85 b85 Min V pin12 ea 5V S A/B e Vb b70 b70 mV Max (fCLK/fO e 50) VOS3 DC Offset Voltage Min V pin12 ea 5V All Modes b70 b100 b100 b70 b100 mV(Note 5) Max (fCLK/fO e 50) b20 b20 b20 VOS2 DC Offset Voltage V pin12 e 0V S A/B e Va b300 b300 mV(Note 5) (f CLK/fO e 100) Vpin12 e 0V S A/B e Vb b140 b140 mV(Note 5) (f CLK/fO e 100) VOS3 DC Offset Voltage V pin12 e 0V All Modes b140 b140 mV(Note 5) (f CLK/fO e 100)

Electrical Characteristics (Continued) V a ea 5.00V and V b eb 5.00V unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A e TJ e 25§C. MF10ACN, MF10CCN, MF10CCJ, MF10AJMF10ACWM, MF10CCWM Symbol Parameter Conditions Typical Tested Design Typical Tested Design Units (Note 8) Limit Limit (Note 8) Limit Limit (Note 9) (Note 10) (Note 9) (Note 10) GBW Op Amp Gain BW Product 2.5 2.5 MHz SR Op Amp Slew Rate 7 7 V/ ms Dynamic Range V pin12 ea 5V 83 83 dB(Note 6) (f CLK/fO e 50) Vpin12 e 0V 80 80 dB(fCLK/fO e 100) ISC Maximum Output Short Source 20 20 mA Circuit Current (Note 7) Sink 3.0 3.0 mA Logic Input Characteristics Boldface limits apply for T MIN to T MAX; all other limits T A e TJ e 25§C MF10ACN, MF10CCN, MF10CCJ, MF10AJMF10ACWM, MF10CCWM Parameter Conditions Typical Tested Design Typical Tested Design Units (Note 8) Limit Limit (Note 8) Limit Limit (Note 9) (Note 10) (Note 9) (Note 10) CMOS Clock Min Logical ‘‘1’’ V a ea 5V, V b eb 5V, a3.0 a3.0 a3.0 V Input Voltage Max Logical ‘‘0’’ VLSh e 0V b3.0 b3.0 b3.0 V Min Logical ‘‘1’’ V a ea 10V, V b e 0V, a8.0 a8.0 a8.0 V Max Logical ‘‘0’’ VLSh ea 5V a2.0 a2.0 a2.0 V TTL Clock Min Logical ‘‘1’’ V a ea 5V, V b eb 5V, a2.0 a2.0 a2.0 V Input Voltage Max Logical ‘‘0’’ VLSh e 0V a0.8 a0.8 a0.8 V Min Logical ‘‘1’’ V a ea 10V, V b e 0V, a2.0 a2.0 a2.0 V Max Logical ‘‘0’’ VLSh a0.8 a0.8 a0.8 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: When the input voltage (V IN) at any pin exceeds the power supply rails (V IN k Vb or V IN l Va) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries wit ha5m A current limit to four. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX, iJA, and the ambient temperature, T A. The maximum allowable power dissipation at any temperature is P D e (TJMAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T JMAX e 125§C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55 §C/W. For the MF10AJ/CCJ, this number increases to 95 §C/W and for the MF10ACWM/CCWM this number is 66 §C/W. Note 4: The accuracy of the Q value is a function of the center frequency (f O). This is illustrated in the curves under the heading ‘‘Typical Performance Characteristics’’. Note 5: VOS1,V OS2, and V OS3 refer to the internal offsets as discussed in the Applications Information Section 3.4. Note 6: For g5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 mV rms for the MF10 with a 50:1 CLK ratio and 280 mV rms for the MF10 with a 100:1 CLK ratio. Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Note 8: Typicals are at 25 §C and represent most likely parametric norm. Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 11: Human body model, 100 pF discharged through a 1.5 k X resistor.

Typical Performance Characteristics vs Power Supply Voltage Power Supply Current (N/AP/HP Output) vs Load Resistance Positive Output Voltage Swing Resistance (N/AP/HP Output) Swing vs Load Negative Output Voltage Swing vs Temperature Negative Output vs Temperature Positive Output Swing Frequency Crosstalk vs Clock Temperature Q Deviation vs Temperature Q Deviation vs Clock Frequency Q Deviation vs Clock Frequency Q Deviation vs vs Temperature f CLK/fO Deviation vs Temperature fCLK/fO Deviation TL/H/10399–2

Typical Performance Characteristics (Continued) vs Clock Frequency fCLK/fO Deviation vs Clock Frequency fCLK/fO Deviation Deviation of fCLK fOvs Nominal Q Deviation of fCLK fOvs Nominal Q TL/H/10399–3 Pin Descriptions LP(1,20), BP(2,19), The second order lowpass, bandpass N/AP/HP(3,18) and notch/allpass/highpass outputs. These outputs can typically sink 1.5 mA and source 3 mA. Each output typically swings to within 1V of each supply. INV(4,17) The inverting input of the summing op- amp of each filter. These are high im- pedance inputs, but the non-inverting in- put is internally tied to AGND, making INV A and INV B behave like summing junctions (low impedance, current in- puts). S1(5,16) S1 is a signal input pin used in the all- pass filter configurations (see modes 4 and 5). The pin should be driven with a source impedance of less than 1 k X.I f S1 is not driven with a signal it should be tied to AGND (mid-supply). S A/B(6) This pin activates a switch that connects one of the inputs of each filter’s second summer to either AGND (S A/B tied to Vb) or to the lowpass (LP) output (S A/B tied to V a). This offers the flexibility needed for configuring the filter in its various modes of operation. V Aa(7),VDa(8) Analog positive supply and digital posi- tive supply. These pins are internally connected through the IC substrate and therefore V Aa and V Da should be de- rived from the same power supply source. They have been brought out separately so they can be bypassed by separate capacitors, if desired. They can be externally tied together and by- passed by a single capacitor. V Ab(14), V Db(13) Analog and digital negative supplies. The same comments as for V A a and VD a apply here.

Pin Descriptions (Continued) LSh(9) Level shift pin; it accommodates various clock levels with dual or single supply operation. With dual g5V supplies, the MF10 can be driven with CMOS clock levels ( g5V) and the LSh pin should be tied to the system ground. If the same supplies as above are used but only TTL clock levels, derived from 0V to a5V supply, are available, the LSh pin should be tied to the system ground. For single supply operation (0V and a10V) the VAb,V Db pins should be connected to the system ground, the AGND pin should be biased at a5V and the LSh pin should also be tied to the system ground for TTL clock levels. LSh should be biased at a5V for CMOS clock lev- els in 10V single-supply applications. CLKA(10), Clock inputs for each switched capaci- CLKB(11) tor filter building block. They should both be of the same level (TTL or CMOS). The level shift (LSh) pin description dis- cusses how to accommodate their lev- els. The duty cycle of the clock should be close to 50% especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal op-amps to settle, which yields optimum filter operation. 50/100/CL(12) By tying this pin high a 50:1 clock-to-fil- ter-center-frequency ratio is obtained. Tying this pin at mid-supplies (i.e, analog ground with dual supplies) allows the fil- ter to operate at a 100:1 clock-to-cen- ter-frequency ratio. When the pin is tied low (i.e., negative supply with dual sup- plies), a simple current limiting circuit is triggered to limit the overall supply cur- rent down to about 2.5 mA. The filtering action is then aborted. AGND(15) This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or bi- ased to mid-supply for single supply op- eration. For a further discussion of mid- supply biasing techniques see the Appli- cations Information (Section 3.2). For optimum filter performance a ‘‘clean’’ ground must be provided.

1.0 Definition of Terms

fCLK: the frequency of the external clock signal applied to pin 10 or 11. fO: center frequency of the second order function complex pole pair. f O is measured at the bandpass outputs of the MF10, and is the frequency of maximum bandpass gain. (Figure 1) fnotch: the frequency of minimum (ideally zero) gain at the notch outputs. fz: the center frequency of the second order complex zero pair, if any. If f z is different from f O and if Q Z is high, it can be observed as the frequency of a notch at the allpass output. (Figure 10) Q: ‘‘quality factor’’ of the 2nd order filter. Q is measured at the bandpass outputs of the MF10 and is equal to f O divided by the b3 dB bandwidth of the 2nd order bandpass filter (Figure 1) . The value of Q determines the shape of the 2nd order filter responses as shown in Figure 6 . QZ: the quality factor of the second order complex zero pair, if any. Q Z is related to the allpass characteristic, which is written: HAP(s) e HOAP # s2 b s0O QZ a 0O2 J s2 a s0O Q a 0O2 where Q Z e Q for an all-pass response. HOBP: the gain (in V/V) of the bandpass output at f e fO. HOLP: the gain (in V/V) of the lowpass output as f x 0H z (Figure 2) . HOHP: the gain (in V/V) of the highpass output as f x fCLK/2 (Figure 3) . HON: the gain (in V/V) of the notch output as f x 0H z and as f x fCLK/2, when the notch filter has equal gain above and below the center frequency (Figure 4) . When the low-frequency gain differs from the high-frequency gain, as in modes 2 and 3a (Figures 11 and 8) , the two quantities below are used in place of H ON. HON1: the gain (in V/V) of the notch output as f x 0 Hz. HON2: the gain (in V/V) of the notch output as f x fCLK/2.

1.0 Definition of Terms (Continued)

FIGURE 1. 2nd-Order Bandpass Response FIGURE 2. 2nd-Order Low-Pass Response FIGURE 3. 2nd-Order High-Pass Response

1.0 Definitions of Terms (Continued)

FIGURE 4. 2nd-Order Notch Response FIGURE 5. 2nd-Order All-Pass Response FIGURE 6. Response of various 2nd-order filters as a function of Q. Gains and center frequencies are normalized to unity.

2.0 Modes of Operation

discussion is based on the well know frequency domain. fnotch e center frequency of the imaginary zero pair e fO. BW e the b3 dB bandwidth of the bandpass output. Note: VIN should be driven from a low impedance ( k1k X) source. FIGURE 7. MODE 1 FIGURE 8. MODE 1a

2.0 Modes of Operation (Continued)

FIGURE 9. MODE 2 problem, connect a small capacitor (10 pF b 100 pF) across R4 to provide some phase lead. FIGURE 10. MODE 3

able, Mode 5 is recommended. FIGURE 11. MODE 3a FIGURE 12. MODE 4

FIGURE 13. MODE 5 FIGURE 14. MODE 6a FIGURE 15. MODE 6b

Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios. Mode BP LP HP N AP Number of Adjustable NotesResistors f CLK/fO 1 ** * 3N o (2) May need input buffer. 1a H OBP1 eb QH OLP a 1 2 No Poor dynamics for HOBP2 ea 1 high Q. 2 ** * 3 Yes (above f CLK/50 or f CLK/100) 3 ** * 4 Yes Universal State-Variable Filter. Best general-purpose mode. 3a ** * * 7 Yes As above, but also includes resistor-tuneable notch. 4 ** * 3N o Gives Allpass response with HOAP eb 1 and H OLP eb 2. 5 ** * 4 Gives flatter allpass response than above if R 1 e R2 e 0.02R4. 6a ** 3 Single pole. (2) 6b H OLP1 ea 1 2 Single Pole. HOLP2 e bR3

3.0 Applications Information

The MF10 is a general-purpose dual second-order state variable filter whose center frequency is proportional to the frequency of the square wave applied to the clock input CLK). By connecting pin 12 to the appropriate DC voltage, the filter center frequency f O can be made equal to either fCLK/100 or f CLK/50. f O can be very accurately set (within g6%) by using a crystal clock oscillator, or can be easily varied over a wide frequency range by adjusting the clock frequency. If desired, the f CLK/fO ratio can be altered by external resistors as in Figures 9, 10, 11, 13, 14 and 15 . The filter Q and gain are determined by external resistors. All of the five second-order filter types can be built using either section of the MF10. These are illustrated in Figures 1 through 5 along with their transfer functions and some relat- ed equations. Figure 6 shows the effect of Q on the shapes of these curves. When filter orders greater than two are desired, two or more MF10 sections can be cascaded.

3.1 DESIGN EXAMPLE

In order to design a second-order filter section using the MF10, we must define the necessary values of three param- eters: f 0, the filter section’s center frequency; H 0, the pass- band gain; and the filter’s Q. These are determined by the characteristics required of the filter being designed. As an example, let’s assume that a system requires a fourth-order Chebyshev low-pass filter with 1 dB ripple, unity gain at DC, and 1000 Hz cutoff frequency. As the system order is four, it is realizable using both second-order sec- tions of an MF10. Many filter design texts include tables that list the characteristics (f O and Q) of each of the second-or- der filter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined above, such a table yields the following characteristics: f0A e 529 Hz Q A e 0.785 f0B e 993 Hz Q B e 3.559 For unity gain at DC, we also specify: H 0A e 1 H0B e 1 The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100 and a 100 kHz clock signal is available. Note that the required center frequencies for the two second-order sections will not be obtainable with clock- to-center-frequency ratios of 50 or 100. It will be necessary to adjust f CLK externally. From Table I, we see that Mode 3 can be used to produce a low-pass filter with resistor-adjust- able center frequency. In most filter designs involving multiple second-order stages, it is best to place the stages with lower Q values ahead of stages with higher Q, especially when the higher Q is greater than 0.707. This is due to the higher relative gain at the center frequency of a higher-Q stage. Placing a stage with lower Q ahead of a higher-Q stage will provide some attenuation at the center frequency and thus help avoid clip- ping of signals near this frequency. For this example, stage A has the lower Q (0.785) so it will be placed ahead of the other stage. For the first section, we begin the design by choosing a convenient value for the input resistance: R 1A e 20k. The absolute value of the passband gain H OLPA is made equal

3.0 Applications Information (Continued)

FIGURE 16. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1. g5V Power Supply. 0V–5V TTL or b5V g5V CMOS Logic Levels. FIGURE 17. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1. Should be Referred to Half-Supply or Applied through a Coupling Capacitor.

FIGURE 18. Three Ways of Generating Va

3.2 SINGLE SUPPLY OPERATION

3.3 DYNAMIC CONSIDERATIONS

3.4 OFFSET VOLTAGE

typical continuous-time active filter integrator. described in the following expressions.

FIGURE 19. MF10 Offset Voltage Sources FIGURE 20. Method for Trimming V OS

OS(BP) in modes 1a and 3, for example).

3.5 SAMPLED DATA SYSTEM CONSIDERATIONS

a frequency less than one-half the sampling frequency. voltages, as discussed in Section 3.4. of the ratio with external resistors. FIGURE 21. The Sampled-Data Output Waveform

Physical Dimensions inches (millimeters) 20-Lead Ceramic Dual-In-Line Package (J) Order Number MF10AJ or MF10CCJ Molded Package (Small Outline) (M) Order Number MF10ACWM or MF10CCWM

MF10 Universal Monolithic Dual Switched Capacitor Filter Physical Dimensions inches (millimeters) (Continued) 20-Lead Molded Dual-In-Line Package (N) Order Number MF10ACN or MF10CCN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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