MF10CCN

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MF10 Universal Monolithic Dual Switched Capacitor Filter Literature Number: SNOS547B

Universal Monolithic Dual Switched Capacitor Filter General Description The MF10 consists of 2 independent and extremely easy to use, general purpose CMOS active filter building blocks. Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd order functions. Each building block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly de- pendent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th order functions can be performed by cascading the two 2nd order building blocks of the MF10; higher than 4th order functions can be obtained by cascading MF10 packages. Any of the classical filter configurations (such as Butter- worth, Bessel, Cauer and Chebyshev) can be formed. For pin-compatible device with improved performance refer to LMF100 datasheet.

Features

n Clock to center frequency ratio accuracy±0.6% n Filter cutoff frequency stability directly dependent on external clock quality n Low sensitivity to external component variation n Separate highpass (or notch or allpass), bandpass, lowpass outputs n fO x Q range up to 200 kHz n Operation up to 30 kHz n 20-pin 0.3" wide Dual-In-Line package n 20-pin Surface Mount (SO) wide-body package System Block Diagram 01039901 Package in 20 pin molded wide body surface mount and 20 pin molded DIP. May 2001 MF10 Universal Monolithic Dual Switched Capacitor Filter © 2001 National Semiconductor Corporation DS010399 www.national.com

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V + −V −) 14V Voltage at Any Pin V + + 0.3V V− − 0.3V Input Current at Any Pin (Note 2) 5 mA Package Input Current (Note 2) 20 mA Power Dissipation (Note 3) 500 mW Storage Temperature 150˚C ESD Susceptability (Note 11) 2000V Soldering Information N Package: 10 sec 260˚C Vapor Phase (60 Sec.) 215˚C Infrared (15 Sec.) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” (Appendix D) for other methods of soldering surface mount devices. Operating Ratings(Note 1) Temperature Range T MIN ≤ TA ≤ TMAX MF10ACN, MF10CCN 0˚C ≤ TA ≤ 70˚C MF10CCWM 0˚C ≤ TA ≤ 70˚C

Electrical Characteristics

V+ = +5.00V and V− = −5.00V unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA =T J = 25˚C. MF10ACN, MF10CCN, MF10CCWM Symbol Parameter Conditions Typical Tested Design Units (Note Limit Limit (Note (Note 10) V+ − Supply Voltage Min 9 V Max 14 V IS Maximum Supply Clock Applied to Pins 10 & 11 81 2 12 mA Current No Input Signal fO Center Frequency Min f O xQ < 200 kHz 0.1 0.2 Hz Range Max 30 20 kHz fCLK Clock Frequency Min 5.0 10 Hz Range Max 1.5 1.0 MHz fCLK /fO 50:1 Clock to Center Frequency Ratio Deviation MF10A Q = 10 Mode 1 V pin12 =5 V fCLK = 250 KHz ±0.2 ±0.6 ±0.6 % fCLK /fO 100:1 Clock to Center Frequency Ratio Deviation MF10A Q = 10 Mode 1 V pin12 =0 V fCLK = 500 kHz ±0.2 ±0.6 ±0.6 % Clock Feedthrough Q = 10 Mode 1 10 mV Q Error (MAX) Q = 10 V pin12 =5 V ±2 ±6 ±6 % (Note 4) Mode 1 f CLK = 250 kHz Vpin12 =0 V ±2 ±6 ±6 % fCLK = 500 kHz H OLP DC Lowpass Gain Mode 1 R1 = R2 = 10k 0 ±0.2 ±0.2 dB VOS1 DC Offset Voltage (Note 5) ±5.0 ±20 ±20 mV VOS2 DC Offset Voltage Min V pin12 = +5V S A/B =V + −150 −185 −185 mV MF10 www.national.com 2

Electrical Characteristics(Continued) V+ = +5.00V and V− = −5.00V unless otherwise specified.Boldface limits apply for TMIN to TMAX ;all other limits TA =T J = 25˚C. MF10ACN, MF10CCN, MF10CCWM Symbol Parameter Conditions Typical Tested Design Units (Note Limit Limit (Note (Note 10) (Note 5) Max (f CLK /fO = 50) −85 −85 Min V pin12 = +5V S A/B =V − −70 mV Max (f CLK /fO = 50) VOS3 DC Offset Voltage Min V pin12 = +5V All Modes −70 −100 −100 mV (Note 5) Max (f CLK /fO = 50) −20 −20 VOS2 DC Offset Voltage V pin12 =0 V S A/B =V + −300 mV (Note 5) (f CLK /fO = 100) Vpin12 =0 V S A/B =V − −140 mV (fCLK /fO = 100) VOS3 DC Offset Voltage V pin12 = 0V All Modes −140 mV (Note 5) (f CLK /fO = 100) VOUT Minimum Output BP, LP Pins R L =5 k ±4.25 ±3.8 ±3.8 V Voltage Swing N/AP/HP Pin GBW Op Amp Gain BW Product 2.5 MHz SR Op Amp Slew Rate 7 V/µs Dynamic Range(Note 6) V pin12 = +5V (fCLK /fO = 50) 83 dB Vpin12 =0 V (fCLK /fO = 100) 80 dB ISC Maximum Output Short Source 20 mA Circuit Current (Note 7) Sink 3.0 mA Logic Input Characteristics Boldface limits apply for TMIN to TMAX ;all other limits TA =T J = 25˚C MF10ACN, MF10CCN, MF10CCWM Parameter Conditions Typical Tested Design Units (Note 8) Limit Limit (Note 9) (Note 10) CMOS Clock Min Logical “1” V + = +5V, V− = −5V, +3.0 +3.0 V Input Voltage Max Logical “0” V LSh = 0V −3.0 −3.0 V Min Logical “1” V + = +10V, V− = 0V, +8.0 +8.0 V Max Logical “0” V LSh = +5V +2.0 +2.0 V TTL Clock Min Logical “1” V + = +5V, V− = −5V, +2.0 +2.0 V Input Voltage Max Logical “0” V LSh = 0V +0.8 +0.8 V MF10 www.national.com3

Logic Input Characteristics(Continued) Boldface limits apply for TMIN to TMAX ;all other limits TA =T J = 25˚C MF10ACN, MF10CCN, MF10CCWM Parameter Conditions Typical Tested Design Units (Note 8) Limit Limit (Note 9) (Note 10) Min Logical “1” V + = +10V, V− = 0V, +2.0 +2.0 V Max Logical “0” V LSh = 0V +0.8 +0.8 V Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2:When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5m A current limit to four. Note 3:The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD =( TJMAX −T A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125˚C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55˚C/W. For the MF10AJ/CCJ, this number increases to 95˚C/W and for the MF10ACWM/CCWM this number is 66˚C/W. Note 4:The accuracy of the Q value is a function of the center frequency (fO ). This is illustrated in the curves under the heading “Typical Performance Characteristics”. Note 5:VOS1 ,V OS2 , and VOS3 refer to the internal offsets as discussed in the Applications Information Section 3.4. Note 6:For ±5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 µV rms for the MF10 with a 50:1 CLK ratio and 280 µV rms for the MF10 with a 100:1 CLK ratio. Note 7:The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Note 8:Typicals are at 25˚C and represent most likely parametric norm. Note 9:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10:Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 11:Human body model, 100 pF discharged through a 1.5 kΩ resistor. MF10 www.national.com 4

Typical Performance Characteristics Power Supply Current vs. Power Supply Voltage Positive Output Voltage Swing vs. Load Resistance (N/AP/HP Output) 01039934 01039935 Negative Output Voltage Swing vs. Load Resistance (N/AP/HP Output) Negative Output Swing vs. Temperature 01039936 01039937 Positive Output Swing vs. Temperature Crosstalk vs. Clock Frequency 01039938 01039939 MF10 www.national.com5

Typical Performance Characteristics(Continued) Q Deviation vs. Temperature Q Deviation vs. Temperature 01039940 01039941 Q Deviation vs. Clock Frequency Q Deviation vs. Clock Frequency 01039942 01039943 fCLK /fO Deviation vs. Temperature f CLK /fO Deviation vs. Temperature 01039944 01039945 MF10 www.national.com 6

Typical Performance Characteristics(Continued) fCLK /fO Deviation vs. Clock Frequency f CLK /fO Deviation vs. Clock Frequency 01039946 01039947 Deviation of fCLK /fO vs. Nominal Q Deviation of f CLK /fO vs. Nominal Q 01039948 01039949 MF10 www.national.com7

LP(1,20), BP(2,19), N/AP/HP(3,18) The second order lowpass, bandpass and notch/allpass/highpass outputs. These outputs can typically sink 1.5 mA and source 3 mA. Each output typically swings to within 1V of each supply. INV(4,17) The inverting input of the summing op-amp of each filter. These are high impedance inputs, but the non-inverting input is internally tied to AGND, making INV A and INVB behave like summing junctions (low impedance, current inputs). S1(5,16) S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5). The pin should be driven with a source impedance of less than 1 kΩ . If S1 is not driven with a signal it should be tied to AGND (mid-supply). S A/B(6) This pin activates a switch that con- nects one of the inputs of each filter’s second summer to either AGND (S A/B tied to V−) or to the lowpass (LP) output (SA/B tied to V+). This offers the flexibil- ity needed for configuring the filter in its various modes of operation. V A +(7),VD +(8) Analog positive supply and digital posi- tive supply. These pins are internally connected through the IC substrate and therefore V A + and VD + should be de- rived from the same power supply source. They have been brought out separately so they can be bypassed by separate capacitors, if desired. They can be externally tied together and by- passed by a single capacitor. V A −(14), VD −(13) Analog and digital negative supplies. The same comments as for VA + and VD + apply here. LSh(9) Level shift pin; it accommodates vari- ous clock levels with dual or single sup- ply operation. With dual ±5V supplies, the MF10 can be driven with CMOS clock levels ( ±5V) and the LSh pin should be tied to the system ground. If the same supplies as above are used but only TTL clock levels, derived from 0V to +5V supply, are available, the LSh pin should be tied to the system ground. For single supply operation (0V and +10V) the V A −,V D −pins should be connected to the system ground, the AGND pin should be biased at +5V and the LSh pin should also be tied to the system ground for TTL clock levels. LSh should be biased at +5V for CMOS clock levels in 10V single-supply applications. CLKA(10), CLKB(11) Clock inputs for each switched capaci- tor filter building block. They should both be of the same level (TTL or CMOS). The level shift (LSh) pin de- scription discusses how to accommo- date their levels. The duty cycle of the clock should be close to 50% especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal op-amps to settle, which yields optimum filter operation. 50/100/CL(12) By tying this pin high a 50:1 clock-to-filter-center-frequency ratio is obtained. Tying this pin at mid-supplies (i.e. analog ground with dual supplies) allows the filter to operate at a 100:1 clock-to-center-frequency ratio. When the pin is tied low (i.e., negative supply with dual supplies), a simple current limiting circuit is triggered to limit the overall supply current down to about 2.5 mA. The filtering action is then aborted. AGND(15) This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or bi- ased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a “clean” ground must be provided.

1.0 Definition of Terms

fCLK :the frequency of the external clock signal applied to pin 10 or 11. fO : center frequency of the second order function complex pole pair. fO is measured at the bandpass outputs of the MF10, and is the frequency of maximum bandpass gain. Figure 1) fnotch: the frequency of minimum (ideally zero) gain at the notch outputs. fz: the center frequency of the second order complex zero pair, if any. If fz is different from fO and if QZ is high, it can be observed as the frequency of a notch at the allpass output. Figure 10) Q: “quality factor” of the 2nd order filter. Q is measured at the bandpass outputs of the MF10 and is equal to fO divided by the −3 dB bandwidth of the 2nd order bandpass filter (Figure 1). The value of Q determines the shape of the 2nd order filter responses as shown inFigure 6. Q Z:the quality factor of the second order complex zero pair, if any. QZ is related to the allpass characteristic, which is written: where QZ = Q for an all-pass response. H OBP :the gain (in V/V) of the bandpass output at f = fO . MF10 www.national.com 8

1.0 Definition of Terms(Continued)

tities below are used in place of HON . H ON1 :the gain (in V/V) of the notch output as f→ 0 Hz. H ON2 :the gain (in V/V) of the notch output as f→ fCLK /2. FIGURE 1. 2nd-Order Bandpass Response

FIGURE 2. 2nd-Order Low-Pass Response

FIGURE 3. 2nd-Order High-Pass Response

FIGURE 4. 2nd-Order Notch Response

FIGURE 5. 2nd-Order All-Pass Response

2.0 Modes of Operation

discussion is based on the well known frequency domain. 1 for a summary of the characteristics of the various modes. fnotch= center frequency of the imaginary zero pair = fO . BW = the −3 dB bandwidth of the bandpass output. Note:VIN should be driven from a low impedance (<1k Ω ) source. FIGURE 6. Response of various 2nd-order filters as a function of Q. Gains and center frequencies are normalized to unity.

2.0 Modes of Operation(Continued)

FIGURE 7. MODE 1 FIGURE 8. MODE 1a

FIGURE 9. MODE 2 problem, connect a small capacitor (10 pF − 100 pF) across R4 to provide some phase lead. FIGURE 10. MODE 3

FIGURE 11. MODE 3a

FIGURE 12. MODE 4 FIGURE 13. MODE 5

Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios. Filter. Best general-purpose mode. than above if R1 =R 2 = 0.02R4. FIGURE 14. MODE 6a FIGURE 15. MODE 6b

3.0 Applications Information

The MF10 is a general-purpose dual second-order state variable filter whose center frequency is proportional to the frequency of the square wave applied to the clock input CLK ). By connecting pin 12 to the appropriate DC voltage, the filter center frequency fO can be made equal to either fCLK /100 or fCLK /50. fO can be very accurately set (within ±6%) by using a crystal clock oscillator, or can be easily varied over a wide frequency range by adjusting the clock frequency. If desired, the f CLK /fO ratio can be altered by external resistors as inFigures 9, 10, 11, 13, 14, 15. The filter Q and gain are determined by external resistors. All of the five second-order filter types can be built using either section of the MF10. These are illustrated inFigure 1 throughFigure 5along with their transfer functions and some related equations.Figure 6shows the effect of Q on the shapes of these curves. When filter orders greater than two are desired, two or more MF10 sections can be cascaded.

3.1 DESIGN EXAMPLE

In order to design a second-order filter section using the MF10, we must define the necessary values of three param- eters: f 0, the filter section’s center frequency; H0, the pass- band gain; and the filter’s Q. These are determined by the characteristics required of the filter being designed. As an example, let’s assume that a system requires a fourth-order Chebyshev low-pass filter with 1 dB ripple, unity gain at DC, and 1000 Hz cutoff frequency. As the system order is four, it is realizable using both second-order sections of an MF10. Many filter design texts include tables that list the characteristics (f O and Q) of each of the second-order filter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined above, such a table yields the following characteristics: f 0A = 529 Hz QA = 0.785 f0B = 993 Hz QB = 3.559 For unity gain at DC, we also specify: H 0A =1 H 0B =1 The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100 and a 100 kHz clock signal is available. Note that the required center frequencies for the two second-order sections will not be obtainable with clock-to-center-frequency ratios of 50 or 100. It will be nec- essary to adjust externally. FromTable 1, we see that Mode 3 can be used to produce a low-pass filter with resistor-adjustable center fre- quency. In most filter designs involving multiple second-order stages, it is best to place the stages with lower Q values ahead of stages with higher Q, especially when the higher Q is greater than 0.707. This is due to the higher relative gain at the center frequency of a higher-Q stage. Placing a stage with lower Q ahead of a higher-Q stage will provide some attenu- ation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage A has the lower Q (0.785) so it will be placed ahead of the other stage. For the first section, we begin the design by choosing a convenient value for the input resistance: R 1A = 20k. The absolute value of the passband gain HOLPA is made equal to 1 by choosing R4A such that: R4A =− HOLPA R 1A =R 1A = 20k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio, we find R 2A by: The resistors for the second section are found in a similar fashion: The complete circuit is shown inFigure 16for split±5V power supplies. Supply bypass capacitors are highly recommended. MF10 www.national.com 20

3.0 Applications Information(Continued)

FIGURE 16. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1. ±5V Power Supply. 0V–5V TTL or −5V±5V CMOS Logic Levels. FIGURE 17. Fourth-Order Chebyshev Low-Pass Filter from Example in 3.1. Should be Referred to Half-Supply or Applied through a Coupling Capacitor.

FIGURE 18. Three Ways of Generating V+/2 for Single-Supply Operation

(Continued)

3.2 SINGLE SUPPLY OPERATION

The MF10 can also operate with a single-ended power sup- ply.Figure 17shows the example filter with a single-ended power supply. VA + and VD + are again connected to the positive power supply (8V to 14V), and VA − and VD − are connected to ground. The AGND pin must be tied to V+/2 for single supply operation. This half-supply point should be very “clean”, as any noise appearing on it will be treated as an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor ( Figure 18a), or a low-impedance half-supply voltage can be made using a three-terminal voltage regulator or an operational amplifier Figure 18band Figure 18c). The passive resistor divider with a bypass capacitor is sufficient for many applications, provided that the time constant is long enough to reject any power supply noise. It is also important that the half-supply reference present a low impedance to the clock frequency, so at very low clock frequencies the regulator or op-amp approaches may be preferable because they will require smaller capacitors to filter the clock frequency. The main power supply voltage should be clean (preferably regulated) and bypassed with 0.1 µF.

3.3 DYNAMIC CONSIDERATIONS

The maximum signal handling capability of the MF10, like that of any active filter, is limited by the power supply volt- ages used. The amplifiers in the MF10 are able to swing to within about 1V of the supplies, so the input signals must be kept small enough that none of the outputs will exceed these limits. If the MF10 is operating on ±5V, for example, the outputs will clip at about 8 Vp–p. The maximum input voltage multiplied by the filter gain should therefore be less than p–p. Note that if the filter Q is high, the gain at the lowpass or highpass outputs will be much greater than the nominal filter gain ( Figure 6). As an example, a lowpass filter withaQo f 10 will have a 20 dB peak in its amplitude response at fO .I f the nominal gain of the filter HOLP is equal to 1, the gain at fO will be 10. The maximum input signal at fO must therefore be less than 800 mVp–p when the circuit is operated on±5V supplies. Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a circuit such as the notch in Mode 1 ( Figure 7). The notch output will be very small at fO , so it might appear safe to apply a large signal to the input. However, the bandpass will have its maximum gain at f O and can clip if overdriven. If one output clips, the performance at the other outputs will be degraded, so avoid overdriving any filter section, even ones whose outputs are not being directly used. Accompanying Figure 7throughFigure 15are equations labeled “circuit dynamics”, which relate the Q and the gains at the various outputs. These should be consulted to determine peak circuit gains and maximum allowable signals for a given applica- tion.

3.4 OFFSET VOLTAGE

The MF10’s switched capacitor integrators have a higher equivalent input offset voltage than would be found in a typical continuous-time active filter integrator. Figure 19 shows an equivalent circuit of the MF10 from which the output DC offsets can be calculated. Typical values for these offsets with S A/B tied to V+ are: Vos1 = opamp offset =±5m V Vos2 = −150 mV @ 50:1: −300 mV @ 100:1 Vos3 = −70 mV @ 50:1: −140 mV @ 100:1 When S A/B is tied to V−,V os2 will approximately halve. The DC offset at the BP output is equal to the input offset of the lowpass integrator (V os3). The offsets at the other outputs depend on the mode of operation and the resistor ratios, as described in the following expressions. MF10 www.national.com23

FIGURE 19. MF10 Offset Voltage Sources FIGURE 20. Method for Trimming VOS

Figure 20. This allows adjust- OS(BP) in modes 1a and 3, for example).

3.5 SAMPLED DATA SYSTEM CONSIDERATIONS

50:1 may be better as it will result in 3 dB lower output noise. the ratio with external resistors. FIGURE 21. The Sampled-Data Output Waveform

See NS Package Number M20B Order Number MF10ACN or MF10CCN See NS Package Number N20A MF10 www.national.com 26

Physical Dimensionsinches (millimeters) unless otherwise noted Molded Package (Small Outline) (M) Order Number MF10ACWM or MF10CCWM 20-Lead Molded Dual-In-Line Package (N) Order Number MF10ACN or MF10CCN MF10 www.national.com27

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com MF10 Universal Monolithic Dual Switched Capacitor Filter National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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