MPC8321EVRADDC FREESCALE | Alldatasheet
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© 2010 Freescale Semiconductor, Inc. All rights reserved. This document provides an overview of the MPC8323E PowerQUICC II Pro processor features. The MPC8323E is a cost-effective, highly integrated communications processor that addresses the requirements of several networking applications, including ADSL SOHO and residential gateways, modem/routers, industrial control, and test and measurement applications. The MPC8323E extends current PowerQUICC offerings, adding higher CPU performance, additional functionality, and faster interfaces, while addressing the requirements related to time-to-market, price, power consumption, and board real estate. This document describes the MPC8323E, and unless otherwise noted, the information also applies to the MPC8323, MPC8321E, and MPC8321. To locate published errata or updates for this document, refer to the MPC8323E product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. Document Number: MPC8323EEC Rev. 4, 09/2010
Contents
- I 19. HDLC, BISYNC, Transparent, and Synchronous MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
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DDR1/DDR2 memory controller. block diagram of the MPC8323E is shown in Figure 1. Figure 1. MPC8323E Block Diagram support for up to OC-3 speeds.
3 MII/RMII4 TDM Ports 1 UL2/8-Bit
2 Virtual
4 Channel DMA
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 3 Overview NOTE The QUICC Engine block can also support a UTOPIA level 2 capable of supporting 31 multi-PHY (MPC8323E- and MPC8323-specific). The MPC8323E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. In summary, the MPC8323E family provides users with a highly integrated, fully programmable communications processor. This helps ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements.
1.1 MPC8323E Features
Major features of the MPC8323E are as follows: High-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for A TM or IP/Ethernet packet processing (or both). MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by supporting programmable protocol termination and network interface termination to meet evolving protocol standards. Single platform architecture supports the convergence of IP packet networks and A TM networks. DDR1/DDR2 memory controller—one 32-bit interface at up to 266 MHz supporting both DDR1 and DDR2. An e300c2 core built on Power Architecture technol ogy with 16-Kbyte instruction and data caches, and dual integer units. Peripheral interfaces such as 32-bit PCI (2.2) interface up to 66-MHz operation, 16-bit local bus interface up to 66-MHz operation, and USB 2.0 (full-/low-speed). Security engine provides acceleration for c ontrol and data plane security protocols. High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration.
1.1.1 Protocols
The protocols are as follows: A TM SAR up to 155 Mbps (OC-3) full duplex, with ATM traffic shaping (ATF TM4.1) Support for ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) Support for IMA and A TM transmission convergence sub-layer A TM OAM handling features compatible with ITU-T I.610 IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing Extensive support for A TM statistics and Ethernet RMON/MIB statistics Support for 64 channels of HDLC/transparent
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
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1.1.2 Serial Interfaces
The MPC8323E serial interfaces are as follows: Support for one UL2 interface with 31 multi-PHY addresses (MPC8323E and MPC8323 only) Support for up to three 10/100 Mbps Ethernet interfaces using MII or RMII Support for up to four T1/E1/J1/E3 or DS-3 serial interfaces (TDM) Support for dual UART and SPI interfaces and a single I 2C interface
1.2 QUICC Engine Block
The QUICC Engine block is a versatile communications complex that integrates several communications peripheral controllers. It provides on-chip system design for a variety of applications, particularly in communications and networking systems. The QUICC Engine block has the following features: One 32-bit RISC controller for flexible support of the communications peripherals Serial DMA channel for receive and transmit on all serial channels Five universal communication controllers (U CCs) supporting the following protocols and interfaces (not all of them simultaneously): — 10/100 Mbps Ethernet/IEEE 802.3® standard — IP support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing — A TM protocol through UTOPIA interface (note that the MPC8321 and MPC8321E do not support the UTOPIA interface) — HDLC /transparent up to 70-Mbps full-duplex — HDLC bus up to 10 Mbps — Asynchronous HDLC — UART — BISYNC up to 2 Mbps — QUICC multi-channel controller (QMC) for 64 TDM channels One UTOPIA interface (UPC1) supporting 31 multi-PHYs (MPC8323E- and MPC8323-specific) Two serial peripheral interfaces (SPI). SPI 2 is dedicated to Ethernet PHY management. Four TDM interfaces Thirteen independent baud rate generators and 19 input clock pins for supplying clocks to UCC serial channels Four independent 16-bit timers that can be interconnected as two 32-bit timers The UCCs are similar to the PowerQUICC II peripherals: SCC (BISYNC, UART, and HDLC bus) and FCC (fast Ethernet, HDLC, transparent, and ATM).
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 5 Overview
1.3 Security Engine
The security engine is optimized to handle all the algorithms associated with IPSec, IEEE 802.11i™ standard, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are: Data encryption standard execution unit (DEU), supporting DES and 3DES Advanced encryption standard unit (AESU), supporting AES Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any algorithm One crypto-channel supporting multi-command descriptor chains
1.4 DDR Memory Controller
The MPC8323E DDR1/DDR2 memory controller includes the following features: Single 32-bit interface supporting both DDR1 and DDR2 SDRAM Support for up to 266-MHz data rate Support for two ×16 devices Support for up to 16 simultaneous open pages Supports auto refresh On-the-fly power management using CKE 1.8-/2.5-V SSTL2 compatible I/O Support for 1 chip select only FCRAM, ECC, hardware/software calibration, bit deskew, QIN stage, or atomic logic are not supported.
1.5 PCI Controller
The MPC8323E PCI controller includes the following features: PCI Specification Revision 2.3 compatible Single 32-bit data PCI interface operates up to 66 MHz PCI 3.3-V compatible (not 5-V compatible) Support for host and agent modes On-chip arbitration, supporting three external masters on PCI Selectable hardware-enforced coherency
1.6 Programmable Interrupt Controller (PIC)
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible solution for general-purpose interrupt control. The PIC programming model is compatible with the MPC8260 interrupt controller, and it supports 8 external and 35 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller.
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
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Electrical Characteristics
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8323E. The MPC8323E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1 Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings 1
- Functional and tested operating conditions are given in Ta bl e 2. Absolute maximum ratings are stress ratings only, and
permanent damage to the device.
- Caution: MVIN must not exceed GVDD by more than 0.3 V . This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
- Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 7
2.1.2 Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8323E. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8323E Figure 2. Overshoot/Undershoot Voltage for GV DD/OVDD Table 2. Recommended Operating Conditions 3
1.8 V ± 90 mV
- GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative
- Minimum temperature is specified with TA; maximum temperature is specified with T J.
- All IO pins should be interfaced with peripherals operating at same voltage level.
- This voltage is the input to the filter discussed in Section 24.2, “PLL Power Supply Filtering” and not necessarily the voltage
at the AVDD pin, which may be reduced due to voltage drop across the filter.
- tinterface refers to the clock period associated with the bus clock interface.
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
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2.1.3 Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
2.1.4 Input Capacitance Specification
Table 4 describes the input capacitance for the CLKIN pin in the MPC8323E.
2.2 Power Sequencing
The device does not require the core supply voltage (VDD) and IO supply voltages (GVDD and OVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input and output pins are actively driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating PORESET. Note that there is no specific power down sequence requirement for the device. I/O voltage supplies (GVDD and OVDD) do not have any ordering requirements with respect to one another. Table 3. Output Drive Capability Table 4. Input Capacitance Specification
- The external clock generator should be able to drive 10 pF .
Figure 3. MPC8323E Power-Up Sequencing Example
3 Power Characteristics
The estimated typical power dissipation for this family of MPC8323E devices is shown in Table 5. Table 6 shows the estimated typical I/O power dissipation for the device. Table 5. MPC8323E Power Dissipation
- The values do not include I/O supply power (OV DD and GVDD) or AVDD. For I/O power values, see Table 6.
- Typical power is based on a nominal voltage of VDD = 1.0 V , ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the MPC8323MDS evaluation board using WC process s ilicon.
- Maximum power is based on a voltage of V DD = 1.07 V, WC process, a junction TJ = 110°C, and an artificial smoke test.
Table 6. Estimated Typical I/O Power Dissipation
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conditions and ambient temperature).
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8323E.
4.1 DC Electrical Characteristics
Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8323E. Table 7. CLKIN DC Electrical Characteristics Table 6. Estimated Typical I/O Power Dissipation (continued)
4.2 AC Electrical Characteristics
(CLKIN/PCI_CLK) AC timing specifications for the MPC8323E.
5 RESET Initialization
Table 8. CLKIN AC Timing Specifications
- Caution: The system, core, security, and QUICC Engine block must not exceed their respective maximum or minimum
- Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V .
- Timing is guaranteed by design and characterization.
- This represents the total input jitter—short term and long term—and is guaranteed by design.
- The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter. Table 9. RESET Initialization Timing Specifications Table 7. CLKIN DC Electrical Characteristics (continued)
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Table 10 provides the PLL lock times.
5.1 Reset Signals DC Electrical Characteristics
Table 11 provides the DC electrical characteristics for the MPC8323E reset signals mentioned in Table 9.
- tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8323E is In PCI host mode the
MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.
- tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8323E is in PCI host mode. See
the MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.
- POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV .
Table 10. PLL Lock Times Table 11. Reset Signals DC Electrical Characteristics Table 9. RESET Initialization Timing Specifications (continued)
6 DDR1 and DDR2 SDRAM
Dn_GVDD(typ) = 1.8 V. The AC electrical specifications are the same for DDR1 and DDR2 SDRAM.
6.1 DDR1 and DDR2 SDRAM DC Electrical Characteristics
MPC8323E when Dn_GVDD(typ) = 1.8 V. Table 13 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V .
- This specification applies when operating from 3.3 V supply.
Table 12. DDR2 SDRAM DC Electrical Characteristics for D n_GVDD(typ) = 1.8 V
- Dn_GVDD is expected to be within 50 mV of the DRAM D n_GVDD at all times.
- MVREFnREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREFnREF may not exceed ±2% of the DC value.
- VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREFnREF. This rail should track variations in the DC level of MVREF nREF.
- Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD.
Table 13. DDR2 SDRAM Capacitance for D n_GVDD(typ) = 1.8 V Table 11. Reset Signals DC Electrical Characteristics (continued)
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MPC8323E when Dn_GVDD(typ) = 2.5 V . Table 15 provides the DDR1 capacitance Dn_GVDD(typ) = 2.5 V .
- This parameter is sampled. D n_GVDD = 1.8 V ± 0.090 V , f = 1 MHz, TA =2 5° C , VOUT = Dn_GVDD ÷ 2,
VOUT (peak-to-peak) = 0.2 V. Table 14. DDR1 SDRAM DC Electrical Characteristics for D n_GVDD(typ) = 2.5 V
- Dn_GVDD is expected to be within 50 mV of the DRAM D n_GVDD at all times.
- MVREFnREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREFnREF may not exceed ±2% of the DC value.
- VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREFnREF. This rail should track variations in the DC level of MVREF nREF.
- Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD.
Table 15. DDR1 SDRAM Capacitance for D n_GVDD(typ) = 2.5 V Interface
- This parameter is sampled. D n_GVDD = 2.5 V ± 0.125 V , f = 1 MHz, TA = 25° C, VOUT = Dn_GVDD ÷ 2,
VOUT (peak-to-peak) = 0.2 V .
6.2 DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR1 and DDR2 SDRAM interface.
6.2.1 DDR1 and DDR2 SDRAM Input AC Timing Specifications
Table 16 provides the input AC timing specifications for the DDR2 SDRAM (Dn_GVDD(typ) = 1.8 V). Table 17 provides the input AC timing specifications for the DDR1 SDRAM (Dn_GVDD(typ) = 2.5 V). Table 18 provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface. Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions with D n_GVDD of 1.8 ± 5%. Table 17. DDR1 SDRAM Input AC Timing Specifications for 2.5 V Interface At recommended operating conditions with D n_GVDD of 2.5 ± 5%. Table 18. DDR1 and DDR2 SDRAM Input AC Timing Specifications At recommended operating conditions with D n_GVDD of (1.8 or 2.5 V) ± 5%.
266 MHz
200 MHz
- tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
- The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t DISKEW. This can be
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Figure 4 shows the input timing diagram for the DDR controller. Figure 4. DDR Input Timing Diagram
6.2.2 DDR1 and DDR2 SDRAM Output AC Timing Specifications
Table 19 provides the output AC timing specifications for the DDR1 and DDR2 SDRAM interfaces. Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications At recommended operating conditions with D n_GVDD of (1.8 or 2.5 V) ± 5%.
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
- All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V .
- ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD
description and understanding of the timing modifications enabled by use of these bits.
- Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data
mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
- All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t DDKHMP follows the
symbol conventions described in note 1. Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with D n_GVDD of (1.8 or 2.5 V) ± 5%.
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Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 5. Timing Diagram for t DDKHMH Figure 6 shows the DDR1 and DDR2 SDRAM output timing diagram. Figure 6. DDR1 and DDR2 SDRAM Output Timing Diagram
7.1 DUART DC Electrical Characteristics
Table 20 provides the DC electrical characteristics for the DUART interface of the MPC8323E.
7.2 DUART AC Electrical Specifications
Table 21 provides the AC timing parameters for the DUART interface of the MPC8323E.
8 Ethernet and MII Management
This section provides the AC and DC electrical characteristics for Ethernet and MII management.
8.1 Ethernet Controller (10/100 Mbps)—MII/RMII Electrical
Table 20. DUART DC Electrical Characteristics
- Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Ta ble 1 and Ta ble 2.
Table 21. DUART AC Timing Specifications
- Actual attainable baud rate is limited by the latency of interrupt processing.
- The middle of a start bit is detected as the 8
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8.1.1 DC Electrical Characteristics
All MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 22.
8.2 MII and RMII AC Timing Specifications
The AC timing specifications for MII and RMII are presented in this section.
8.2.1 MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1 MII Transmit AC Timing Specifications
Table 23 provides the MII transmit AC timing specifications. Table 22. MII and RMII DC Electrical Characteristics Table 23. MII Transmit AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 10%.
Figure 7 shows the MII transmit AC timing diagram. Figure 7. MII Transmit AC Timing Diagram
8.2.1.2 MII Receive AC Timing Specifications
Table 24 provides the MII receive AC timing specifications.
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. used with the appropriate letter: R (rise) or F (fall). Table 24. MII Receive AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 10%. Table 23. MII Transmit AC Timing Specifications (continued) At recommended operating conditions with OVDD of 3.3 V ± 10%.
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Figure 8 provides the AC test load. Figure 8. AC Test Load Figure 9 shows the MII receive AC timing diagram. Figure 9. MII Receive AC Timing Diagram
8.2.2 RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
with the appropriate letter: R (rise) or F (fall). Table 24. MII Receive AC Timing Specifications (continued) At recommended operating conditions with OVDD of 3.3 V ± 10%.
8.2.2.1 RMII Transmit AC Timing Specifications
Table 23 provides the RMII transmit AC timing specifications. Figure 10 shows the RMII transmit AC timing diagram. Figure 10. RMII Transmit AC Timing Diagram
8.2.2.2 RMII Receive AC Timing Specifications
Table 24 provides the RMII receive AC timing specifications. Table 25. RMII Transmit AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 10%.
- The symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for
convention is used with the appropriate letter: R (rise) or F (fall). Table 26. RMII Receive AC Timing Specifications At recommended operating conditions with OVDD of 3.3 V ± 10%.
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Figure 11 provides the AC test load. Figure 11. AC Test Load Figure 12 shows the RMII receive AC timing diagram. Figure 12. RMII Receive AC Timing Diagram
8.3 Ethernet Management Interface Electrical Characteristics
- The symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for
the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time. convention is used with the appropriate letter: R (rise) or F (fall). Table 26. RMII Receive AC Timing Specifications (continued) At recommended operating conditions with OVDD of 3.3 V ± 10%.
8.3.1 MII Management DC Electrical Characteristics
MDIO and MDC are provided in Table 27.
8.3.2 MII Management AC Electrical Specifications
Table 28 provides the MII management AC timing specifications. Table 27. MII Management DC Electrical Characteristics When Powered at 3.3 V Table 28. MII Management AC Timing Specifications At recommended operating conditions with OVDD is 3.3 V ± 10%.
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
data timing (MD) for the time t MDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. convention is used with the appropriate letter: R (rise) or F (fall).
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Figure 13 shows the MII management AC timing diagram. Figure 13. MII Management Interface Timing Diagram
9 Local Bus
9.1 Local Bus DC Electrical Characteristics
Table 29 provides the DC electrical characteristics for the local bus interface.
9.2 Local Bus AC Electrical Specifications
Table 30 describes the general timing parameters of the local bus interface of the MPC8323E. Table 29. Local Bus DC Electrical Characteristics Table 30. Local Bus General Timing Parameters
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Figure 15 through Figure 17 show the local bus signals. Figure 15. Local Bus Signals, Nonspecial Signals Only Figure 16. Local Bus Sign als, GPCM/UPM Signals for LCRR[CLKDIV] = 2
Figure 17. Local Bus Sign als, GPCM/UPM Signals for LCRR[CLKDIV] = 4
10 JTAG
10.1 JTAG DC Electrical Characteristics
Table 31. JTAG Interface DC Electrical Characteristics
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10.2 JTAG AC Electrical Characteristics
Table 32. JTAG AC Timing Specifications (Independent of CLKIN) 1 At recommended operating conditions (see Ta ble 2). Table 31. JTAG Interface DC Electrical Characteristics (continued)
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Figure 21 provides the boundary-scan timing diagram. Figure 21. Boundary-Scan Timing Diagram Figure 22 provides the test access port timing diagram. Figure 22. Test Access Port Timing Diagram
11 I 2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8323E.
11.1 I 2C DC Electrical Characteristics
Table 33 provides the DC electrical characteristics for the I2C interface of the MPC8323E.
11.2 I 2C AC Electrical Specifications
Table 34 provides the AC timing parameters for the I2C interface of the MPC8323E. Table 33. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 10%.
- Output voltage (open drain or open collector) condition = 3 mA sink current.
B = capacitance of one bus line in pF .
- Refer to the MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for information on the
- I/O pins obstructs the SDA and SCL lines if OV DD is switched off.
Table 34. I2C AC Electrical Specifications All values refer to VIH (min) and VIL (max) levels (see Ta ble 33).
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Figure 23 provides the AC test load for the I2C. Figure 23. I2C AC Test Load Figure 24 shows the AC timing diagram for the I2C bus. Figure 24. I2C Bus AC Timing Diagram
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
letter: R (rise) or F (fall).
- MPC8323E provides a hold time of at least 300 ns for the SDA signal (referred to the V IH(min) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
- The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (t I2CL) of the SCL signal.
- CB = capacitance of one bus line in pF .
Table 34. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Ta ble 33).
12 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8323E.
12.1 PCI DC Electrical Characteristics
Table 35 provides the DC electrical characteristics for the PCI interface of the MPC8323E.
12.2 PCI AC Electrical Specifications
is configured as a host or agent device. Table 36 shows the PCI AC timing specifications at 66 MHz. Table 35. PCI DC Electrical Characteristics 1,2
- Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Ta ble 1 and Ta ble 2.
- Ranges listed do not meet the full range of the DC specifications of the PCI 2.3 Local Bus Specifications.
Table 36. PCI AC Timing Specifications at 66 MHz
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
(R) went high (H) relative to the frame signal (F) going to the valid (V) state.
- See the timing measurement conditions in the PCI 2.3 Local Bus Specifications .
- For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
- Input timings are measured at the pin.
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Table 37 shows the PCI AC timing specifications at 33 MHz. Figure 25 provides the AC test load for PCI. Figure 25. PCI AC Test Load Figure 26 shows the PCI input AC timing conditions. Figure 26. PCI Input AC Timing Measurement Conditions Table 37. PCI AC Timing Specifications at 33 MHz
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
(R) went high (H) relative to the frame signal (F) going to the valid (V) state.
- See the timing measurement conditions in the PCI 2.3 Local Bus Specifications .
- For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
- Input timings are measured at the pin.
Figure 27 shows the PCI output AC timing conditions. Figure 27. PCI Output AC Timing Measurement Condition
13 Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8323E.
13.1 Timer DC Electrical Characteristics
13.2 Timer AC Timing Specifications
Table 39 provides the timer input and output AC timing specifications. Table 38. Timer DC Electrical Characteristics Table 39. Timer Input AC Timing Specifications 1
- Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
- Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any
external synchronous logic. Timer inputs are required to be valid for at least t TIWID ns to ensure proper operation.
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Figure 28 provides the AC test load for the timers. Figure 28. Timers AC Test Load
14 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8323E.
14.1 GPIO DC Electrical Characteristics
Table 11 provides the DC electrical characteristics for the MPC8323E GPIO.
14.2 GPIO AC Timing Specifications
Table 41 provides the GPIO input and output AC timing specifications. Table 40. GPIO DC Electrical Characteristics
- This specification applies when operating from 3.3-V supply.
Table 41. GPIO Input AC Timing Specifications 1
- Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
- GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least t PIWID ns to ensure proper operation.
Figure 29 provides the AC test load for the GPIO. Figure 29. GPIO AC Test Load
15 IPIC
15.1 IPIC DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the external interrupt pins of the MPC8323E.
15.2 IPIC AC Timing Specifications
Table 43 provides the IPIC input and output AC timing specifications. Table 42. IPIC DC Electrical Characteristics 1,2
- This table applies for pins IRQ [0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts.
- IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins.
Table 43. IPIC Input AC Timing Specifications 1
- Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
- IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
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16 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8323E.
16.1 SPI DC Electrical Characteristics
Table 44 provides the DC electrical characteristics for the MPC8323E SPI.
16.2 SPI AC Timing Specifications
Table 45 and provide the SPI input and output AC timing specifications. Figure 30 provides the AC test load for the SPI. Figure 30. SPI AC Test Load Table 44. SPI DC Electrical Characteristics Table 45. SPI AC Timing Specifications 1
- Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
Figure 31 shows the SPI timing in slave mode (external clock). Figure 31. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 32 shows the SPI timing in master mode (internal clock). Figure 32. SPI AC Timing in Master Mode (Internal Clock) Diagram
17 TDM/SI
17.1 TDM/SI DC Electrical Characteristics
Table 46 provides the DC electrical characteristics for the MPC8323E TDM/SI. Table 46. TDM/SI DC Electrical Characteristics Note: The clock edge is selectable on SPI. Note: The clock edge is selectable on SPI.
42 Freescale Semiconductor
17.2 TDM/SI AC Timing Specifications
Table 47 provides the TDM/SI input and output AC timing specifications. Figure 33 provides the AC test load for the TDM/SI. Figure 33. TDM/SI AC Test Load Figure 34. TDM/SI AC Timing (External Clock) Diagram Table 47. TDM/SI AC Timing Specifications 1
- Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
Table 46. TDM/SI DC Electrical Characteristics (continued) Note: The clock edge is selectable on TDM/SI.
18 UTOPIA
This section describes the UTOPIA DC and AC electrical specifications of the MPC8323E. The MPC8321E and MPC8321 do not support UTOPIA.
18.1 UTOPIA DC Electrical Characteristics
Table 48 provides the DC electrical characteristics for the MPC8323E UTOPIA.
18.2 UTOPIA AC Timing Specifications
Table 49 provides the UTOPIA input and output AC timing specifications. Table 48. UTOPIA DC Electrical Characteristics Table 49. UTOPIA AC Timing Specifications 1
- Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
44 Freescale Semiconductor
Figure 35 provides the AC test load for the UTOPIA. Figure 35. UTOPIA AC Test Load Figure 36 shows the UTOPIA timing with external clock. Figure 36. UTOPIA AC Timing (External Clock) Diagram Figure 37 shows the UTOPIA timing with internal clock. Figure 37. UTOPIA AC Timing (Internal Clock) Diagram
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 45 HDLC, BISYNC, Transparent, and Synchronous UART
19 HDLC, BISYNC, Transparent, and Synchronous
This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BISYNC, transparent, and synchronous UART of the MPC8323E.
19.1 HDLC, BISYNC, Transparent, and Synchronous UART DC
Table 50 provides the DC electrical characteristics for the MPC8323E HDLC, BISYNC, transparent, and synchronous UART protocols.
19.2 HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
Table 51 provides the input and output AC timing specifications for HDLC, BISYNC, and transparent UART protocols. Table 50. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications 1
46 Freescale Semiconductor
Figure 38 provides the AC test load. Figure 38. AC Test Load
- Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 52. Synchronous UART AC Timing Specifications 1
- Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications 1 (continued)
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20 USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8323E.
20.1 USB DC Electrical Characteristics
Table 53 provides the DC electrical characteristics for the USB interface.
20.2 USB AC Electrical Specifications
Table 54 describes the general timing parameters of the USB interface of the MPC8323E. Figure 41 provide the AC test load for the USB. Figure 41. USB AC Test Load Table 53. USB DC Electrical Characteristics 1
- Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Ta ble 1 and Table 2.
Table 54. USB General Timing Parameters
- The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(state)(signal) for receive signals
transmit signals skew (TS) between TXP and TXN (PN).
- Skew measurements are done at OV DD/2 of the rising or falling edge of the signals.
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 49 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8323E is available in a thermally enhanced Plastic Ball Grid Array (PBGA); see Section 21.1, “Package Parameters for the MPC8323E PBGA,” and Section 21.2, “Mechanical Dimensions of the MPC8323E PBGA,” for information on the PBGA.
21.1 Package Parameters for the MPC8323E PBGA
The package parameters are as provided in the following list. The package type is 27 mm × 27 mm, 516 PBGA. Package outline 27 mm × 27 mm Interconnects 516 Pitch 1.00 mm Module height (typical) 2.25 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZQ package) 95.5 Sn/0.5 Cu/4Ag (VR package) Ball diameter (typical) 0.6 mm
21.2 Mechanical Dimensions of the MPC8323E PBGA
Figure 42 shows the mechanical dimensions and bottom surface nomenclature of the MPC8323E, 516-PBGA package.
50 Freescale Semiconductor
1.All dimensions are in millimeters. 2.Dimensions and tolerances per ASME Y14.5M-1994. 3.Maximum solder ball diameter measured parallel to datum A. 4.Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 42. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8323E PBGA
21.3 Pinout Listings
Table 55 shows the pin list of the MPC8323E. Table 55. MPC8323E PBGA Pinout Listing
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Table 55. MPC8323E PBGA Pinout Listing (continued)
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- This pin is an open drain signal. A weak pull-up resistor (1 k Ω) should be placed on this pin to OV
- This pin is an open drain signal. A weak pull-up resistor (2–10 k Ω) should be placed on this pin to OVDD.
- This output is actively driven during reset rather than being three-stated during reset.
- These JTAG and local bus pins have weak internal pull-up P-FETs that are always enabled.
- This pin should have a weak pull up if the chip is in PCI host mode. Follow the PCI specification’s recommendation.
has weak internal pull-up yet it is recommended to apply an external pull-up.
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22 Clocking
Figure 43 shows the internal distribution of clocks within the MPC8323E. Figure 43. MPC8323E Clock Subsystem on whether the device is configured in PCI host or PCI agent mode, respectively.
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 65 Clocking
22.1 Clocking in PCI Host Mode
When the MPC8323E is configured as a PCI host device (RCWH[PCIHOST] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the PCI_SYNC_OUT and PCI_CLK_OUT multiplexors. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system.
22.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:2])
When the MPC8323E is configured as a PCI host, it provides three separate clock output signals, PCI_CLK_OUT[0:2], for external PCI agents. When the device comes out of reset, the PCI clock outputs are disabled and are actively driven to a steady low state. Each of the individual clock outputs can be enabled (enable toggling of the clock) by setting its corresponding OCCR[PCICOEn] bit. All output clocks are phase-aligned to each other.
22.2 Clocking in PCI Agent Mode
When the MPC8323E is configured as a PCI agent device, PCI_CLK is the primary input clock. In agent mode, the CLKIN signal should be tied to GND, and the clock output signals, PCI_CLK_OUTn and PCI_SYNC_OUT, are not used.
22.3 System Clock Domains
As shown in Figure 43, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create three major clock domains: The coherent system bus clock ( csb_clk) The QUICC Engine clock ( ce_clk) The internal clock for the DDR controller ( ddr_clk) The internal clock for the local bus controller ( lb_clk) The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = [PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)] × SPMF In PCI host mode, PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV) is the CLKIN frequency. The csb_clk serves as the clock input to the e300c2 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. See the “Reset Configuration” section in the MPC8323E PowerQUICC II Pro Communications Processor Reference Manual for more information.
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The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk. is the same frequency as ddr_clk. PowerQUICC II Pro Communications Processor Reference Manual for more information. II Pro Communications Processor Reference Manual for a detailed description. Table 56. Configurable Clock Units Table 57. Operating Frequencies for PBGA
22.4 System PLL Configuration
encodings for the system PLL. frequency is in the range of 300–600 MHz. LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2 The DDR1/DDR2 data rate is 2× the DDR1/DDR2 memory bus frequency. csb_clk frequency (depending on RCWL[LBCM]). Table 58. System PLL Multiplication Factors
0000 Reserved
0001 Reserved
Table 57. Operating Frequencies for PBGA (continued)
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Table 59. CSB Frequency Options
1 CFG_CLKIN_DIV_B is only used for host mode; CLKIN must be tied low and
CFG_CLKIN_DIV_B must be pulled up (high) in agent mode. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
22.5 Core PLL Configuration
in Table 60 should be considered reserved. core VCO frequency is in the range of 500–800 MHz. Table 60. e300 Core PLL Configuration
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22.6 QUICC Engine PLL Configuration
shows the multiplication factor encodings for the QUICC Engine PLL. The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in Table 62. QUICC Engine frequency is not restricted by the CSB and core frequencies. according to the performance requirements. Table 61. QUICC Engine PLL Multiplication Factors Table 62. QUICC Engine PLL VCO Divider
11 Reserved
22.7 Suggested PLL Configurations
common input clock. Table 63 shows suggested PLL configurations for 33, 25, and 66 MHz input clocks.
23 Thermal
This section describes the thermal specifications of the MPC8323E.
23.1 Thermal Characteristics
Table 64 provides the package thermal characteristics for the 516 27 × 27 mm PBGA of the MPC8323E. Table 63. Suggested PLL Configurations Table 64. Package Thermal Characteristics for PBGA
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23.2 Thermal Management Information
For the following sections, PD = (VDD × IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers.
23.2.1 Estimation of Junction Temperature with Junction-to-Ambient
planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible.
23.2.2 Estimation of Junction Temperature with Junction-to-Board
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
- Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
- Per JEDEC JESD51-6 with the board horizontal.
- Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
- Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 64. Package Thermal Characteristics for PBGA (continued)
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 73 Thermal (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB × PD) where: TJ = junction temperature (°C) TB = board temperature at the package perimeter (°C) RθJB = junction-to-board thermal resistance (°C/W) per JESD51-8 PD = power dissipation in package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
23.2.3 Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TJ = junction temperature (°C) TT = thermocouple temperature on top of package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
23.2.4 Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink is required to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case to ambient thermal resistance: R θJA = RθJC + RθCA
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
74 Freescale Semiconductor
where: RθJA = junction-to-ambient thermal resistance (°C/W) RθJC = junction-to-case thermal resistance (°C/W) RθCA = case-to-ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. Heat sink vendors include the following list: Aavid Thermalloy 603-224-9988 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 408-567-8082 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) 408-436-8770 Loroco Sites
671 East Brokaw Road
San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics 800-522-2800 Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 75 Thermal Wakefield Engineering 603-635-5102 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com Interface material vendors include the following: Chomerics, Inc. 781-935-4850 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation 800-248-2481 Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 800-347-4572 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com
23.3 Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force. If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements.
23.3.1 Experimental Determination of the Junction Temperature with a
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
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interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. TJ = TC + (RθJC × PD) where: TC = case temperature of the package (°C) RθJC = junction-to-case thermal resistance (°C/W) PD = power dissipation (W)
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8323E.
24.1 System Clocking
The MPC8323E includes three PLLs. The system PLL (A V DD2) generates the system clock from the externally supplied CLKIN input. The frequency ratio between the system and CLKIN is selected using the system PLL ratio configuration bits as described in Section 22.4, “System PLL Configuration.” The e300 core PLL (A V DD3) generates the core clock as a slave to the system clock. The frequency ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio configuration bits as described in Section 22.5, “Core PLL Configuration.” The QUICC Engine PLL (A V DD1) which uses the same reference as the system PLL. The QUICC Engine block generates or uses external sources for all required serial interface clocks.
24.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The voltage level at each A VDDn pin should always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent filter circuits as illustrated in Figure 44, one to each of the five A VDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor.
pin, which is on the periphery of package, without the inductance of vias. Figure 44 shows the PLL power supply filter circuit. Figure 44. PLL Power Supply Filter Circuit
24.3 Decoupling Recommendations
power surges and high frequency noise in its power supply, especially while driving large capacitive loads. placed directly under the device using a standard escape pattern. Others may surround the part. capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. feeding the VDD, OVDD, and GVDD planes, to enable quick recharging of the smaller chip capacitors. to minimize inductance. Suggested bulk capacitors—100–330 µF (A VX TPS tantalum or Sanyo OSCON).
24.4 Connection Recommendations
should be connected to GND. All NC (no-connect) signals must remain unconnected.
24.5 Output Buffer DC Impedance
is a push-pull single-ended driver type (open drain for I2C).
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output impedance is the average of two components, the resistances of the pull-up and pull-down devices. other in value. Then, Z0 = (RP + RN)/2. Figure 45. Driver Impedance Measurement Rterm × (V1/V2 – 1). The drive current is then Isource =V 1/Rsource.
24.6 Configuration Pin Multiplexing
configuration pins). These pins are generally used as output only pins in normal operation. Table 65. Impedance Characteristics Note: Nominal supply voltages. See Ta ble 1, Tj = 105°C.
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 79
Ordering Information
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured.
24.7 Pull-Up Resistor Requirements
The MPC8323E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins including I2C pins, Ethernet Management MDIO pin, and IPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, see AN3361, “MPC8321E/MPC8323E PowerQUICC Design Checklist,” Rev. 1. This section presents ordering information for the devices discussed in this document, and it shows an example of how the parts are marked. Ordering information for the devices fully covered by this document is provided in Section 25.1, “Part Numbers Fully Addressed by This Document.”
25.1 Part Numbers Fully Addressed by This Document
Table 66 provides the Freescale part numbering nomenclature for the MPC8323E family. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the maximum processor core frequency, the part numbering scheme also includes the maximum effective DDR memory speed and QUICC Engine bus frequency. Each part number also contains a revision code which refers to the die mask revision number. Table 66. Part Numbering Nomenclature
- Contact local Freescale office on availability of parts with C temperature r ange.
- See Section 21, “Package and Pin Listings,” for more information on available package types.
- Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification
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25.2 Part Marking
Parts are marked as in the example shown in Figure 46. Figure 46. Freescale Part Marking for PBGA Devices
26 Document Revision History
Table 67 provides a revision history for this hardware specification. Table 67. Document Revision History 4 09/2010 Replaced all instances of “LCCR” with “LCRR” throughout. 3 12/2009 Removed references for note 4 from Table 1. Added Figure 2 in Section 2.1.2, “Power Supply Voltage Specification. Added symbol T A in Ta bl e 2. Added footnote 2 in Table 2. Added a note in Section 4, “Clock Input Timing for rise/fall time of QE input pins. Modified CLKIN, PCI_CLK rise/fall time parameters in Ta ble 8. Modified min value of tMCK in Table 19. Modified formula for ce_clk calculation in Section 22.3, “System Clock Domains. Added a note in Section 22.4, “System PLL Configuration. Removed the signal ECID_TMODE_IN from Ta ble 5 5. Removed all references of RST signals from Ta ble 55. ATWL YYWW is the traceability code. YWWLAZ is the assembly traceability code.
Voltage Specification,” and footnotes 4 and 5 from Table 1. Corrected QUIESCE signal to be an output signal in Ta bl e 5 5. Added column for GVDD (1.8 V) - DDR2 - to Table 6 with 0.212-W typical power dissipation. Added Figure 4 DDR input timing diagram. Removed CE_TRB* and CE_PIO* signals from Ta ble 5 5. Added row in Ta ble 2 stating junction temperature range of 0 to 105C. C. Modified Section 2.2, “Power Sequencing,” to include PORESET requirement. 1 6/2007 Correction to descriptive text in Section 2.2.
Document Number: MPC8323EEC Rev. 4 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
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