MCZ5203SE SHINDENGEN | Alldatasheet
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ELECTRIC MFG.CO.,LTD - 1 - Confidential MCZ5203SE APPLICATION NOTE MAR, 2012 Ver1.0
ELECTRIC MFG.CO.,LTD - 2 - Confidential Cautions for Use Thank you for purchasing our products. This manual contains important information on the safe use of our products. Your safety is of the utmost importance to us. Please read these instructions carefully before using our products. The following symbols mean: ! Warning Improper use of the products can result in death, serious injury, or expensive damage to equipment. ! Caution Improper use of the products can result in minor injuries or damage to equipment. Warning Warning Although we are constantly making every effort to improve the quality and reliability of our products, there nevertheless remains a certain probability that the semiconductor products may occasionally fail or malfunction. Please take careful precautions against product failures or malfunctions to avoid any injuries, fire accidents or social loss by implementing safety designs such as redundancy designs, designs for fire spread prevention, and designs for preventing malfunctions. Our semiconductor products listed in this document are not designed or ma nufactured to be used in devices or systems requiring extremely high levels of quality and reliability, or the failure or malfunction of which may directly threaten human lives or cause injury. In the cases where the products are to be used in devices or systems for special applications or devices or systems for specialized applications shown below, always make sure to consult us in advance. Special Applications Transportation devices (automotive, marine, etc.), communication devices for core network, traffic signal devices, fire prevention/anticrime devices, various safety devices, medical devices, etc. Specialized Applications Nuclear power control systems, aircraft and aerospace devices, submarine relay devices, and systems for preserving life, etc. Even if it is not for a special or specialized application, when IC products are to be used for devices or systems that are desired to last for a long period under continuous operation, please make sure to consult us in advance. Caution Caution Caution Caution Caution Do not attempt under any conditions to repair or mod ify IC products by yourself. Doing so could result in electric shock, device breakage, fire, and malfunction. When an abnormal condition occurs, an excessive voltage or under voltage may be generated across the output terminals of the circuit. Install preventative measures (e.g. over-voltage protection, over-current protection) for the device by considering the possibility of a malfunction and/or breakage of a load in an abnormal condition. Do not switch on the circuit before confirming the proper connec tion and polarity of input and output terminals as an erroneous connection may cause breakage of the protection device or smoke/fire. Do not use the circuit beyond the rated input voltage and install a protection device on the input rail to prevent smoke/fire that may be caused from an abnormal condition. If a breakdown or other abnormal condition occurs during the use of the device, immediately stop power to the device and consult us at your earliest possible convenience.
- We reserve the right to make any changes to the contents of this manual without prior notice in accordance with modifications to IC products.
- Details of specifications should be exchanged at the adoption of the IC products.
- All information included in this manual is believed to be accurate and reliable. However, our company takes no responsibility for any injury or damage incurred when using the IC products as described in this manual. Neither do we take any responsibility for issues arising from infringement of patent or other rights caused by using this manual.
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- No part of this manual may be reproduced or copied without the specific written consent of Shindengen Electric Mfg. Co., Ltd. We are happy to provide circuit design support for safe use of the IC. Please consult our sales representative . MCZ5203SE Standard Power Supply
ELECTRIC MFG.CO.,LTD - 3 - Confidential Index 1 : General description 1.1: Features 4 1.2: Block diagram (SOP22) 4 1.3: Pin assignment 5 1.4: Functions 5 1.5: Application circuits 6 2 : Symmetric LLC converter Operating description 2.1: Features 7 2.2: Fundamental circuitry 7 2.3: Operating waveform example 7 2.4: Control characteristics 8 2.5: Major parameters and components 8 2.6: IC operation 9 - 10 3 : Selecting peripheral components 3.1: Oscillator（Rt） 11 3.2: Vsense brown-out protection（RvsenseL） 12 3.3: Soft start（Css） 12-13 3.4: OCP （Rocpdet/RocpL） 13-14 3.5: di/dt protection 14 3.6: Timer latch protection（CTimer） 15 3.7: High side floating Vcc (VB) 16 3.8: Gate driver 16 4 : Circuit diagram 4.1: Typical circuit example 17 5 : Dimensions 5.1: SOP22 (MCZ5203SE) 18
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1 General description
MCZ5203 is an advanced symmetric LLC current resonant mode controller for bridge converter. Bulit-in high voltage direct gate drivers, control circuit and optimized protections allow simplified and space/cost-saving design of power supplies for : Large screen flat panel TVs (PDP / LCD ) PSU Laser printer PSU High power adapters
1.1 Features
- Robust 600V gate driver directly drives high side Switch. 2. Optimized gate drive capability minimizes the number of components for gate drive circuit. 3. Optimized protective functions (OCP/burst/Timer delayed latch/Thermal) for LLC converter 4. Advanced ZVS boundary chaser (capacitive mode protection) eliminates below resonant (capacitive di/dt) operation. 5. OCP operates by detecting peak primary current with 0.345V / threshold. 6. Vcc supplies up to 35V with 13.5V/8.4V UVLO 7. Built-in voltage regulator of 10V for gate driver 8. Independent high side / low side Gate driver UVLO with hysterisis 9. Adjustable soft starting function 10. Anti-di/dt startup function eliminates improper startup of Non ZVS operation 11. Optimized brown out protection
1.2 Block diagram （SOP22）
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1.3 Pin assignment
1.4 Functions
1 Vsen DC input voltage monitoring
2 FB Feedback signal input with Feedback loop open detection
3 Ct Timing capacitor Ct determines Dead time and fmin (minimum
operating frequency) and also fss(startup frequency)
4 Rt Timing resistor Rt determines fmin
5 GND Signal ground. This pin should be connected to PGND directly.
7 TIMER CTimer determines the time period of burst mode in OCP or another
abnormal operation.
8 SS Startup timing capacitor Css determines the soft-starting time
10 Vc1 Voltage supply input for control circuit with 13.5V/8.4V UVLO Maximum rated voltage is 35V 12 OCP Main resonant current sensing with +0.345V threshold for peak current limiting ,+/- 60mV for didt protection
13 Vc2 Voltage regulator output for Gate driver
Vc2=10V.
14 PGND Power ground
This pin should be connected to low side MOSFET source directly
15 VGL Low side gate driver output
6,9,11,16, 17,18,19 (NC) No connection
20 VB Voltage source of High side gate driver supplied from Vc2 through
Floating driver reference voltage ( = Source pin of high side MOSFET)
22 VGH High side gate driver output
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1.5 Applicable circuits
Most simpleSEPP(Single Ended Push-Pull) Input ripple current reduction(Half Bridge) High power (Full Bridge)
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2 Symmetric LLC converter Operating Description
2.1 Features
Symmetric LLC resonant converter application is expanding widely due to its extremely high power conversion efficiency and low noise characteristics. It’sresonant tank consists of L/L/C connected in series. ZVS/ZCS operation minimizes switching loss and voltage spike. a) The voltage applied to main switch is clamped to input voltage (Vbulk), consequently no spike voltage is generated. b) Main switch turn-off current can be kept to constant and low level independent of load condition. c) Transformer is excited symmetrically, thus magnetics size can be minimized. d) Sinusoidal resonant current waveform results in extremely low EMI characteristics. e) Output rectified current is also partially sinusoidal, and Trr loss and switching noise can be minimized. f) The voltage applied to output diode is clamped to the output voltage (or x2) independent of load condition or input voltage. g) Excellent cross regulation characteristics for multiple output converters due to symmetric bridge operation. h) No requirement of auxiliary 3rd winding helps to optimize resonant condition and transformer design
2.2 Fundamental circuitry（SEPP）
Fig.1 LLC configuration Lr :1st resonant inductance Lm :2nd resonant inductance (magnetizing inductance) Cr :resonant capacitance Cp1/2 :ZVS resonant capacitance Q1/Q2 :Main switch D1/D2 :Commutating diode RL :Equivalent Load resistance Fig.2 simplified dc/dc converter
2.3 Operating waveform example
Fig.3 Vds / Idrain / Vo ripple Fig.4 Zoom of turn off period Output ripple voltage(Vo) Q2 Vds (Vds2) Q2 Idrain (Id(2)
2.4 Control characteristics
2.5 Major parameters and components
Table 1. Major parameters considering resonant condition and hold-up time. High voltage assured type is recommended. recommended. In case of MLCC, type CH or COG. Primary current sensing filtering capacitor.1000pF-10000pF. Limiting I(F/B) and setting fmax. Normally a few k ohms. Refer to characteristic diagrams. Table 3. Circuit constants obtained from the formulas Obtained from Vbulkreset and RvsenseH.
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2.6 IC operation
Power ON（mode A）: Under the condition of input bulk voltage Vbulk is applied (Vsense >1.4V), operation starts when Vc1 terminal voltage reaches 13.5V. After soft starting period (tss), the frequency is stabilized at nominal operating frequency depending on resonant tank and input/output condition. Power ON（mode B）: When Vbulk is applied after Vc1 is supplied, gate drive pulse is generated at Vsense>1.1V with fixed fss operation. Then normal soft starting operation begins when Vsense reaches 1.4V and operation is stabilized in normal operating frequency after the soft starting period as mode A. Power OFF（mode A）: Under the condition of input bulk voltage Vbulk is applied （Vsense >1.4V）, IC operation stops when Vc1 reaches the threshold of Vc1 UVLO OFF（8.4V）. Power OFF（mode B）: When Vbulk decreases under the condition of continuous Vc1 supplied, operating frequency decreases toward fmin. The frequency starts increasing to fss level soon after Vsense decreases to 1.4V. Gate drive stops when Vsense voltage decreases to 0.7V. Fig 6. Power ON / OFF timing diagram
ELECTRIC MFG.CO.,LTD - 10 - Confidential Under Abnormal condition: a) Feedback loop open: When operation is out of control due to input/output conditions beyond the controllable operating area,the frequency becomes to minimum (fmin). F/B loop open detector then will be activated and the gate output stops after the period of tTimer set by timing capacitor (CTimer). After the time period set by the burst mode(tb), the output restarts and is latched off in the case where this timer-latch protection operating cycle repeats twice. Restart Vc1 to release latching. b) OCP / OLP : When the voltage applied to OCP terminal exceeds Vocpth (0.345V typ), the frequency increases instantaneously and when this condition is retained, the operation follows same as above. c) Di/dt Timerection : In close to below resonant condition, di/dt Timerection activates by detecting the threshold of Vdidt (+/- 60mV), limits the frequency to decrease and restrains the output voltage. See section 3.5 for detail. d) Thermal Timerection : If IC internal temperature exceeds 140°C , output will be stopped with 40°C temperature hysteresis. Remarks: When Vbulk keeps low level, the converter is unable to stay in normal operation due to the F/B loop open Timerection and Vsense, even if Vc1 exceeds 14V. If starting the operation with Vbulk slow-up is required, adding external components as described below and in Fig.7 is recommended. 1) connect Rsen1 between Vc1 and Vsense to apply 1.5V or more to Vsense terminal, and 2) connect RTimer1 between TIMERand SGND to disable F/B loop open protection. Please note this circuit is for investigation only. Do not switch on/off the Vbulk when using Rsen1 as 1) to protect MOSFETs from undesired heavy switching stress especially in mid -heavy load condition. Rt Ct Ctimer Css 0.01uF 10V 1000p COG/CH Vbulk 10000pF 10V Gate(H) Source(H) Gate(L) Source(L) x uF 10V x uF 10V 1% 1% RocpL RvsenseL RvsenseH Fig.7 additional components
ELECTRIC MFG.CO.,LTD - 11 - Confidential Selecting the Components of Peripheral Circuit
3.1 Oscillator (selecting Rt)
The timing of gate drive pulse VG(L) and VG(H) is determined by charging and discharging time of timing capacitor Ct. VG(L) and VG(H) drive main switches alternately and shoot through current of main switches is prohibited by dead time (DT) that is equal to discharging time of Ct +140ns as shown in Fig.8. The IC adopts non-constant dead time architecture, and the frequency and ON- duty varies according to F/B terminal current and frequency increases respectively as shown in Fig.9. Larger dead time in light load condition secures ZVS over a wide frequency range. Minimum frequency (fmin) is determined by Ct and Rt. Less than 300kHz for fmax is recommended in continuous operation considering power consumption. fss depends on Ct, for example 185kHz with Ct=1000pF typically See characteristic diagram sheet for detail. Fig.8 Gate drive pulse timing diagram Fig.9 frequency/duty vs I(F/B) The value of tentative Rt, Rt(init), will be obtained from formula(1) using fmin and Ct value. Approximate value of fmin will be obtained from formula(2) using actual value of Rt.(Ct=680pF , Rt=18.9kohm) Refer to characteristic curves to confirm Ct/Rt condition. 88.1 52.2 102.4 88.1 min t t initt C C fR [ohm] ---(1) t ttt R CRC f /52.2102.4 88.1 52.2 88.12 min [Hz] ---(2) Fig.10 Ct / Rt internal block CtRt GND 2.5V 100 200 300 400 500 0 1 2 3 4 5 IFB [mA] frequency [kHz] Duty[%] Ct=680pF Rt=18.9k Ω Ct=820pF Rt=16.8k Ω Ct=1000pF Rt=13.2k Ω Ct=1200pF Rt=11.6k Ω
ELECTRIC MFG.CO.,LTD - 12 - Confidential Vc1 Ct VG(H) Vsense Css 1.4V 13.5V VG(L) 0.7V 1.1V Fig.11 Vsense internal block Fig.12 Vsense brown out timing diagram
3.2 Brown-out protection (selecting RvsenseL)
Vsense terminal monitors the input voltage for halting gate drive pulse and varying the frequency. UVLO function avoids below-resonant state caused by supplying Vbulk remaining Vc1 is applied, brown-out (quick decrease of input voltage) or black-out (instantaneous interruption). Timing diagram of brown-out protection is shown in Fig.12. High side resistor of voltage divider is RvsenseH :greater than 3Mohm is recommended. Required minimum sink current of Vsense terminal is 1uA. Low side resistor, RvsenseL(init) is obtained from formula(3) and correct value of Vbulkreset threshold is obtained from formula(4) by using actual value of RvsenseL. This 1.4V threshold is for Css resetting without hysterisis,and 1.1V is for ON/OFF with 0.4V hysterisis.Vsense pin can be simply used for ON/OFF function. [ohm] ---(3) [Vdc] ---(4) RvsenseH of 3Mohm as an example consumes 40mW constantly at AC240V (without PFC operating). In the case where PFC converter with independent OVP function is installed, the voltage divider (associated power consumption) can be eliminated by obtaining Vsense voltage from OVP detector of the PFC converter. Connect filtering capacitor of around 3.3-10nF between Vsense terminal and GND.
3.3 Soft start (selecting Css)
Tentative value of soft start timing capacitor Css(init) is obtained from approximate formula(5). tss is the time period of which the frequency stabilizes at fmin after VCss reaches around 0.8V. Correct value of tss, soft start time period, is obtained from formula(6) using actual value of Css. Characteristics of Css voltage vs operating frequency at Css = 4.7uF (tss = 200ms) is shown in Fig.13. ss ss ss)init(ss 1023 Ct 1023tC [F] ---(5) [sec] ---(6) 1.4R RRV 1.4-V R1.4R vsenseL vsenseLvsenseH bulkreset bulkreset vsenseH (init)vsenseL
ELECTRIC MFG.CO.,LTD - 13 - Confidential SS time vs frequency and terminal voltage 100 150 200 250 0 50 100 150 200 250 Time [ms] fss [kHz] 0.0 0.5 1.0 1.5 2.0 SSterminalvoltage[V] fss [kHz] Vss [V] Ct=1000pF Rt=13.2k Ω Css=4.7uF Fig.13. fss characteristics
3.4 Over-current Protection（selecting Rocpdet / RocpL）
OCP(over current protection) operates by detecting positive peak current of resonant tank (drain current of high-side MOSFET) beyond the threshold of +0.345V. The current is detected by sensing resistor Rocpdet and its detected voltage is applied to OCP terminal through R/C filter. When the voltage applied to OCP terminal reaches +0.345V, timing capacitor Ct is charged rapidly and consequently the frequency is increased to limit the current / MOSFET drain current. Threshold level is low enough to minimize ineffective power loss of sensing resistor. Filter capacitor is connected between OCP and SGND to eliminate the influence of parasitic inductance of sensing resistor or parasitic inductance. The capacitance value of 1000pF to 10000pF is recommended. Fig.14. OCP Timing diagram
ELECTRIC MFG.CO.,LTD - 14 - Confidential Rocpdet is obtained from formula( 7) with desired OCP threshold Ipk. Tentative value of RocpL(init) is obtained from formula( 8) and correct value of Ipk(th) is calculated from formula( 9) using actual value of RocpL. 10-47 ohm is recommended as RocpH considering OCP terminal sourcing current (180uA typ.)。 Ipk(th) value should be determined carefully to have enough margins in low input voltage / Pomax or switching load condition. RocpL Rocpdet Cr C116 10000pF Fig.15. Main resonant current detecting configuration OCP function of MCZ5203 activates by detecting positive current (drain current of high-side MOSFET) so keep suitable winding direction if half-wave rectification is applied in multiple output converter usage. If OCP activates (in the period of high-side driven), succeeding period of low-side driven is limited to 1/ (2 x fmin x 1.8). Large negative voltage applied to OCP terminal may cause OCP malfunction. If OCP terminal negative voltage is greater than -0.8V , add 40V 1A SBD to clamp the negative voltage. 3.5 di/dt mode protection MCZ5203 adopts pulse by pulse bidirectional didt protection to avoid below resonant mode operation. This function helps to avoid hard switching of main switches in below ZVS boundary operation. When OCP terminal voltage (Vocp) exceeds 60mV during the period of Ct voltage going bottom to 2.1V (Ct masking period), didt protection is ready to activate. In identical Ct saw tooth period, Vocp decreasing to 60mV again results in instantaneous Ct discharging and gate drive turns off. In negative current direction, threshold voltage is -60mV. During didt protection is operating , CTimer is not charged. Please note didt threshold is about 1/6 of OCP threshold. Fig.16. OCP protection Fig.17. di/dt protection )9(]A[0.345RR R10I )8(]ohm[0.345RIpk 100.345R )7(]ohm[Ipk 0.345R detocpocpL ocpL )th(pk detocp )init(ocpL detocp
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3.6 Timer Protection （selecting CTimer ）
TIMER terminal has 2 threshold, 3V and 0.3V. When OCP or F/B loop open protection operates, CTimer charging starts and continuous abnormal condition keeps charging CTimer with constant 215uA until V(CTimer) reaches 3.0V. Once V(CTimer) reached 3V, gate output stops and CTimer discharging with constant 10uA sinking starts and continues until V(CTimer) decreases to 0.3V. At the moment V(CTimer) reaches 0.3V, CTimer 215uA charging restarts and Gate output also restarts with soft starting function.TIMER counter counts the number of times of 3V charging.If count is twice, output will be latched off. When abnormal condition is eliminated and converter enters in normal operation before abnormal 2 counts, CTIMER is rapidly discharged with 2mA sinking and the counting result is reset. To release latching , restart with supplying Vc1 of less than 8V Timing chart is shown in Fig.18. 6103 215 tTIMERCTIMER [F] ----(10) TIMER burst timing ratio is tTimer1 : tb = 1 : (20+tss), In case of CTimer=4.7uF / Css=2.2uF, tTimer=70msec , tb=1.5sec. abnormal signal Latch counter PROT refresh (1) (2) reset Vss 2.5V latch Gate out Fig.18. Timer delayed burst and latching timing chart
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3.7 High side floating Vcc (VB)
Floating High side gate drive voltage source (VB) is produced by bootstrapping configuration from stabilized Vc2 10V. 600V soft recovery type UFRD (ultra fast recovery diode) is recommended like D1NK60 (Shindengen). VB = Vc2 –Vf (Dboot) VS terminal is the reference potential for VB, so if negative spike voltage due to turn off current of low side switch and pattern parasitic inductance is too large,VB will be over charged. In case of VB max exceeds 15V , zener diode clamping is recommended to avoid high side logic malfunction. Np MCZ DbootCboot 0.1 uF 16V D1NK60 D1FK60 20 15 14 132122 Vc2PGNDVG(L)VBVSVG(H) Fig.19. Boot Strapping configuration
3.8 Gate driver
The gate drivers have 0.18A sourcing and 0.53A sinking current capability at Vc2=10V. Typical configurations are shown in Fig.20a) b). If using small low Qg MOSFET like 30nC or less, R122/125 and D112/113 will not be required like Fig.20 C) due to optimized unbalanced drive capability of MCZ5203. Fig.20. Gate driving configuration
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4 Circuit diagram
4.1 circuit example C201 R202 IC201 T101 R203 R211 R210 R213 C231 R231 D201 D203 VGH VS VB (NC) VGL PGND Vc2 Vsen FB Ct Rt GND Timer SS Vc1 OCP IC101 C122 R110 R111 C115C114C113R131C112 R108 PC101 R107 R102 R101 C121 C120 D110 C119 R124 R126 R121 R123 1 C110 Q101 Q102 F101 C117 R112 C116 CN102 C123 C126 C111 Q113 GND VCC Vin GND GND ON/OFF R103 C205 V2D205 D206 GND C202 (NC) (NC) (NC) (NC) (NC)(NC) Fig.21. dual output LLC
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5 Dimensions
5.1 SOP22 (MCZ5203SE)
Units : mm