33903 NXP | Alldatasheet
Document overview
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- PDF pages: 107
Technical content
Features
- Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with possibility of usage external PNP to extend current capability and share power dissipation
- Voltage, current, and temperature protection
- Extremely low quiescent current in LP modes
- Fully-protected embedded 5.0 V regulator for the CAN driver
- Multiple undervoltage detections to address various MCU specifications and system operation modes (i.e. cranking)
- Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection
- MUX output pin for device internal analog signal monitoring and power supply monitoring
- Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring.
- Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and VDD overcurrent detection.
- ISO11898-5 high-speed CAN interface co mpatibility for baud rates of 40 kb/s to 1.0 Mb/s
- Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J2602-2 and LIN 2.1 33903/33903/4/5 EK Suffix (Pb-free) 98ASA10556D 32-PIN SOIC EK Suffix (Pb-free) 98ASA10506D 54-PIN SOIC
Applications
- Aircraft and marine systems
- Automotive and robotic systems
- Farm equipment
- Industrial actuator controls
- Lamp and inductive load controls
- DC motor control applications requiring diagnostics
- Applications where high-side switch control is require d SYSTEM BASIS CHIP
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1 Simplified application diagrams
Figure 1. 33905D simplified application diagram Figure 2. 33905S simplified application diagram
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Figure 3. 33904 simplified application diagram Figure 4. 33903 simplified application diagram
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Figure 7. 33903P simplified application diagram
2 Orderable part
Table 1. MC33905 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
2 Wake-up + 2 LIN terms
3 Wake-up + 1 LIN terms
4 Wake-up + no LIN terms
- Design changes in the ‘B’ version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. ‘B’
version has an errata linked to the SPI operation.
- Design changes in the ‘C’ version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
- ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes. Table 2. MC33904 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
- Design changes in the “B” version resolved V SUP slow ramp up issues, enhanced device current consumption and improved oscillator stability.
‘B’ version has an errata linked to the SPI operation.
- Design changes in the “C” version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
- ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes.
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Table 3. MC33903 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
3.3 V(7)
5.0 V(7)MCZ33903C5EK/R2 C
1 Wake-up + 2 LIN terms
2 Wake-up + 1 LIN terms
3 Wake-up + no LIN terms
5.0 VMCZ33903CD5EK/R2 C
5.0 VMCZ33903CS5EK/R2 C
- V DD does not allow usage of an external PNP on the 33903.
- Design changes in the ‘B’ version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. ‘B’
version has an errata linked to the SPI operation.
- Design changes in the “C” version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
- ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes.
3 Internal block diagrams
Figure 8. 33905 internal block diagram Figure 9. 33904 internal block diagram
5 V-CAN
5 V Auxiliary
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Figure 10. 33903 internal block diagram
4 Pin Connections
4.1 Pinout diagram
Figure 11. 33905D, MC33905S, MC33904 and MC33903 pin connections
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Figure 12. 33905D, MC33905S, MC33904 and MC33903 pin connections Note: MC33903D, MC33903S, and MC33903P are footprint compatible.
4.2 Pin definitions
A functional description of each pin can be found in the Functional pin description section beginning on page 32. Table 4. 33903/4/5 pin definitions
54 Pin
32 Pin
master node termination resistor. RST pin, etc.). Open drain structure. 10 7 7 7 7 7 7 CANH Output CAN High CAN high output. 11 8 8 8 8 8 8 CANL Output CAN Low CAN low output.
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Auxiliary Output pin for the auxiliary voltage. activated for a cyclic sense function. mode, no watchdog refresh is necessary. selection of Safe mode functionality.
23 N/A N/A N/A 14 N/A N/A TXD-L2 Input LIN Transmit
24,31 N/A N/A N/A 15, 18 15, 18 15, 18 GND Ground Ground Ground of the IC.
25 N/A N/A N/A 16 N/A N/A RXD-L2 Output LIN Receive
Data LIN bus receive data output.
26 N/A N/A N/A 17 N/A N/A LIN2 Input/
Output LIN bus LIN bus input output connected to the LIN bus. Output LIN bus LIN bus input output connected to the LIN bus. Data LIN bus receive data output. during high voltage transients. I/O-0 for a cyclic sense function in (LP) mode. Table 4. 33903/4/5 pin definitions (continued)
Connection to the external PNP path transistor.
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ELECTRICAL CHARACTERISTICS
5 Electrical characteristics
5.1 Maximum ratings
Table 5. Maximum ratings
- The voltage on non-VSUP pins should never exceed the V SUP voltage at any time or permanent damage to the device may occur.
- If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external VDD ballast current sharing functionality may be damaged.
- Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON.
Figure 13. PCB with top and bottom layer dissipation area (dual layer)
- ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), the Charge Device Model (CDM),
and Robotic (CZAP = 4.0 pF).
- Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
- NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
orderable parts, and review parametrics.
- This parameter was measured according to Figure 13:
Table 5. Maximum ratings (continued)
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5.2 Static electrical characteristics
Table 6. Static electrical characteristics the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
- All parameters in spec (ex: V DD regulator tolerance).
- Device functional, some parameters could be out of spec. V DD is active, device is not in Reset mode if the lowest VDD undervoltage reset threshold
is selected (approx. 3.4 V). CAN and I/Os are not operational.
- In Run mode, CAN interface in Sleep mode, 5 V-CAN and VAUX turned OFF. IOUT at VDD < 50 mA. Ballast: turned OFF or not connected.
- VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. Therefore, ISUP1 and ISUP2 cannot
VDD Voltage regulator, VDD pin VOUT-5.0 VOUT-5.0-EMC VOUT-3.3 Output Voltage VDD = 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA VDD = 5.0 V, under EMC immunity test condition VDD = 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA 4.9 4.9 3.234 5.0 5.0 3.3 5.1 5.15 3.4 V (22) VDROP Drop voltage without external PNP pass transistor VDD = 5.0 V, IOUT = 100 mA VDD = 5.0 V, IOUT = 150 mA 330 450 500 mV (23) VDROP-B Drop voltage with external transistor IOUT = 200 mA (I_BALLAST + I_INTERNAL) - 350 500 mV (23) VSUP1-3.3 VSUP/1 to maintain VDD within VOUT-3.3 specified voltage range VDD = 3.3 V, IOUT = 150 mA VDD = 3.3 V, IOUT = 200 mA, external transistor implemented 4.0 4.0 V K External ballast versus internal current ratio (I_BALLAST = K x Internal current) 1.5 2.0 2.5 ILIM Output Current limitation, without external transistor 150 350 550 mA TPW Temperature pre-warning (Guaranteed by design) - 140 - °C TSD Thermal shutdown (Guaranteed by design) 160 - - °C CEXT Range of decoupling capacitor (Guaranteed by design) 4.7 - 100 μF (24) VDDLP LP mode VDD ON, IOUT ≤ 50 mA (time limited) VDD = 5.0 V, 5.6 V ≤ VSUP ≤ 28 V VDD = 3.3 V, 5.6 V ≤ VSUP ≤ 28 V 4.75 3.135 5.0 3.3 5.25 3.465 V LP-IOUTDC LP mode VDD ON, dynamic output current capability (Limited duration. Ref. to device description). - - 50 mA LP-ITH LP VDD ON mode: Overcurrent Wake-up threshold. Hysteresis 1.0 0.1 3.0 1.0 mA LP-VDROP LP mode VDD ON, drop voltage, at IOUT = 30 mA (Limited duration. Ref. to device description) - 200 400 mV (23) LP-MINVS LP mode VDD ON, min VSUP operation (Below this value, a VDD, undervoltage reset may occur) 5.5 - - V VDD_OFF VDD when VSUP < VSUP-TH1, at I_VDD ≤ 10 μA (Guaranteed by design) - - 0.3 V VDD_START UP VDD when VSUP ≥ VSUP-TH1, at I_VDD ≤ 40 mA (Guaranteed with parameter VSUP-TH1 3.0 - - V Notes 22. Guaranteed by design. During immunity tests, according to IEC62132-4, with RF injection applied to CAN or LIN pins. No filter components on CAN or LIN pins. When immunity tests are performed with a CAN filter component (common mode choke) or LIN filter component (capacitor), the VDD specification is 5.0 V ±2%. 23. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout voltage parameter cannot be specified. 24. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance. Table 6. Static electrical characteristics (continued) the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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Voltage regulator for CAN interface supply, 5.0 V-CAN pin 5V-C OUT Output voltage, VSUP/2 = 5.5 to 40 V IOUT 0 to 160 mA 4.75 5.0 5.25 V 5V-C ILIM Output Current limitation 160 280 - mA (25) 5V-C UV Undervoltage threshold 4.1 4.5 4.7 V 5V-CTS Thermal shutdown (Guaranteed by design) 160 - - °C CEXT-CAN External capacitance (Guaranteed by design) 1.0 - 100 μF V auxiliary output, 5.0 and 3.3 V selectable pin VB-Aux, VC-Aux, Vaux VAUX VAUX output voltage VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA 4.75 3.135 5.0 3.3 5.25 3.465 V VAUX-UVTH VAUX undervoltage detector (VAUX configured to 5.0 V) Low Threshold Hysteresis VAUX undervoltage detector (VAUX configured to 3.3 V, default value) 4.2 0.06 2.75 4.5 3.0 4.70 0.12 3.135 V VAUX-ILIM VAUX overcurrent threshold detector VAUX set to 3.3 V VAUX set to 5.0 V 250 230 360 330 450 430 mA VAUX CAP External capacitance (Guaranteed by design) 2.2 - 100 μF Undervoltage reset and reset function, RST pin VRST-TH1 VDD undervoltage threshold down - 90% VDD (VDD 5.0 V) VDD undervoltage threshold up - 90% VDD (VDD 5.0 V) VDD undervoltage threshold down - 90% VDD (VDD 3.3 V) VDD undervoltage threshold up - 90% VDD (VDD 3.3 V) 4.5 2.75 4.65 3.0 4.85 4.90 3.135 3.135 V (26), (28) (26), (28) VRST-TH2-5 VDD undervoltage reset threshold down - 70% VDD (VDD 5.0 V) 2.95 3.2 3.45 V (27), (28) VRST-HYST Hysteresis for threshold 90% VDD, 5.0 V device for threshold 70% VDD, 5.0 V device Hysteresis 3.3 V VDD for threshold 90% VDD, 3.3 V device 150 150 150 mV VRST-LP VDD undervoltage reset threshold down - LP VDD ON mode (Note: device change to Normal Request mode). VDD 5.0 V (Note: device change to Normal Request mode). VDD 3.3 V 4.0 2.75 4.5 3.0 4.85 3.135 V VOL Reset VOL @ 1.5 mA, VSUP 5.5 to 28 V - 300 500 mV IRESET LOW Current limitation, Reset activated, VRESET = 0.9 x VDD 2.5 7.0 10 mA RPULL-UP Pull-up resistor (to VDD pin) 8.0 11 15 kΩ Notes 25. Current limitation will be reported by setting a flag. 26. Generate a Reset or an INT. SPI programmable 27. Generate a Reset 28. In Non-LP modes the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Undervoltage reset and reset function, RST PIN (continued) VSUP-RSTL VSUP to guaranteed reset low level 2.5 - - V (29) VRST-VTH Reset input threshold Low threshold, VDD = 5.0 V High threshold, VDD = 5.0 V Low threshold, VDD = 3.3 V High threshold, VDD = 3.3 V 1.5 0.99 3.5 2.31 V VHYST Reset input hysteresis 0.5 1.0 1.5 V I/O pins when function selected is output VI/O-0 HSDRP I/O-0 HS switch drop @ I = -12 mA, VSUP = 10.5 V - 0.5 1.4 V VI/O-2-3 HSDRP I/O-2 and I/O-3 HS switch drop @ I = -20 mA, VSUP = 10.5 V - 0.5 1.4 V VI/O-1 HSDRP I/O-1, HS switch drop @ I = -400 μA, VSUP = 10.5 V - 0.4 1.4 V VI/O-01 LSDRP I/O-0, I/O-1 LS switch drop @ I = 400 μA, VSUP = 10.5 V - 0.4 1.4 V II/O_LEAK Leakage current, I/O-x ≤ VSUP - 0.1 3.0 μA I/O pins when function selected is input VI/O_NTH Negative threshold 1.4 2.0 2.9 V VI/O_PTH Positive threshold 2.1 3.0 3.8 V VI/O_HYST Hysteresis 0.2 1.0 1.4 V II/O_IN Input current, I/O ≤ VSUP/2 -5.0 1.0 5.0 μA RI/O-X I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in register, 2.0 V < VI/O-X <16 V (Guaranteed by design). - 100 - kΩ VSENSE input VSENSE_TH VSENSE undervoltage threshold (Not active in LP modes) Low Threshold High threshold Hysteresis 8.1 0.1 8.6 0.25 9.0 9.1 0.5 V RVSENSE Input resistor to GND. In all modes except in LP modes. (Guaranteed by design). - 125 - kΩ Notes 29. Reset must be kept low the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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VOUT_MAX Output Voltage Range, with external resistor to GND >2.0 kΩ 0.0 - VDD - 0.5 V RMI Internal pull-down resistor for regulator output current sense 0.8 1.9 2.8 kΩ CMUX External capacitor at MUX OUTPUT (Guaranteed by design) - - 1.0 nF (30) TEMP-COEFF Chip temperature sensor coefficient (Guaranteed by design and device characterization) VDD = 5.0 V VDD = 3.3 V 13.2 13.9 14.6 mv/°C VTEMP Chip temperature: MUX-OUT voltage VDD = 5.0 V, TA = 125 °C VDD = 3.3 V, TA = 125 °C 3.6 2.45 3.75 2.58 3.9 2.65 V VTEMP(GD) Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) TA = -40 °C, VDD = 5.0 V TA = 25 °C, VDD = 5.0 V TA = -40 °C, VDD = 3.3 V TA = 25 °C, VDD = 3.3 V 0.12 1.5 0.07 1.08 0.30 1.65 0.19 1.14 0.48 1.8 0.3 1.2 V VSENSE GAIN Gain for VSENSE, with external 1.0 k 1% resistor VDD = 5.0 V VDD = 3.3 V 5.42 8.1 5.48 8.2 5.54 8.3 VSENSE OFFSET Offset for VSENSE, with external 1.0 k 1% resistor -20 - 20 mV VSUP/1 RATIO Divider ratio for VSUP/1 VDD = 5.0 V VDD = 3.3 V 5.335 7.95 5.5 8.18 5.665 8.45 VI/O RATIO Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: VDD = 5.0 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to VDD = 5.0 V, (Gain, MUX-OUT register bit 3 set to 0) VDD = 3.3 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to VDD = 3.3 V, (Gain, MUX-OUT register bit 3 set to 0) 3.8 5.6 4.0 2.0 5.8 1.3 4.2 6.2 VREF Internal reference voltage VDD = 5.0 V VDD = 3.3 V 2.45 1.64 2.5 1.67 2.55 1.7 V IDD_RATIO Current ratio between VDD output & IOUT at MUX-OUT (IOUT at MUX-OUT = IDD out / IDD_RATIO) At IOUT = 50 mA I_OUT from 25 to 150 mA 62.5 115 117 SAFE output VOL SAFE low level, at I = 500 μA 0.0 0.2 1.0 V ISAFE-IN Safe leakage current (VDD low, or device unpowered). VSAFE 0 to 28 V. - 0.0 1.0 μA Notes 30. When C is higher than CMUX, a serial resistor must be inserted the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
VOL Output low voltage, IOUT = 1.5 mA - 0.2 1.0 V RPU Pull-up resistor 6.5 10 14 kΩ VOH-LPVDDON Output high level in LP VDD ON mode (Guaranteed by design) 3.9 4.3 V VMAX Leakage current INT voltage = 10 V (to allow high-voltage on MCU INT pin) - 35 100 μA I SINK Sink current, VINT > 5.0 V, INT low state 2.5 6.0 10 mA MISO, MOSI, SCLK, CS pins VOL Output low voltage, IOUT = 1.5 mA (MISO) - - 1.0 V VOH Output high voltage, IOUT = -0.25 mA (MISO) VDD -0.9 - V VIL Input low voltage (MOSI, SCLK,CS) - - 0.3 x VDD V VIH Input high voltage (MOSI, SCLK,CS) 0.7 x VDD - - V IHZ Tri-state leakage current (MISO) -2.0 - 2.0 μA IPU Pull-up current (CS) 200 370 500 μA CAN logic input pins (TXD) VIH High Level Input Voltage 0.7 x VDD - VDD + 0.3 V VIL Low Level Input Voltage -0.3 - 0.3 x VDD V IPDWN Pull-up Current, TXD, VIN = 0 V VDD = 5.0 V VDD = 3.3 V -850 -500 -650 -250 -200 -175 µA CAN data output pins (RXD) VOUTLOW Low Level Output Voltage IRXD = 5.0 mA 0.0 - 0.3 x VDD V VOUTHIGH High Level Output Voltage IRX = -3.0 mA 0.7 x VDD - VDD V IOUTHIGH High Level Output Current VRXD = VDD - 0.4 V 2.5 5.0 9.0 mA IOUTLOW Low Level Input Current VRXD = 0.4 V 2.5 5.0 9.0 mA the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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CAN output pins (CANH, CANL) VCOM Bus pins common mode voltage for full functionality -12 - 12 V VCANH-VCANL Differential input voltage threshold 500 - 900 mV VDIFF-HYST Differential input hysteresis 50 - - mV RIN Input resistance 5.0 - 50 kΩ RIN-DIFF Differential input resistance 10 - 100 kΩ RIN-MATCH Input resistance matching -3.0 0.0 3.0 % VCANH CANH output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state 2.75 2.0 3.5 2.5 4.5 3.0 V VCANL CANL output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state 0.5 2.0 1.5 2.5 2.25 3.0 V VOH-VOL Differential output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state 1.5 -0.5 2.0 0.0 3.0 0.05 V ICANH CAN H output current capability - Dominant state - - -30 mA ICANL CAN L output current capability - Dominant state 30 - - mA ICANL-OC CANL overcurrent detection - Error reported in register 75 120 195 mA ICANH-OC CANH overcurrent detection - Error reported in register -195 -120 -75 mA RINSLEEP CANH, CANL input resistance to GND, device supplied, CAN in Sleep mode, V_CANH, V_CANL from 0 to 5.0 V 5.0 - 50 kΩ VCANLP CANL, CANH output voltage in LP VDD OFF and LP VDD ON modes -0.1 0.0 0.1 V ICAN-UN_SUP1 CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device unpowered (VSUP, VDD, 5V-CAN: open). - 3.0 10 µA (31) ICAN-UN_SUP2 CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device unpowered (VSUP, VDD, 5V-CAN: open). - - 250 µA (31) VDIFF-R-LP Differential voltage for recessive bit detection in LP mode - - 0.4 V (32) VDIFF-D-LP Differential voltage for dominant bit detection in LP mode 1.15 - - V (32) CANH and CANL diagnostic information VLG CANL to GND detection threshold 1.6 1.75 2.0 V VHG CANH to GND detection threshold 1.6 1.75 2.0 V VLVB CANL to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V - VSUP -2.0 - V VHVB CANH to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V - VSUP -2.0 - V VL5 CANL to VDD detection threshold 4.0 VDD -0.43 - V VH5 CANH to VDD detection threshold 4.0 VDD -0.43 - V Notes 31. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization. 32. Guaranteed by design and device characterization. the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Loaded condition ISPLIT = ±500 µA Unloaded condition Rmeasure > 1.0 MΩ 0.3 x VDD 0.45 x VDD 0.5 x VDD 0.5 x VDD 0.7 x VDD 0.55 x VDD V ILSPLIT Leakage current -12 V < VSPLIT < +12 V -22 to -12 V < VSPLIT < +12 to +35 V 0.0 5.0 200 µA LIN terminals (LIN-T/1, LIN-T2) VLT_HSDRP LIN-T1, LIN-T2, HS switch drop @ I = -20 mA, VSUP > 10.5 V - 1.0 1.4 V LIN1 & LIN2 33903D/5D pin - LIN 33903S/5S pin (parameters guaranteed for VSUP/1, VSUP2 7.0 V ≤ VSUP ≤ 18 V) VBAT Operating Voltage Range 8.0 - 18 V VSUP Supply Voltage Range 7.0 - 18 V IBUS_LIM Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V 40 90 200 mA IBUS_PAS_DOM Input Leakage Current at the receiver Driver off; VBUS = 0 V; VBAT = 12 V -1.0 - - mA IBUS_PAS_REC Leakage Output Current to GND Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT - - 20 µA IBUS_NO_GND Control unit disconnected from ground (Loss of local ground must not affect communication in the residual network) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V (Guaranteed by design) -1.0 - 1.0 mA IBUSNO_BAT VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition). (Guaranteed by design) - - 100 µA VBUSDOM Receiver Dominant State - - 0.4 VSUP VBUSREC Receiver Recessive State 0.6 - - VSUP VBUS_CNT Receiver Threshold Center (VTH_DOM + VTH_REC)/2 0.475 0.5 0.525 VSUP VHYS Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) - - 0.175 VSUP VBUSWU LIN Wake-up threshold from LP VDD ON or LP VDD OFF mode - 5.3 5.8 V RSLAVE LIN Pull-up Resistor to VSUP 20 30 60 kΩ TLINSD Overtemperature Shutdown (Guaranteed by design) 140 160 180 °C TLINSD_HYS Overtemperature Shutdown Hysteresis (Guaranteed by design) - 10 - °C the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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5.3 Dynamic electrical characteristics
Table 7. Dynamic electrical characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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LIN physical layer: driver characteristics for normal slew rate - 20.0 kBit/sec according to lin physical layer specification Duty Cycle 1: THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V 0.396 - - Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.581 LIN physical layer: driver characteristics for slow slew rate - 10.4 kBit/sec according to lin physical layer specification Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V 0.417 - - Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.590 LIN physical layer: driver characteristics for fast slew rate SRFAST LIN Fast Slew Rate (Programming Mode) - 20 - V / μs 10 nF / 500 Ω. See Figure 18, page 30. t REC_PD t REC_SYM Propagation Delay and Symmetry (See Figure 18, page 30 and Figure 19, page 31) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR - 2.0 4.2 6.0 2.0 μs t PROPWL Bus Wake-up Deglitcher (LP VDD OFF and LP VDD ON modes) (See Figure 20, page 30 for LP VDD OFF mode and Figure 21, page 31 for LP mode) 42 70 95 μs t WAKE_LPVDDOFF t WAKE_LPVDDON Bus Wake-up Event Reported From LP VDD OFF mode From LP VDD ON mode 1.0 1500 μs t TXDDOM TXD Permanent Dominant State Delay (Guaranteed by design) 0.65 1.0 1.35 s Table 7. Dynamic electrical characteristics (continued) noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
5.4 Timing diagrams
Figure 14. SPI timing Figure 15. CAN signal propagation loop delay TXD to RXD Figure 16. CAN signal propagation delays TXD to CAN and CAN to RXD
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Figure 17. Test circuit for CAN timing characteristics Figure 18. LIN timing measurements for normal slew rate
5 V_CAN
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6 Functional description
6.1 Introduction
The MC33903_4_5 is the second generation of System Basis Chip, combining: - Advanced power management unit for the MCU, the integrated CAN interface and for the additional ICs such as sensors, CAN transceiver. - Built in enhanced high speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostic, protection, and fail-safe operation mode. - Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection. - Innovative hardware configurable fail-safe state machine solution. - Multiple LP modes, with low current consumption. - Family concept with pin compatibility; with and without LIN interface devices.
6.2 Functional pin description
6.2.1 Power supply (VSUP/1 and VSUP2)
Note: VSUP1 and VSUP2 supplies are externally available on all devices except the 33903D, 33903S, and 33903P, where these are connected internally. VSUP1 is the input pin for the internal supply and the VDD regulator. VSUP2 is the input pin for the 5 V-CAN regulator, LIN’s interfaces and I/O functions. The VSUP block includes over and undervoltage detections which can generate interrupt. The device includes a loss of battery detector connected to VSUP/1. Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset).
6.2.2 VDD voltage regulator (VDD)
The regulator has two main modes of operation (Normal mode and LP mode). It can operate with or without an external PNP transistor. In Normal mode, without external PNP, the max DC capability is 150 mA. Current limitation, temperature pre-warning flag and A 3.3 V option is available via dedicated part number. If current higher than 150 mA is required, an external PNP transistor must be connected to VE (PNP emitter) and VB (PNP base) pins, in order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See External transistor Q1 (VE and VB). The PNP can be used even if current is less than 150 mA, depending upon ambient temperature, maximum supply and thermal resistance. Typically, above 100-200 mA, an external ballast transistor is recommended.
6.2.3 VDD regulator in LP mode
When the device is set in LP VDD ON mode, the VDD regulator is able to supply the MCU with a DC current below typically 1.5 mA (LP- ITH). Transient current can also be supplied up to a tenth of a mA. Current in excess of 1.5 mA is detected, and this event is managed by the device logic (Wake-up detection, timer start for overcurrent duration monitoring or watchdog refresh).
6.2.4 External transistor Q1 (VE and VB)
The device has a dedicated circuit to allow usage of an external “P” type transistor, with the objective to share the power dissipation between the internal transistor of the VDD regulator and the external transistor. The recommended bipolar PNP transistor is MJD42C or BCP52-16. When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI. The device is able to operate without an external transistor. In this case, the VE and VB pins must remain open.
6.2.5 5 V-CAN voltage regulator for CAN and analog MUX This regulator is supplied from the VSUP/2 pin. A capacitor is required at 5 V-CAN pin. Analog MUX and part of the LIN interfaces are supplied from 5 V-CAN. Consequently, the 5 V-CAN must be ON in order to have Analog MUX operating and to have the LIN interface operating in TXD/RXD mode. The 5 V-CAN regulator is OFF by default and must be turned ON by SPI. In Debug mode, the 5 V-CAN is ON by default. 6.2.6 V auxiliary output, 5.0 and 3.3 V selectable (VB-Aux, VC-Aux, and VCaux) - Q2 The VAUX block is used to provide an auxiliary voltage output, 5.0 or 3.3 V, selectable by the SPI. It uses an external PNP pass transistor for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16. An overcurrent and undervoltage detectors are provided. VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and overcurrent information will disable VAUX, and are reported in the SPI and can generate INT. VAUX is OFF by default and must be turned ON by the SPI.
6.2.7 Undervoltage reset and reset function (RST)
The RST pin is an open drain structure with an internal pull-up resistor. The LS driver has limited current capability when asserted low, in The RST pin reports an undervoltage condition to the MCU at the VDD pin, as a RST failure in the watchdog refresh operation. VDD undervoltage reset also operates in LP VDD ON mode. Two VDD undervoltage thresholds are included. The upper (typically 4.65 V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected by the SPI. When “RST-TH2-5“is selected, in Normal mode, an INT is asserted when VDD falls below “RST-TH1-5“, then, when VDD falls
6.2.8 I/O pins (I/O-0: I/O-3)
I/Os are configurable input/output pins. They can be used for small loads or to drive external transistors. When used as output drivers, the I/Os are either a HS or LS type. They can also be set to high-impedance. I/Os are controlled by the SPI and at power on, the I/Os are set as inputs. They include overload protection by temperature or excess of a voltage drop. When I/O-0/-1/-2/-3 voltage is greater than VSUP/2 voltage, the leakage current (II/O_LEAK) parameter is not applicable
- I/O-0 and I/O-1 will have current flowing into the device through three diodes limited by an 80 kOhm resistor (in series).
- I/O-2 and I/O-3 will have unlimited current flowing into the device through one diode. In LP mode, the state of the I/O can be turned ON or OFF, with extremely low power consumption (except when there is a load). Protection is disabled in LP mode. When cyclic sense is used, I/O-0 is the HS/LS switch, I/O-1, -2 and -3 are the wake inputs. I/O-2 and I/O-3 pins share the LIN Master pin function.
6.2.9 VSENSE input (VSENSE)
This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to GND. It incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX-OUT pin.
6.2.10 MUX-output (MUXOUT)
The MUX-OUT pin (Figure 22) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUX-OUT is selected via the SPI, from one of the following functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V reference, die temperature sensor, VDD current copy. Voltage divider or amplifier is inserted in the chain, as shown in Figure 22. For the VDD current copy, a resistor must be added to the MUX-OUT pin, to convert current into voltage. Device includes an internal 2.0 k resistor selectable by the SPI. Voltage range at MUX-OUT is from GND to VDD. It is automatically limited to VDD (max 3.3 V for 3.3 V part numbers). The MUX-OUT buffer is supplied from 5 V-CAN regulator, so the 5 V-CAN regulator must be ON in order to have:
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2) SPI selection of the analog function. If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND and the SPI command that selects one of the analog inputs is ignored. mainly upon the 5 V-CAN capacitor and load on 5 V-CAN. The delay can be estimated using the following formula: delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN. I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator (parameter 5 V-C ILIM). undervoltage flag (bit4 of the 0xDF00 SPI command). Figure 22. Analog multiplexer block diagram
6.2.11 DGB (DGB) and debug mode
6.2.11.1 Primary function
voltage at the DEBUG pin to be between a range of 8.0 to 10 V, and activates the Debug mode. software routines (i.e. SPI commands). present. The SPI command has a higher priority than providing 8.0 to 10 V at the DEBUG pin.
6.2.11.2 Secondary function
The resistor connected between the DBG pin and the GND selects the Fail-Safe mode operation. DBG pin can also be connected directly to GND (this prevents the usage of Debug mode). Flexibility is provided to select SAFE output operation via a resistor at the DBG pin or via a SPI command. The SPI command has higher priority than the hardware selection via Debug resistor. When the Debug mode is selected, the SAFE modes cannot be configured via the resistor connected at DBG pin.
6.2.12 SAFE
6.2.12.1 Safe output pin
This pin is an output and is asserted low when a fault event occurs. The objective is to drive electrical safe circuitry and set the ECU in a known state, independent of the MCU and SBC, once a failure has been detected. The SAFE output structure is an open drain, without a pull-up.
6.2.13 Interrupt ( INT)
The INT output pin is asserted low or generates a low pulse when an interrupt condition occurs. The INT condition is enabled in the INT register. The selection of low level or pulse and pulse duration are selected by SPI. No current will flow inside the INT structure when VDD is low, and the device is in LP VDD OFF mode. This allows the connection of an external pull-up resistor and connection of an INT pin from other ICs without extra consumption in unpowered mode. INT has an internal pull-up structure to VDD. In LP VDD ON mode, a diode is inserted in series with the pull-up, so the high level is slightly lower than in other modes.
6.2.14 CANH, CANL, SPLIT, RXD, TXD
These are the pins of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is provided in the document.
6.2.15 LIN, LIN-T, TXDL and RXDL
These are the pins of the LIN physical interface. Device contains zero, one or two LIN interfaces. The MC33903, MC33903P, and MC33904 do not have a LIN interface. However, the MC33903S/5S (S = Single) and MC33903D/5D (D=Dual) contain 1 and 2 LIN interfaces, respectively. LIN, LIN1 and LIN2 pins are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TXD, TXD-L1 and TXD-L2 and RXD, RXD-L1 and RXD-L2 pins. The device also includes one or two HS switches to VSUP/2 pin which can be used as a LIN master termination switch. Pins LINT, LINT- 1 and LINT-2 pins are the same as I/O-2 and I/O-3.
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FUNCTIONAL DEVICE OPERATION
7 Functional device operation
7.1 Mode and state description
The device has several operation modes. The transitions and conditions to enter or leave each mode are illustrated in the state diagram.
7.1.1 INIT reset
This mode is automatically entered after the device is “powered on”. In this mode, the RST pin is asserted low, for a duration of typically 1.0 ms. Control bits and flags are ‘set’ to their default reset condition. The BATFAIL is set to indicate the device is coming from an unpowered condition, and all previous device configurations are lost and “reset” the default value. The duration of the INIT reset is typically 1.0 ms. INIT reset mode is also entered from INIT mode if the expected SPI command does not occur in due time (Ref. INIT mode), and if the device is not in the debug mode.
7.1.2 INIT
This mode is automatically entered from the INIT Reset mode. In this mode, the device must be configured via SPI within a time of 256 ms max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be, and can only be configured during INIT mode. Other registers can be written in this and other modes. Once the INIT register configuration is done, a SPI Watchdog Refresh command must be sent in order to set the device into Normal mode. If the SPI watchdog refresh does not occur within the 256 ms period, the device will return into INIT Reset mode for typically 1.0 ms, and then re enter into INIT mode. Register read operation is allowed in INIT mode to collect device status or to read back the INIT register configuration. When INIT mode is left by a SPI watchdog refresh command, it is only possible to re-enter the INIT mode using a secured SPI command. In INIT mode, the CAN, LIN1, LIN2, VAUX, I/O_x and Analog MUX functions are not operating. The 5 V-CAN is also not operating, except if the Debug mode is detected.
7.1.3 Reset
In this mode, the RST pin is asserted low. Reset mode is entered from Normal mode, Normal Request mode, LP VDD on mode and from the Flash mode when the watchdog is not triggered, or if a VDD low condition is detected. The duration of reset is typically 1.0 ms by default. You can define a longer Reset pulse activation only when the Reset mode is entered following a VDD low condition. Reset pulse is always 1.0 ms, when reset mode is entered due to wrong watchdog refresh command. Reset mode can be entered via the secured SPI command.
7.1.4 Normal request
This mode is automatically entered after RESET mode, or after a Wake-up from LP VDD ON mode. A watchdog refresh SPI command is necessary to transition to NORMAL mode. The duration of the Normal request mode is 256 ms when Normal Request mode is entered after RESET mode. Different durations can be selected by SPI when normal request is entered from LP VDD ON mode. If the watchdog refresh SPI command does not occur within the 256 ms (or the shorter user defined time out), then the device will enter into RESET mode for a duration of typically 1.0 ms. Note: in init reset, init, reset and normal request modes as well as in LP modes, the VDD external PNP is disabled.
7.1.5 Normal
In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request mode, or from INIT mode. During Normal mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. When an incorrect or missing watchdog refresh command is initiated, the device will enter into Reset mode. While in Normal mode, the device can be set to LP modes (LP VDD ON or LP VDD OFF) using the SPI command. Dedicated, secured SPI commands must be used to enter from Normal mode to Reset mode, INIT mode or Flash mode.
FUNCTIONAL DEVICE OPERATION
7.1.6 Flash
In this mode, the software watchdog period is extended up to typically 32 seconds. This allow programming of the MCU flash memory while minimizing the software over head to refresh the watchdog. The flash mode is entered by Secured SPI command and is left by SPI command. Device will enter into Reset mode. When an incorrect or missing watchdog refresh command device will enter into Reset mode. An interrupt can be generated at 50% of the watchdog period. CAN interface operates in Flash mode to allow flash via CAN bus, inside the vehicle.
7.1.7 Debug
Debug is a special operation mode of the device which allows for easy software and hardware debugging. The debug operation is detected after power up if the DBG pin is set to 8.0 to 10 V range. When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT mode, watchdog refresh of Normal mode and Flash mode, Normal Request time out (256 ms or user defined value) are not operating and will not lead to transition into INIT reset or Reset mode. When the device is in Debug mode, the SPI command can be sent without any time constraints with respect to the watchdog operation and the MCU program can be “halted” or “paused” to verify proper operation. Debug can be left by removing 8 to 10 V from the DEBUG pin, or by the SPI command (Ref. to MODE register). The 5 V-CAN regulator is ON by default in Debug mode.
7.2 LP modes
The device has two main LP modes: LP mode with VDD OFF, and LP mode with VDD ON. Prior to entering into LP mode, I/O and CAN Wake-up flags must be cleared (Ref. to mode register). If the Wake-up flags are not cleared, the device will not enter into LP mode. In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared, in order to meet the LP current consumption specification.
7.2.1 LP - V DD off
In this mode, VDD is turned OFF and the MCU connected to VDD is unsupplied. This mode is entered using SPI. It can also be entered by an automatic transition due to fail-safe management. 5 V-CAN and VAUX regulators are also turned OFF. When the device is in LP VDD OFF mode, it monitors external events to Wake-up and leave the LP mode. The Wake-up events can occur from:
- C A N
- LIN interface, depending upon device part number
- Expiration of an internal timer
- I/O-0, and I/O-1 inputs, and depending upon device pa rt number and configuration, I/O-2 and/or -3 input
- Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense of I/O-2 and -3 input, associated by I/O-0 activation When a Wake-up event is detected, the device enters into Reset mode and then into Normal Request mode. The Wake-up sources are reported to the device SPI registers. In summary, a Wake-up event from LP VDD OFF leads to the VDD regulator turned ON, and the MCU operation restart.
7.2.2 LP - V DD ON
In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to 100 μA or a few mA, as the ECU is in reduced power operation mode. During this mode, the 5 V-CAN and VAUX regulators are OFF. The optional external PNP at VDD will also be automatically disabled when entering this mode. The same Wake-up events as in LP VDD OFF mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP VDD on mode. In addition, two additional Wake-up conditions are available.
- Dedicated SPI command. When device is in LP V DD ON mode, the Wake-up by SPI command uses a write to “Normal Request mode”, 0x5C10.
- Output current from VDD exceeding L P-ITH threshold.
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FUNCTIONAL DEVICE OPERATION In LP VDD ON mode, the device is able to source several tenths of mA DC. The current source capability can be time limited, by a selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceed the output current threshold typically 1.5 mA. This allows for instance, a periodic activation of the MCU, while the device remains in LP VDD on mode. If the duration exceed the selected time (ex 32 ms), the device will detect a Wake-up. Wake-up events are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation.
7.2.2.1 Watchdog function in LP V DD on mode
It is possible to enable the watchdog function in LP VDD ON mode. In this case, the principle is timeout. Refresh of the watchdog is done either by:
- a dedicated SPI command (different from any other SPI command or simple CS activation which would Wake-up - Ref. to the previous paragraph)
- or by a temporary (less than 32 ms max) VDD over current Wake-up (IDD > 1.5 mA typically). As long as the watchdog refresh occurs, the device remains in LP VDD on mode.
7.2.2.2 Mode transitions
Mode transitions are either done automatically (i.e. after a timeout expired or voltage conditions), or via a SPI command, or by an external event such as a Wake-up. Some mode changes are performed using the Secured SPI commands.
7.3 State diagram
Figure 23. State diagram (4) VDD external PNP is disable in all mode except Normal and Flash modes.
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FUNCTIONAL DEVICE OPERATION
7.4 Mode change
7.4.1 ‘Secured SPI’ description A request is done by a SPI command, the device provide on MISO an unpredictable ‘random code’. Software must perform a logical change on the code and return it to the device with the new SPI command to perform the desired action. The ‘random code’ is different at every exercise of the secured procedure and can be read back at any time. The secured SPI uses the Special MODE register for the following transitions: - from Normal mode to INT mode - from Normal mode to Flash mode - from Normal mode to Reset mode (reset request). “Random code” is also used when the ‘advance watchdog’ is selected.
7.4.2 Changing of device critical parameters
Some critical parameters are configured one time at device power on only, while the batfail flag is set in the INIT mode. If a change is required while device is no longer in INIT mode, device must be set back in INIT mode using the “SPI secure” procedure.
7.5 Watchdog operation
7.5.1 In normal request mode
In Normal Request mode, the device expects to receive a watchdog configuration before the end of the normal request time out period. This period is reset to a long (256 ms) after power on and when BATFAIL is set. The device can be configured to a different (shorter) time out period which can be used after Wake-up from LP VDD on mode. After a software watchdog reset, the value is restored to 256 ms, in order to allow for a complete software initialization, similar to a device power up. In Normal Request mode the watchdog operation is “timeout” only and can be triggered/observed any time within the period.
7.5.2 Watchdog type selection
Three types of watchdog operation can be used: - Window watchdog (default) - Timeout operation - Advanced The selection of watchdog is performed in INIT mode. This is done after device power up and when the BATFAIL flag is set. The Watchdog configuration is done via the SPI, then the Watchdog mode selection content is locked and can be changed only via a secured SPI procedure.
7.5.2.1 Window watchdog operation
The window watchdog is available in Normal mode only. The watchdog period selection can be kept (SPI is selectable in INIT mode), while the device enters into LP VDD ON mode. The watchdog period is reset to the default long period after BATFAIL. The period and the refresh of watchdog are done by the SPI. A refresh must be done in the open window of the period, which starts at 50% of the selected period and ends at the end of the period. If the watchdog is triggered before 50%, or not triggered before end of period, a reset has occurred. The device enters into Reset mode.
7.5.2.2 Watchdog in debug mode
When the device is in Debug mode (entered via the DBG pin), the watchdog continues to operate but does not affect the device operation by asserting a reset. For the user, operation appears without the watchdog. When Debug mode is left by software (SPI mode reg), the watchdog period starts at the end of the SPI command. When Debug mode is left by hardware (DBG pin below 8-10 V), the device enters into Reset mode.
FUNCTIONAL DEVICE OPERATION
7.5.2.3 Watchdog in flash mode
During Flash mode, watchdog can be set to a long timeout period. Watchdog is timeout only and an INT pulse can be generated at 50% of the time window.
7.5.2.4 Advance watchdog operation
When the Advance watchdog is selected (at INIT mode), the refresh of the watchdog must be done using a random number and with 1, 2, or 4 SPI commands. The number for the SPI command is selected in INIT mode. The software must read a random byte from the device, and then must return the random byte inverted to clear the watchdog. The random byte write can be performed in 1, 2, or 4 different SPI commands. If one command is selected, all eight bits are written at once. If two commands are selected, the first write command must include four of the eight bits of the inverted random byte. The second command must include the next four bits. This completes the watchdog refresh. If four commands are selected, the first write command must include two of the eight bits of the inverted random byte. The second command must include the next two bits, the 3rd command must include the next two, and the last command, must include the last two. This completes the watchdog refresh. When multiple writes are used, the most significant bits are sent first. The latest SPI command needs to be done inside the open window time frame, if window watchdog is selected. 7.5.3 Detail SPI operation and SPI commands for all watchdog types. All SPI commands and examples do not use parity functions. In INIT mode, the watchdog type (window, timeout, advance and number of SPI commands) is selected using the register Init watchdog, bits 1, 2 and 3. The watchdog period is selected using the TIM_A register. The watchdog period selection can also be done in Normal mode or in Normal Request mode. Transition from INIT mode to Normal mode or from Normal Request mode to Normal mode is done using a single watchdog refresh command (SPI 0x 5A00). While in Normal mode, the Watchdog Refresh Command depends upon the watchdog type selected in INIT mode. They are detailed in the paragraph below:
7.5.3.1 Simple watchdog
The Refresh command is 0x5A00. It can be send any time within the watchdog period, if the timeout watchdog operation is selected (INIT- watchdog register, bit 1 WD N/Win = 0). It must be send in the open window (second half of the period) if the Window Watchdog operation was selected (INIT-watchdog register, bit 1 WD N/Win = 1).
7.5.3.2 Advance watchdog
The first time the device enters into Normal mode (entry on Normal mode using the 0x5A00 command), Random (RNDM) code must be read using the SPI command, 0x1B00. The device returns on MISO second byte the RNDM code. The full 16 bits MISO is called 0x XXRD. RD is the complement of the RD byte.
7.5.3.3 Advance watchdog, re fresh by 1 SPI command
The refresh command is 0x5ARD. During each refresh command, the device will return on MISO, a new Random Code. This new Random Code must be inverted and send along with the next refresh command. It must be done in an open window, if the Window operation was selected.
7.5.3.4 Advance watchdog, refr esh by two SPI commands
The refresh command is split in two SPI commands. The first partial refresh command is 0x5Aw1, and the second is 0x5Aw2. Byte w1 contains the first four inverted bits of the RD byte plus the last four bits equal to zero. Byte w2 contains four bits equal to zero plus the last four inverted bits of the RD byte. During this second refresh command the device returns on MISO a new Random Code. This new random code must be inverted and send along with the next two refresh commands and so on. The second command must be done in an open window if the Window operation was selected.
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FUNCTIONAL DEVICE OPERATION
7.5.3.5 Advance watchdog, refr esh by four SPI commands
The refresh command is split into four SPI commands. The first partial refresh command is 0x5Aw1, the second is 0x5Aw2, the third is 0x5Aw3, and the last is 0x5Aw4. Byte w1 contains the first two inverted bits of the RD byte, plus the last six bits equal to zero. Byte w2 contains two bits equal to zero, plus the next two inverted bits of the RD byte, plus four bits equal to zero. Byte w3 contains four bits equal to zero, plus the next two inverted bits of the RD byte, plus two bits equal to zero. Byte w4 contains six bits equal to zero, plus the next two inverted bits of the RD byte. During this fourth refresh command, the device will return, on MISO, a new Random Code. This new Random Code must be inverted and send along with the next four refresh commands. The fourth command must be done in an open window if the Window operation was selected.
7.5.4 Proper response to INT
During a device detect upon an INT, the software handles the INT in a timely manner: Access of the INT register is done within two watchdog periods. This feature must be enabled by SPI using the INIT watchdog register bit 7.
7.6 Functional block operation versus mode
The 5 V-CAN default is ON when the device is powered-up and set in Debug mode. It is fully controllable via the SPI command. Table 8. Device block operation for each state
- With limited current capability
- 5 V-CAN is ON in Debug mode.
- I/O-0 and I/O-1, configured as an output high-si de switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request.
- I/O-0, configured as an output low-side switch and ON in Norm al mode will turn OFF when entering Reset mode, resume operation in Normal
- I/O-1, configured as an output low-side switch and ON in Norm al mode will remain ON in RESET, INIT or Normal Request.
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7.7 Illustration of d evice mode transitions
Figure 24. Power up normal and LP modes
Figure 25. Wake-up from LP modes
7.8 Cyclic sense operation during LP modes
This function can be used in both LP modes: VDD OFF and VDD ON. switch in order to minimize consumption via the contact pull-up resistor.
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7.8.1 Principle
A dedicated timer provides an opportunity to select a cyclic sense period from 3.0 to 512 ms (selection in timer B). 1.6 ms). The I/O-0 HS transistor or LS transistor can be activated. The selection is done by the state of I/O-0 prior to entering in LP mode. During the T-CSON duration, the I/O-x’s are monitored. If one of them is high, the device will detect a Wake-up. (Figure 26). Cyclic sense period is selected by the SPI configuration prior to entering LP mode. Upon entering LP mode, the I/O-0 should be activated. with I/O-0 HS active and I/O-1 Wake-up at high level. Figure 26. Cyclic sense operation - switch to GND, wake-up by open switch contact switches are closed. In LP mode, 1 contact switch is open. High level is detected on I/O-x, and device wakes up.
FUNCTIONAL DEVICE OPERATION
7.9 Cyclic INT operation during LP VDD on mode
7.9.1 Principle
This function can be used only in LP VDD ON mode (LP VDD ON). When Cyclic INT is selected and device is in LP VDD ON mode, the device will generate a periodic INT pulse. Upon reception of the INT pulse, the MCU must acknowledge the INT by sending SPI commands before the end of the next INT period in order to keep the process going. When Cyclic INT is selected and operating, the device remains in LP VDD ON mode, assuming the SPI commands are issued properly. When no/improper SPI commands are sent, the device will cease Cyclic INT operation and leave LP VDD ON mode by issuing a reset. The device will then enter into Normal Request mode. VDD current capability and VDD regulator behavior is similar as in LP VDD ON mode.
7.9.1.1 Operation
Cyclic INT period selection: register timer B SPI command in hex 0x56xx [example; 0x560E for 512ms cyclic Interrupt period (SPI command without parity bit)]. This command must be send while the device is in Normal mode. SPI commands to acknowledge INT: (2 commands) - read the Random code via the watchdog register address using the following command: MOSI 0x1B00 device report on MISO second byte the RNDM code (MISO bit 0-7). - write watchdog refresh command using the random code inverted: 0x5A RNDb. These commands can occur at any time within the period. Initial entry in LP mode with Cyclic INT: after the device is set in LP VDD ON mode, with cyclic INT enable, no SPI command is necessary until the first INT pulse occurs. The acknowledge process must start only after the 1st INT pulse. Leave LP mode with Cyclic INT: This is done by a SPI Wake-up command, similar to SPI Wake-up from LP VDD ON mode: 0x5C10. The device will enter into Normal Request mode. Improper SPI command while Cyclic INT operates: When no/improper SPI commands are sent, while the device is in LP VDD ON mode with Cyclic INT enable, the device will cease Cyclic INT operation and leave LP VDD ON mode by issuing a reset. The device will then enter into Normal Request mode. Figure 27 describes the complete Cyclic Interrupt operation.
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Figure 27. Cyclic interrupt operation
7.10 Behavior at power up and power down
7.10.1 Device power up
the two VDD undervoltage reset thresholds. VSUP/1 is above VSUP TH 1 parameters.
Figure 28. VDD start-up versus VSUP/1 tramp
7.10.2 Device power down
7.10.2.1 Crank bit reset (INIT watchdog register, Bit 0 =0)
Bit 0 = 0 is the default state for this bit. 3.2 V typically, threshold selected by the SPI). When device is in Reset, if VSUP/1 is below “VSUP_TH1”, VDD is turned OFF.
7.10.2.2 Crank bit set (INIT watchdog register, Bit 0 =1)
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Figure 29. VDD behavior during VSUP/1 ramp down
7.11 Fail-safe operation
7.11.1 Overview
pin. Safe mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin. I/O (if configured as inputs). Upon Wake-up, the device operation is resumed: enter in Reset mode.
7.11.2 Fail-safe functionality
7.11.2.1 Description
7.11.2.2 Mode A
control the device and properly refresh the watchdog).
7.11.2.3 Modes B1, B2 and B3
events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3. (ignition key on/off signal). SPI command related to Debug resistor change is send, operates according to the detected resistor. The INIT MISC register allow you to verify and change the device behavior, to either confirm or change the hardware selected behavior. Device will then operate according to the SAFE mode configured by the SPI. Table 9. Fail-safe options typically 33 kohm (RB2 - Selection of SAFE mode B2 B2 Turn OFF when I/O-1 low level detected. detection AND when I/O-1 low level detected.
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7.11.2.4 Exit of safe mode
Figure 30. Safe operation flow chart
7.11.2.5 Conditions to set SAFE pin active low
clamped to a low level preventing the MCU to operate. If this is the case, the Safe mode is entered. 5) detection of 8 consecutive watchdog failures: no correct SPI watchdog refresh command occurred for duration of 8 x 256 ms. between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes. 7) 8 second timer for bus idle timeout. I/O-1 high to low transition.
7.11.2.6 SAFE mode A illustration
Figure 31 illustrates the event and consequences when SAFE mode A is selected via the appropriate debug resistor or SPI configuration. Figure 31. SAFE mode A behavior illustration
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7.11.2.7 SAFE mode B1, B2 and B3 illustration
Figure 32. SAFE modes B1, B2, or B3 behavior illustration
8.1 CAN interface description
to GND in CAN Sleep mode. A dedicated split buffer provides a low-impedance 2.5 V to the SPLIT pin, for recessive level stabilization. Figure 33. CAN interface block diagram
8.1.1 Can interface supply
VSUP/2 pin. This pass is used in CAN Sleep mode to allow Wake-up detection. mode, the current is sourced from the VSUP/2 pin.
8.1.2 TXD/RXD mode
CAN bus state is reported on the RXD pin.
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8.1.2.1 Receive only mode
This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN state on the RXD pin. The TXD pin has no effect on CAN bus lines. The 5 V-CAN regulator must be ON. The SPLIT pin is active and a 2.5 V biasing is provided on the SPLIT output pin.
8.1.2.2 Operation in TXD/RXD mode
The CAN driver will be enabled as soon as the device is in Normal mode and the TXD pin is recessive. When the CAN interface is in Normal mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin. When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set with 5 V-CAN divided by 2, or approx. 2.5 V. When TXD is low, the bus is set into the dominant state, and CANL and CANH drivers are active. CANL is pulled low and CANH is pulled high. The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV). If “CANH minus CANL” is below the threshold, the bus is recessive and RXD is set high. If “CANH minus CANL” is above the threshold, the bus is dominant and RXD is set low. The SPLIT pin is active and provides a 2.5 V biasing to the SPLIT output.
8.1.2.3 TXD/RXD mode and slew rate selection
The CAN signal slew rate selection is done via the SPI. By default and if no SPI is used, the device is in the fastest slew rate. Three slew rates are available. The slew rate controls the recessive to dominant, and dominant to recessive transitions. This also affects the delay time from the TXD pin to the bus and from the bus to the RXD. The loop time is thus affected by the slew rate selection.
8.1.2.4 Minimum baud rate
The minimum baud rate is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag). The shortest TXD dominant detection time of 300 μs lead to a single bit time of: 300 μs / 12 = 25 μs. So the minimum Baud rate is 1 / 25 μs = 40 kBaud.
8.1.2.5 Sleep mode
Sleep mode is a reduced current consumption mode. CANH and CANL drivers are disabled and CANH and CANL lines are terminated to GND via the RIN resistor, the SPLIT pin is high-impedance. In order to monitor bus activities, the CAN Wake-up receiver can be enabled. It is supplied internally from VSUP/2. Wake-up events occurring on the CAN bus pin are reporting by dedicated flags in SPI and by INT pulse, and results in a device Wake-up if the device was in LP mode. When the device is set back into Normal mode, CANH and CANL are set back into the recessive level. This is illustrated in Figure 34.
Figure 34. Bus signal in TXD/RXD and LP mode
8.1.2.6 Wake-up
Wake-up. The Wake-up by the CAN is enabled or disabled via the SPI. Figure 35. Single dominant pulse wake-up
8.1.2.7 Pattern wake-up
valid. When three pulses meet these conditions, the wake signal is detected. This is illustrated by the following figure.
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Figure 36. Pattern wake-up - multiple dominant detection
8.1.3 BUS termination
- Differential termination resistor s between CANH and CANL lines.
- SPLIT termination concept, with the mid point of the differential termination connected to GND through a capacitor and to the SPLIT pin.
- In application, the device can also be used without termination.
- Figure 37 illustrates some of the most common terminations.
Figure 37. Bus termination options
8.2 CAN bus fault diagnostic
by a logic circuitry to properly determine the failure and report it.
Figure 38. CAN bus simplified structure truth table for failure detection The following table indicates the state of the comparators when there is a bus failure, and depending upon the driver state.
8.2.1 Detection principle
measured by the Hg comparator is also close to zero. on, and in the dominant state.
8.2.1.1 Number of samples for proper failure detection
error for five recessive-dominant cycles, the error is not reported.
8.2.2 Bus clamping detection
If the bus is detected to be in dominant for a time longer than (TDOM), the bus failure flag is set and the error is reported in the SPI. which are terminated to internal 2.5 V biasing or to GND (Sleep mode). Table 10. Failure detection truth table
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TXD. The bus dominant clamp circuit will help to determine such failure situation.
8.2.3 RXD permanent recessive failure (d oes not apply to ‘C’ and ‘D’ versions)
Figure 39. RXD path simplified schematic, RXD short to VDD detection
8.2.3.1 Implementation for detection
RXD will be tied to a high level and can be detected at the next low to high transition of the differential receiver. As soon as the RXD permanent recessive is detected, the RXD driver is deactivated. Once the error is detected the driver is disabled and the error is reported via SPI in CAN register.
8.2.3.2 Recovery condition
The internal recovery is done by sampling a correct low level at TXD as shown in the following illustration. Figure 40. RXD path simplified schematic, RXD short to VDD detection The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
8.2.4 TXD permanent dominant
8.2.4.1 Principle
If the TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The device has a TXD permanent timeout detector. After the timeout (TDOUT), the bus driver is disabled and the bus is released into a recessive state. The TXD permanent flag is set.
8.2.4.2 Recovery
The TXD permanent dominant is used and activated when there is a TXD short to RXD. The recovery condition for a TXD permanent dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal mode controlled by the MCU or when TXD is recessive while RXD change from recessive to dominant.
8.2.5 TXD to RXD short-circuit
8.2.5.1 Principle
When TXD is shorted to RXD during incoming dominant information, RXD is set to low. Consequently, the TXD pin is low and drives CANH and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible.
8.2.5.2 Detection and recovery
The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant bit, the bus will then be stuck in dominant again. The recovery condition is same as the TXD dominant failure
8.2.6 Important information fo r bus driver reactivation
The driver stays disabled until the failure is/are removed (TXD and/or RXD is no longer permanent dominant or recessive state or shorted) and the failure flags cleared (read). The CAN driver must be set by SPI in TXD/RXD mode in order to re enable the CAN bus driver.
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9 LIN block
9.1 LIN interface description
The physical interface is dedicated to automotive LIN sub-bus applications. The interface has 20 kbps and 10 kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior when a LIN bus short-to-ground, or a LIN bus leakage during LP mode. Digital inputs are related to the device VDD pin.
9.1.1 Power supply pin (VSUP/2)
The VSUP/2 pin is the supply pin for the LIN interface. To avoid a false bus message, an undervoltage on VSUP/2 disables the transmission path (from TXD to LIN) when VSUP/2 falls below 6.1 V.
9.1.2 Ground pin (GND)
When there is a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus pin when in the recessive state.
9.1.3 LIN bus pin (LIN, lin1, lin2)
The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal mode.
9.1.3.1 Driver characteristics
The LIN driver is a LS MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ must be added when the device is used in the master node. The 1.0 kΩ pull-up resistor can be connected to the LIN pin or to the ECU battery supply. The LIN pin exhibits no reverse current from the LIN bus line to VSUP/2, even in the event of a GND shift or VSUP/2 disconnection. The transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI.
9.1.3.2 Receiver characteristics
The receiver thresholds are ratiometric with the device VSUP/2 voltage. If the VSUP/2 voltage goes below typically 6.1 V, the LIN bus enters into a recessive state even if communication is sent on TXD. If LIN driver temperature reaches the overtemperature threshold, the transceiver and receiver are disabled. When the temperature falls below the overtemperature threshold, LIN driver and receiver will be automatically enabled.
9.1.4 Data input pin (T XD-L, TXD-L1, TXD-L2)
The TXD-L,TXD-L1 and TXD-L2 input pin is the MCU interface to control the state of the LIN output. When TXD-L is LOW (dominant), LIN output is LOW. When TXD-L is HIGH (recessive), the LIN output transistor is turned OFF. This pin has an internal pull-up current source to VDD to force the recessive state if the input pin is left floating. If the pin stays low (dominant sate) more than t TXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag in LIN register.
9.1.5 Data output pin (R XD-L, RXD-L1, RXD-L2)
This output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage on RXD, LIN LOW (dominant) is reported by a low voltage on RXD.
9.2 LIN operational modes
The LIN interface have two operational modes, Transmit receiver and LIN disable modes.
9.2.1 Transmit receive
In the TXD/RXD mode, the LIN bus can transmit and receive information. When the 20 kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1. When the 10 kbps baud rate is selected, the slew rate and timing are compatible with J2602-2. When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition. while TXD-L is low, the command is ignored.
9.2.2 Sleep mode
This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP/2 is very low (typically 3.0 μA). disconnected. The LIN block can be awakened from Sleep mode by detection of LIN bus activity.
9.2.2.1 LIN bus activity detection
mode. The Wake-up can be enable or disable by the SPI. Table 11 describes the LIN block behavior when there is a failure. Table 11. LIN block failure
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10 Serial peripheral interface
10.1 High level overview
- bits 15 and 14 (called C1 and C0) are control bits to select the SPI operation mode (write control bit to device register, read back of the control bits, read of device flag).
- bit 13 to 9 (A4 to A0) to select the register address.
- bit 8 (P/N) has two functions: parity bit in write mode (optional, = 0 if not used), Next bit ( = 1) in read mode.
- bit 7 to 0 (D7 to D0): control bits MISO, Master In Slave Out bits:
- bits 15 to 8 (S15 to S8) are device status bits
- bits 7 to 0 (Do7 to Do0) are either extended device status bits, device internal control register content or device flags. The SPI implementation does not support daisy chain capability. Figure 41 is an overview of the SPI implementation.
Figure 41. SPI overview
10.2 Detail operation
The SPI operation deviation (does not apply to ‘C’ and ‘D’ versions). a ‘corrupted SPI command’. Important: Due to this, the tLEAD and tCSLOW parameters must be carefully acknowledged. guarantee proper operation, the following steps must be taken.
- Ensure the duration of the Chip Select Low (tCSLOW) state is >5.5 μs.
x tPCLK + tLAG (sum = 4.06 μs). and sampled at falling edge. Msb first.
SERIAL PERIPHERAL INTERFACE 2. Ensure SPI timing parameter tLEAD is a min. of 550 ns. Note: In data sheet revisions prior to 7.0, the tLEAD parameter is a min of 30 ns. 3. Make sure to include a SPI read command after a SPI write command. In case a series of SPI write commands is used, only one additional SPI read is necessary. The recommended SPI read command is “device ID read: 0x2580” so device operation is not affected (ex: clear flag). Other SPI read commands may also be used. When the previous steps are implemented, the device will operate as follows: For a given SPI write command (named SPI write ‘n’):
- In case the SPI write command ‘n’ is not accepted, the following SPI command (named SPI ‘n+1’) will finish the write process of the SPI write ‘n’, thanks to step 2 (tLAG > 550 ns) and step 3 (which is the additional SPI command ‘n+1’).
- By applying steps 1, 2, and 3, no SPI co mmand is ignored. Worst case, the SPI write ‘n’ is executed at the time the SPI ‘n+1’ is sent. This will lead to a delay in device operation (delay between SPI command ‘n’ and ‘n+1’). Note: Occurrence of an incorrect command is reduced, thanks to step 1 (extension of tCSLOW duration to >5.5 μs). Sequence examples: Example 1:
- 0x60C0 (CAN interface control) – in case this co mmand is missed, next write command will complete it
- 0x66C0 (LIN interface control) – in case this command is missed, next read command will complete it
- 0x2580 (read device ID) – Additional command to comp lete previous LIN command, in case it was missed Example 2:
- 0x60C0 (CAN interface control) - in case this co mmand is missed, next write command will complete it
- 0x66C0 (LIN interface control) - in case this co mmand is missed, next read command will complete it
- 0x2100 (read CAN register content) – this command will complete previous one, in case it was missed
- 0x2700 (read LIN register content) SPI Operation if the CSB low flag is set to '1' (All product versions) When the ‘CSB low’ flag is set (Bit 4 = '1' using the 0xE300 SPI command), the next SPI write commands are executed by the device only if the SPI tLEAD time is between 30 ns and 2.5 µs maximum for the ‘C’ and ‘D’ versions, and 550 ns and 2.5 µs maximum for others versions. The occurrence of the CSB flag set to ‘1’ is extremely low and is directly linked to an intermittent short to ground on the board trace or a CSB driven low by the MCU. In both cases, the CSB pin must be asserted low for more than 2.0 ms to set the flag. The tLEAD time is represented in the SPI timing diagram (Figure 14) and corresponds to the time between CSB high to low transition and first SCLK signal. Note: If the flag is cleared by a read command and the fault is no longer present, the 2.5 µs maximum of tLEAD time does not apply, but can also be respected. This means if all the SPI write commands use a maximum tLEAD time of 2.5 µs, they are all interpreted by the device, whatever the indication of the ‘CSB low’ flag.
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10.2.1 Bits 15, 14, and 8 functions
Table 12 summarizes the various SPI operation, depending upon bit 15, 14, and 8.
10.2.2 Bits 13-9 functions
The device contains several registers coded on five bits (bits 13 to 9). written) is correct. In addition, some of the registers are used to report device flags.
10.2.2.1 Device status on MISO
status (bits 15 to 8) and the next eight bits will be the content of the selected register.
10.2.3 Register adress table
Table 13 is a list of device registers and addresses, coded with bits 13 to 9. Table 12. SPI operations (bits 8, 14, & 15)
1 Bit 8 must be set to 1, independently of the parity function
0 If bit 8 is set to “0”: means parity not selected OR
10 Reserved
11 Read of device flags
Table 13. Device registers with corresponding address 0_0000 Analog Multiplexer MUX 1) Write ‘device control bits’ to register address. 1) Write ‘data byte’ to register address. 1) Write ‘device initialization control bits’ to register address.
10.2.4 Complete SPI operation
Table 14 is a compiled view of all the SPI capabilities and options. Both MOSI and MISO information are described. Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity is selected and parity = 1.
10.2.5 Parity bit 8
10.2.5.1 Calculation
15-9,7-0 sequence (this is the entire 16 bits of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even. 2) Read back register ‘control bits’. 3) Read device flags from each of the register addresses. Table 14. SPI capabilities with options Table 13. Device registers with corresponding address (continued)
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10.2.5.2 Examples 1:
10.2.5.3 Examples 2:
10.2.5.4 Parity function selection
All SPI commands and examples do not use parity functions. The parity function is optional. It is selected by bit 6 in INIT MISC register. If parity function is not selected (bit 6 of INIT MISC = 0), then Parity bits in all SPI commands (bit 8) must be ‘0’.
10.3 Detail of control bits and register mapping
10.3.1 MUX and RAM registers
Table 15. MUX Register(42)
011 Device internal temperature sensor voltage
100 Voltage at I/O-0. Attenuation or gain is selected by bit 3. 101 Voltage at I/O-1. Attenuation or gain is selected by bit 3. 0 Internal 2.0 kohm resistor disable. An external resistor must be connected between AMUX and GND. 1 Internal 2.0 kohm resistor enable.
- The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while 5V-CAN is OFF, the
command is ignored, and the MXU register content is reset to default state (all control bits = 0).
10.3.2 INIT registers
Table 16. Internal memory registers A, B, C, and D, RAM_A, RAM_B, RAM_C, and RAM_D Table 17. Initialization regulator registers, INIT REG (note: register can be written only in INIT mode)
0 I/O-1 sense anytime
1 I/O-1 sense during I/O-0 activation
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Table 18. Initialization watchdog registers, INIT watchdog (note: register can be written only in INIT mode) 0 Function disable. No constraint between INT occurrence and INT source read. 1 INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods. 00 In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. 01 In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. 10 In LP VDD ON mode, VDD overcurrent for a time > 100 μs (typically) is a wake-up event.
0 SAFE pin is set low at the time of the RST pin low activation
1 SAFE pin is set low at the second consecutive time RST pulse
00 Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI
01 Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits. 10 Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.
11 Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.
0 Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period
1 Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period)
Table 19. Initialization LIN and I/O registers, INIT LIN I/O (note: register can be written only in INIT mode) 1 Enable I/O-1 turn off, when VDD or VAUX overvoltage condition is detected.
11 N/A
0 Disable HS and LS drivers of pin I/O-1. I/O-1 can only be used as input. 1 Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver. 0 Disable HS and LS drivers of I/O-0 can only be used as input. 1 Enable HS and LS drivers of the I/O-0 pin. Pin can be used as input and output drivers.
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is disable (HS and LS drivers OFF). of the active time, for the duration of the cyclic sense period. Table 20. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT mode)
0 Function disable: the LP mode can be entered without usage of Random Code
1 Function enabled: the LP mode is entered using the Random Code
0 Function disable: the parity is not used. The parity bit must always set to logic 0. 1 Function enable: the parity is used, and parity must be calculated.
0 INT pin will assert a low level pulse, duration selected by bit [b4]
1 INT pin assert a permanent low level (no pulse)
0 INT pulse duration is typically 100 μs. Ref. to dynamic parameter table for exact value. 1 INT pulse duration is typically 25 μs. Ref. to dynamic parameter table for exact value. Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash mode.
- Bits b2,1 and 0 allow the following operation:
register (Ref. to device flag table).
10.3.3 Specific mode register
10.3.3.1 The SPE mode register is used for the following operation
- Set the device in RESET mode, to exercise or test the RESET functions.
- Go to INIT mode, using the Secure SPi command.
- Go to FLASH mode (in this mode the watchdog timer can be extended up to 32 s).
- Activate the SAFE pin by S/W.
Table 21. Specific mode register, SPE_MODE
00 RESET mode
01 INIT mode
10 FLASH mode
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10.3.4 Timer registers
Table 22. Timer register A, LP VDD overcurrent & watchdog period normal mode, TIM_A Table 23. Timer register B, cyclic sense and cyclic INT, in device LP mode, TIM_B
10.3.5 Watchdog and mode registers
Table 24. Timer register C, watchdog LP mode or flash mode and forced wake-up timer, TIM_C Table 25. Typical timing values Table 26. Watchdog refresh register, watchdog(44)
- The Simple Watchdog Refresh command is in hexadecimal: 5A00 . This command is used to refresh the watchdog and also to
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Prior to enter in LP VDD ON or LP VDD OFF, the Wake-up flags must be cleared or read. When the device is in LP VDD ON mode, the Wake-up by a SPI command uses a write to ‘Normal Request mode’, 0x5C10. Table 27. MODE register, mode Table 28. LP VDD off selection and FWU / cyclic sense selection Table 29. LP VDD on selection and operation mode Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command.
10.3.5.1 Mode register features
These global commands are built using the MODE register address bit [13-9], along with several combinations of bit [15-14] and bit [7]. Note, bit [8] is always set to 1.
10.3.5.2 Entering into LP mo de using random code
- LP mode using Random Code must be selected in INIT mode via bit 7 of the INIT MISC register.
- In Normal mode, read the Random Code using 0x1D00 or 0x1D80 command. The 3 Random Code bits are available on MISO bits 2,1 and 0.
- Write LP mode by inverting the 3 random bits.
- in hex: 0x5C60 to enter in LP VDD OFF mode without using the 3 random code bits.
- if Random Code is selected, the commands are:
MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1], Rnd_[0]. Table 31 describes MISO bits 7-0, used to decode the device’s current mode. Table 30. Device modes Read device current mode, Leave debug mode. Release SAFE pin (turn OFF). Read device current mode, Leave debug mode. Release SAFE pin (turn OFF).
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Table 32 describes the SAFE and DEBUG bit decoding. Table 31. MISO bits 7-3
1 XXXX Low Power mode (Table 29)
Table 32. SAFE and DEBUG status
0 SAFE pin ON, driver activated
1 SAFE pin OFF, not activated
0 Debug mode OFF
1 Debug mode Active
10.3.6 Regulator, CAN, I/O , INT and lin registers
Table 33. Regulator register
00 Regulator OFF
detected after 1.0 ms blanking time.
0 External VDD ballast disable
1 External VDD ballast Enable
0 Disable the automatic activation of the external ballast
1 Enable the automatic activation of the external ballast, if VDD > typically 60 mA
0 Disable Usage of LP VDD OFF mode
1 Enable Usage of LP VDD OFF mode
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Table 34. CAN register(45) 00 CAN interface in Sleep mode, CAN Wake-up disable. 01 CAN interface in receive only mode, CAN driver disable. CAN Wake-up is reported by device Wake-up. In device Normal mode, CAN Wake-up reported by INT. 11 CAN interface in transmit and receive mode.
01 MEDIUM
10 SLOW
1 Single dominant pulse Wake-up mechanism
1 Select INT generation as soon as a bus failure is detected, event if not fully identified
- The first time the device is set to Normal mode, the CAN is in Sleep Wake-up enabled (bit7 = 1, bit 6 =0). The next time the device is
set in Normal mode, the CAN state is controlled by bits 7 and 6.
Table 35. I/O register
00 I/O-3 driver disable, Wake-up capability disable
01 I/O-3 driver disable, Wake-up capability enable.
00 I/O-2 driver disable, Wake-up capability disable
01 I/O-2 driver disable, Wake-up capability enable.
00 I/O-1 driver disable, Wake-up capability disable
01 I/O-1 driver disable, Wake-up capability enable.
00 I/O-0 driver disable, Wake-up capability disable
01 I/O-0 driver disable, Wake-up capability enable.
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Table 36. INT register
0 INT disable
- If VDD undervoltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 69.
- Bit 2 is used in conjunction with bi t 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request.
Table 37. LIN/1 Register(49)
00 LIN/1 disable, Wake-up capability disable
10 LIN/1 disable, Wake-up capability enable
11 LIN/1 Transmit Receive mode(48)
00 Slew rate for 20 kbit/s baud rate
01 Slew rate for 10 kbit/s baud rate
10 Slew rate for fast baud rate
11 Slew rate for fast baud rate
0 LIN/1 termination OFF
1 LIN/1 termination ON
1 LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.
- The LIN interface can be set in TXD/RXD mode only when the TXD-L i nput signal is in recessive state. An attempt to set TXD/RXD
mode, while TXD-L is low, will be ignored and the LIN interface remains disabled.
- In order to use the LIN interface, the 5V-CAN regulator must be set to ON.
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10.4 Flags and device status
10.4.1 Description
commands do not use parity functions). They are obtained using the following commands.
- [1 1] for failure flags
- - [0 0] for I/O real time status , device identification and CAN LIN driver receiver real time state.
- bit 13 to 9 are the register address from which the flags is to be read.
- b i t 8 = 1 (this is not parity bit function, as this is a read command). When a failure event occurs, the respective flag is set and remains latched until it is cleared by a read command (provided the failure event has recovered).
Table 38. LIN2 register(51)
00 LIN2 disable, Wake-up capability disable
10 LIN2 disable, Wake-up capability enable
11 LIN2 Transmit Receive mode(50)
0 LIN 2 termination OFF
1 LIN 2 termination ON
1 LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.
- The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in a recessive state. An attempt to set TXD/RXD
mode while TXD-L is low, will be ignored and the LIN interface will remain disabled.
- In order to use the LIN interface, the 5V-CAN regulator must be set to ON.
Table 39. Device flag, I/O real time and device identification
0 CAN
1 CAN_UF CAN_F CANL
0 HS3 short
1 I/O_1-3
0 INT
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- Not available on ‘C’ and ‘D’ versions
Table 40. Flag descriptions Description Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold. Description Report that current out of VAUX regulator is above VAUX_OC threshold. Set / Reset condition Set: Current above threshold for t >100 μs. Reset: Current below threshold and flag read by SPI.
5 V-CAN_
Description Report that the 5 V-CAN regulator has reached overtemperature threshold. Description Reports that 5 V-CAN regulator output voltage is lower than the 5 V-CAN UV threshold. Description Report that the CAN driver output current is above threshold. Description Reports that VSENSE pin is lower than the VSENSE LOW threshold. Description Reports that VSUP/1 pin is lower than the VS1_LOW threshold. Description Report that current out of VDD pin is higher that IDD-OC threshold, while device is in Normal mode. Description Report that the VDD has reached overtemperature threshold, and was turned off. Description Report that the device voltage at VSUP/1 pin was below BATFAIL threshold.
(0x2180) do not clear the flag, as it is “real time” information. Description Report that the CAN interface has reach overtemperature threshold. RXD low(53) Description Report that RXD pin is shorted to GND. Description Report that RXD pin is shorted to recessive voltage. Description Report that TXD pin is shorted to GND. Description Report that the CAN current is above CAN overcurrent threshold.
- Not available on ‘C’ and ‘D’ versions
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Description Report SPI parity error was detected. Description Report that VSUP/2 is below VS2_LOW threshold. Description Report that VSUP/1 is above VS_HIGH threshold. Description Report that the I/O-0 HS switch has reach overtemperature threshold. Description Report that the watchdog period has reach 50% of its value, while device is in Flash mode. Description Report that Wake-up source is SPI command, in LP VDD ON mode. Description Report that INT timeout error detected. Set / Reset condition Set: INT service timeout expired. Reset: flag read. Description Report that LP VDD OFF mode was selected, prior Wake-up occurred. Description Report that RST source is an request from a SPI command (go to RST mode). Set / Reset condition Set: device leave debug mode due to hardware cause. Reset: flag read.
SERIAL PERIPHERAL INTERFACE INT INT request Description Report that INT source is an INT request from a SPI command. Set / Reset condition Set: INT occurred. Reset: flag read (SPI) RST high Description Report that RST pin is shorted to high voltage. Set / Reset condition Set: RST failure detection. Reset: flag read. DBG resistor Description Report that the resistor at DBG pin is different from expected (different from SPI register content). Set / Reset condition Set: failure detected. Reset: correct resistor and flag read (SPI). VDD TEMP PRE- WARNING Description Report that the VDD has reached overtemperature pre-warning threshold. Set / Reset condition Set: VDD thermal sensor above threshold. Reset: VDD thermal sensor below threshold and flag read (SPI) VDD UV Description Reports that VDD pin is lower than the VDDUV threshold. Set / Reset condition Set: VDD below threshold for t >100 μs typically. Reset: VDD above threshold and flag read (SPI) VDD overVOLTAGE Description Reports that VDD pin is higher than the typically VDD + 0.6 V threshold. I/O-1 can be turned OFF if this function is selected in INIT register. Set / Reset condition Set: VDD above threshold for t >100 μs typically. Reset: VDD below threshold and flag read (SPI) VAUX_overVOL TAGE Description Reports that VAUX pin is higher than the typically VAUX + 0.6 V threshold. I/O-1 can be turned OFF if this function is selected in INIT register. Set / Reset condition Set: VAUX above threshold for t >100 μs typically. Reset: VAUX below threshold and flag read (SPI) VDD LOW >100 ms Description Reports that VDD pin is lower than the VDDUV threshold for a time longer than 100 ms Set / Reset condition Set: VDD below threshold for t >100 ms typically. Reset: VDD above threshold and flag read (SPI) VDD LOW Description Report that VDD is below VDD undervoltage threshold. Set / Reset condition Set: VDD below threshold. Reset: fag read (SPI) VDD (5.0 V or 3.3 V) Description 0: mean 3.3 V VDD version 1: mean 5.0 V VDD version Set / Reset condition N/A Device P/N1 and 0
Description
Describe the device part number: 00: MC33903 01: MC33904 10: MC33905S 11: MC333905D Set / Reset condition N/A Device id 4 to Describe the silicon revision number 10010: silicon revision A (Pass 3.1) 10011: silicon revision B (Pass 3.2) 10100: silicon revision C and D Set / Reset condition N/A RST low >100 ms Description Report that the RST pin has detected a low level, longer than 100 ms (Reset permanent low) Set / Reset condition Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI) Multiple Resets Description Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong watchdog refresh. Set / Reset condition Set: after detection of multiple reset pulses. Reset: flag read (SPI) watchdog refresh failure Description Report that a wrong or missing watchdog failure occurred. Set / Reset condition Set: failure detected. reset: flag read (SPI)
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10.4.2 Fix and extended device status
Fix Status: when a device read operation is performed (MOSI bits 15-14, bits C1 C0 = 00 or 11). command (0x2780 or 0x2980) do not clear it, as it is ‘real time’ flag. (means LIN signal will not be detected and will not Wake-up the device). not clear the flag, as it is ‘real time’ information. Description Report that the LIN/1/2 interface has reach overtemperature threshold. Description Report that RXD/1/2 pin is shorted to GND. Description Report that RXD/1/2pin is shorted to recessive voltage. Description Report that TXD/1/2 pin is shorted to GND. Table 41. Status bits description
1 VREG-0
INT Indicates that an INT has occurred and that INT flags are pending to be read. WU Indicates that a Wake-up has occurred and that Wake-up flags are pending to be read. RST Indicates that a reset has occurred and that the flags that report the reset source are pending to be read. CAN-G The INT, WU, or RST source is CAN interface. CAN local or CAN bus source. I/O-G The INT, WU, or RST source is I/O interfaces. CAN-LOC The INT, WU, or RST source is CAN interface. CAN local source. CAN-BUS The INT, WU, or RST source is CAN interface. CAN bus source.
SERIAL PERIPHERAL INTERFACE LIN2 The INT, WU, or RST source is LIN2 interface LIN/LIN1 The INT, WU, or RST source is LIN1 interface I/O-0 The INT, WU, or RST source is I/O interface, flag from I/O sub adress Low (bit 7 = 0) I/O-1 The INT, WU, or RST source is I/O interface, flag from I/O sub adress High (bit 7 = 1) VREG-1 The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 = 1) VREG-0 The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 = 0) Bits Description
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11 Typical applications
Figure 42. 33905D typical application schematic
- Tested per specific OEM EMC requirements for CAN and LIN with additional
Figure 43. 33905S typical application schematic
- Tested per specific OEM EMC requirements for CAN and LIN with additional
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Figure 44. 33904 typical application schematic
- Tested per specific OEM EMC requirements for CAN and LIN with additional
Figure 45. 33903 typical application schematic
- Tested per specific OEM EMC requirements for CAN and LIN with additional
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Figure 46. 33903D typical application schematic
- Tested per specific OEM EMC requirements for CAN and LIN with additional
Figure 47. 33903S typical application schematic
- Tested per specific OEM EMC requirements for CAN and LIN with additional
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Figure 48. 33903P typical application schematic
- Tested per specific OEM EMC requirements for CAN and LIN with additional
MCU during the cranking pulse and temporary (50 ms) loss of the VBAT supply. Applications without an external ballast on VDD and without using the VAUX regulator are illustrated as well. Figure 49. Application options Optimized solution for cranking pulses. C1 is sized for MCU power supply buffer only. delivered by internal path transistor.
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12 Packaging
12.1 SOIC 32 package dimensions
For the most current package revision, visit www.NXP.com and perform a keyword search using the “98A” listed below.
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12.2 SOIC 54 package dimensions
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REVISION HISTORY
Revision Date Description of changes 4.0 9/2010
- Initial Release - This docum ent supersedes document MC33904_5.
- Initial release of document includes the MC33903 part number, the VDD 3.3 V version description, and the silicon revision rev. 3.2. Change details available upon request. 5.0 12/2010
- Added 7.9. Cyclic INT operation during LP VDD on mode 47
- Changed VSUP pin to VSUP1 and pin 2 (NC) to VSUP2 for the 33903 device
- Removed . Drop voltage without external PNP pass transistor 19 for VDD=3.3 V devices
- Added V SUP1-3.3 to . VDD Voltage regulator, VDD pin 19.
- Added . Pull-up Current, TXD, VIN = 0 V 23 for VDD=3.3 V devices
- Revised 10.3.1. MUX and RAM registers 68
- Revised 41. Status bits description 90 6.0 4/2011
- Removed part numbers MCZ33905S3EK/R2, MCZ33904A3EK/R2 and MCZ33905D3EK/R2, and added part numbers MCZ33903BD3EK/R2, MCZ33903BD5EK/R2, MCZ33903BS3EK/R2 and MCZ33903BS5EK/R2.
- Voltage Supply was improved from 27V to 28V.
- Changed Classification from Advance Information to Technical Data.
- Updated Notes in Tables 8.
- Revised Tables 8; Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: to reflect a Typical value.
- Corrected typographical errors throughout.
- Added Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) parameter to Tables 8.
- Updated I/O pins (I/O-0: I/O-3) on page 33. 7.0 9/2011
- Updated VOUT-5.0-EMC maximum
- Updated t LEAD parameter
- Added t CSLOW parameter
- Updated the Detail operation section to reflect the importance of acknowledging tLEAD and tCSLOW.
- Corrected typographical error in Tables 34 CAN REGISTER for Slew Rate bits b5,b4 8.0 1/2011
- Added 12 PCZ devices to the ordering information
- Bit label change on Table 39 from INT to SAFE
- Revised notes on Table 1 to include “C” version
- S p l i t Falling Edge of CS to Rising Edge of SCLK to differentiate the “C” version
- Added “C” version note to Table 39 and Table 40
- Added device ID 10100 Rev C, Pass 3.3 to Device id 4 to 0
- Added Debug mode DBG voltage range parameter. Already detailed in text.
- Added the MC33903P device, making additions throughout the document, where applicable. 9.0 2/2012 • Changed all PC devices to MC devices. 4/2013 • No technical changes. Revised back page. Updated docum ent properties. Added SMARTMOS sentence to first paragraph. 10.0 2/2014
- Added package type in Table 1.
- Added new parameter to Output Voltage on page 19 for VDD
- Added (22) 11.0 8/2014
- Changed t CS-TO in the Dynamic electrical characteristics from 2.5 to 2.0
- Note added to MUX-output (MUXOUT) on page 33 of Functional pin description
- Added a paragraph in the SPI Detail operation section for the maximum tLEAD time in case the ‘CSB low’ flag is set
- Added maximum t LEAD time in case the ‘CSB low’ flag is set to 1 in the Dynamic electrical characteristics table 12.0 8/2016
- Updated as per CIN 201608012I
- Added ‘D’ version orderable part numbers to Table 1, Table 2, and Table 3
- Updated note (2), (5), (9)
- Added note (3), (6), (10) (‘C’ versions are no longer recommended for new design) to Table 1, Table 2, and Table 3
- Added reference to ‘D’ version in the document where applicable
- Updated flag description for device id 4 to 0 in Table 40
- Updated to NXP document format and style 13.0 5/2017
- Updated Figure 29 to include 3.3 V information
- Updated workflow step 3 in Figure 30 (SPI commands: changed 0xDD00 to 0x1D80)
- Updated bit 1 description in Table 32 14.0 2/2018
- Updated note (7) (deleted “Output current limited to 100 mA”)
- Updated values for V RST-VTH in Table 6 as per CIN 201712019I
- Removed typ. and max. values for V RST-VTH (Low threshold, VDD = 5.0 V)
- Removed min. and typ. values for V RST-VTH (High threshold, VDD = 5.0 V)
- Removed typ. and max. values for V RST-VTH (Low threshold, VDD = 3.3 V)
- Removed min. and typ. values for V RST-VTH (High threshold, VDD = 3.3 V)
Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP B.V. 2018. Document Number: MC33903_4_5 Rev. 14.0