MCZ33903B5EK

MC33903 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 98

Technical content

Features

• Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with possib ility of usage external PNP to extend current capability and share power dissipation
• Voltage, current, and temperature protection
• Extremely low quiescent current in low power modes
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Multiple under-voltage detections to address various MCU specifica tions and system operation modes (i.e. cranking)
• Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with over-curren t detection and under-voltage protection
• MUX output pin for device internal analog signal monitoring and pow er supply monitoring
• Advanced SPI, MCU, ECU power supply, and critical pins dia gnostics and monitoring.
• Multiple wake-up sources in low power modes: CAN or LIN bus, I/O tra nsition, automatic timer, SPI message, and VDD over-current detection.
• ISO11898-5 high speed CAN interface co mpatibility for baud rates of 40 kb/s to 1.0 Mb/s
• Pb-free packaging designated by suffix code EK

2 Freescale Semiconductor

Table 1. Device Variations - (All devices rated at TA = -40 TO 125 °C)

1. V DD does not allow usage of an external PNP on the 33903. Output current limited to 100 mA.

Analog Integrated Circuit Device Data Freescale Semiconductor 3 33903/4/5 TABLE OF CONTENTS TABLE OF CONTENTS

4 Freescale Semiconductor

Figure 1. 33905D Simplified Application Diagram Figure 2. 33905S Simplified Application Diagram

6 Freescale Semiconductor

5 V Auxiliary

Figure 5. 33905D Internal Block Diagram

Figure 6. 33905S Internal Block Diagram

8 Freescale Semiconductor

Figure 7. 33904 Internal Block Diagram Figure 8. 33903 Internal Block Diagram

Figure 9. 33903/4/5 Pin Connections

10 Freescale Semiconductor

Table 2. 33903/4/5 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 30.

33903 Pin Name Pin Function Formal Name Definition

regulator, I/O and LIN pins. drain-source over-voltage detection, is available. drain-source over-voltage detection, is available. drain-source over-voltage detection is available. on the RESET pin, etc.). Open drain structure. 9 6 6 6 5 V-CAN Output 5V-CAN Output voltage for the embedded CAN interface. A capacitor must be connected to this pin. 10 7 7 7 CANH Output CAN High CAN high output. 11 8 8 8 CANL Output CAN Low CAN low output.

16 13 13 N/A VAUX Output VOUT Auxiliary Output pin for the auxiliary voltage. DD current sense measurements.

23 N/A N/A N/A TXD-L2 Input LIN Transmit

24,31 N/A N/A N/A GND Ground Ground Ground of the IC.

25 N/A N/A N/A RXD-L2 Output LIN Receive

LIN bus receive data output. 26 N/A N/A N/A LIN2 Input/Output LIN bus LIN bus input output connected to the LIN bus. Input/Output LIN bus LIN bus input output connected to the LIN bus. LIN bus receive data output. cyclic sense function in Low Power mode. Table 2. 33903/4/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 30.

12 Freescale Semiconductor

structure with an internal pull up resistor to VDD. 50 31 31 N/A VE Voltage Emitter Connection to the external PNP path transistor. A functional description of each pin can be found in the Functional Pin Description section beginning on page 30.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33903/4/5

ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings permanent damage to the device.

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

Figure 10. PCB with Top and Bottom Layer Dissipation Area (Dual Layer)

1. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), the Cha rge Device Model

(CDM), and Robotic (CZAP = 4.0 pF).

1. The voltage on non-VSUP pins should never exceed the V SUP voltage at any time or permanent damage to the device may occur. Pin

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets P b-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. ( i.e. MC33xxxD enter 33xxx), and review parametrics.

1. This parameter was measured according to Figure 10:

Table 3. Maximum Ratings (continued) permanent damage to the device.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33903/4/5 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

1. All parameters in spec (ex: V DD regulator tolerance).
2. Device functional, some parameters could be out of spec. V DD is active, device is not in Reset mode if the lowest VDD under-voltage

reset threshold is selected (approx. 3.4 V). CAN and I/Os are not operational.

1. In Run mode, CAN interface in Sleep mode, 5 V-CAN and VAUX turned off. IOUT at VDD < 50 mA. Ballast: turned off or not connected.

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS VDD VOLTAGE REGULATOR, VDD PIN Output Voltage VDD = 5.0 V, VSUP 5.5 to 27 V, IOUT 0 to 150 mA VDD = 3.3 V, VSUP 5.5 to 27 V, IOUT 0 to 150 mA VOUT-5.0 VOUT-3.3 4.9 3.234 5.0 3.3 5.1 3.366 V Drop voltage without external PNP pass transistor(9) VDD = 5.0 V, IOUT = 100 mA VDD = 5.0 V, IOUT = 150 mA VDROP 330 450 500 mV Drop voltage with external transistor(9) IOUT = 200 mA (I_BALLAST + I_INTERNAL) VDROP-B - 350 500 mV VSUP1 to maintain VDD within VOUT-3.3 specified voltage range VDD = 3.3 V, IOUT = 150 mA VDD = 3.3 V, IOUT = 200 mA, external transistor implemented VSUP1-3.3 4.0 4.0 V External ballast versus internal current ratio (I_BALLAST = K x Internal current) K 1.5 2.0 2.5 Output Current limitation, without external transistor MC33904, 33905 MC33903 ILIM 150 100 350 550 mA Temperature prewarning (guaranteed by design) TPW - 140 - °C Thermal shutdown (guaranteed by design) TSD 160 - - °C Range of decoupling capacitor (guaranteed by design)(10) CEXT 4.7 - 100 μF Low Power mode VDD ON, output voltage -5.0 V, IOUT ≤ 50 mA (time limited) VDD = 5.0 V, 5.6 V ≤ VSUP ≤ 27 V VDD = 3.3 V, 5.6 V ≤ VSUP ≤ 27 V VDDLP 4.75 3.135 5.0 3.3 5.25 3.465 V Low Power mode VDD ON, dynamic output current capability (Limited duration. Ref to device description). LP-IOUTDC - - 50 mA Low Power VDD ON mode: Over-current wake-up threshold. Hysteresis LP-ITH 1.0 0.1 3.0 1.0 mA Low Power mode VDD ON, drop voltage, at IOUT = 30 mA (Limited duration. Ref to device description). LP-VDROP - 200 400 mV Low Power mode VDD ON, min VSUP operation (Below this value, a VDD, under-voltage reset may occur) LP-MINVS 5.5 - - V VDD when VSUP < VSUP-TH1, at I_VDD ≤ 10 μA (guaranteed by design) VDD_OFF - - 0.3 V VDD when VSUP ≥ VSUP-TH1, at I_VDD ≤ 40 mA (guaranteed with parameter VSUP-TH1 VDD_START UP 3.0 - - V Notes 9. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout voltage parameter cannot be specified. 10. The regulator is stable without external capacitor. Usage of external capacitor recommended for AC performance. Table 4. Static Electrical Characteristics (continued) noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33903/4/5 STATIC ELECTRICAL CHARACTERISTICS VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY, 5.0 V-CAN PIN Output voltage, VSUP2 = 5.5 to 40 V IOUT 0 to 160 mA 5V-C OUT 4.75 5.0 5.25 V Output Current limitation (11) 5V-C ILIM 160 280 - mA Under-voltage threshold 5V-C UV 4.1 4.5 4.7 V Thermal shutdown (guaranteed by design) 5V-CTS 160 - - °C External capacitance (guaranteed by design) CEXT-CAN 1.0 - 100 μF V AUXILIARY OUTPUT, 5.0 AND 3.3 V SELECTABLE PIN VB-AUX, VC-AUX, VAUX VAUX output voltage VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX 4.75 3.135 5.0 3.3 5.25 3.465 V VAUX under-voltage detector (VAUX configured to 5.0 V) Low Threshold Hysteresis VAUX under-voltage detector (VAUX configured to 3.3 V, default value) VAUX-UVTH 4.2 0.06 2.75 4.5 3.0 4.70 0.12 3.135 V VAUX over-current threshold detector VAUX set to 3.3 V VAUX set to 5.0 V VAUX-ILIM 250 230 360 330 450 430 mA External capacitance (guaranteed by design) VAUX CAP 2.2 - 100 μF UNDER-VOLTAGE RESET AND RESET FUNCTION, RST PIN VDD under-voltage threshold down - 90% VDD (VDD 5.0 V)(12), (14) VDD under-voltage threshold up - 90% VDD (VDD 5.0 V) VDD under-voltage threshold down - 90% VDD (VDD 3.3 V)(12), (14) VDD under-voltage threshold up - 90% VDD (VDD 3.3 V) VRST-TH1 4.5 2.75 4.65 3.0 4.85 4.90 3.135 3.135 V VDD under-voltage reset threshold down - 70% VDD (VDD 5.0 V)(13), (14) VRST-TH2-5 2.95 3.2 3.45 V Hysteresis for threshold 90% VDD, 5.0 V device for threshold 70% VDD, 5.0 V device Hysteresis 3.3 V VDD for threshold 90% VDD, 5.0 V device VRST-HYST 150 150 150 mV VDD under-voltage reset threshold down - Low Power VDD ON mode (note: device change to Normal Request mode). VDD 5.0 V (note: device change to Normal Request mode). VDD 3.3 V VRST-LP 4.0 2.75 4.5 3.0 4.85 3.135 V Notes 11. Current limitation will report into a flag. 12. Generate a reset or an INT. SPI programmable 13. Generate a reset 14. In Run mode noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS UNDER-VOLTAGE RESET AND RESET FUNCTION, RST PIN (CONTINUED) Reset VOL @ 1.5 mA, VSUP 4.1 to 40 V VOL - 300 500 mV Current limitation, Reset activated, VRESET = 0.9 x VDD IRESET LOW 2.5 7.0 10 mA Pull-up resistor (to VDD pin) RPULL-UP 8.0 11 15 kΩ VSUP to guaranteed reset low level(15) VSUP-RSTL 2.5 - - V Reset input threshold Low threshold, VDD = 5.0 V High threshold, VDD = 5.0 V Low threshold, VDD = 3.3 V High threshold, VDD = 3.3 V VRST-VTH 1.5 2.5 0.99 1.65 1.9 3.0 1.17 2.0 2.2 3.5 1.32 2.31 V Reset input hysteresis VHYST 0.5 1.0 1.5 V I/O PINS WHEN FUNCTION SELECTED IS OUTPUT I/O-0 high side switch drop @ I = -12 mA, VSUP = 10.5 V VI/O-0 HSDRP - 0.5 1.4 V I/O-2 and I/O-3 high side switch drop @ I = -20 mA, VSUP = 10.5 V VI/O-2-3 HSDRP - 0.5 1.4 V I/O-1, high side switch drop @ I = -400 μA, VSUP = 10.5 V VI/O-1 HSDRP - 0.4 1.4 V I/O-0, I/O-1 low side switch drop @ I = 400 μA, VSUP = 10.5 V VI/O-01 LSDRP - 0.4 1.4 V Leakage current II/O_LEAK - 0.1 3.0 μA I/O PINS WHEN FUNCTION SELECTED IS INPUT Negative threshold VI/O_NTH 1.4 2.0 2.9 V Positive threshold VI/O_PTH 2.1 3.0 3.8 V Hysteresis VI/O_HYST 0.2 1.0 1.4 V Input current II/O_IN -5.0 1.0 5.0 μA I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in MUX register, 2.0 V < VI/O-X <16 V (guaranteed by design). RI/O-X - 100 - kΩ VSENSE INPUT VSENSE under-voltage threshold (Not active in Low Power modes) Low Threshold High threshold Hysteresis VSENSE_TH 8.1 0.1 8.6 0.25 9.0 9.1 0.5 V Input resistor to GND. In all modes except in Low Power modes. (guaranteed by design). RVSENSE - 125 - kΩ Notes 15. Reset must be maintained low noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33903/4/5 STATIC ELECTRICAL CHARACTERISTICS ANALOG MUX OUTPUT Output Voltage Range, with external resistor to GND >2.0 kΩ VOUT_MAX 0.0 - VDD - 0.5 V Internal pull-down resistor for regulator output current sense RMI 0.8 1.9 2.8 kΩ External capacitor at MUX OUTPUT(16) (guaranteed by design) CMUX - - 1.0 nF Chip temperature sensor coeff (guaranteed by design and device characterization) TEMP-COEFF 20 21 22 mv/°C Chip temperature: MUX-OUT voltage TA = 25 °C, guaranteed by design and characterization VDD = 5.0 V, TA = 125 °C VDD = 3.3 V, TA = 125 °C VTEMP 1.5 3.6 2.45 1.65 3.75 2.58 1.8 3.9 2.65 V Gain for VSENSE, with external 1.0 k 1% resistor VDD = 5.0 V VDD = 3.3 V VSENSE GAIN 5.13 8.1 5.48 8.2 5.67 8.3 Offset for VSENSE, with external 1.0 k 1% resistor VSENSE OFFSET -20 - 20 mV Divider ratio for VSUP1 VDD = 5.0 V VDD = 3.3 V VSUP1 RATIO 5.335 7.95 5.5 8.18 5.665 8.45 Divider ratio for I/O-0 and I/O-1 actual voltage - with attenuation selected (MUX-OUT register bit 3 set to 1); VDD =5.0 V, VSUP = 16 V VDD =5.0 V, - with gain selected (MUX-OUT register bit 3 set to 0) VDD =3.3 V, VSUP = 16 V VDD =3.3 V, - with gain selected (MUX-OUT register bit 3 set to 0) VI/O RATIO 3.8 5.6 4.0 2.0 5.8 2.0 4.2 6.2 Internal reference voltage VDD =5.0 V VDD =3.3 V VREF 2.45 1.64 2.5 1.67 2.55 1.7 V Current ratio between VDD output & IOUT at MUX-OUT (IOUT at MUX-OUT = IDD out / IDD_RATIO) At IOUT = 50 mA I_OUT from 25 to 150 mA IDD_RATIO 62.5 115 117 SAFE OUTPUT SAFE low level, at I = 500 μA VOL 0.0 0.2 1.0 V Safe leakage current (VDD low, or device unpowered). VSAFE 0 to 27 V. ISAFE-IN - 0.0 1.0 μA Notes 16. When C is higher than CMUX, a serial resistor must be inserted noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS INTERRUPT Output low voltage, IOUT = 1.5 mA VOL - 0.2 1.0 V Pull-up resistor RPU 6.5 10 14 kΩ Output high level in Low Power VDD ON mode (guaranteed by design) VOH-LPVDDON 3.9 4.3 V Leakage current INT voltage = 10 V (to allow high-voltage on MCU INT pin) VMAX - 35 100 μA Sink current, VINT > 5.0 V, INT low state I SINK 2.5 6.0 10 mA MISO, MOSI, SCLK, CS PINS Output low voltage, IOUT = 1.5 mA (MISO) VOL - - 1.0 V Output high voltage, IOUT = -0.25 mA (MISO) VOH VDD -0.9 - V Input low voltage (MOSI, SCLK,CS) VIL - - 0.3 x VDD V Input high voltage (MOSI, SCLK,CS) VIH 0.7 x VDD - - V Tri-state leakage current (MISO) IHZ -2.0 - 2.0 μA Pull-up current (CS) IPU 200 370 500 μA CAN LOGIC INPUT PINS (TXD) High Level Input Voltage VIH 0.7 x VDD - VDD + 0.3 V Low Level Input Voltage VIL -0.3 - 0.3 x VDD V Pull-up Current, TxD, VIN = 0 V VDD =5.0 V VDD =3.3 V IPDWN -850 -500 -650 -250 -200 -175 µA CAN DATA OUTPUT PINS (RXD) Low Level Output Voltage IRXD = 5.0 mA VOUTLOW 0.0 - 0.3 x VDD V High Level Output Voltage IRX = -3.0 mA VOUTHIGH 0.7 x VDD - VDD V High Level Output Current VRXD = VDD - 0.4 V IOUTHIGH 2.5 5.0 9.0 mA Low Level Input Current VRXD = 0.4 V IOUTLOW 2.5 5.0 9.0 mA noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33903/4/5 STATIC ELECTRICAL CHARACTERISTICS CAN OUTPUT PINS (CANH, CANL) Bus pins common mode voltage for full functionality VCOM -12 - 12 V Differential input voltage threshold VCANH-VCANL 500 - 900 mV Differential input hysteresis VDIFF-HYST 50 - - mV Input resistance RIN 5.0 - 50 kΩ Differential input resistance RIN-DIFF 10 - 100 kΩ Input resistance matching RIN-MATCH -3.0 0.0 3.0 % CANH output voltage (45 Ω < RBUS < 65 Ω) TxD dominant state TxD recessive state VCANH 2.75 2.0 3.5 2.5 4.5 3.0 V CANL output voltage (45 Ω < RBUS < 65 Ω) TxD dominant state TxD recessive state VCANL 0.5 2.0 1.5 2.5 2.25 3.0 V Differential output voltage (45 Ω < RBUS < 65 Ω) TxD dominant state TxD recessive state VOH-VOL 1.5 -0.5 2.0 0.0 3.0 0.05 V CAN H output current capability - Dominant state ICANH - - -30 mA CAN L output current capability - Dominant state ICANL 30 - - mA CANL over-current detection - Error reported in register ICANL-OC 75 120 195 mA CANH over-current detection - Error reported in register ICANH-OC -195 -120 -75 mA CANH, CANL input resistance to gnd, device supplied, CAN in Sleep mode, V_CANH, V_CANL from 0 to 5.0 V RINSLEEP 5.0 - 50 kΩ CANL, CANH output voltage in Low Power VDD OFF and Low Power VDD ON modes VCANLP -0.1 0.0 0.1 V CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device unpowered (VSUP, VDD, 5V-CAN: open).(17) ICAN-UN_SUP1 - 3.0 10 µA CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device unpowered (VSUP, VDD, 5V-CAN: open).(17) ICAN-UN_SUP2 - - 250 µA Differential voltage for recessive bit detection in LP mode(18) VDIFF-R-LP - - 0.4 V Differential voltage for dominant bit detection in LP mode(18) VDIFF-D-LP 1.15 - - V CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND detection threshold VLG 1.6 1.75 2.0 V CANH to GND detection threshold VHG 1.6 1.75 2.0 V CANL to VBAT detection threshold, VSUP1 and VSUP2 > 8.0 V VLVB - VSUP -2.0 - V CANH to VBAT detection threshold, VSUP1 and VSUP2 > 8.0 V VHVB - VSUP -2.0 - V CANL to VDD detection threshold VL5 4.0 VDD -0.43 - V CANH to VDD detection threshold VH5 4.0 VDD -0.43 - V Notes 17. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization. 18. Guaranteed by design and device characterization. noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS SPLIT Output voltage Loaded condition ISPLIT = ±500 µA Unloaded condition Rmeasure > 1.0 MΩ VSPLIT 0.3 x VDD 0.45 x VDD 0.5 x VDD 0.5 x VDD 0.7 x VDD 0.55 x VDD V Leakage current -12 V < VSPLIT < +12 V -22 to -12 V < VSPLIT < +12 to +35 V ILSPLIT 0.0 5.0 200 µA LIN TERM1, LIN TERM2 LIN-T1, LIN-T2, high side switch drop @ I = -20 mA, VSUP > 10.5 V VLT_HSDRP - 1.0 1.4 V LIN1 AND LIN 2 MC33905D PIN - LIN1 MC33905S PIN (Parameters guaranteed for VSUP1, VSUP2 7.0 V ≤ VSUP ≤ 18 V) Operating Voltage Range VBAT 8.0 - 18 V Supply Voltage Range VSUP 7.0 - 18 V Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V IBUS_LIM 40 90 200 mA Input Leakage Current at the receiver Driver off; VBUS = 0 V; VBAT = 12 V IBUS_PAS_DOM -1.0 - - mA Leakage Output Current to GND Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT IBUS_PAS_REC - - 20 µA Control unit disconnected from ground (Loss of local ground must not affect communication in the residual network) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V (guaranteed by design) IBUS_NO_GND -1.0 - 1.0 mA VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition) IBUSNO_BAT - - 100 µA Receiver Dominant State VBUSDOM - - 0.4 VSUP Receiver Recessive State VBUSREC 0.6 - - VSUP Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VBUS_CNT 0.475 0.5 0.525 VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VHYS - - 0.175 VSUP LIN Wake-up threshold from Low Power VDD ON or Low Power VDD OFF mode VBUSWU - 5.3 5.8 V LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 kΩ Over-temperature Shutdown (guaranteed by design) TLINSD 140 160 180 °C Over-temperature Shutdown Hysteresis (guaranteed by design) TLINSD_HYS - 10 - °C noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33903/4/5 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS STATE DIGRAM TIMINGS Delay for SPI Timer A, Timer B or Timer C write command after entering Normal mode (No command should occur within tD_NM. tD_NM delay definition: from CS rising edge of "Go to Normal mode (i.e 0x5A00)" command to CS falling edge of “Timer write” command) tD_NM 60 - - μs Tolerance for: W/D period in all modes, FWU delay, Cyclic sense period and active time, Cyclic Interrupt period, LP mode over-current (unless otherwise noted)(22) tTIMING-ACC -10 - 10 % CAN DYNAMIC CHARACTERISTICS TXD Dominant State Timeout tDOUT 300 600 1000 µs Bus dominant clamping detection tDOM 300 600 1000 µs Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate) tLRD 60 120 210 ns Propagation delay TXD to CAN, recessive to dominant tTRD - 70 110 ns Propagation delay CAN to RXD, recessive to dominant tRRD - 45 140 ns Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate) tLDR 100 120 200 ns Propagation delay TXD to CAN, dominant to recessive tTDR - 75 150 ns Propagation delay CAN to RXD, dominant to recessive tRDR - 50 140 ns Loop time TXD to RXD, Medium Slew rate (Selected by SPI) Rec to Dom Dom to Rec tLOOP-MSL 200 200 ns Loop time TXD to RXD, Slow Slew rate (Selected by SPI) Rec to Dom Dom to Rec tLOOP-SSL 300 300 ns CAN wake-up filter time, single dominant pulse detection(19) (See Figure 32) tCAN-WU1-F 0.5 2.0 5.0 μs CAN wake-up filter time, 3 dominant pulses detection(20) tCAN-WU3-F 300 - - ns CAN wake-up filter time, 3 dominant pulses detection timeout(21) (See Figure 33) tCAN-WU3-TO - - 120 μs Notes 19. No wake-up for single pulse shorter than t CAN-WU1 min. Wake-up for single pulse longer than tCAN-WU1 max. 20. Each pulse should be greater than t CAN-WU3-F min. Guaranteed by design, and device characterization. 21. The 3 pulses should occur within t CAN-WU3-TO. Guaranteed by design, and device characterization. 22. Guaranteed by design. values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 33903/4/5 DYNAMIC ELECTRICAL CHARACTERISTICS LIN 1 AND LIN 2 PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION Duty Cycle 1: THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V 0.396 - - Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.581 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V 0.417 - - Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.590 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming mode) SRFAST - 20 - V / μs LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS Propagation Delay and Symmetry (See Figure 15, page 27 and Figure 16, page 28) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR t REC_PD t REC_SYM - 2.0 4.2 6.0 2.0 μs Bus Wake-up Deglitcher (Low Power VDD OFF and Low Power VDD ON modes) (See Figure 17, page 27 for Low Power VDD OFF mode and Figure 18, page 28 for Low Power mode) t PROPWL 42 70 95 μs Bus Wake-up Event Reported From Low Power VDD OFF mode From Low Power VDD ON mode t WAKE_LPVDD OFF t WAKE_LPVDD ON 1.0 1500 μs TXD Permanent Dominant State Delay (guaranteed by design) t TXDDOM 0.65 1.0 1.35 s values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

Undefined Don’t Ca Di n Don’t Ca tLEAD tSIHtSISU tLAG tPCLK tWCLKH tWCLKL tVALID Do n tSODIS CS SCLK MOSI MISO tSOEN Figure 11. SPI Timings Figure 12. CAN Signal Propagation Loop Delay TXD to RXD Figure 13. CAN Signal Propagation Delays TXD to CAN and CAN to RXD

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33903/4/5 22 ¬µ 10 ¬µ SPLITGND TXD RXD Signal generator All pins are not shown RBUS 15 pF CBus 100 pF60 Ω 100 nF

5 V_CAN

Figure 14. Test Circuit for CAN Timing Characteristics Figure 15. LIN Timing Measurements for Normal Slew Rate

tBUS_DOM(MAX) tBUS_REC(MIN) tREC_PDF(1) 77.8% VSUP 38.9% VSUP 61.6% VSUP 25.1% VSUP tBUS_REC(MAX) VLIN_REC tBUS_DOM(MIN) RXD Output of receiving Node 1 Output of receiving Node 2 THREC(MAX) THDOM(MAX) THREC(MIN) THDOM(MIN) Thresholds of receiving node 1 Thresholds of receiving node 2 tREC_PDR(1) tREC_PDF(2)tREC_PDR(2) Analog Integrated Circuit Device Data

28 Freescale Semiconductor

Figure 16. LIN Timing Measurements for Slow Slew Rate Figure 17. LIN Wake-up Low Power VDD OFF Mode Timing

VLIN_REC TT Dominant level 0.4 V V IRQ stays low until SPI reading command PROPWL WAKE BUSWU SUP Analog Integrated Circuit Device Data Freescale Semiconductor 29 33903/4/5 Figure 18. LIN Wake-up Low Power VDD ON Mode Timing

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

The MC33903_4_5 is the second generation of System Basis Chip, combining: - Advanced power management unit for the MCU, the integrated CAN interface and for additional ICs such as sensors, CAN transceiver. - Built in enhanced high speed CAN interface (ISO11898- 2 and -5), with local and bus failure diagnostic, protection and fail safe operation mode. - Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection. - Innovative and hardware configurable fail safe state machine solution. - Multiple low power modes, with low current consumption. - Family concept; with and without LIN interface devices with pin compatibility. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY (VSUP1 AND VSUP2) VSUP1 is the input pin for the device internal supply and the VDD regulator. VSUP2 is the input pin for the 5 V-CAN regulator, LINs interfaces and I/O functions. The VSUP block includes over and under-voltage detections which can generate interrupt. The device includes a loss of battery detector connected to VSUP1. Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset). VDD VOLTAGE REGULATOR (VDD) The regulator has two main modes of operation (Normal mode and Low Power mode). It can operate with or without an external PNP transistor. In Normal mode, without external PNP, the max DC capability is 150 mA. Current limitation, temperature prewarning flag and over-temperature shutdown features are included. When VDD is turned ON, rise time from 0 to 5.0 V is controlled. Output voltage is 5.0 V. A 3.3 V option is available via dedicated part number. If current higher than 150 mA is required, an external PNP transistor must be connected to VEM (PNP emitter) and VB (PNP base) pins, in order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See External Transistor Q1 (VE and VB). The PNP can be used even if current is less than 150 mA, depending upon ambient temperature, maximum supply and thermal resistance. Typically, above 100-200 mA, an external ballast transistor is recommended. VDD REGULATOR IN LOW POWER MODE When the device is set in Low Power VDD ON mode, the VDD regulator is able to supply the MCU with a DC current below typ 1.5 mA (LP-ITH). Transient current can also be supplied up to a tenth of a mA. Current in excess of 1.5 mA is detected, and this event is managed by the device logic (wake-up detection, timer start for over-current duration monitoring or watchdog refresh). EXTERNAL TRANSISTOR Q1 (VE AND VB) The device has a dedicated circuit to allow usage of an external P type transistor, with the objective to share the power dissipation between the internal transistor of the VDD regulator and the external transistor. The bipolar PNP recommended transistor are MJD42C or BCP52-16. When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI. The device is able to operate without an external transistor. In this case, the VEM and VB pins must remain open.

5 V-CAN VOLTAGE REGULATOR FOR CAN AND

This regulator is supplied from the VSUP2 pin. A capacitor is required at 5 V-CAN pin. Analog MUX and part of the LIN interfaces are supplied from 5 V-CAN. Consequently, the

5 V-CAN must be ON in order to have Analog MUX operating

and to have the LIN interface operating in TxD/RxD mode.

5 V-CAN regulator is OFF by default and must be turn ON

by SPI. In Debug mode 5 V-CAN is ON be default. V AUXILIARY OUTPUT, 5.0 AND 3.3 V SELECTABLE (VB-AUX, VC-AUX, AND VCAUX) - The VAUX block is used to provide an auxiliary voltage output, 5.0 or 3.3 V, selectable by the SPI. It uses an external PNP pass transistor for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16. An over-current and under-voltage detectors are provided. VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and over-current information will disable VAUX, and are reported in the SPI and can generate INT. VAUX is OFF by default and must be turned ON by the SPI.

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33903/4/5 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION UNDER-VOLTAGE RESET AND RESET FUNCTION (RST) The RESET pin is an open drain structure with an internal pull-up resistor. The low side driver has limited current capability when asserted low, in order to tolerate a short to 5.0 V.The RESET pin voltage is monitored in order to detect failure (e.g. RESET pin shorted to 5.0 V or GND). The RESET pin reports to the MCU under-voltage condition at the VDD pin, as well as failure in watchdog refresh operation. VDD under-voltage reset operate also in Low Power VDD ON mode. Two VDD under-voltage threshold are included. The upper on (typ 4.65 V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected by the SPI. When “RST-TH2-5“is selected, in Normal mode, an INT is asserted when VDD falls below “RST-TH1-5“, then when VDD falls below “RST-TH2-5” a Reset will occur. This will allow the MCU to operate in a degraded mode, for example, with 4.0 V VDD. I/O PINS (I/O-0: I/O-3) I/O s are configurable input output pins. They can be used for small load or to drive external transistors. When used as output drivers, the I/Os are high side or low side type. They can also be set to high-impedance. I/Os are controlled by the SPI and at power on, the I/Os are set as inputs. They include over load protection by temperature or excess of drop voltage. In Low Power mode, state of the I/O can be turned on or off, with extremely low extra consumption (except load). Protection is disabled in low power mode. When cyclic sense is used, I/O-0 is the high side/low side switch, I/O-1, -2 and -3 and the wake inputs. I/O-2 and I/O-3 pins share also the LIN Master pin function. VSENSE INPUT (VSENSE) This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to gnd. It incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX-OUT pin. MUX-OUTPUT (MUXOUT) The MUX-OUT pin (Figure 19) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUX- OUT is selected via the SPI, from one of the following functions: V SUP1, VSENSE, I/O-0, I/O-1, Internal 2.5 V reference, die temperature sensor, VDD current copy. Voltage divider or amplifier are inserted in the chain, as shown in Figure 19. For the VDD current copy, a resistor must be added to the MUX-OUT pin, to convert current into voltage. Device includes an internal 2.0 k resistor selectable by the SPI. Voltage range at MUX-OUT is from GND to VDD. It is automatically limited to VDD (max 3.3 V for 3.3 V part numbers). The MUX-OUT buffer is supplied from 5 V-CAN regulator, so the 5 V-CAN regulator must be ON in order to have: 1) MUX-OUT functionality and 2) SPI selection of the analog function. If 5 V-CAN is OFF, MUX-OUT voltage is near gnd and the SPI command that selects one of the analog input is ignored. Delay must be respected between SPI commands for 5 V- CAN turn ON and SPI to select MUX-OUT function. The delay depends mainly upon the 5 V-CAN capacitor and load on 5 V-CAN. The delay can be estimated using the following formula: delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN. C = cap at 5 V-CAN regulator, U = 5.0 V, I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator (parameter 5 V-C ILIM).

32 Freescale Semiconductor

Figure 19. Analog Multiplexer Block Diagram within the 8.0 to 10 V range, and activate the debug mode. hardware and software routines (i.e SPI commands).

10 V range, the debug mode is left, an d device start W/D

higher priority than providing 8.0 to 10 V at the DEBUG pin. operation via a resistor at the DBG pin or via a SPI command. selection via Debug resistor. t be configured via the resistor connected at DBG pin. SBC, once a failure has been detected. as well as pulse duration are selected by SPI.

Analog Integrated Circuit Device Data Freescale Semiconductor 33 33903/4/5 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION INT has an internal pull-up structure to VDD. In Low Power VDD ON mode, a diode is inserted in series with the pull-up, so the high level is slightly lower than in other modes. CANH, CANL, SPLIT, RXD, TXD These are the pins of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is provided in the document. LIN, TXDL, RXDL AND LINTERM These are the pins of the LIN physical interface. Device contains zero, one or two LIN interfaces. The MC33903 and MC33904 do not have a LIN interface. However, the MC33905S (S = Single) and MC33905D (D = Dual) contain 1 and 2 LIN interfaces, respectively. LIN1 and LIN2 pins are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TxDL1 (TxDL2) and RxDL1 (RxDL2) pins. The device also include one or two high side switches to VSUP2 pin which can be used as a LIN master termination switch. Pins LINT-1 and LINT-2 are the same as I/O-2 and I/O-3. A detail description is provided in the document

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION The device has several operation modes. The transitions and conditions to enter or leave each modes are illustrated in the state diagram. INIT RESET This mode is automatically entered after device “power on”. In this mode, the RST pin is asserted low, for a duration of typ 1.0 ms. Control bits and flags are “set” to their default reset condition. The BATFAIL is set to indicated that the device is coming from an unpowered condition, and that all previous device configuration are lost and “reset” the default value. The duration of the INIT reset is typ 1.0 ms. INIT reset mode is also entered from INIT mode in case the expected SPI command does not occur in due time (ref. INIT mode), and if device is not in debug mode. INIT This mode is automatically entered from “INIT reset” mode. In this mode, the device must be configured via SPI within a time of 256 ms max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be and can only be configured during INIT mode. Other registers can be written in this mode, however they can be also written in other modes. Once the INIT registers configuration is done, a SPI Watchdog Refresh command must be send in order to set the device into Normal mode. If the SPI W/D refresh does not occur within the 256 ms period, the device will return into INIT reset mode for typ 1.0 ms, and then re enter into INIT mode. Register read operation is allowed in INIT mode to collect device status or to read back the INIT register configuration When INIT mode is left by a SPI W/D refresh command, it is only possible to re enter the INIT mode using a secured SPI command. In INIT mode, the CAN, LIN1, LIN2, VAUX, I/O_x and Analog MUX functions are not operating. The 5V-CAN is also not operating, except if the Debug mode is detected. RESET In this mode, the RST pin is asserted low. Reset mode is entered from Normal mode, Normal Request mode, LP VDD on mode and from Flash mode, when the W/D is not triggered, or if a V DD low condition is detected. The duration of reset is typ 1.0 ms by default. The user can defined a longer Reset pulse activation only for the case the reset mode is entered following a VDD low condition. Reset pulse is always 1.0 ms, in case reset mode is entered due to wrong a watchdog refresh command. Reset mode can be entered via secured SPI command. NORMAL REQUEST This mode is automatically entered after RESET mode, or after a wake-up from Low Power VDD ON mode. A watchdog refresh SPI command is necessary to transition to NORMAL mode. The duration of the Normal request mode is 256 ms when Normal Request mode is entered after RESET mode. Different duration can be selected by SPI for the case when normal request is entered from LP VDD ON mode. If the watchdog refresh SPI command does not occur within the 256 ms (or the shorter user defined time out), then the device will enter into RESET mode, for a duration of typ 1.0 ms. Note: in init reset, init, reset and normal request modes as well as in low power modes, the VDD external PNP is disabled. NORMAL In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request mode, or from INIT mode. During Normal mode, the device watchdog function is operating, and a periodic watchdog refresh must occurs. In case of incorrect or missing watchdog refresh command device will enter into Reset mode. From Normal mode, the device can be set by SPI command into Low Power modes (Low Power VDD ON or Low Power VDD OFF modes). Dedicated secured SPI commands must be used to enter from Normal mode in Reset mode, INIT mode or Flash mode. FLASH In this mode, the software watchdog period is extended up to typ 32 seconds. This allow programming of the MCU flash memory while minimizing the software over head to refresh the watchdog. The flash mode is entered by Secured SPI command and is left by SPI command. Device will enter into Reset mode. In case of incorrect or missing watchdog refresh command device will enter into Reset mode. An interrupt can be generated at 50% of the watchdog period. CAN interface operates in Flash mode to allow flash via CAN bus, inside the vehicle. DEBUG Debug is a special operation mode of the device which allows system easy software and hardware debugging. The debug operation is detected after power up if the DBG pin is set in the 8.0 to 10 V range. When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT mode, watchdog refresh of Normal mode and Flash mode, Normal Request time out (256 ms or user defined value) are not operating and will not lead to transition into INIT reset or Reset mode. When device is in Debug, SPI command can be send without any time constraints with respect to watchdog

Analog Integrated Circuit Device Data Freescale Semiconductor 35 33903/4/5 FUNCTIONAL DEVICE OPERATION LOW POWER MODES operation, MCU program can be “halted” or “paused” to verify proper operation. Debug can be left by removing 8 to 10 V from the DEBUG pin, or by SPI command (ref to MODE register). 5 V-CAN regulator is ON by default in debug mode. LOW POWER MODES The device has two main Low Power modes: Low Power mode with VDD OFF, and Low Power mode with VDD on. Prior to entering into Low Power mode, I/O and CAN wake up flags must be cleared (ref to mode register). If the wake- up flags are not cleared, the device will not enter into Low Power mode. In addition, the CAN failure flags (i.e CAN_F and CAN_UF) must be cleared, in order to meet the Low Power current consumption specification. LOW POWER - VDD OFF In this mode, VDD is turned off and the MCU connected to VDD is unsupplied. This mode is entered by the SPI. It can also be entered by automatic transition due to fail safe management. 5 V-CAN and VAUX regulators are also turned OFF. When the device is in Low Power VDD OFF mode, it monitors external events to wake-up and leave the LP mode. The wake-up events can occurs from:

• C A N
• LIN interface, depending upon device part number
• Expiration of an internal timer
• I/O-0, and I/O-1 inputs, and depending upon device part number and configuration, I/O-2 and/or -3 input
• Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense of I/O-2 and -3 input, associated by I/O-0 activation When a wake-up event is detected, the device enters into reset mode and then into Normal Request mode. The wake- up source are reported into the device SPI registers. In summary, a wake-up event from LP VDD OFF, lead to VDD regulator turn ON, and MCU operation restart. LOW POWER - VDD ON In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to 100 μA or a few mA, as the ECU is in reduced power operation mode. During this mode, the 5 V-CAN and VAUX regulators are OFF. The optional external PNP at VDD will also be automatically disabled when entering this mode. The same wake-up events as in LP VDD OFF mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP VDD on mode. In addition, two additional wake-up conditions are available.
• Dedicated SPI command. When device is in LP VDD ON mode, the wake-up by SPI command uses a write to “Normal Request mode”, 0x5C10.
• Output current from VDD exceeding L P-ITH threshold. In Low Power VDD ON mode, the device is able to source several tenths of mA DC. The current source capability can be time limited, by a selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceed the output current threshold typ 1.5 mA. This allow for instance a periodic activation of the MCU, while the device remains in LP VDD on mode. If the duration exceed the selected time (ex 32 ms), the device will detect a wake-up. Wake-up events are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation. Watchdog Function in LP VDD ON mode It is possible to enable the watchdog function in Low Power VDD ON mode. In this case, the principle is timeout. Refresh of the watchdog is done either by:
• a dedicated SPI command (different from any other SPI command or simple CS activation which would wake-up - ref to the previous paragraph)
• or by a temporary (less than 32 ms max) VDD over current wake-up (IDD > 1.5 mA typ). As long as the watchdog refresh occurs, the device remains in LP VDD on mode. MODE transition Mode transitions are either done automatically (i.e after timeout expired or voltage conditions), or via a SPI command, or by external event such as a wake-up. Some mode change are performed via “secured” SPI commands.

36 Freescale Semiconductor

(4) VDD external PNP is disable in all mode except Normal and Flash modes. Figure 20. State Diagram

Analog Integrated Circuit Device Data Freescale Semiconductor 37 33903/4/5 FUNCTIONAL DEVICE OPERATION MODE CHANGE MODE CHANGE “SECURED SPI” DESCRIPTION: A request is done by a SPI command, the device provide on MISO an unpredictable “random code”. Software must perform a logical change on the code and return it to the device with the new SPI command to perform the desired action. The “random code” is different at every exercise of the secured procedure and can be read back at any time. The secured SPI uses the Special MODE register for the following transitions: - from Normal mode to INT mode - from Normal mode to Flash mode - from Normal mode to Reset mode (reset request). “Random code” is also used when the “advance watchdog” is selected. CHANGING OF DEVICE CRITICAL PARAMETERS Some critical parameters are configured one time at device power on only, while the batfail flag is set in the INIT mode. If a change is required while device is no longer in INIT mode, device must be set back in INIT mode using the “SPI secure” procedure. WATCHDOG OPERATION IN NORMAL REQUEST MODE In Normal Request mode, the device expects to receive a watchdog configuration before the end of the normal request time out period. This period is reset to a long (256 ms) after power on and when BATFAIL is set. The device can be configured to a different (shorter) time out period which can be used after wake-up from LP VDD on mode. After a software watchdog reset, the value is restored to 256 ms, in order to allow for a complete software initialization, similar to a device power up. In Normal Request mode the watchdog operation is “timeout” only and can be triggered/served any time within the period. WATCHDOG TYPE SELECTION Three types of W/D operation can be used: - Window watchdog (default) - Timeout operation - Advanced The selection of W/D is performed in INIT mode. This is done after device power up and when the BATFAIL flag is set. W/D configuration is done via the SPI. Then, the W/D mode selection content is locked and can be changed only via a secured SPI procedure. Window Watchdog Operation The window watchdog is available in Normal mode only. The watchdog period selection can be kept (SPI is selectable in INIT mode), while the device enters into Low Power V DD ON mode. The watchdog period is reset to the default long period after BATFAIL. The period and the refresh of watchdog is done by the SPI. A refresh must be done in the open window of the period, which starts at 50% of the selected period and ends at the end of the period. If the watchdog is triggered before 50%, or not triggered before end of period, a reset has occurred. The device enters into Reset mode. Watchdog in Debug Mode When the device is in Debug mode (entered via the DBG pin), the watchdog continues to operate but does not affect the device operation by asserting a reset. For the user, operation appears without the watchdog. When debug is left by software (SPI mode reg) the watchdog period starts at the end of the SPI command. When debug mode is left by hardware (DBG pin below 8- 10 V), the device enters into Reset mode. Watchdog in Flash Mode During Flash mode operation, the watchdog can be set to a long timeout period. Watchdog is timeout only and an INT pulse can be generated at 50% of the time window. Advance Watchdog Operation When the Advance watchdog is selected (at INIT mode), the refresh of the watchdog must be done using a random number and with 1, 2, or 4 SPI commands. The number for the SPI command is selected in INIT mode. The software must read a random byte from the device, and then must return the random byte inverted to clear the watchdog. The random byte write can be performed in 1, 2, or 4 different SPI commands. If one command is selected, all eight bits are written at once. If two commands are selected, first write command must include four of the eight bits of the inverted random byte. The second command must include the next four bits. This complete the watchdog refresh. If four commands are selected, the first write command must include two of the eight bits of the inverted random byte. The second command must include the next two bits, the 3rd command the next two, and the last command, the last two. This complete the watchdog refresh.

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION WATCHDOG OPERATION When multiple writes are used, the most significant bits are send first. The latest SPI command needs to be done inside the open window time frame, if window watchdog is selected. DETAIL SPI OPERATION AND SPI COMMANDS FOR ALL WATCHDOG TYPES. All SPI commands and examples given in this document do not make use of the parity functions. In INIT mode, the watchdog type (window, timeout, advance and number of SPI commands) is selected using register Init W/D, bits 1, 2 and 3. The watchdog period is selected via TIM_A register. The watchdog period selection can also be done in Normal mode or in Normal Request mode. Transition from INIT mode to Normal mode or from Normal Request mode to Normal mode is done via a single W/D refresh command (SPI 0x 5A00). While in Normal mode, the watchdog refresh command depends upon the watchdog type selected in INIT mode. They are detailed in the paragraph below: Simple Watchdog: Refresh command is 0x5A00. It can be send any time within the watchdog period, if the timeout watchdog operation is selected (INIT-watchdog register, bit 1 WD N/Win = 0). It must be send in the open window (second half of the period) if the Window Watchdog operation was selected (INIT-watchdog register, bit 1 WD N/Win = 1). Advance Watchdog: The first time device enters in Normal mode (entry on Normal mode using the 0x5A00 command), Random (RNDM) code must be read using SPI command 0x1B00. Device returns on MISO second byte the RNDM code. The full 16 bits MISO is called 0x XXRD. RD is the complement of the RD byte. Advance Watchdog, Refresh by 1 SPI Command: The refresh command is 0x5ARD. During each refresh command device returns on MISO a new Random Code. This new random code must be inverted and send along with the next refresh command and so on. It must be done in the open window if the Window operation was selected. Advance Watchdog, Refresh by two SPI Commands: The refresh command is splitted in two SPI commands. The first partial refresh command is 0x5Aw1, and the second is 0x5Aw2. Byte w1 contains the first four inverted bits of the RD byte plus the last four bits equal to zero. Byte w2 contains four bits equal to zero plus the last four inverted bits of the RD byte. During this second refresh command device return on MISO a new Random Code. This new random code must be inverted and send along with the next two refresh commands and so on. The second command must be done in the open window if the Window operation was selected. Advance Watchdog, Refresh by four SPI Commands: The refresh command is splitted in four SPI commands. The first partial refresh command is 0x5Aw1, the second is 0x5Aw2, the third is 0x5Aw3, and the last is 0x5Aw4. Byte w1 contains the first two inverted bits of the RD byte, plus the last six bits equal to zero. Byte w2 contains two bits equal to zero, plus the next two inverted bits of the RD byte, plus four bits equal to zero. Byte w3 contains four bits equal to zero, plus the next two inverted bits of the RD byte, plus two bits equal to zero. Byte w4 contains six bits equal to zero, plus the next two inverted bits of the RD byte. During this fourth refresh command device return on MISO a new Random Code. This new random code must be inverted and send along with the next four refresh commands. The fourth command must be done in the open window if the Window operation was selected. PROPER RESPONSE TO INT A device detect, that upon an INT, the software handles the INT in a timely manner: Access of the INT register is done within two watchdog periods. Such feature must be enabled by SPI via the INIT watchdog register bit 7

Table 6. Device Block Operation for Each State internal 30k pull-up active.

1. With limited current capability
2. 5 V-CAN is ON in Debug mode.

The 5 V-CAN default is ON when the device is powered-up and set in Deb ug mode. It is fully controllable via the SPI command. ILLUSTRATION OF DEVICE MODE TRANSITIONS. Figure 21. Power Up Normal and Low Power Modes

40 Freescale Semiconductor

ILLUSTRATION OF DEVICE MODE TRANSITIONS. Figure 22. Wake-up from Low Power Modes

the contact pull-up resistor. m 3.0 to 512 ms (selection in timer B). the state of I/O-0 prior to enter in low power mode. of them is high, the device will detect a wake-up. (Figure 23). contact switches are closed. In LP mode, 1 contact switch is open. High level is detected on I/O-x, and device wakes up. Figure 23. Cyclic Sense Operation - Switch to GND, Wake-up by Open Switch

42 Freescale Semiconductor

mode, the device will generate a periodic INT pulse. end of the next INT period in order to keep the process going. cyclic Interrupt period (SPI command without parity bit)]. MISO second byte the RNDM code (MISO bit 0-7). These commands can occur at any time within the period. acknowledge process must start only after the 1st INT pulse. enter into Normal Request mode. Figure 24. Cyclic Interrupt Operation

the Crank bit and the two VDD under-voltage reset thresholds. enable when VSUP1 is above VSUP TH 1 parameters. Figure 25. VDD Start-up Versus VSUP1 Tramp under-voltage reset selection. Bit 0 = 0 is the default state fo r this bit. remains ON until device detects a POR and set BATFAIL. This occurs for a VSUP approx 3.0 V.

44 Freescale Semiconductor

Figure 26. VDD Behavior During VSUP1 Ramp Down

Analog Integrated Circuit Device Data Freescale Semiconductor 45 33903/4/5 FAIL SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN FAIL SAFE OPERATION OVERVIEW Fail safe mode is entered when specific fail conditions occur. The “Safe state” condition is defined by the resistor connected at the DGB pin. Safe mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin. Exit of the safe state is alwa ys possible by a wake-up event: in the safe state the device is automatically wakeable CAN and I/O (if configured as inputs). Upon wake-up, the device operation is resumed: enter in Reset mode. FAIL SAFE FUNCTIONALITY Upon dedicated event or issue detected at a device pin (i.e RESET), the Safe mode can be entered. In this mode, the SAFE pin is active low.

Description

Upon activation of the SAFE pin, and if the failure cond ition that make the SAFE pin activated have not recovered, the device can help to reduce ECU consumption, assuming that the MCU is not able to set the whole ECU in low power mode. Two main cases are available: Mode A: Upon SAFE activation, the MCU remains powered (V DD stays ON), until the failure condition recovers (i.e S/W is able to properly control the devic e and properly refresh the watchdog). Modes B1, B2 and B3: Upon SAFE activation, the system continues to monitor external event, and disable the MCU supply (turn VDD OFF). The external events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3. Note: no CAN traffic indicates that the ECU of the vehicle are no longer active, thus that the car is being parked and stopped. The I/O low level detection can also indicate that the vehicle is being shutdown, if the I/O-1 pin is connected for instance to a switched battery signal (ignition key on/off signal). The selection of the monitored events is done by har dware, via the resistor connected at DBG pin, but can be over written by software, via a specific SPI command. By default, after power up the device detect the resistor valu e at DBG pin (upon transition from INIT to Normal mode), and, if no specific SPI command related to Debug resistor change is send, operates according to the detected resistor. The INIT MISC register allow to verify and change the de vice behaviour, to either confirm or change the hardware selected behaviour. Device will then operate according to the SAFE mode configured by the SPI. Table 7 illustrates the complete options available: Table 7. Fail Safe Options B1 Turn OFF 8.0 s after CAN traffic bus idle detection. B2 Turn OFF when I/O-1 low level detected. SPI flags reporting the SAFE conditions.

46 Freescale Semiconductor

5) detection of 8 consecutive W/D failures: no correct SPI W/D refresh command occurred for duration of 8 x 256 ms. between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes. 7) 8 second timer for bus idle timeout. I/O-1 high to low transition. Figure 27. Safe Operation Flow Chart as the RESET pin is set low. is the case, the Safe mode is entered.

48 Freescale Semiconductor

resistor or SPI configuration. Figure 29. SAFE Modes B1, B2, or B3 Behavior Illustration

Figure 30. CAN Interface Block Diagram The supply voltage for the CAN driver is the 5 V-CAN pin. mode to allow wake-up detection. e CAN interface current is sourced from the 5 V-CAN pin. pin level, and the CAN bus state is reported on the RXD pin. asing is provided on the SPLIT output pin. effect on CAN bus lines. The 5 V-CAN regulator must be ON. mode and the TXD pin is recessive.

50 Freescale Semiconductor

5 V-CAN divided by 2, or approx. 2.5 V. affected by the slew rate selection. error flag and its echo error flag). to a single bit time of: 300 μs / 12 = 25 μs. So the minimum Baud rate is 1 / 25 μs = 40 kBaud. Sleep mode is a reduced current consumption mode. results in a device wake-up if device was in Low Power mode. Figure 31. Bus Signal in TxD/RxD and Low Power Mode

52 Freescale Semiconductor

Figure 34. Bus Termination Options monitor the bus level in the recessive and dominant states. properly determine the failure and report it. Figure 35. CAN Bus Simplified Structure Truth Table for Failure Detection The following table indicates the state of the comparators in case of a bus failure, and depending upon the driver state. Table 8. Failure Detection Truth Table

comparator is also close to zero. dominant cycles, the error is not reported. to internal 2.5 V biasing or to GND (Sleep mode). The RxD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 36. RxD Path Simplified Schematic, RxD Short to VDD Detection is reported via SPI in CAN register.

54 Freescale Semiconductor

l at TXD as shown in the following illustration. The RxD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 37. RxD Path Simplified Schematic, RxD Short to VDD Detection into dominant level, and no communication is possible. a recessive state. The TXD permanent flag is set. change from recessive to dominant. in order to re enable the CAN bus driver.

Analog Integrated Circuit Device Data Freescale Semiconductor 55 33903/4/5 LIN BLOCK LIN INTERFACE DESCRIPTION LIN BLOCK LIN INTERFACE DESCRIPTION The physical interface is dedicated to automotive LIN sub- bus applications. The interface has 20 kbps and 10 kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior in case of a LIN bus short-to-ground, or a LIN bus leakage during low power mode. Digital inputs are related to the device VDD pin. POWER SUPPLY PIN (VSUP2) The VSUP2 pin is the supply pin for the LIN interface. To avoid a false bus message, an under-voltage on VSUP2 disables the transmission path (from TXD to LIN) when VSUP falls below 6.1 V. GROUND PIN (GND) In case of a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus pin when in the recessive state. LIN BUS PIN (LIN1, LIN2) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal mode. Driver Characteristics The LIN driver is a low side MOSFET with internal over- current thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ must be added when the device is used in the master node. The 1.0 kΩ pull-up resistor can be connected to the LIN pin or to the ECU battery supply. The LIN pin exhibits no reverse current from the LIN bus line to VSUP2, even in the event of a GND shift or VSUP2 disconnection. The transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI. Receiver Characteristics The receiver thresholds are ratiometric with the device VSUP2 voltage. If the VSUP2 voltage goes below typ 6.1 V, the LIN bus enters into a recessive state even if communication is sent on TXD. If LIN driver temperature reaches the over-temperature threshold, the transceiver and receiver are disabled. When the temperature falls below the over-temperature threshold, LIN driver and receiver will be automatically enabled. DATA INPUT PIN (TXDL1, TXDL2) The TXDl1 (TXDL2) input pin is the MCU interface to control the state of the LIN output. When TXDL is LOW (dominant), LIN output is LOW. When TXDL is HIGH (recessive), the LIN output transistor is turned OFF. This pin has an internal pull-up current source to VDD to force the recessive state if the input pin is left floating. If the pin stays low (dominant sate) more than t TXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag in LIN register. DATA OUTPUT PIN (RXDL1, RXDL2) The RXDl output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage on RXD, LIN LOW (dominant) is reported by a low voltage on RXD. LIN OPERATIONAL MODES The LIN interface have two operational modes, Transmit receiver and LIN disable modes. TRANSMIT RECEIVE In the TxD/RxD mode, the LIN bus can transmit and receive information. When the 20 kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1. When the 10 kbps baud rate is selected, the slew rate and timing are compatible with J2602-2. When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition. The LIN interface can be set by the SPI command in TxD/RxD mode, only when TXDL is at a high level. When the SPI command is send while TXDL is low, the command is ignored. SLEEP MODE This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP2 is very low (typ 3.0 μA). LIN bus is monitor to detect wake-up event. In

56 Freescale Semiconductor

ected and the 30 kOhm disconnected. transition. This is illustrated in Figures 17 and 18. The wake-up can be enable or disable by the SPI. 9 describes the LIN block behavior in case of failure. Table 9. LIN Block Failure

58 Freescale Semiconductor

Table 10 summarizes the various SPI operation, depending upon bit 15, 14, and 8. Table 10. SPI Operations (bits 8, 14 & 15)

00 Read back of register

1 Bit 8 must be set to 1, independently of the parity function

01 Write to register

0 If bit 8 is set to “0”: means parity not selected OR

10 Reserved

11 Read of device flags

coded on five bits (bits 13 to 9). device operation or set default value or behavior. address, coded with bits 13 to 9. Table 11. Device Registers with Corresponding Address 0_0000 Analog Multiplexer MUX 1) Write “device control bits” to register address. 0_0001 Memory byte A RAM_A 1) Write “data byte” to register address. 0_0101 Initialization Regulators Init REG 1) Write “device initialization control bits” to register address.

options. Both MOSI and MISO information are described. Table 12. SPI Capabilities with Options er address (bit 13-9), and sub address (bit 7). om the selected address and sub-address. of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even. because the command contains 7 bits with logic 1. 0_1010 Timer_A: W/D & Low Power MCU consumption TIM_A 1) Write “timing values” to register address. 2) Read back register “control bits”. 3) Read device flags from each of the register addresses.

Analog Integrated Circuit Device Data

60 Freescale Semiconductor

SERIAL PERIPHERAL INTERFACE DETAIL OPERATION Examples 2: MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1, because the command contains 4 bits with logic 1. Thus the Exact command will then be: MOSI [bit 15-0] = 01 00 011 1 0100 0000 Parity function selection: All SPI commands and examples given in this document do not make use of the parity functions. The parity function is optional. It is selected by bit 6 in INIT MISC register. If parity function is not selected (bit 6 of INIT MISC = 0), then Parity bits in all SPI commands (bit 8) must be “0”.

Table 13. MUX Register(25)

011 Device internal temperature sensor voltage

100 Voltage at I/O-0. Attenuation or gain is selected by bit 3. 101 Voltage at I/O-1. Attenuation or gain is selected by bit 3. 0 Internal 2.0 kohm resistor disable. An external resist or must be connected between AMUX and GND. 1 Internal 2.0 kohm resistor enable.

1. The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while

5V-CAN is OFF, the command is ignored, and the MXU register content is reset to default state (all control bits = 0).

Table 14. Internal Memory Registers A, B, C and D, RAM_A, RAM_B, RAM_C and RAM_D

62 Freescale Semiconductor

Table 15. Initialization Regulator Registers, INIT REG (note : register can be written only in INIT mode)

0 I/O-1 sense anytime

1 I/O-1 sense during I/O-0 activation

Table 16. Initialization Watchdog Registers, INIT W/D (no te: register can be written only in INIT mode) 0 Function disable. No constraint between I NT occurrence and INT source read. 1 INT source read must occur before the remaining of the current W/D period plus 2 complete W/D periods. W/D + 00 In Low Power VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command. W/D + 01 In Low Power VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. W/D refresh must occur by SPI command. W/D + 10 In Low Power VDD ON mode, VDD over-current for a time > 100 μs (t yp) is a wake-up event.

0 SAFE pin is set low at the time of the RESET pin low activation

1 SAFE pin is set low at the second consecutive time RESET pulse

00 Simple Watchdog selection: W/D refresh done by a 8 bits or 16 bits SPI

01 Enhanced 1: Refresh is done using the R andom Code, and by a single 16 bits. 10 Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command. 11 Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.

0 Watchdog operation is TIMEOUT, W/D refresh can occur anytime in the period

1 Watchdog operation is WINDOW, W/D refresh must occur in the open window (second half of period)

64 Freescale Semiconductor

Table 17. Initialization LIN and I/O Registers, INIT LIN I/O (n ote: register can be written only in INIT mode) 1 Enable I/O-1 turn off, in case VDD or VAUX over-voltage condition is detected.

11 N/A

0 Disable high side and low side drivers of pin I/O-1. I/O-1 can only be used as input. 1 Enable high side and low side drivers of pin I/O-1. Pin can be used as input and output driver. 0 Disable high side and low side drivers of. I/O-0 can only be used as input. 1 Enable high side and low side drivers of the I/O-0 pin. Pin can be used as input and output driver. side and low side drivers OFF). duration of the cyclic sense period.

Table 18. Initialization Miscellaneous Functions, INIT MISC (No te: Register can be written only in INIT mode) b7 LPM w RNDM - This e nables the usage of random bits 2, 1 and 0 of the MODE register to enter into Low Power VDD OFF or Low Power VDD ON.

0 Function disable: the Low Power mode can b e entered without usage of Random Code

1 Function enabled: the Low Power mode is entered using the Random Code

0 Function disable: the parity is not used. The parity bit must always set to logic 0. 1 Function enable: the parity is used, and parity must be calculated.

0 INT pin will assert a low level pulse, duration selected by bit [b4]

1 INT pin assert a permanent low level (no pulse)

0 INT pulse duration is typ 100 μs. Ref to dynamic parameter table for exact value. 1 INT pulse duration is typ 25 μs. Ref to dynamic parameter table for exact value. Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in flash mode.

1. Bits b2,1 and 0 allow the following operation:

register (ref to device flag table).

66 Freescale Semiconductor

Table 19. Specific Mode Register, SPE_MODE b7, b6 Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command.

00 RESET mode

01 INIT mode

10 FLASH mode

• Go to INIT mode, using the Secure SPi command.
• Activate the SAFE pin by S/W.

68 Freescale Semiconductor

Table 20. Timer Register A, Low Power VDD Over-current & Watchdog Period Normal Mode, TIM_A Table 21. Timer Register B, Cyclic Sense and Cycl ic INT, in Device Low Power Mode, TIM_B

Table 22. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C Table 23. Typical Timing Values

70 Freescale Semiconductor

Table 24. Watchdog Refresh Register, W/D(27)

1. The Simple Watchdog Refresh command is in hexadecimal: 5A00. T his command is used to refresh the W/D and also to transition

Table 25. MODE Register, MODE Table 26. Low Power VDD OFF Selection and FWU / Cyclic Sense Selection Table 27. Low Power VDD ON selection and operation mode

flags must be cleared or read. 14] and bit [7]. Note, bit [8] is always set to 1. mode via bit 7 of the INIT MISC register.

• Write LP Mode by inverting the 3 random bits.

1. in hex: 0x5C60 to enter in LP VDD OFF mode without
2. if Random Code is selected, the commands are:

Table 28. Device Modes Read device current mode, Leave debug mode. Release SAFE pin (turn OFF). Read device current mode, Leave debug mode. Release SAFE pin (turn OFF).

72 Freescale Semiconductor

allow to decode the device current mode. Table 29. MISO bits 7-3 Table 30. SAFE and DEBUG status

0 SAFE pin OFF, not activated

1 SAFE pin ON, driver activated.

0 Debug mode OFF

1 Debug mode Active

Table 31. REGULATOR Register, REG

00 Regulator OFF

detected after 1.0 ms blanking time. blanking time for UV and OC detection. time for UV and OC detection. etected after 25 μs blanking t ime.

0 External VDD ballast disable

1 External VDD ballast Enable

0 Disable the automatic activation of the external ballast

1 Enable the automatic activation of the external ballast, if VDD > typ 60 mA

Analog Integrated Circuit Device Data Freescale Semiconductor 73 33903/4/5 SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING

0 Disable Usage of Low Power VDD OFF mode

1 Enable Usage of Low Power VDD OFF mode

Table 32. CAN Register, CAN(28) 00 CAN interface in Sleep mode, CAN wake-up disable. 01 CAN interface in receive only mode, CAN driver disable. CAN wake-up is reported by device wake-up. In device normal mode, CAN wake-up reported by INT. 11 CAN interface in transmit and receive mode.

00 FAST

01 MEDIUM

10 SLOW

11 SLOW

1 Single dominant pulse wake-up mechanism

1 Select INT generation as soon as a bus failure is detected, event if not fully identified

1. The first time the device is set in Normal mode, the CAN is in Sleep wake- up enable (bit7 = 1, bit 6 =0). The next time the device is

set in Normal mode, the CAN state is controlled by bits 7 and 6.

74 Freescale Semiconductor

Table 33. I/O Register, I/O

00 I/O-3 driver disable, Wake-up capability disable

01 I/O-3 driver disable, Wake-up capability enable. 10 I/O-3 High Side driver enable. 11 I/O-3 High Side driver enable.

00 I/O-2 driver disable, Wake-up capability disable

01 I/O-2 driver disable, Wake-up capability enable. 10 I/O-2 High Side driver enable. 11 I/O-2 High Side driver enable.

00 I/O-1 driver disable, Wake-up capability disable

01 I/O-1 driver disable, Wake-up capability enable. 10 I/O-1 Low Side driver enable. 11 I/O-1 High Side driver enable.

00 I/O-0 driver disable, Wake-up capability disable

01 I/O-0 driver disable, Wake-up capability enable. 10 I/O-0 Low Side driver enable. 11 I/O-0 High Side driver enable.

Table 34. INT Register, INT

0 INT disable

1. If VDD under-voltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 63.
2. Bit 2 is used in conjunction with bi t 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request.

76 Freescale Semiconductor

Table 35. LIN 1 Register, LIN1(32)

00 LIN1 disable, wake-up capability disable

10 LIN1 disable, wake-up capability enable

11 LIN1 Transmit Receive mode(31)

00 Slew rate for 20 kbit/s baud rate

01 Slew rate for 10 kbit/s baud rate

10 Slew rate for fast baud rate

11 Slew rate for fast baud rate

0 LIN 1 termination OFF

1 LIN 1 termination ON

1 LIN continues operation below VSUP2 6.0 V, until 5 V-CAN is disabled.

1. The LIN interface can be set in TxD/RxD mode only when the TXDL input signal is in re cessive state. An attempt to set TxD/RxD

mode, while TXDL is low, will be ignored and the LIN interface remains disabled.

1. In order to use LIN interface, the 5V-CAN regulator must be ON.

Table 36. LIN 2 Register, LIN2(34)

00 LIN2 disable, wake-up capability disable

10 LIN2 disable, wake-up capability enable

11 LIN2 Transmit Receive mode(33)

0 LIN 2 temination OFF

1 LIN 2 temination ON

1 LIN continues operation below VSUP2 6.0 V, until 5 V-CAN is disabled.

1. The LIN interface can be set in TxD/RxD mode only when the TXDL input signal is in recessive state. An attempt to set TxD/RxD mode,

while TXDL is low, will be ignored and the LIN interface remains disabled.

1. In order to use LIN interface, the 5V-CAN regulator must be ON.

78 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 79 33903/4/5 SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS FLAGS AND DEVICE STATUS The table below is a summary of the device flags, I/O real time level, device Identification and includes examples of SPI commands (SPI command do not use parity functions). They are obtained using the following commands. This command is composed of the following: bits 15 and 14:

• [1 1] for failure flags
• - [0 0] for I/O real time st atus, device identification and CAN LIN driver receiver real time state.
• bit 13 to 9 are the register address from which the flags is to be read.
• b i t 8 = 1 (this is not parity bit function, as this is a read command). When a failure event occurs, the respective flag is set and remains latched until it is cleared by a read command (provided the failure event has recovered).

Table 37. Device Flag, I/O Real Time and Device Identification

1 CAN_UF CAN_F CANL

1 I/O_1-3

80 Freescale Semiconductor

Table 38. Flag Descriptions VAUX_LOW Description Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold. Description Report that current out of VAUX regulator is above VAUX_OC threshold. Set / Reset condition Set: Current above threshold for t >100 μs. Reset: Current below threshold and flag read by SPI.

5 V-CAN_

Description Report that the 5 V-CAN regulator has reached over-temperature threshold. 5V-CAN_UV Description Reports that 5 V-CAN regulator output voltage is lower than the 5 V-CAN UV threshold. Description Report that the CAN driver output current is above threshold. Description Reports that VSENSE pin is lower than the VSENSE LOW threshold. Description Reports that VSUP1 pin is lower than the VSUP1 LOW threshold. Description Report that current out of VDD pin is higher that IDD-OC threshold, while device is in Normal mode. Description Report that the VDD has reached over-temperature threshold, and was turned off. Description Report that the device voltage at VSUP1 pin was below BATFAIL threshold.

(0x2180) do not clear the flag, as it is “real time” information. Description Report that the CAN interface has reach over-temperature threshold. RxD low Description Report that RxD pin is shorted to GND. Rxd high Description Report that RxD pin is shorted to recessive voltage. TxD dom Description Report that TxD pin is shorted to GND. Description Report that the CAN current is above CAN over-current threshold.

82 Freescale Semiconductor

Description Report SPI parity error was detected. VSUP2-UV Description Report that VSUP2 is below VSUP2-UV threshold. VSUP1-OV Description Report that VSUP1 is above VSUP1-OV threshold. I/O-0 thermal Description Report that the I/O-0 high side switch has reach over-temperature threshold. Description Report that the W/D period has reach 50% of its value, while device is in Flash mode. SPI wake-up Description Report that wake-up source is SPI command, in Low Power VDD ON mode. Description Report that INT timeout error detected. Set / Reset condition Set: INT service timeout expired. Reset: flag read. Description Report that Low Power VDD OFF mode was selected, prior wake-up occurred. Reset request Description Report that RST source is an request from a SPI command (go to RST mode). Set / Reset condition Set: device leave debug mode due to hardware cause. Reset: flag read.

INT request Description Report that INT source is an INT request from a SPI command. RST high Description Report that RST pin is shorted to high voltage. Set / Reset condition Set: RST failure detection. Reset: flag read. DBG resistor Description Report that the resistor at DBG pin is different from expected (different from SPI register content). Set / Reset condition Set: failure detected. Reset: correct resistor and flag read (SPI). Description Report that the VDD has reached over-temperature prewarning threshold. VDD UV Description Reports that VDD pin is lower than the VDDUV threshold. function is selected in INIT register. function is selected in INIT register. VDD LOW Description Report that VDD is below VDD under-voltage threshold. Description Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong W/D refresh. Description Report that a wrong or missing W/D failure occurred.

84 Freescale Semiconductor

command (0x2780 or 0x2980) do not clear it, as it is “real time” flag. (means LIN signal will not be detected and will not wake up the device). not clear the flag, as it is “real time” information. Description Report that the LIN1 or LIN 2 interface has reach over-temperature threshold. RxD1/2 low Description Report that RxD1/2 pin is shorted to GND. RxD1/2 high Description Report that RxD1/2pin is shorted to recessive voltage. TxD1/2 dom Description Report that TxD1/2 pin is shorted to GND.

Table 39. Status Bits Description INT Indicate that an INT has occurred and that INT flags are pending to be read. WU Indicate that a wake-up has occurred and that wake-up flags are pending to be read. RST Indicate that a reset has occurred and that the flags that report the reset source are pending to be read. CAN-G The INT, WU or RST source is CAN interface. CAN local or CAN bus source. I/O-G The INT, WU or RST source is I/O interfaces. CAN-LOC The INT, WU or RST source is CAN interface. CAN local source. CAN-BUS The INT, WU or RST source is CAN interface. CAN bus source.

86 Freescale Semiconductor

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

Figure 39. 33905D Typical Application Schematic

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

Figure 40. 33905S Typical Application Schematic

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

88 Freescale Semiconductor

Figure 41. 33904 Typical Application Schematic

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

Figure 42. 33903 Typical Application Schematic

90 Freescale Semiconductor

without using the VAUX regulator are illustrated as well. Optimized solution for cranking pulses. C1 is sized for MCU power supply buffer only. delivered by internal path transistor. Figure 43. Application Options

Analog Integrated Circuit Device Data Freescale Semiconductor 91 33903/4/5 PACKAGING SOIC 32 PACKAGE DIMENSIONS PACKAGING SOIC 32 PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D

EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D Analog Integrated Circuit Device Data

92 Freescale Semiconductor

SOIC 32 PACKAGE DIMENSIONS

EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor 93 33903/4/5 PACKAGING SOIC 32 PACKAGE DIMENSIONS

EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data

94 Freescale Semiconductor

SOIC 54 PACKAGE DIMENSIONS SOIC 54 PACKAGE DIMENSIONS

EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor 95 33903/4/5 PACKAGING SOIC 54 PACKAGE DIMENSIONS

EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data

96 Freescale Semiconductor

SOIC 54 PACKAGE DIMENSIONS

Analog Integrated Circuit Device Data Freescale Semiconductor 97 33903/4/5

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 4.0 9/2010 5.0 12/2010

• Initial Release - This document supersedes document MC33904_5.
• Initial release of document in cludes the MC33903 part number, the VDD 3.3 V version description, and the silicon revision rev. 3.2. Change details available upon request.
• Added Cyclic INT Operation During Low Power VDD ON Mode on page 42
• Changed VSUP pin to VSUP1 and pin 2 (NC) to VSUP2 for the 33903 device
• Removed Drop voltage without external PNP pass transistor (9) on page 16 for VDD=3.3 V devices
• Added V SUP1-3.3 to VDD Voltage regulator, VDD pin on page 16.
• Added Pull-up Current, TxD, VIN = 0 V on page 20 for VDD=3.3 V devices
• R e v i s e d MUX and RAM registers on page 61
• R e v i s e d Status Bits Description on page 85
• Added Entering into LP Mode using Random Code on page 71.

How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. MC33903_4_5 Rev. 5.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.