MCZ33903B3R2

33903 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 104

Technical content

Features

• Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with po ssibility of usage external PNP to extend current capability and share power dissipation
• Voltage, current, and temperature protection
• Extremely low quiescent current in (LP) Modes
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Multiple under-voltage detections to address various MCU specifications and system operation modes (i.e. cranking)
• Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with over-curren t detection and under-voltage protection
• MUX (except 33903) output pin for device internal analog signal moni toring and power supply monitoring
• Advanced SPI, MCU, ECU power supply, and critical pins di agnostics and monitoring.
• Multiple Wake-Up sources in (LP) Modes: CAN or LIN bus, I/O t ransition, automatic timer, SPI message, and VDD over-current detection.
• ISO11898-5 high speed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s

Analog Integrated Circuit Device Data

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Figure 3. 33904 Simplified Application Diagram Figure 4. 33903 Simplified Application Diagram

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Table 1. Device Variations - (All devices rated at TA = -40 TO 125 °C)

2 SOIC 54 pin

1 SOIC 32 pin

2 SOIC 32 pin

2 Wake-Up + 1 LIN terms

3 Wake-U

1. V DD does not allow usage of an external PNP on the 33903. Output current limited to 100 mA.

enhanced device current consumption and improved oscillator stability.

2 Wake-Up + 2 LIN terms

4 Wake-Up + no LIN terms

3 Wake-Up + 1 LIN terms

4 Wake-U

1 Wake-Up + 2 LIN terms

2 Wake-U

3 Wake-Up + no LIN terms

5 V Auxiliary

Figure 7. 33905D Internal Block Diagram

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Figure 8. 33905S Internal Block Diagram

Figure 9. 33904 Internal Block Diagram Figure 10. 33903 Internal Block Diagram

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Figure 11. 33903D Internal Block Diagram

Figure 12. 33903S Internal Block Diagram

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Figure 13. 33905D, MC33905S, MC33904 and MC33903 Pin Connections

Note: MC33903D and MC33903S are footprint compatible. Figure 14. 33905D, MC33905S, MC33904 and MC33903 Pin Connections

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Table 2. 33903/4/5 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 34.

54 Pin

32 Pin

LIN2 master node termination resistor. pin, etc.). Open drain structure. 10 7 7 7 7 7 CANH Output CAN High CAN high output.

11 8 8 8 8 8 CANL Output CAN Low CAN low output. Output pin for the auxiliary voltage. be activated for a cyclic sense function.

23 N/A N/A N/A 14 N/A TXD-L2 Input LIN Transmit

internal pull-up resistor to VDD. 24,31 N/A N/A N/A 15, 18 15, 18 GND Ground Ground Ground of the IC.

25 N/A N/A N/A 16 N/A RXD-L2 Output LIN Receive

LIN bus receive data output.

26 N/A N/A N/A 17 N/A LIN2 Input/

internal pull-up resistor to VDD. LIN bus receive data output. Table 2. 33903/4/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 34.

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current during high voltage transients. internal pull up resistor to VDD. regulator for the Microcontroller supply. A functional description of each pin can be found in the Functional Pin Description section beginning on page 34.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33903/4/5

ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings

1. The voltage on non-VSUP pins should never exceed the V SUP voltage at any time or permanent damage to the device may occur.
2. If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external VDD ballast current sharing functionality may be
3. Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON.

Analog Integrated Circuit Device Data

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Figure 15. PCB with Top and Bottom Layer Dissipation Area (Dual Layer)

1. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), the Cha rge Device Model

(CDM), and Robotic (CZAP = 4.0 pF).

1. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets P b-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. ( i.e. MC33xxxD enter 33xxx), and review parametrics.

1. This parameter was measured according to Figure 15:

Table 3. Maximum Ratings (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33903/4/5 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

1. All parameters in spec (ex: V DD regulator tolerance).
2. Device functional, some param eters could be out of spec. VDD is active, device is not in Reset Mode if the lowest VDD under-voltage

reset threshold is selected (approx. 3.4 V). CAN and I/Os are not operational.

1. In Run Mode, CAN interface in Sleep Mode, 5 V-CAN and VAUX turned OFF. IOUT at VDD < 50 mA. Ballast: turned OFF or not connected.
2. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. Therefore, ISUP1 and ISUP2

cannot be measured individually.

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STATIC ELECTRICAL CHARACTERISTICS VDD VOLTAGE REGULATOR, VDD PIN Output Voltage VDD = 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA VDD = 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA VOUT-5.0 VOUT-3.3 4.9 3.234 5.0 3.3 5.1 3.366 V Drop voltage without external PNP pass transistor(13) VDD = 5.0 V, IOUT = 100 mA VDD = 5.0 V, IOUT = 150 mA VDROP 330 450 500 mV Drop voltage with external transistor(13) IOUT = 200 mA (I_BALLAST + I_INTERNAL) VDROP-B - 350 500 mV VSUP/1 to maintain VDD within VOUT-3.3 specified voltage range VDD = 3.3 V, IOUT = 150 mA VDD = 3.3 V, IOUT = 200 mA, external transistor implemented VSUP1-3.3 4.0 4.0 V External ballast versus internal current ratio (I_BALLAST = K x Internal current) K 1.5 2.0 2.5 Output Current limitation, without external transistor ILIM 150 350 550 mA Temperature pre-warning (Guaranteed by design) TPW - 140 - °C Thermal shutdown (Guaranteed by design) TSD 160 - - °C Range of decoupling capacitor (Guaranteed by design)(14) CEXT 4.7 - 100 μF LP Mode VDD ON, IOUT ≤ 50 mA (time limited) VDD = 5.0 V, 5.6 V ≤ VSUP ≤ 28 V VDD = 3.3 V, 5.6 V ≤ VSUP ≤ 28 V VDDLP 4.75 3.135 5.0 3.3 5.25 3.465 V LP Mode VDD ON, dynamic output current capability (Limited duration. Ref. to device description). LP-IOUTDC - - 50 mA LP VDD ON Mode: Over-current Wake-Up threshold. Hysteresis LP-ITH 1.0 0.1 3.0 1.0 mA LP Mode VDD ON, drop voltage, at IOUT = 30 mA (Limited duration. Ref. to device description) (13) LP-VDROP - 200 400 mV LP Mode VDD ON, min VSUP operation (Below this value, a VDD, under-voltage reset may occur) LP-MINVS 5.5 - - V VDD when VSUP < VSUP-TH1, at I_VDD ≤ 10 μA (Guaranteed by design) VDD_OFF - - 0.3 V VDD when VSUP ≥ VSUP-TH1, at I_VDD ≤ 40 mA (Guaranteed with parameter VSUP-TH1 VDD_START UP 3.0 - - V Notes 13. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout voltage parameter cannot be specified. 14. The regulator is stable without an external capacitor. Us age of an external capacitor is recommended for AC performance. Table 4. Static Electrical Characteristics (continued) noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33903/4/5 STATIC ELECTRICAL CHARACTERISTICS VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY, 5.0 V-CAN PIN Output voltage, VSUP/2 = 5.5 to 40 V IOUT 0 to 160 mA 5V-C OUT 4.75 5.0 5.25 V Output Current limitation (15) 5V-C ILIM 160 280 - mA Under-voltage threshold 5V-C UV 4.1 4.5 4.7 V Thermal shutdown (Guaranteed by design) 5V-CTS 160 - - °C External capacitance (Guaranteed by design) CEXT-CAN 1.0 - 100 μF V AUXILIARY OUTPUT, 5.0 AND 3.3 V SELECTABLE PIN VB-AUX, VC-AUX, VAUX VAUX output voltage VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA VAUX 4.75 3.135 5.0 3.3 5.25 3.465 V VAUX under-voltage detector (VAUX configured to 5.0 V) Low Threshold Hysteresis VAUX under-voltage detector (VAUX configured to 3.3 V, default value) VAUX-UVTH 4.2 0.06 2.75 4.5 3.0 4.70 0.12 3.135 V VAUX over-current threshold detector VAUX set to 3.3 V VAUX set to 5.0 V VAUX-ILIM 250 230 360 330 450 430 mA External capacitance (Guaranteed by design) VAUX CAP 2.2 - 100 μF UNDER-VOLTAGE RESET AND RESET FUNCTION, RST PIN VDD under-voltage threshold down - 90% VDD (VDD 5.0 V)(16), (18) VDD under-voltage threshold up - 90% VDD (VDD 5.0 V) VDD under-voltage threshold down - 90% VDD (VDD 3.3 V)(16), (18) VDD under-voltage threshold up - 90% VDD (VDD 3.3 V) VRST-TH1 4.5 2.75 4.65 3.0 4.85 4.90 3.135 3.135 V VDD under-voltage reset threshold down - 70% VDD (VDD 5.0 V)(17), (18) VRST-TH2-5 2.95 3.2 3.45 V Hysteresis for threshold 90% VDD, 5.0 V device for threshold 70% VDD, 5.0 V device Hysteresis 3.3 V VDD for threshold 90% VDD, 3.3 V device VRST-HYST 150 150 150 mV VDD under-voltage reset threshold down - LP VDD ON Mode (Note: device change to Normal Request Mode). VDD 5.0 V (Note: device change to Normal Request Mode). VDD 3.3 V VRST-LP 4.0 2.75 4.5 3.0 4.85 3.135 V Notes 15. Current limitation will be reported by setting a flag. 16. Generate a Reset or an INT. SPI programmable 17. Generate a Reset 18. In Non-LP Modes noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS UNDER-VOLTAGE RESET AND RESET FUNCTION, RST PIN (CONTINUED) Reset VOL @ 1.5 mA, VSUP 5.5 to 28 V VOL - 300 500 mV Current limitation, Reset activated, VRESET = 0.9 x VDD IRESET LOW 2.5 7.0 10 mA Pull-up resistor (to VDD pin) RPULL-UP 8.0 11 15 kΩ VSUP to guaranteed reset low level(19) VSUP-RSTL 2.5 - - V Reset input threshold Low threshold, VDD = 5.0 V High threshold, VDD = 5.0 V Low threshold, VDD = 3.3 V High threshold, VDD = 3.3 V VRST-VTH 1.5 2.5 0.99 1.65 1.9 3.0 1.17 2.0 2.2 3.5 1.32 2.31 V Reset input hysteresis VHYST 0.5 1.0 1.5 V I/O PINS WHEN FUNCTION SELECTED IS OUTPUT I/O-0 HS switch drop @ I = -12 mA, VSUP = 10.5 V VI/O-0 HSDRP - 0.5 1.4 V I/O-2 and I/O-3 HS switch drop @ I = -20 mA, VSUP = 10.5 V VI/O-2-3 HSDRP - 0.5 1.4 V I/O-1, HS switch drop @ I = -400 μA, VSUP = 10.5 V VI/O-1 HSDRP - 0.4 1.4 V I/O-0, I/O-1 LS switch drop @ I = 400 μA, VSUP = 10.5 V VI/O-01 LSDRP - 0.4 1.4 V Leakage current, I/O-x ≤ VSUP II/O_LEAK - 0.1 3.0 μA I/O PINS WHEN FUNCTION SELECTED IS INPUT Negative threshold VI/O_NTH 1.4 2.0 2.9 V Positive threshold VI/O_PTH 2.1 3.0 3.8 V Hysteresis VI/O_HYST 0.2 1.0 1.4 V Input current, I/O ≤ VSUP/2 II/O_IN -5.0 1.0 5.0 μA I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in register, 2.0 V < VI/O-X <16 V (Guaranteed by design). RI/O-X - 100 - kΩ VSENSE INPUT VSENSE under-voltage threshold (Not active in LP Modes) Low Threshold High threshold Hysteresis VSENSE_TH 8.1 0.1 8.6 0.25 9.0 9.1 0.5 V Input resistor to GND. In all modes except in LP Modes. (Guaranteed by design). RVSENSE - 125 - kΩ Notes 19. Reset must be kept low noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33903/4/5 STATIC ELECTRICAL CHARACTERISTICS ANALOG MUX OUTPUT Output Voltage Range, with external resistor to GND >2.0 kΩ VOUT_MAX 0.0 - VDD - 0.5 V Internal pull-down resistor for regulator output current sense RMI 0.8 1.9 2.8 kΩ External capacitor at MUX OUTPUT(20) (Guaranteed by design) CMUX - - 1.0 nF Chip temperature sensor coefficient (Guaranteed by design and device characterization) VDD = 5.0 V VDD = 3.3 V TEMP-COEFF 13.2 13.9 14.6 mv/°C Chip temperature: MUX-OUT voltage VDD = 5.0 V, TA = 125 °C VDD = 3.3 V, TA = 125 °C VTEMP 3.6 2.45 3.75 2.58 3.9 2.65 V Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) TA = -40 °C, VDD = 5.0 V TA = 25 °C, VDD = 5.0 V TA = -40 °C, VDD = 3.3 V TA = 25 °C, VDD = 3.3 V VTEMP(GD) 0.12 1.5 0.07 1.08 0.30 1.65 0.19 1.14 0.48 1.8 0.3 1.2 V Gain for VSENSE, with external 1.0 k 1% resistor VDD = 5.0 V VDD = 3.3 V VSENSE GAIN 5.42 8.1 5.48 8.2 5.54 8.3 Offset for VSENSE, with external 1.0 k 1% resistor VSENSE OFFSET -20 - 20 mV Divider ratio for VSUP/1 VDD = 5.0 V VDD = 3.3 V VSUP/1 RATIO 5.335 7.95 5.5 8.18 5.665 8.45 Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: VDD = 5.0 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1) VDD = 5.0 V, (Gain, MUX-OUT register bit 3 set to 0) VDD = 3.3 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to 1) VDD = 3.3 V, (Gain, MUX-OUT register bit 3 set to 0) VI/O RATIO 3.8 5.6 4.0 2.0 5.8 1.3 4.2 6.2 Internal reference voltage VDD = 5.0 V VDD = 3.3 V VREF 2.45 1.64 2.5 1.67 2.55 1.7 V Current ratio between VDD output & IOUT at MUX-OUT (IOUT at MUX-OUT = IDD out / IDD_RATIO) At IOUT = 50 mA I_OUT from 25 to 150 mA IDD_RATIO 62.5 115 117 SAFE OUTPUT SAFE low level, at I = 500 μA VOL 0.0 0.2 1.0 V Safe leakage current (VDD low, or device unpowered). VSAFE 0 to 28 V. ISAFE-IN - 0.0 1.0 μA Notes 20. When C is higher than CMUX, a serial resistor must be inserted noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS INTERRUPT Output low voltage, IOUT = 1.5 mA VOL - 0.2 1.0 V Pull-up resistor RPU 6.5 10 14 kΩ Output high level in LP VDD ON Mode (Guaranteed by design) VOH-LPVDDON 3.9 4.3 V Leakage current INT voltage = 10 V (to allow high-voltage on MCU INT pin) VMAX - 35 100 μA Sink current, VINT > 5.0 V, INT low state I SINK 2.5 6.0 10 mA MISO, MOSI, SCLK, CS PINS Output low voltage, IOUT = 1.5 mA (MISO) VOL - - 1.0 V Output high voltage, IOUT = -0.25 mA (MISO) VOH VDD -0.9 - V Input low voltage (MOSI, SCLK,CS) VIL - - 0.3 x VDD V Input high voltage (MOSI, SCLK,CS) VIH 0.7 x VDD - - V Tri-state leakage current (MISO) IHZ -2.0 - 2.0 μA Pull-up current (CS) IPU 200 370 500 μA CAN LOGIC INPUT PINS (TXD) High Level Input Voltage VIH 0.7 x VDD - VDD + 0.3 V Low Level Input Voltage VIL -0.3 - 0.3 x VDD V Pull-up Current, TXD, VIN = 0 V VDD =5.0 V VDD =3.3 V IPDWN -850 -500 -650 -250 -200 -175 µA CAN DATA OUTPUT PINS (RXD) Low Level Output Voltage IRXD = 5.0 mA VOUTLOW 0.0 - 0.3 x VDD V High Level Output Voltage IRX = -3.0 mA VOUTHIGH 0.7 x VDD - VDD V High Level Output Current VRXD = VDD - 0.4 V IOUTHIGH 2.5 5.0 9.0 mA Low Level Input Current VRXD = 0.4 V IOUTLOW 2.5 5.0 9.0 mA noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 33903/4/5 STATIC ELECTRICAL CHARACTERISTICS CAN OUTPUT PINS (CANH, CANL) Bus pins common mode voltage for full functionality VCOM -12 - 12 V Differential input voltage threshold VCANH-VCANL 500 - 900 mV Differential input hysteresis VDIFF-HYST 50 - - mV Input resistance RIN 5.0 - 50 kΩ Differential input resistance RIN-DIFF 10 - 100 kΩ Input resistance matching RIN-MATCH -3.0 0.0 3.0 % CANH output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state VCANH 2.75 2.0 3.5 2.5 4.5 3.0 V CANL output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state VCANL 0.5 2.0 1.5 2.5 2.25 3.0 V Differential output voltage (45 Ω < RBUS < 65 Ω) TXD dominant state TXD recessive state VOH-VOL 1.5 -0.5 2.0 0.0 3.0 0.05 V CAN H output current capability - Dominant state ICANH - - -30 mA CAN L output current capability - Dominant state ICANL 30 - - mA CANL over-current detection - Error reported in register ICANL-OC 75 120 195 mA CANH over-current detection - Error reported in register ICANH-OC -195 -120 -75 mA CANH, CANL input resistance to GND, device supplied, CAN in Sleep Mode, V_CANH, V_CANL from 0 to 5.0 V RINSLEEP 5.0 - 50 kΩ CANL, CANH output voltage in LP VDD OFF and LP VDD ON modes VCANLP -0.1 0.0 0.1 V CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device unpowered (VSUP, VDD, 5V-CAN: open).(21) ICAN-UN_SUP1 - 3.0 10 µA CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device unpowered (VSUP, VDD, 5V-CAN: open).(21) ICAN-UN_SUP2 - - 250 µA Differential voltage for recessive bit detection in LP Mode(22) VDIFF-R-LP - - 0.4 V Differential voltage for dominant bit detection in LP Mode(22) VDIFF-D-LP 1.15 - - V CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND detection threshold VLG 1.6 1.75 2.0 V CANH to GND detection threshold VHG 1.6 1.75 2.0 V CANL to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V VLVB - VSUP -2.0 - V CANH to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V VHVB - VSUP -2.0 - V CANL to VDD detection threshold VL5 4.0 VDD -0.43 - V CANH to VDD detection threshold VH5 4.0 VDD -0.43 - V Notes 21. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization. 22. Guaranteed by design and device characterization. noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS SPLIT Output voltage Loaded condition ISPLIT = ±500 µA Unloaded condition Rmeasure > 1.0 MΩ VSPLIT 0.3 x VDD 0.45 x VDD 0.5 x VDD 0.5 x VDD 0.7 x VDD 0.55 x VDD V Leakage current -12 V < VSPLIT < +12 V -22 to -12 V < VSPLIT < +12 to +35 V ILSPLIT 0.0 5.0 200 µA LIN TERMINALS (LIN-T/1, LIN-T2) LIN-T1, LIN-T2, HS switch drop @ I = -20 mA, VSUP > 10.5 V VLT_HSDRP - 1.0 1.4 V LIN1 & LIN2 33903D/5D PIN - LIN 33903S/5S PIN (Parameters guaranteed for VSUP/1, VSUP2 7.0 V ≤ VSUP ≤ 18 V) Operating Voltage Range VBAT 8.0 - 18 V Supply Voltage Range VSUP 7.0 - 18 V Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V IBUS_LIM 40 90 200 mA Input Leakage Current at the receiver Driver off; VBUS = 0 V; VBAT = 12 V IBUS_PAS_DOM -1.0 - - mA Leakage Output Current to GND Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT IBUS_PAS_REC - - 20 µA Control unit disconnected from ground (Loss of local ground must not affect communication in the residual network) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V (Guaranteed by design) IBUS_NO_GND -1.0 - 1.0 mA VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition). (Guaranteed by design) IBUSNO_BAT - - 100 µA Receiver Dominant State VBUSDOM - - 0.4 VSUP Receiver Recessive State VBUSREC 0.6 - - VSUP Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VBUS_CNT 0.475 0.5 0.525 VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VHYS - - 0.175 VSUP LIN Wake-up threshold from LP VDD ON or LP VDD OFF Mode VBUSWU - 5.3 5.8 V LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 kΩ Over-temperature Shutdown (Guaranteed by design) TLINSD 140 160 180 °C Over-temperature Shutdown Hysteresis (Guaranteed by design) TLINSD_HYS - 10 - °C noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33903/4/5 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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DYNAMIC ELECTRICAL CHARACTERISTICS INTERRUPT INT pulse duration (refer to SPI for selection. Guaranteed by design) short (25 to 125 °C) short (-40 °C) long (25 to 125 °C) long (-40 °C) tINT-PULSE 100 100 130 140 μs STATE DIGRAM TIMINGS Delay for SPI Timer A, Timer B or Timer C write command after entering Normal Mode (No command should occur within tD_NM. tD_NM delay definition: from CS rising edge of “Go to Normal Mode (i.e. 0x5A00)” command to CS falling edge of “Timer write” command) tD_NM 60 - - μs Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense period and active time, Cyclic Interrupt period, LP Mode over-current (unless otherwise noted)(26) tTIMING-ACC -10 - 10 % CAN DYNAMIC CHARACTERISTICS TXD Dominant State Timeout tDOUT 300 600 1000 µs Bus dominant clamping detection tDOM 300 600 1000 µs Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate) tLRD 60 120 210 ns Propagation delay TXD to CAN, recessive to dominant tTRD - 70 110 ns Propagation delay CAN to RXD, recessive to dominant tRRD - 45 140 ns Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate) tLDR 100 120 200 ns Propagation delay TXD to CAN, dominant to recessive tTDR - 75 150 ns Propagation delay CAN to RXD, dominant to recessive tRDR - 50 140 ns Loop time TXD to RXD, Medium Slew Rate (Selected by SPI) Recessive to Dominant Dominant to Recessive tLOOP-MSL 200 200 ns Loop time TXD to RXD, Slow Slew Rate (Selected by SPI) Recessive to Dominant Dominant to Recessive tLOOP-SSL 300 300 ns CAN Wake-Up filter time, single dominant pulse detection(23) (See Figure 37) tCAN-WU1-F 0.5 2.0 5.0 μs CAN Wake-Up filter time, 3 dominant pulses detection(24) tCAN-WU3-F 300 - - ns CAN Wake-Up filter time, 3 dominant pulses detection timeout(25) (See Figure 38) tCAN-WU3-TO - - 120 μs Notes 23. No Wake-Up for single pulse shorter than t CAN-WU1 min. Wake-up for single pulse longer than tCAN-WU1 max. 24. Each pulse should be greater than t CAN-WU3-F min. Guaranteed by design, and device characterization. 25. The 3 pulses should occur within t CAN-WU3-TO. Guaranteed by design, and device characterization. 26. Guaranteed by design. values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 29 33903/4/5 DYNAMIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION Duty Cycle 1: THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V 0.396 - - Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.581 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V 0.417 - - Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.590 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) SRFAST - 20 - V / μs LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS Propagation Delay and Symmetry (See Figure 20, page 31 and Figure 21, page 32) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR t REC_PD t REC_SYM - 2.0 4.2 6.0 2.0 μs Bus Wake-up Deglitcher (LP VDD OFF and LP VDD ON modes) (See Figure 22, page 31 for LP VDD OFF Mode and Figure 23, page 32 for LP Mode) t PROPWL 42 70 95 μs Bus Wake-up Event Reported From LP VDD OFF Mode From LP VDD ON Mode t WAKE_LPVDD OFF t WAKE_LPVDD ON 1.0 1500 μs TXD Permanent Dominant State Delay (Guaranteed by design) t TXDDOM 0.65 1.0 1.35 s values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

Undefined Don‚ÄöÐÑÐ¥ Di n Don‚ÄöÐÑÐ¥ tLEAD tSIHtSISU tLAG tPCLK tWCLKH tWCLKL tVALID Do n tSODIS CS SCLK MOSI MISO tSOEN Figure 16. SPI Timings Figure 17. CAN Signal Propagation Loop Delay TXD to RXD Figure 18. CAN Signal Propagation Delays TXD to CAN and CAN to RXD

Analog Integrated Circuit Device Data Freescale Semiconductor 31 33903/4/5 22 ¬¨ 10 ¬¨ SPLITGND TXD RXD Signal generator All pins are not shown RBUS 15 pF CBus 100 pF60 Ω 100 nF

5 V_CAN

Figure 19. Test Circuit for CAN Timing Characteristics Figure 20. LIN Timing Measurements for Normal Slew Rate

tBUS_DOM(MAX) tBUS_REC(MIN) tREC_PDF(1) 77.8% VSUP 38.9% VSUP 61.6% VSUP 25.1% VSUP tBUS_REC(MAX) VLIN_REC tBUS_DOM(MIN) RXD Output of receiving Node 1 Output of receiving Node 2 THREC(MAX) THDOM(MAX) THREC(MIN) THDOM(MIN) Thresholds of receiving node 1 Thresholds of receiving node 2 tREC_PDR(1) tREC_PDF(2)tREC_PDR(2) Analog Integrated Circuit Device Data

32 Freescale Semiconductor

Figure 21. LIN Timing Measurements for Slow Slew Rate Figure 22. LIN Wake-up LP VDD OFF Mode Timing

VLIN_REC TT Dominant level 0.4 V V IRQ stays low until SPI reading command PROPWL WAKE BUSWU SUP Analog Integrated Circuit Device Data Freescale Semiconductor 33 33903/4/5 Figure 23. LIN Wake-up LP VDD ON Mode Timing

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

The MC33903_4_5 is the second generation of System Basis Chip, combining: - Advanced power management unit for the MCU, the integrated CAN interface and for the additional ICs such as sensors, CAN transceiver. - Built in enhanced high speed CAN interface (ISO11898- 2 and -5), with local and bus failure diagnostic, protection and fail-safe operation mode. - Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection. - Innovative hardware configurable fail-safe state machine solution. - Multiple LP Modes, with low current consumption. - Family concept with pin compatibility; with and without LIN interface devices. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY (VSUP/1 AND VSUP2) Note: VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. VSUP1 is the input pin for the internal supply and the VDD regulator. VSUP2 is the input pin for the 5 V-CAN regulator, LIN’s interfaces and I/O functions. The VSUP block includes over and under-voltage detections which can generate interrupt. The device includes a loss of battery detector connected to VSUP/1. Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset). VDD VOLTAGE REGULATOR (VDD) The regulator has two main modes of operation (Normal Mode and LP Mode). It can operate with or without an external PNP transistor. In Normal Mode, without external PNP, the max DC capability is 150 mA. Current limitation, temperature pre- warning flag and over-temperature shutdown features are included. When VDD is turned ON, rise time from 0 to 5.0 V is controlled. Output voltage is 5.0 V. A 3.3 V option is available via dedicated part number. If current higher than 150 mA is required, an external PNP transistor must be connected to VE (PNP emitter) and VB (PNP base) pins, in order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See External Transistor Q1 (VE and VB). The PNP can be used even if current is less than 150 mA, depending upon ambient temperature, maximum supply and thermal resistance. Typically, above 100-200 mA, an external ballast transistor is recommended. VDD REGULATOR IN LP MODE When the device is set in LP VDD ON Mode, the VDD regulator is able to supply the MCU with a DC current below typically 1.5 mA (LP-ITH). Transient current can also be supplied up to a tenth of a mA. Current in excess of 1.5 mA is detected, and this event is managed by the device logic (Wake-Up detection, timer start for over-current duration monitoring or watchdog refresh). EXTERNAL TRANSISTOR Q1 (VE AND VB) The device has a dedicated circuit to allow usage of an external “P” type transistor, with the objective to share the power dissipation between the internal transistor of the VDD regulator and the external transistor. The recommended bipolar PNP transistor is MJD42C or BCP52-16. When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI. The device is able to operate without an external transistor. In this case, the VE and VB pins must remain open.

5 V-CAN VOLTAGE REGULATOR FOR CAN AND

This regulator is supplied from the VSUP/2 pin. A capacitor is required at 5 V-CAN pin. Analog MUX and part of the LIN interfaces are supplied from 5 V-CAN. Consequently, the

5 V-CAN must be ON in order to have Analog MUX operating

and to have the LIN interface operating in TXD/RXD Mode. The 5 V-CAN regulator is OFF by default and must be turned ON by SPI. In Debug Mode, the 5 V-CAN is ON by default. V AUXILIARY OUTPUT, 5.0 AND 3.3 V SELECTABLE (VB-AUX, VC-AUX, AND VCAUX) - The VAUX block is used to provide an auxiliary voltage output, 5.0 or 3.3 V, selectable by the SPI. It uses an external PNP pass transistor for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16. An over-current and under-voltage detectors are provided.

Analog Integrated Circuit Device Data Freescale Semiconductor 35 33903/4/5 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and over-current information will disable VAUX, and are reported in the SPI and can generate INT. VAUX is OFF by default and must be turned ON by the SPI. UNDER-VOLTAGE RESET AND RESET FUNCTION (RST) The RESET pin is an open drain structure with an internal pull-up resistor. The LS driver has limited current capability when asserted low, in order to tolerate a short to 5.0 V. The RESET pin voltage is monitored in order to detect failure (e.g. RESET pin shorted to 5.0 V or GND). The RESET pin reports an under-voltage condition to the MCU at the VDD pin, as well as failure in the watchdog refresh operation. VDD under-voltage reset also operates in LP VDD ON Mode. Two VDD under-voltage thresholds are included. The upper (typically 4.65 V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected by the SPI. When “RST-TH2-5“is selected, in Normal Mode, an INT is asserted when VDD falls below “RST-TH1-5“, then, when VDD falls below “RST-TH2-5” a Reset will occur. This will allow the MCU to operate in a degraded mode (i.e., with 4.0 V VDD). I/O PINS (I/O-0: I/O-3) I/Os are configurable input/output pins. They can be used for small loads or to drive external transistors. When used as output drivers, the I/Os are either a HS or LS type. They can also be set to high-impedance. I/Os are controlled by the SPI and at power on, the I/Os are set as inputs. They include over-load protection by temperature or excess of a voltage drop. When I/O-0/-1/-2/-3 voltage is greater than VSUP/2 voltage, the leakage current (II/O_LEAK) parameter is not applicable

• I/O-0 and I/O-1 will have current flowing into the device through three diodes limited by an 80 kOhm resistor (in series).
• I/O-2 and I/O-3 will have unlimited current flowing into the device through one diode. In LP Mode, the state of the I/O can be turned ON or OFF, with extremely low power consumption (except when there is a load). Protection is disabled in LP Mode. When cyclic sense is used, I/O-0 is the HS/LS switch, I/O- 1, -2 and -3 are the wake inputs. I/O-2 and I/O-3 pins share the LIN Master pin function. VSENSE INPUT (VSENSE) This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to GND. It incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to measure the V SENSE voltage via the MUX-OUT pin. MUX-OUTPUT (MUXOUT) The MUX-OUT pin (Figure 24) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUX- OUT is selected via the SPI, from one of the following functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V reference, die temperature sensor, VDD current copy. Voltage divider or amplifier is inserted in the chain, as shown in Figure 24. For the VDD current copy, a resistor must be added to the MUX-OUT pin, to convert current into voltage. Device includes an internal 2.0 k resistor selectable by the SPI. Voltage range at MUX-OUT is from GND to VDD. It is automatically limited to VDD (max 3.3 V for 3.3 V part numbers). The MUX-OUT buffer is supplied from 5 V-CAN regulator, so the 5 V-CAN regulator must be ON in order to have: 1) MUX-OUT functionality and 2) SPI selection of the analog function. If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND and the SPI command that selects one of the analog inputs is ignored. Delay must be respected between SPI commands for 5 V- CAN turned ON and SPI to select MUX-OUT function. The delay depends mainly upon the 5 V-CAN capacitor and load on 5 V-CAN. The delay can be estimated using the following formula: delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN. C = cap at 5 V-CAN regulator, U = 5.0 V, I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator (parameter 5 V-C ILIM).

36 Freescale Semiconductor

Figure 24. Analog Multiplexer Block Diagram hardware and software routines (i.e. SPI commands). ot be configured via the resistor connected at DBG pin. SBC, once a failure has been detected. pulse and pulse duration are selected by SPI.

Analog Integrated Circuit Device Data Freescale Semiconductor 37 33903/4/5 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION INT has an internal pull-up structure to VDD. In LP VDD ON Mode, a diode is inserted in series with the pull-up, so the high level is slightly lower than in other modes. CANH, CANL, SPLIT, RXD, TXD These are the pins of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is provided in the document. LIN, LIN-T, TXDL AND RXDL These are the pins of the LIN physical interface. Device contains zero, one or two LIN interfaces. The MC33903 and MC33904 do not have a LIN interface. However, the MC33903S/5S (S = Single) and MC33903D/5D (D=Dual) contain 1 and 2 LIN interfaces, respectively. LIN, LIN1 and LIN2 pins are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TXD, TXD-L1 and TXD-L2 and RXD, RXD-L1 and RXD-L2 pins. The device also includes one or two HS switches to VSUP/ 2 pin which can be used as a LIN master termination switch. Pins LINT, LINT-1 and LINT-2 pins are the same as I/O-2 and I/O-3.

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION The device has several operation modes. The transitions and conditions to enter or leave each mode are illustrated in the state diagram. INIT RESET This mode is automatically entered after the device is “powered on”. In this mode, the RST pin is asserted low, for a duration of typically 1.0 ms. Control bits and flags are “set” to their default reset condition. The BATFAIL is set to indicate the device is coming from an unpowered condition, and all previous device configurations are lost and “reset” the default value. The duration of the INIT reset is typically 1.0 ms. INIT reset mode is also entered from INIT Mode if the expected SPI command does not occur in due time (Ref. INIT Mode), and if the device is not in the debug mode. INIT This mode is automatically entered from the INIT Reset Mode. In this mode, the device must be configured via SPI within a time of 256 ms max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be, and can only be configured during INIT Mode. Other registers can be written in this and other modes. Once the INIT register configuration is done, a SPI Watchdog Refresh command must be sent in order to set the device into Normal Mode. If the SPI watchdog refresh does not occur within the 256 ms period, the device will return into INIT Reset Mode for typically 1.0 ms, and then re enter into INIT Mode. Register read operation is allowed in INIT Mode to collect device status or to read back the INIT register configuration. When INIT Mode is left by a SPI watchdog refresh command, it is only possible to re-enter the INIT Mode using a secured SPI command. In INIT Mode, the CAN, LIN1, LIN2, VAUX, I/O_x and Analog MUX functions are not operating. The 5 V-CAN is also not operating, except if the Debug Mode is detected. RESET In this mode, the RST pin is asserted low. Reset Mode is entered from Normal Mode, Normal Request Mode, LP VDD on Mode and from the Flash Mode when the watchdog is not triggered, or if a VDD low condition is detected. The duration of reset is typically 1.0 ms by default. You can define a longer Reset pulse activation only when the Reset Mode is entered following a V DD low condition. Reset pulse is always 1.0 ms, when reset mode is entered due to wrong watchdog refresh command. Reset Mode can be entered via the secured SPI command. NORMAL REQUEST This mode is automatically entered after RESET Mode, or after a Wake-Up from LP VDD ON Mode. A watchdog refresh SPI command is necessary to transition to NORMAL Mode. The duration of the Normal request mode is 256 ms when Normal Request Mode is entered after RESET Mode. Different durations can be selected by SPI when normal request is entered from LP VDD ON Mode. If the watchdog refresh SPI command does not occur within the 256 ms (or the shorter user defined time out), then the device will enter into RESET Mode for a duration of typically 1.0 ms. Note: in init reset, init, reset and normal request modes as well as in LP Modes, the VDD external PNP is disabled. NORMAL In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request Mode, or from INIT Mode. During Normal Mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. When an incorrect or missing watchdog refresh command is initiated, the device will enter into Reset Mode. While in Normal Mode, the device can be set to LP Modes (LP VDD ON or LP VDD OFF) using the SPI command. Dedicated, secured SPI commands must be used to enter from Normal Mode to Reset Mode, INIT Mode or Flash Mode. FLASH In this mode, the software watchdog period is extended up to typically 32 seconds. This allow programming of the MCU flash memory while minimizing the software over head to refresh the watchdog. The flash mode is entered by Secured SPI command and is left by SPI command. Device will enter into Reset Mode. When an incorrect or missing watchdog refresh command device will enter into Reset Mode. An interrupt can be generated at 50% of the watchdog period. CAN interface operates in Flash Mode to allow flash via CAN bus, inside the vehicle. DEBUG Debug is a special operation mode of the device which allows for easy software and hardware debugging. The debug operation is detected after power up if the DBG pin is set to 8.0 to 10 V range. When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT Mode, watchdog refresh of Normal Mode and Flash Mode, Normal Request time out (256 ms or user defined value) are not operating and will not lead to transition into INIT reset or Reset Mode. When the device is in Debug Mode, the SPI command can be sent without any time constraints with respect to the watchdog operation and the MCU program can be “halted” or “paused” to verify proper operation.

Analog Integrated Circuit Device Data Freescale Semiconductor 39 33903/4/5 FUNCTIONAL DEVICE OPERATION LP MODES Debug can be left by removing 8 to 10 V from the DEBUG pin, or by the SPI command (Ref. to MODE register). The 5 V-CAN regulator is ON by default in Debug Mode. LP MODES The device has two main LP modes: LP Mode with VDD OFF, and LP Mode with VDD ON. Prior to entering into LP Mode, I/O and CAN Wake-Up flags must be cleared (Ref. to mode register). If the Wake-Up flags are not cleared, the device will not enter into LP Mode. In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared, in order to meet the LP current consumption specification. LP - VDD OFF In this mode, VDD is turned OFF and the MCU connected to VDD is unsupplied. This mode is entered using SPI. It can also be entered by an automatic transition due to fail safe management. 5 V-CAN and VAUX regulators are also turned OFF. When the device is in LP VDD OFF Mode, it monitors external events to Wake-Up and leave the LP Mode. The Wake-Up events can occur from:

• C A N
• LIN interface, depending upon device part number
• Expiration of an internal timer
• I/O-0, and I/O-1 inputs, and depending upon device part number and configuration, I/O-2 and/or -3 input
• Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense of I/O-2 and -3 input, associated by I/O-0 activation When a Wake-Up event is detected, the device enters into Reset Mode and then into Normal Request Mode. The Wake- Up sources are reported to the device SPI registers. In summary, a Wake-Up event from LP VDD OFF leads to the VDD regulator turned ON, and the MCU operation restart. LP - VDD ON In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to 100 μA or a few mA, as the ECU is in reduced power operation mode. During this mode, the 5 V-CAN and VAUX regulators are OFF. The optional external PNP at VDD will also be automatically disabled when entering this mode. The same Wake-Up events as in LP VDD OFF Mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP VDD on Mode. In addition, two additional Wake-Up conditions are available.
• Dedicated SPI command. When device is in LP VDD ON Mode, the Wake-Up by SPI command uses a write to “Normal Request Mode”, 0x5C10.
• Output current from VDD exceeding L P-ITH threshold. In LP VDD ON Mode, the device is able to source several tenths of mA DC. The current source capability can be time limited, by a selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceed the output current threshold typically 1.5 mA. This allows for instance, a periodic activation of the MCU, while the device remains in LP VDD on Mode. If the duration exceed the selected time (ex 32 ms), the device will detect a Wake-Up. Wake-up events are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation. Watchdog Function in LP VDD ON Mode It is possible to enable the watchdog function in LP VDD ON Mode. In this case, the principle is timeout. Refresh of the watchdog is done either by:
• a dedicated SPI command (different from any other SPI command or simple CS activation which would Wake- Up - Ref. to the previous paragraph)
• or by a temporary (less than 32 ms max) VDD over current Wake-Up (IDD > 1.5 mA typically). As long as the watchdog refresh occurs, the device remains in LP VDD on Mode. Mode Transitions Mode transitions are either done automatically (i.e. after a timeout expired or voltage conditions), or via a SPI command, or by an external event such as a Wake-Up. Some mode changes are performed using the Secured SPI commands.

40 Freescale Semiconductor

(4) VDD external PNP is disable in all mode except Normal and Flash modes. Figure 25. State Diagram

Analog Integrated Circuit Device Data Freescale Semiconductor 41 33903/4/5 FUNCTIONAL DEVICE OPERATION MODE CHANGE MODE CHANGE “SECURED SPI” DESCRIPTION: A request is done by a SPI command, the device provide on MISO an unpredictable “random code”. Software must perform a logical change on the code and return it to the device with the new SPI command to perform the desired action. The “random code” is different at every exercise of the secured procedure and can be read back at any time. The secured SPI uses the Special MODE register for the following transitions: - from Normal Mode to INT Mode - from Normal Mode to Flash Mode - from Normal Mode to Reset Mode (reset request). “Random code” is also used when the “advance watchdog” is selected. CHANGING OF DEVICE CRITICAL PARAMETERS Some critical parameters are configured one time at device power on only, while the batfail flag is set in the INIT Mode. If a change is required while device is no longer in INIT Mode, device must be set back in INIT Mode using the “SPI secure” procedure. WATCHDOG OPERATION IN NORMAL REQUEST MODE In Normal Request Mode, the device expects to receive a watchdog configuration before the end of the normal request time out period. This period is reset to a long (256 ms) after power on and when BATFAIL is set. The device can be configured to a different (shorter) time out period which can be used after Wake-Up from LP VDD on Mode. After a software watchdog reset, the value is restored to 256 ms, in order to allow for a complete software initialization, similar to a device power up. In Normal Request Mode the watchdog operation is “timeout” only and can be triggered/observed any time within the period. WATCHDOG TYPE SELECTION Three types of watchdog operation can be used: - Window watchdog (default) - Timeout operation - Advanced The selection of watchdog is performed in INIT Mode. This is done after device power up and when the BATFAIL flag is set. The Watchdog configuration is done via the SPI, then the Watchdog Mode selection content is locked and can be changed only via a secured SPI procedure. Window Watchdog Operation The window watchdog is available in Normal Mode only. The watchdog period selection can be kept (SPI is selectable in INIT Mode), while the device enters into LP V DD ON Mode. The watchdog period is reset to the default long period after BATFAIL. The period and the refresh of watchdog are done by the SPI. A refresh must be done in the open window of the period, which starts at 50% of the selected period and ends at the end of the period. If the watchdog is triggered before 50%, or not triggered before end of period, a reset has occurred. The device enters into Reset Mode. Watchdog in Debug Mode When the device is in Debug Mode (entered via the DBG pin), the watchdog continues to operate but does not affect the device operation by asserting a reset. For the user, operation appears without the watchdog. When Debug Mode is set by software (SPI Mode reg), the watchdog period starts at the end of the SPI command. When Debug Mode is set by hardware (DBG pin below 8- 10 V), the device enters into Reset Mode. Watchdog in Flash Mode During Flash Mode, watchdog can be set to a long timeout period. Watchdog is timeout only and an INT pulse can be generated at 50% of the time window. Advance Watchdog Operation When the Advance watchdog is selected (at INIT Mode), the refresh of the watchdog must be done using a random number and with 1, 2, or 4 SPI commands. The number for the SPI command is selected in INIT Mode. The software must read a random byte from the device, and then must return the random byte inverted to clear the watchdog. The random byte write can be performed in 1, 2, or 4 different SPI commands. If one command is selected, all eight bits are written at once. If two commands are selected, the first write command must include four of the eight bits of the inverted random byte. The second command must include the next four bits. This completes the watchdog refresh. If four commands are selected, the first write command must include two of the eight bits of the inverted random byte. The second command must include the next two bits, the 3rd command must include the next two, and the last command,

Analog Integrated Circuit Device Data

42 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION WATCHDOG OPERATION must include the last two. This completes the watchdog refresh. When multiple writes are used, the most significant bits are sent first. The latest SPI command needs to be done inside the open window time frame, if window watchdog is selected. DETAIL SPI OPERATION AND SPI COMMANDS FOR ALL WATCHDOG TYPES. All SPI commands and examples do not use parity functions. In INIT Mode, the watchdog type (window, timeout, advance and number of SPI commands) is selected using the register Init watchdog, bits 1, 2 and 3. The watchdog period is selected using the TIM_A register. The watchdog period selection can also be done in Normal Mode or in Normal Request Mode. Transition from INIT Mode to Normal Mode or from Normal Request Mode to Normal Mode is done using a single watchdog refresh command (SPI 0x 5A00). While in Normal Mode, the Watchdog Refresh Command depends upon the watchdog type selected in INIT Mode. They are detailed in the paragraph below: Simple Watchdog The Refresh command is 0x5A00. It can be send any time within the watchdog period, if the timeout watchdog operation is selected (INIT-watchdog register, bit 1 WD N/Win = 0). It must be send in the open window (second half of the period) if the Window Watchdog operation was selected (INIT- watchdog register, bit 1 WD N/Win = 1). Advance Watchdog The first time the device enters into Normal Mode (entry on Normal Mode using the 0x5A00 command), Random (RNDM) code must be read using the SPI command, 0x1B00. The device returns on MISO second byte the RNDM code. The full 16 bits MISO is called 0x XXRD. RD is the complement of the RD byte. Advance Watchdog, Refresh by 1 SPI Command The refresh command is 0x5ARD. During each refresh command, the device will return on MISO, a new Random Code. This new Random Code must be inverted and send along with the next refresh command. It must be done in an open window, if the Window operation was selected. Advance Watchdog, Refresh by two SPI Commands: The refresh command is split in two SPI commands. The first partial refresh command is 0x5Aw1, and the second is 0x5Aw2. Byte w1 contains the first four inverted bits of the RD byte plus the last four bits equal to zero. Byte w2 contains four bits equal to zero plus the last four inverted bits of the RD byte. During this second refresh command the device returns on MISO a new Random Code. This new random code must be inverted and send along with the next two refresh commands and so on. The second command must be done in an open window if the Window operation was selected. Advance Watchdog, Refresh by four SPI Commands The refresh command is split into four SPI commands. The first partial refresh command is 0x5Aw1, the second is 0x5Aw2, the third is 0x5Aw3, and the last is 0x5Aw4. Byte w1 contains the first two inverted bits of the RD byte, plus the last six bits equal to zero. Byte w2 contains two bits equal to zero, plus the next two inverted bits of the RD byte, plus four bits equal to zero. Byte w3 contains four bits equal to zero, plus the next two inverted bits of the RD byte, plus two bits equal to zero. Byte w4 contains six bits equal to zero, plus the next two inverted bits of the RD byte. During this fourth refresh command, the device will return, on MISO, a new Random Code. This new Random Code must be inverted and send along with the next four refresh commands. The fourth command must be done in an open window if the Window operation was selected. PROPER RESPONSE TO INT During a device detect upon an INT, the software handles the INT in a timely manner: Access of the INT register is done within two watchdog periods. This feature must be enabled by SPI using the INIT watchdog register bit 7.

Table 6. Device Block Operation for Each State internal 30k pull-up active.

1. With limited current capability
2. 5 V-CAN is ON in Debug Mode.
3. I/O-0 and I/O-1, configured as an output high-side switch and ON in Normal Mode w ill remain ON in RESET, INIT or Normal
4. I/O-0, configured as an output low-side switch and ON in Nor mal mode will turn OFF when entering Reset mode, resume
5. I/O-1, configured as an output low-side switch and ON in No rmal mode will remain ON in RESET, INIT or Normal Request.

The 5 V-CAN default is ON when the device is powered-up and set in Deb ug Mode. It is fully controllable via the SPI command.

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ILLUSTRATION OF DEVICE MODE TRANSITIONS. ILLUSTRATION OF DEVICE MODE TRANSITIONS. Figure 26. Power Up Normal and LP Modes

ILLUSTRATION OF DEVICE MODE TRANSITIONS. Figure 27. Wake-up from LP Modes

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Wake-Up from either LP Mode. the contact pull-up resistor. sense period from 3.0 to 512 ms (selection in timer B). of I/O-0 prior to entering in LP Mode. one of them is high, the device will detect a Wake-Up. contact switches are closed. In LP Mode, 1 contact switch is open. High level is detected on I/O-x, and device wakes up. Figure 28. Cyclic Sense Operation - Switch to GND, Wake-up by Open Switch

Mode, the device will generate a periodic INT pulse. end of the next INT period in order to keep the process going. cyclic Interrupt period (SPI command without parity bit)]. MISO second byte the RNDM code (MISO bit 0-7). These commands can occur at any time within the period. acknowledge process must start only after the 1st INT pulse. enter into Normal Request Mode. Figure 29. Cyclic Interrupt Operation

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the Crank bit and the two VDD under-voltage reset thresholds. enabled when VSUP/1 is above VSUP TH 1 parameters. Figure 30. VDD Start-up Versus VSUP/1 Tramp VDD under-voltage reset selection. Bit 0 = 0 is the default state fo r this bit. “VSUP_TH1”, VDD is turned OFF. BATFAIL. This occurs for a VSUP/1 approx 3.0 V.

Figure 31. VDD Behavior During VSUP/1 Ramp Down

Analog Integrated Circuit Device Data

50 Freescale Semiconductor

BEHAVIOR AT POWER UP AND POWER DOWN FAIL SAFE OPERATION OVERVIEW Fail Safe Mode is entered when specific fail conditions occur. The “Safe state” condition is defined by the resistor connected at the DGB pin. Safe Mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin. Exiting the safe state is always possible by a Wake-Up even t: in the safe state, the device can automatically be awakened by CAN and I/O (if configured as inputs). Upon Wake-Up, the device operation is resumed: enter in Reset Mode. FAIL SAFE FUNCTIONALITY Upon dedicated event or issue detected at a device pin (i.e. RESET), the Safe Mode can be entered. In this mode, the SAFE pin is active low.

Description

Upon activation of the SAFE pin, and if the failure cond ition that make the SAFE pin activated have not recovered, the device can help to reduce ECU consumption, assuming that the MCU is not able to set the whole ECU in LP Mode. Two main cases are available: Mode A Upon SAFE activation, the MCU remains powered (V DD stays ON), until the failure condition recovers (i.e. S/W is able to properly control the devic e and properly refresh the watchdog). Modes B1, B2 and B3 Upon SAFE activation, the system continues to monitor external event, and disable the MCU supply (turn VDD OFF). The external events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3. Note: no CAN traffic indicates that the ECU of the vehicle are no longer active, thus that the car is being parked and stopped. The I/O low level detection can also indicate that the vehicle is being shutdown, if the I/O-1 pin is connected for instance to a switched battery signal (ignition key on/off signal). The selection of the monitored events is done by har dware, via the resistor connected at DBG pin, but can be over written by software, via a specific SPI command. By default, after power up the device detect the resistor valu e at DBG pin (upon transition from INIT to Normal Mode), and, if no specific SPI command related to Debug resistor change is send, operates according to the detected resistor. The INIT MISC register allow you to verify and change the de vice behavior, to either confirm or change the hardware selected behavior. Device will then operate according to the SAFE Mode configured by the SPI. Table 7 illustrates the complete options available: Table 7. Fail Safe Options B1 Turn OFF 8.0 s after CAN traffic bus idle detection. B2 Turn OFF when I/O-1 low level detected.

5) detection of 8 consecutive watchdog failures: no correct SPI watchdog refresh command occurred for duration of 8 x 256 ms. between RESET and NORMAL REQUEST Mode, or INIT RESET and INIT modes. 7) 8 second timer for bus idle timeout. I/O-1 high to low transition. Figure 32. Safe Operation Flow Chart time as the RESET pin is set low. is the case, the Safe Mode is entered.

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Figure 33. SAFE Mode A Behavior Illustration

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Figure 35. CAN Interface Block Diagram The supply voltage for the CAN driver is the 5 V-CAN pin. Mode to allow Wake-Up detection. e CAN interface current is sourced from the 5 V-CAN pin. pin level and the CAN bus state is reported on the RXD pin. asing is provided on the SPLIT output pin. effect on CAN bus lines. The 5 V-CAN regulator must be ON. Mode and the TXD pin is recessive.

5 V-CAN divided by 2, or approx. 2.5 V. affected by the slew rate selection. error flag and its echo error flag). to a single bit time of: 300 μs / 12 = 25 μs. So the minimum Baud rate is 1 / 25 μs = 40 kBaud. Sleep Mode is a reduced current consumption mode. results in a device Wake-Up if the device was in LP Mode. Figure 36. Bus Signal in TXD/RXD and LP Mode enabled or disabled via the SPI.

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Figure 37. Single Dominant Pulse Wake-up dominant pulses, by default when the CANWU bit is low. occur after a single pulse duration of 2.0 μs (typically). Figure 38. Pattern Wake-up - Multiple Dominant Detection

• Differential termination resistors between CANH and CANL lin es.
• SPLIT termination concept, with the mid point of the di fferential termination connected to GND through a capacitor and to the SPLIT pin.
• In application, the device can also be used without terminatio
• Figure 39 illustrates some of the most common terminations.

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comparator is also close to zero. dominant cycles, the error is not reported. 2.5 V biasing or to GND (Sleep Mode). thus, proper failure identification requires five pulses on TXD. The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 41. RXD Path Simplified Schematic, RXD Short to VDD Detection each low to high transition of the differential receiver. transition of the differential receiver. is reported via SPI in CAN register. Table 8. Failure Detection Truth Table

l at TXD as shown in the following illustration. The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register. Figure 42. RXD Path Simplified Schematic, RXD Short to VDD Detection into dominant level, and no communication is possible. a recessive state. The TXD permanent flag is set. change from recessive to dominant. in order to re enable the CAN bus driver.

Analog Integrated Circuit Device Data

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The physical interface is dedicated to automotive LIN sub- bus applications. The interface has 20 kbps and 10 kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior when a LIN bus short-to-ground, or a LIN bus leakage during LP Mode. Digital inputs are related to the device VDD pin. POWER SUPPLY PIN (VSUP/2) The VSUP/2 pin is the supply pin for the LIN interface. To avoid a false bus message, an under-voltage on VSUP/2 disables the transmission path (from TXD to LIN) when VSUP/2 falls below 6.1 V. GROUND PIN (GND) When there is a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus pin when in the recessive state. LIN BUS PIN (LIN, LIN1, LIN2) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal Mode. Driver Characteristics The LIN driver is a LS MOSFET with internal over-current thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ must be added when the device is used in the master node. The 1.0 kΩ pull-up resistor can be connected to the LIN pin or to the ECU battery supply. The LIN pin exhibits no reverse current from the LIN bus line to VSUP/2, even in the event of a GND shift or VSUP/2 disconnection. The transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI. Receiver Characteristics The receiver thresholds are ratiometric with the device VSUP/2 voltage. If the VSUP/2 voltage goes below typically 6.1 V, the LIN bus enters into a recessive state even if communication is sent on TXD. If LIN driver temperature reaches the over-temperature threshold, the transceiver and receiver are disabled. When the temperature falls below the over-temperature threshold, LIN driver and receiver will be automatically enabled. DATA INPUT PIN (TXD-L, TXD-L1, TXD-L2) The TXD-L,TXD-L1 and TXD-L2 input pin is the MCU interface to control the state of the LIN output. When TXD-L is LOW (dominant), LIN output is LOW. When TXD-L is HIGH (recessive), the LIN output transistor is turned OFF. This pin has an internal pull-up current source to VDD to force the recessive state if the input pin is left floating. If the pin stays low (dominant sate) more than t TXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag in LIN register. DATA OUTPUT PIN (RXD-L, RXD-L1, RXD-L2) This output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage on RXD, LIN LOW (dominant) is reported by a low voltage on RXD. LIN OPERATIONAL MODES The LIN interface have two operational modes, Transmit receiver and LIN disable modes. TRANSMIT RECEIVE In the TXD/RXD Mode, the LIN bus can transmit and receive information. When the 20 kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1. When the 10 kbps baud rate is selected, the slew rate and timing are compatible with J2602-2. When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition. The LIN interface can be set by the SPI command in TXD/RXD Mode, only when TXD-L is at a high level. When the SPI command is send while TXD-L is low, the command is ignored. SLEEP MODE This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP/2 is very low (typically 3.0 μA). LIN bus is monitor to detect Wake-Up

s connected and the 30 kOhm disconnected. transition. This is illustrated in Figures 22 and 23. The Wake-Up can be enable or disable by the SPI. Table 9. LIN Block Failure

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• bits 15 and 14 (called C1 and C0) are control bits to sele ct the SPI operation mode (write control bit to device register, read back of the control bits, read of device flag).
• bit 13 to 9 (A4 to A0) to select the register address.
• bit 8 (P/N) has two functions: parity bit in write mode (option al, = 0 if not used), Next bit ( = 1) in read mode.
• bit7 to 0 (D7 to D0): control bits MISO, Master In Slave Out bits:
• bits 15 to 8 (S15 to S8) are device status bits
• bits 7 to 0 (Do7 to Do0) are either extended device sta tus bits, device internal control register content or device flags. The SPI implementation does not support daisy chain capa bility. Figure 43 is an overview of the SPI implementation. Bit 15 Bit 13 Bit 11 Bit 12 Bit 10Bit 14 Bit 9 Bit 8 C1 A4 A2C0 Bit 7 Bit 5 Bit 3 Bit 4 Bit 2Bit 6 Bit 1 Bit 0 D7 D5 D3 D4 D2D6 D1 D0 control bits register address Parity (optional) or A0A1 P/N data MOSI S15 S13 S11S14 Do7 Do5 Do3 Do4 Do2Do6 Do1 Do0S12 S9S10 S8MISO Device Status Extended Device Status, Register Control bits or Device Flags Next bit = 1 CS SCLK MOSI MISO Tri-state Tri-state SPI Wave Form, and Signals Polarity S15 S14 Do0 C1 C0 D0 SCLK signal is low outside of CS active CS active low. Must rise at end of 16 clocks, MOSI and MISO data changed at SCLK rising edge and sampled at falling edge. Msb first. MISO tri-state outside of CS active Don’t CareDon’t Care for write commands, MOSI bits [15, 14] = ¬¨‚Ć[0

Figure 43. SPI Overview

Table 10 summarizes the various SPI operation, depending upon bit 15, 14, and 8. Table 10. SPI Operations (bits 8, 14 & 15)

00 Read back of register

1 Bit 8 must be set to 1, independently of the parity function

01 Write to register

0 If bit 8 is set to “0”: means parity not selected OR

10 Reserved

11 Read of device flags

device operation or to set the default value or behavior. Table 11. Device Registers with Corresponding Address 0_0000 Analog Multiplexer MUX 1) Write “device control bits” to register address. 0_0001 Memory byte A RAM_A 1) Write “data byte” to register address. 0_0101 Initialization Regulators Init REG 1) Write “device initialization control bits” to register address.

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options. Both MOSI and MISO information are described. Table 12. SPI Capabilities with Options er address (bit 13-9), and sub address (bit 7). om the selected address and sub-address. of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even. because the command contains 7 bits with logic 1. 0_1010 Timer_A: watchdog & LP MCU consumption TIM_A 1) Write “timing values” to register address. 2) Read back register “control bits”. 3) Read device flags from each of the register addresses.

Analog Integrated Circuit Device Data Freescale Semiconductor 65 33903/4/5 SERIAL PERIPHERAL INTERFACE DETAIL OPERATION Examples 2: MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1, because the command contains 4 bits with logic 1. Thus the Exact command will then be: MOSI [bit 15-0] = 01 00 011 1 0100 0000 Parity Function Selection All SPI commands and examples do not use parity functions. The parity function is optional. It is selected by bit 6 in INIT MISC register. If parity function is not selected (bit 6 of INIT MISC = 0), then Parity bits in all SPI commands (bit 8) must be “0”.

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Table 13. MUX Register(32)

011 Device internal temperature sensor voltage

100 Voltage at I/O-0. Attenuation or gain is selected by bit 3. 101 Voltage at I/O-1. Attenuation or gain is selected by bit 3. 0 Internal 2.0 kohm resistor disable. An external resist or must be connected between AMUX and GND. 1 Internal 2.0 kohm resistor enable.

1. The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while

5V-CAN is OFF, the command is ignored, and the MXU register content is reset to default state (all control bits = 0).

Table 14. Internal Memory Registers A, B, C and D, RAM_A, RAM_B, RAM_C and RAM_D

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Table 15. Initialization Regulator Registers, INIT REG (no te: register can be written only in INIT Mode)

0 I/O-1 sense anytime

1 I/O-1 sense during I/O-0 activation

Table 16. Initialization Watchdog Registers , INIT watchdog (note: register can be written only in INIT Mode) 0 Function disable. No constraint between I NT occurrence and INT source read. 1 INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods. In LP VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. In LP VDD ON Mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command. In LP VDD ON Mode, VDD over-current for a time > 100 μs (typi cally) is a Wake-Up event.

0 SAFE pin is set low at the time of the RESET pin low activation

1 SAFE pin is set low at the second consecutive time RESET pulse

00 Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI

01 Enhanced 1: Refresh is done using the R andom Code, and by a single 16 bits. 10 Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command. 11 Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.

0 Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period

1 Watchdog operation is WINDOW, watchdog refresh must occu r in the open window (second half of period)

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Table 17. Initialization LIN and I/O Registers, INIT LIN I/O (n ote: register can be written only in INIT Mode) 1 Enable I/O-1 turn off, when VDD or VAUX over-voltage condition is detected.

11 N/A

0 Disable HS and LS drivers of pin I/O-1. I/ O-1 can only be used as input. 1 Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver. 0 Disable HS and LS drivers of I/O-0 can only be used as input. 1 Enable HS and LS drivers of the I/O-0 pin. P in can be used as input and output drivers.

Table 18. Initialization Miscellaneous Functions, INIT MISC (No te: Register can be written only in INIT Mode) b7 LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD ON.

0 Function disable: the LP Mode can be entered without usage of Random Code

1 Function enabled: the LP Mode is entered using the Random Code

0 Function disable: the parity is not used. The parity bit must always set to logic 0. 1 Function enable: the parity is used, and parity must be calculated.

0 INT pin will assert a low level pulse, duration selected by bit [b4]

1 INT pin assert a permanent low level (no pulse)

0 INT pulse duration is typically 100 μs. Ref. to dynamic parameter table for exact value. 1 INT pulse duration is typically 25 μs. Ref . to dynamic parameter table for exact value. Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash Mode.

1. Bits b2,1 and 0 allow the following operation:

register (Ref. to device flag table).

Table 19. Specific Mode Register, SPE_MODE b7, b6 Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI command.

00 RESET Mode

01 INIT Mode

10 FLASH Mode

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• Go to INIT Mode, using the Secure SPi command.
• Activate the SAFE pin by S/W.

Table 20. Timer Register A, LP VDD Over-current & Watchdog Period Normal Mode, TIM_A Table 21. Timer Register B, Cyclic Sense and Cyclic INT, in Device LP Mode, TIM_B

Table 22. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C Table 23. Typical Timing Values

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Table 24. Watchdog Refresh Register, watchdog(34)

1. The Simple Watchdog Refresh command is in hexadecimal: 5A00. T his command is used to refresh the watchdog and also to

Table 25. MODE Register, MODE Table 26. LP VDD OFF Selection and FWU / Cyclic Sense Selection Table 27. LP VDD ON selection and operation mode

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flags must be cleared or read. 14] and bit [7]. Note, bit [8] is always set to 1. Mode via bit 7 of the INIT MISC register.

• Write LP Mode by inverting the 3 random bits.

1. in hex: 0x5C60 to enter in LP VDD OFF Mode without
2. if Random Code is selected, the commands are:

Table 28. Device Modes Read device current mode, Leave debug mode. Release SAFE pin (turn OFF). Read device current mode, Leave debug mode. Release SAFE pin (turn OFF).

decode the device’s current mode. Table 29. MISO bits 7-3 Table 30. SAFE and DEBUG status

0 SAFE pin OFF, not activated

1 SAFE pin ON, driver activated.

0 Debug Mode OFF

1 Debug Mode Active

Table 31. Regulator Register

00 Regulator OFF

detected after 1.0 ms blanking time. blanking time for UV and OC detection. time for UV and OC detection. OC detected after 25 μs b lanking time.

0 External VDD ballast disable

1 External VDD ballast Enable

0 Disable the automatic activation of the external ballast

1 Enable the automatic activation of the external ballast, if VDD > typically 60 mA

0 Disable Usage of LP VDD OFF Mode

1 Enable Usage of LP VDD OFF Mode

Table 32. CAN Register(35) 00 CAN interface in Sleep Mode, CAN Wake-Up disable. 01 CAN interface in receive only mode, CAN driver disable. CAN Wake-Up is reported by device Wake-Up. In device Nor mal Mode, CAN Wake-Up reported by INT. 11 CAN interface in transmit and receive mode.

00 FAST

01 MEDIUM

10 SLOW

11 SLOW

1 Single dominant pulse Wake-Up mechanism

1 Select INT generation as soon as a bus failure is detected, event if not fully identified

1. The first time the device is set to Norm al Mode, the CAN is in Sleep Wake-Up enabled (bit7 = 1, bit 6 =0). The next time the device is

set in Normal Mode, the CAN state is controlled by bits 7 and 6.

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Table 33. I/O Register

00 I/O-3 driver disable, Wake-up capability disable

01 I/O-3 driver disable, Wake-up capability enable.

00 I/O-2 driver disable, Wake-up capability disable

01 I/O-2 driver disable, Wake-up capability enable.

00 I/O-1 driver disable, Wake-up capability disable

01 I/O-1 driver disable, Wake-up capability enable.

00 I/O-0 driver disable, Wake-up capability disable

01 I/O-0 driver disable, Wake-up capability enable.

Table 34. INT Register

0 INT disable

1. If VDD under-voltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 68.
2. Bit 2 is used in conjunction with bi t 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request.

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Table 35. LIN/1 Register(39)

00 LIN/1 disable, Wake-Up capability disable

10 LIN/1 disable, Wake-Up capability enable

11 LIN/1 Transmit Receive Mode(38)

00 Slew rate for 20 kbit/s baud rate

01 Slew rate for 10 kbit/s baud rate

10 Slew rate for fast baud rate

11 Slew rate for fast baud rate

0 LIN/1 termination OFF

1 LIN/1 termination ON

1 LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.

1. The LIN interface can be set in TXD/RXD Mode only when the TXD- L in put signal is in recessive state. An attempt to set TXD/RXD

Mode, while TXD-L is low, will be ignored and the LIN interface remains disabled.

1. In order to use the LIN interface, the 5V-CAN regulator must be set to ON.

Table 36. LIN2 Register(41)

00 LIN2 disable, Wake-Up capability disable

10 LIN2 disable, Wake-Up capability enable

11 LIN2 Transmit Receive Mode(40)

0 LIN 2 termination OFF

1 LIN 2 termination ON

1 LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.

1. The LIN interface can be set in TXD/RXD Mode only when the TXD-L input signal is in a recessive state. An attempt to set TXD/RXD

Mode while TXD-L is low, will be ignored and the LIN interface will remain disabled.

1. In order to use the LIN interface, the 5V-CAN regulator must be set to ON.

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Analog Integrated Circuit Device Data Freescale Semiconductor 83 33903/4/5 SERIAL PERIPHERAL INTERFACE FLAGS AND DEVICE STATUS FLAGS AND DEVICE STATUS The table below is a summary of the device flags, I/O real time level, device Identification, and includes examples of SPI commands (SPI commands do not use parity functions). They are obtained using the following commands. This command is composed of the following: bits 15 and 14:

• [1 1] for failure flags
• - [0 0] for I/O real time st atus, device identification and CAN LIN driver receiver real time state.
• bit 13 to 9 are the register address from which the flags is to be read.
• b i t 8 = 1 (this is not parity bit function, as this is a read command). When a failure event occurs, the respective flag is set and remains latched until it is cleared by a read command (provided the failure event has recovered).

Table 37. Device Flag, I/O Real Time and Device Identification

1 CAN_UF CAN_F CANL

1 I/O_1-3

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Table 38. Flag Descriptions VAUX_LOW Description Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold. Description Report that current out of VAUX regulator is above VAUX_OC threshold. Set / Reset condition Set: Current above threshold for t >100 μs. Reset: Current below threshold and flag read by SPI.

5 V-CAN_

Description Report that the 5 V-CAN regulator has reached over-temperature threshold. 5V-CAN_UV Description Reports that 5 V-CAN regulator output voltage is lower than the 5 V-CAN UV threshold. Description Report that the CAN driver output current is above threshold. Description Reports that VSENSE pin is lower than the VSENSE LOW threshold. Description Reports that VSUP/1 pin is lower than the VSUP/1 LOW threshold. Description Report that current out of VDD pin is higher that IDD-OC threshold, while device is in Normal Mode. Description Report that the VDD has reached over-temperature threshold, and was turned off. Description Report that the device voltage at VSUP/1 pin was below BATFAIL threshold.

(0x2180) do not clear the flag, as it is “real time” information. Description Report that the CAN interface has reach over-temperature threshold. RXD low Description Report that RXD pin is shorted to GND. Rxd high Description Report that RXD pin is shorted to recessive voltage. TXD dom Description Report that TXD pin is shorted to GND. Description Report that the CAN current is above CAN over-current threshold.

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Description Report SPI parity error was detected. VSUP/2-UV Description Report that VSUP/2 is below VSUP/2-UV threshold. VSUP/1-OV Description Report that VSUP/1 is above VSUP/1-OV threshold. I/O-0 thermal Description Report that the I/O-0 HS switch has reach over-temperature threshold. Description Report that the watchdog period has reach 50% of its value, while device is in Flash Mode. SPI Wake-Up Description Report that Wake-Up source is SPI command, in LP VDD ON Mode. Description Report that INT timeout error detected. Set / Reset condition Set: INT service timeout expired. Reset: flag read. LP VDD OFF Description Report that LP VDD OFF Mode was selected, prior Wake-Up occurred. Reset request Description Report that RST source is an request from a SPI command (go to RST Mode). Set / Reset condition Set: device leave debug mode due to hardware cause. Reset: flag read.

INT request Description Report that INT source is an INT request from a SPI command. RST high Description Report that RST pin is shorted to high voltage. Set / Reset condition Set: RST failure detection. Reset: flag read. DBG resistor Description Report that the resistor at DBG pin is different from expected (different from SPI register content). Set / Reset condition Set: failure detected. Reset: correct resistor and flag read (SPI). Description Report that the VDD has reached over-temperature pre-warning threshold. VDD UV Description Reports that VDD pin is lower than the VDDUV threshold. this function is selected in INIT register. this function is selected in INIT register. VDD LOW Description Report that VDD is below VDD under-voltage threshold. Description Report that a wrong or missing watchdog failure occurred.

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command (0x2780 or 0x2980) do not clear it, as it is “real time” flag. (means LIN signal will not be detected and will not Wake-Up the device). not clear the flag, as it is “real time” information. Description Report that the LIN/1/2 interface has reach over-temperature threshold. Description Report that RXD/1/2 pin is shorted to GND. Description Report that RXD/1/2pin is shorted to recessive voltage. Description Report that TXD/1/2 pin is shorted to GND.

Table 39. Status Bits Description INT Indicates that an INT has occurred and that INT flags are pending to be read. WU Indicates that a Wake-Up has occurred and that Wake-Up flags are pending to be read. RST Indicates that a reset has occurred and that the flags that report the reset source are pending to be read. CAN-G The INT, WU or RST source is CAN interface. CAN local or CAN bus source. I/O-G The INT, WU or RST source is I/O interfaces. CAN-LOC The INT, WU or RST source is CAN interface. CAN local source. CAN-BUS The INT, WU or RST source is CAN interface. CAN bus source.

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1. Tested per specific OEM EMC requirements for CAN and LIN with additional

Figure 44. 33905D Typical Application Schematic

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

Figure 45. 33905S Typical Application Schematic

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

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Figure 46. 33904 Typical Application Schematic

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

Figure 47. 33903 Typical Application Schematic

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

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Figure 48. 33903D Typical Application Schematic

1. Tested per specific OEM EMC requirements for CAN and LIN with additional

Figure 49. 33903S Typical Application Schematic

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without using the VAUX regulator are illustrated as well. Optimized solution for cranking pulses. C1 is sized for MCU power supply buffer only. delivered by internal path transistor. Figure 50. Application Options

Analog Integrated Circuit Device Data Freescale Semiconductor 97 33903/4/5 PACKAGING SOIC 32 PACKAGE DIMENSIONS PACKAGING SOIC 32 PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D

EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D Analog Integrated Circuit Device Data

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SOIC 32 PACKAGE DIMENSIONS

EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor 99 33903/4/5 PACKAGING SOIC 32 PACKAGE DIMENSIONS

EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data

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SOIC 54 PACKAGE DIMENSIONS SOIC 54 PACKAGE DIMENSIONS

EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor 101 33903/4/5 PACKAGING SOIC 54 PACKAGE DIMENSIONS

EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data

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SOIC 54 PACKAGE DIMENSIONS

Analog Integrated Circuit Device Data Freescale Semiconductor 103 33903/4/5

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 4.0 9/2010 5.0 12/2010 6.0 4/2011

• Initial Release - This document supersedes document MC33904_5.
• Initial release of document in cludes the MC33903 part number, the VDD 3.3 V version description, and the silicon revision rev. 3.2. Change details available upon request.
• Added Cyclic INT Operation During LP VDD ON Mode 47
• Changed VSUP pin to VSUP1 and pin 2 (NC) to VSUP2 for the 33903 device
• Removed Drop voltage without external PNP pass transistor (13) 20 for VDD=3.3 V devices
• Added V SUP1-3.3 to VDD Voltage regulator, VDD pin 20.
• Added Pull-up Current, TXD, VIN = 0 V 24 for VDD=3.3 V devices
• R e v i s e d MUX and RAM registers 66
• R e v i s e d Status Bits Description 89
• Added Entering into LP Mode using Random Code 76.
• Removed part numbers MCZ33905S3EK/R2, MCZ33904A3EK/R2 and MCZ33905D3EK/R2, and added part numbers MCZ33903BD3EK/R2, MCZ33903BD5EK/R2, MCZ33903BS3EK/R2 and MCZ33903BS5EK/R2.
• Votalge Supply was improved from 27V to 28V.
• Changed Classification from Advance Information to Technical Data.
• Updated Notes in Tables 6.
• R e v i s e d Tables 6 ; Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: to reflect a Typical value.
• Corrected typographical errors throughout.
• Added Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) parameter to Tables 6
• Updated I/O pins (I/O-0: I/O-3) on page 35.

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