MCZ33897AEF FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • Waveshaping for Low Electromagnetic Interference (EMI)
  • Detects and Automatically Handles Loss of Ground
  • Worst-Case Sleep Mode Current of Only 60 µA (75 µA on the 33897T)
  • Current Limit Prevents Damage Due to Bus Shorts
  • Built-In Thermal Shutdown on Bus Output
  • Protected Against Vehicular Electrical Transients
  • Undervoltage Lockout Prevents False Data with Low Battery
  • Pb-Free Packaging Designated by Suffix Code EF SINGLE WIRE CAN TRANSCEIVER 33897/A/B/C/D/T D SUFFIX EF (PB-FREE) SUFFIX 98ASB42565B 14-TERMINAL SOICN EF (PB-FREE) SUFFIX 98ASB42564B 8-TERMINAL SOICN

ORDERING INFORMATION

Contains Lead Pb-Free RoHS Temperature Range (TA) Package MC33897D/R2 MC33897AD/R2 MC33897EF/R2 MC33897AEF/R2 MCZ33897EF/R2 MCZ33897TEF/R2 MCZ33897AEF/R2 *MCZ33897CEF/R2 - 40°C to 125°C

14 SOICN

MC33897BEF/R2 MCZ33897BEF/R2 *MCZ33897DEF/R2 8 SOICN *Recommended device for all new designs

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Figure 1. 33897/A/C Simplified Application Diagram Figure 2. 33897B/D Simplified Application Diagram

Table 1. Device Variations

1.0 V Max

  • 14-Pin Package 8 33897T
  • 14-Pin Package
  • Quiescent Current in Sleep Mode, 5.0V ∠ VΒΑΤΤ ∠ 13V, Typical - 55 µA, Max - 75µA
  • ESD Voltage: Machine Model ±100V 6, 7, 8 33897A

0.1 V Max

  • 14-Pin Package
  • Removes diode drop during Sleep Mode
  • May not detect Loss of Ground under certain module characteristics. 33897B
  • 8-Pin Package
  • Removes diode drop during Sleep Mode
  • Does not include the CNTL terminal
  • May not detect Loss of Ground under certain module characteristics. *33897C
  • 14-Pin Package
  • Removes diode drop during Sleep Mode
  • Effectively detects Loss of Ground
  • ESD Voltage: Human Body Model ±1500V, Machine Model ±100V *33897D
  • 8-Pin Package
  • Removes diode drop during Sleep Mode
  • Effectively detects Loss of Ground
  • Does not include the CNTL terminal
  • ESD Voltage: Human Body Model ±1500V, Machine Model ±100V

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Figure 3. 33897/A/B/C/D/T Simplified Internal Block Diagram *CNTL terminal is present on 33897/A/C/T only.

Figure 4. 33897/A/B/C/D/T Pin Connections Table 2. Pin Definitions A functional description of each terminal can be found in the Functional Pin Description section, beginning on page 13. will also reduce the die temperature. the bus, a logic [1] will make the bus go to the recessive state. dominant bus = logic [0]. An external pullup is required. 9 – CNTL Control Provides a battery-level logic signal. the event of loss of module ground. 12 7 BUS Bus This terminal connects to the bus through external components.

  1. Module boards can be planned for the 14-terminal package and still use the 8-terminal package.

Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted.

  1. ESD testing is performed in accord ance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω),

Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

  1. When using the 8-terminal device, consider the power dissipation at a high operating voltage and maximum network loading at ambient

temperatures exceeding 85°C.

  1. Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

  1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33897/A/B/C/D/T STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

5.0 V ≤ VBATT ≤ 13 V (6) 33897/A/B/C/D

  1. Thermal shutdown causes the BUS output driver to be disabled. Guaranteed by characterization.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS LOAD LOAD Voltage Rise (8) Normal Speed and Voltage Mode, Transmit High- Voltage Mode, Transmit High-Speed Mode IIN = 1.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V Sleep Mode IIN = 7.0 mA 33897/T IIN = 7.0 mA (9) 33897A/B/C/D Loss of Battery IIN = 7.0 mA VLDRISE 0.1 1.0 0.1 1.0 V LOAD Leakage During Loss of Module Ground (10)

0.0 V ≤ VBATT ≤ 18 V 33897/A/B/T

0.0 V ≤ VBATT ≤ 18 V 33897C/D

0.0 -10 - 90 µA BUS Passive Out BUS Leakage Passive In 0.0 V ≤ VBATT ≤ 26.5 V, -1.5 V ≤ VBUS < 0 V Active In 0.0 V ≤ VBATT ≤ 26.5 V, 0 V < VBUS ≤ 12.5 V BUS Leakage During Loss of Module Ground (11) -5.0 -5.0 -10 0.0 5.0 5.0 -90 µA High-Voltage Wake-up Mode Output High Voltage 12 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω 33897/T 33897A/B/C/D

5.0 V ≤ VBATT < 12 V, 200 Ω ≤ RL ≤ 3332 Ω

9.7 9.9 Lesser of VBAT - 1.5 or 9.7 12.5 12.5 VBATT V High-Speed Mode Output High Voltage

8.0 V ≤ VBATT ≤ 16 V, 75 Ω ≤ RL ≤ 135 Ω

4.2 – 5.1 V Normal Mode Output High Voltage 6.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω 5.0 V ≤ VBATT < 6.0 V, 200 Ω ≤ RL ≤ 3332 Ω VNOHF VNOHO 4.4 Lesser of VBATT - 1.6 or 4.4 5.1 Lesser of VBATT or 5.1 V BUS Low Voltage 5.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω VOL - 0.2 – 0.2 V Short Circuit BUS Output Current Dominant State, 5.0 V ≤ VBATT ≤ 26.5 V IBSC -350 – - 150 mA Notes 8. GMW3089V2.4 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode. The maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.4. 9. 33897A/B/C/D remove diode drop during Sleep mode. 10. LOAD terminal is at system ground voltage. 11. BUS terminal is at system ground voltage Table 4. Static Electrical Characteristics (continued) otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33897/A/B/C/D/T STATIC ELECTRICAL CHARACTERISTICS BUS (CONTINUED) Input Threshold Awake 5.0 V ≤ VBATT ≤ 26.5 V Sleep 12 V ≤ VBATT ≤ 26.5 V Sleep

5.0 V ≤ VBATT < 12 V

2.0 6.6 Lesser of 6.6 V or VBATT - 4.3 2.2 7.9 Lesser of 7.9 V or VBATT - 3.25 V otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

Analog Integrated Circuit Device Data

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

8.0 V ≤ VBATT ≤ 16 V

  1. V BUSMOD is the voltage at the BUSMOD node in Figure 7, page 15.
  2. V BUS is the voltage at the BUS terminal in Figure 8, page 15.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33897/A/B/C/D/T DYNAMIC ELECTRICAL CHARACTERISTICS BUS (CONTINUED) High-Voltage Rising Output Delay 200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs Measured from TXD=VIL to VBUS as follows: Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (14) Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (14) Max Time to VBUSMOD = 9.4 V, 12.0 V ≤ VBATT ≤ 26.5 V (14) t DLYHVRO 2.0 2.0 2.0 6.3 6.3 µs High-Voltage Falling Output Delay 200 Ω ≤ RL ≤ 3332 Ω, 1.0 µs ≤ Load Time Constants ≤ 4.0 µs, 12.0 V ≤ VBATT ≤ 26.5 V Measured from TXD=VIH to VBUS as follows: Max Time to VBUSMOD = 1.0 V (14) Min Time to VBUSMOD = 3.7 V (14) t DLYHVFO 1.8 1.8 µs RECEIVER RXD Receive Delay Time (5.0 V ≤ VBATT ≤ 26.5 V) Awake t RDLY 0.2 – 1.0 µs Receive Delay Time (BUS Rising to RXD Falling, 5.0 V ≤ VBATT ≤ 26.5 V) Sleep t RDLYSL 10 – 70 µs CNTL CNTL Falling Delay Time (5.0 V ≤ VBATT ≤ 26.5 V) (33897/A/C/T only) t CNTLFDLY 300 – 1000 ms Notes 14. V BUSMOD is the voltage at the BUSMOD node in Figure 7, page 15. Table 5. Dynamic Electrical Characteristics (continued) otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.

Analog Integrated Circuit Device Data

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Figure 5. TXD, Bus and RXD Waveforms in Normal Mode Figure 6. TXD, Bus and RXD Waveforms in High Speed Mode

  • VBUSMOD is the voltage at the BUSMOD node in Figure 7.
  • VBUS is the voltage at the BUS terminal in Figure 8.

device in a Single Wire CAN communications bus. single wire using a common ground for a current return path. higher rate could be an issue. high-speed, and high-voltage wake-up). diameter holes the layout can use. mode versus the logic levels on MODE0 and MODE1. the bus is in either the normal or high-voltage dominant state. pass current to or from the bus. This logic level signal is used to control a VCC regulator. all the devices powered by VCC when the IC is in sleep mode. to sleep mode if both MODE Pins are low. Table 6. Mode Control Logic Levels

Analog Integrated Circuit Device Data

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FUNCTIONAL BLOCK DIAGRAM COMPONENTS diode is generally used to protect the entire module from reverse battery and should be selected accordingly. BUS I /O This input / output may require electrostatic discharge (ESD) and /or EMI external circuitry. A set of components is shown in the simplified application diagrams on page 16 of this datasheet. The value of the capacitor should be adjusted downward in direct proportion to the added capacitance of the ESD or EMI circuits. The series resistance of the inductor should be kept below 3.5 Ω to prevent its voltage drop from significantly degrading system noise margins. FUNCTIONAL BLOCK DIAGRAM COMPONENTS Timer OSC This circuit generates a 500 kHz signal to be used for internal logic. It is the reference for some of the required delays. Timers This circuit contains the timing logic used to hold the CNTL active for the required time after the conditions for sleep mode have been met. It is also used to keep the TXD driver active for a period of time after it has generated a passive level on the bus. Mode Control This circuit contains the control logic for the various operating modes and conditions required for the IC. BUS RCVR This circuit translates the levels on the BUS terminal to a CMOS level indicating the presence of a logic [0] or a logic [1]. It also determines the presence of a high-voltage wake-up (HVWU) signal that is passed to Mode Control and Timers circuits. An analog filter is used to “de-glitch” the high- voltage wake-up signal and prevent false exits from the sleep mode. TXD BUS DRVR This circuit drives the BUS. It can drive it with the higher voltage wake-up signals when enabled by the Mode Control circuit. It can also provide waveshaping for reduced EMI or not provide it for the higher data rate mode. The actual data is received on TXD at CMOS logic levels, then translated by this circuit to the necessary operating voltages. Undervoltage Detect This circuit monitors internal operating voltage to assure proper operation of the part. If a low-voltage condition is detected, it sends a signal to disable the BUS RCVR and TXD BUS DRVR circuits. This prevents incorrect data from being put on the bus or sent to the MCU. Load Switch The LOAD switch provides a path for an external resistor connected to the BUS to be connected to ground. When a loss of ground is detected, this switch is opened to prevent the current that would normally be flowing to the ground from the module from going back through the load resistor and raising the bus level. The circuit is opened when the voltage between GND and VBATT becomes too low as would be the case if module ground were lost.

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into Sleep mode by having an Enable terminal. See Figure 9. lowered when it goes into sleep mode. Figure 9. 33897/A/C/T Typical Application Schematic Figure 10. 33897B/D Typical Application Schematic

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33897/A/B/C/D/T PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current Package revision, visit www.freescale.com and perform a Keyword Search on the “98A” drawing number below. D SUFFIX EF (Pb-FREE) SUFFIX 14-TERMINAL SOICN PLASTIC PACKAGE 98ASB42565B ISSUE H

Analog Integrated Circuit Device Data

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PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (CONTINUED) EF (Pb-FREE) SUFFIX 8-TERMINAL SOICN PLASTIC PACKAGE 98ASB42564B ISSUE U

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33897/A/B/C/D/T

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 9.0 5/2005 • Converted to Freescale format

  • Added A & B Versions
  • Updated Device Variation Table, and Note “* Recommended device for all new designs”
  • Added EF (Pb-Free) Devices, and higher soldering temperature 10.0 8/2005 • Implemented Revision History page
  • Updated Simplified Application Diagrams
  • Updated Typical Application Schematic 11.0 12/2005 • Added 33897C and D versions and Timing Diagrams 12.0 1/2006 • Updated Table 4, Static Electrical C haracteristics - LOAD and BUS parameters
  • Updated Ordering Information. 13.0 6/2006 • Removed “Unless otherwise not ed” from Static Electrical Characteristics & Dynamic Electrical Characteristics table introductions 14.0 8/2006 • Added Part Numbers MC33897TD and MC33897TEF to Ordering Information on Page 1.
  • Added 33897T to Table 1, Device Variations on Page 3, Referencing Electrical Changes per Errata MC33897TER, Revision 3 and specifying ESD variations 15.0 10/2006 • Removed Part Numbers MC33897TD/R2, MC33897TEF/R2, MC33897CLEF/R2, PC33897CLEF/R2, MC33897DLEF/R2, and PC33897DLEF/R2
  • Added Part Numbers MCZ33897EF/R2, MCZ33897TEF/R2, MCZ33897AEF/R2, MCZ33897CEF/R2, MCZ33897BEF/R2, and MCZ33897DEF/R2 to the Ordering Information block on Page 1.
  • Updated Device Variations on page 3 for “T” suffix products
  • Split out Human Body Model on page 6 to differentiate between T and non-T versions
  • Added Undervoltage Hysteresis on page 7
  • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 6. Added note with instructions to obtain this information from www.freescale.com. 16.0 6/2007 • Removed watermark, “Advance Information” from page 1.

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