MC33897 NXP
Document overview
- Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
- PDF pages: 19
Technical content
Features
- Waveshaping for low Electrom agnetic Interference (EMI)
- Detects and automatically handles loss of ground
- Worst-case Sleep mode current of only 60 μA
- Current limit prevents damage due to bus shorts
- Built-in thermal shutdown on bus output
- Protected against vehicular electrical transients
- Under-voltage lockout prevent s false data with low battery
Figure 1. 33897 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MCZ33897TEF/R2 -40 to 125 °C 14 SOICN *MC33897CTEF/R2 *Recommended device for all new designs VBATT MODE 1 MODE 0 RXD TXD GND LOAD CNTL BUSMCU BatteryVoltage EN Power source Regulator VCC SWC Bus 33897
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Table 1. Device Variations
Figure 2. 33897 Simplified Internal Block Diagram
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Figure 3. 33897 Pin Connections Table 2. Pin Definitions A functional description of each pin can be found in the Functional Pin Description section, beginning on page 12.
33897 Pin Pin Name Formal Name Definition
will make the bus go to the recessive state. = logic [0]. An external pull-up is required. 6, 13 NC No Connect No internal connection to these Pins. Pin 13 can be connected to GND. 9 CNTL Control Provides a battery level logic signal. 10 VBATT Battery Power input. An external diode is needed for reverse battery protection.
11 LOAD Load The external bus load resistor connects here to prevent bus pull-up in the event of
12 BUS Bus This pin connects to the bus through external components.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 33897
ELECTRICAL CHARACTERISTICS
Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
- ESD testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω),
Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
- Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
5.0 V ≤ VBATT ≤ 13 V (4)
- Thermal shutdown causes the BUS output driver to be disabled. Guaranteed by characterization.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33897 STATIC ELECTRICAL CHARACTERISTICS LOAD LOAD Voltage Rise (6) Normal Speed and Voltage Mode, Transmit High- Voltage Mode, Transmit High Speed Mode IIN = 1.0 mA, 5.0 V ≤ VBATT ≤ 26.5 V Sleep Mode IIN = 7.0 mA 33897T IIN = 7.0 mA (7) 33897CT Loss of Battery IIN = 7.0 mA VLDRISE 0.1 1.0 0.1 1.0 V LOAD Leakage During Loss of Module Ground (8)
0.0 V ≤ VBATT ≤ 18 V 33897T
0.0 V ≤ VBATT ≤ 18 V 33897CT
0.0 -10 - 90 μA BUS Passive Out BUS Leakage Passive In 0.0 V ≤ VBATT ≤ 26.5 V, -1.5 V ≤ VBUS < 0 V Active In 0.0 V ≤ VBATT ≤ 26.5 V, 0 V < VBUS ≤ 12.5 V BUS Leakage During Loss of Module Ground (9) -5.0 -5.0 -10 0.0 5.0 5.0 -90 μA High Voltage Wake-up Mode Output High Voltage 12 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω 33897T 33897CT
5.0 V ≤ VBATT < 12 V, 200 Ω ≤ RL ≤ 3332 Ω
9.7 9.9 Lesser of VBAT - 1.5 or 9.7 12.5 12.5 VBATT V High Speed Mode Output High Voltage
8.0 V ≤ VBATT ≤ 16 V, 75 Ω ≤ RL ≤ 135 Ω
4.2 – 5.1 V Normal Mode Output High Voltage 6.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω 5.0 V ≤ VBATT < 6.0 V, 200 Ω ≤ RL ≤ 3332 Ω VNOHF VNOHO 4.4 Lesser of VBATT - 1.6 or 4.4 5.1 Lesser of VBATT or 5.1 V Notes 6. GMW3089V2.4 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode. The maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.4. 7. 33897CT removes the diode drop during Sleep mode. 8. LOAD pin is at system ground voltage. 9. BUS pin is at system ground voltage Table 4. Static Electrical Characteristics (continued) otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
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STATIC ELECTRICAL CHARACTERISTICS BUS (CONTINUED) BUS Low Voltage 5.0 V ≤ VBATT ≤ 26.5 V, 200 Ω ≤ RL ≤ 3332 Ω VOL - 0.2 – 0.2 V Short-circuit BUS Output Current Dominant State, 5.0 V ≤ VBATT ≤ 26.5 V IBSC -350 – - 100 mA Input Threshold Awake 5.0 V ≤ VBATT ≤ 26.5 V Sleep 12 V ≤ VBATT ≤ 26.5 V Sleep
5.0 V ≤ VBATT < 12 V
2.0 6.6 Lesser of 6.6 V or VBATT - 4.3 2.2 7.9 Lesser of 7.9 V or VBATT - 3.25 V otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
Analog Integrated Circuit Device Data Freescale Semiconductor 9 33897 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
8.0 V ≤ VBATT ≤ 16 V
- V BUSMOD is the voltage at the BUSMOD node in Figure 6, page 13.
- V BUS is the voltage at the BUS pin in Figure 7, page 14.
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DYNAMIC ELECTRICAL CHARACTERISTICS BUS (CONTINUED) High Voltage Rising Output Delay 200 Ω ≤ RL ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs Measured from TXD=VIL to VBUS as follows: Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V (12) Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V (12) Max Time to VBUSMOD = 9.4 V, 12.0 V ≤ VBATT ≤ 26.5 V (12) t DLYHVRO 2.0 2.0 2.0 6.3 6.3 μs High Voltage Falling Output Delay 200 Ω ≤ RL ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs, 12.0 V ≤ VBATT ≤ 26.5 V Measured from TXD=VIH to VBUS as follows: Max Time to VBUSMOD = 1.0 V (12) Min Time to VBUSMOD = 3.7 V (12) t DLYHVFO 1.8 1.8 μs RECEIVER RXD Receive Delay Time (5.0 V ≤ VBATT ≤ 26.5 V) Awake t RDLY 0.2 – 1.0 μs Receive Delay Time (BUS Rising to RXD Falling, 5.0 V ≤ VBATT ≤ 26.5 V) Sleep t RDLYSL 10 – 70 μs CNTL CNTL Falling Delay Time (5.0 V ≤ VBATT ≤ 26.5 V) t CNTLFDLY 300 – 1000 ms Notes 12. V BUSMOD is the voltage at the BUSMOD node in Figure 6, page 13. Table 5. Dynamic Electrical Characteristics (continued) otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
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device in a Single Wire CAN communications bus. high speed, and high voltage wake-up). mode versus the logic levels on MODE0 and MODE1. bus is in either the normal or high voltage dominant state. This logic level signal is used to control a VCC regulator. all the devices powered by VCC when the IC is in Sleep mode. Sleep mode levels in order to keep this pin from going low. Table 6. Mode Control Logic Levels
reverse battery and should be selected accordingly. degrading system noise margins. operating modes and conditions required for the IC. signal and prevent false exits from the Sleep mode. this circuit to the necessary operating voltages. being put on the bus or sent to the MCU. case if module ground were lost. Figure 6. Transmitter Delays in Normal and Transmit High Voltage Wake-up Modes Note: The letter ’n’ represents the number of nodes in the system.
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Figure 7. Transmitter Delays in Transmit High Speed Mode Note: The letter ’n’ represents the number of nodes in the system.
module’s regulator is in Sleep mode, the module is turned off. Figure 8. 33897 Typical Application Schematic
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Important: For the most current Package revision, visit www.freescale.com and perform a Keyword Search on the 98ASB42565B drawing number below. Dimensions shown are provided for reference ONLY. EF (Pb-FREE) SUFFIX 14-pin SOICN 98ASB42565B ISSUE J
Analog Integrated Circuit Device Data Freescale Semiconductor 17 33897 PACKAGING PACKAGE DIMENSIONS EF (Pb-FREE) SUFFIX 14-pin SOICN 98ASB42565B ISSUE J
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REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 9.0 5/2005 • Converted to Freescale format
- Added A & B Versions
- Updated Device Variation Table, and Note “* Recommended device for all new designs”
- Added EF (Pb-Free) Devices, and higher soldering temperature 10.0 8/2005 • Implemented Revision History page
- Updated Simplified Application Diagrams
- Updated Typical Application Schematic 11.0 12/2005 • Added 33897C and D versions and Timing Diagrams 12.0 1/2006 • Updated Table 4, Static Electrical C haracteristics - LOAD and BUS parameters
- Updated Ordering Information. 13.0 6/2006 • Removed “Unless otherwise noted” from Static El ectrical Characteristics & Dynamic Electrical Characteristics table introductions 14.0 8/2006 • Added Part Numbers MC33897TD and MC33897TEF to Ordering Information on Page 1.
- Added 33897T to Table 1, Device Variations on P age 3, Referencing Electrical Changes per Errata 15.0 10/2006 • Removed Part Numbers MC33897TD/R2, MC33897TEF/R2, MC33897CLEF/R2, PC33897CLEF/ R2, MC33897DLEF/R2, and PC33897DLEF/R2
- Added Part Numbers MCZ33897EF/R2, MCZ33897TEF/R2, MCZ33897AEF/R2, MCZ33897CEF/ R2, MCZ33897BEF/R2, and MCZ33897DEF/R2 to the Ordering Information block on Page 1.
- Updated Device Variations on page 2 for “T” suffix products
- Split out Human Body Model on page 5 to differentiate between T and non-T versions
- Added Under-voltage Hysteresis on page 6
- Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5. Added note with instructions to obtain this information from www.freescale.com. 16.0 6/2007 • Removed watermark, “Advance Information” from page 1. 17.0 1/2011 • Improved HBM ESD All Pins Except BUS to ±2.0 kV on MC33897CT
- Added MC33897CTEKF/R2 to the ordering information
- Removed all 8-Pin SOICN device information
- Changed Short-circuit BUS Output Current to -100 mA (Approved by GM) 18.0 4/2012 • Updated Quiescent Current IQSLP to 60 μA max.
Document Number: MC33897 Rev. 18.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qorivva, StarCore, and Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, Processor expert, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support