33793 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- Conforms to DSI Specification Version 1
- 4-Channel, 8-Bit Analog-to-Digital Converter (ADC)
- 4 Pins Configurable as Analog or Logic Inputs or as Logic Outputs
- Provides Regulated +5.0 V Output for Sensor Power from Bus
- Additional High-Drive Logic Output
- Undervoltage Fault Detection and Signaling
- On-Board Clock (No External Elements Required)
- Field-Programmable Address
- Default and Field-Programmable as a DSI Daisy Chain Device
- Recognizes Reverse Initialization for Open Bus Fault Tolerance
- Detects Short to Battery on Bus Switch and Prevents Its Closure
- Pb-Free Packaging Designated by Suffix Code EF
Figure 1. 33793 Simplified Application Diagram
ORDERING INFORMATION
Range (TJ) Package MC33793D/R2 -40°C to 150°C 16 SOICNMCZ33793EF/R2 MCZ33793AEF/R2 SCALE 2:1 DISTRIBUTED SYSTEM INTERFACE D SUFFIX EF SUFFIX (Pb-FREE) 98ASB42566B 16-PIN SOICN BusIN 33793 DSIO 33790 GND Error Test X Y VCC GND X-Y Accelerometer BUSIN I/O0 I/O1 I/O2 H_Cap REGOUT AGND LOGOUT BUSRTN BUSOUTI/O3
33793 Multiple
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Table 1. Device Variations
Figure 2. 33793 Simplified Internal Block Diagram
4.0 MHz
4 Bits NVM
5.0 V Regulator
8 Bits
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Figure 3. 33793 Pin Connections Table 2. 33793 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. 1 BUSRTN Power Bus Return This pin provides the common return for power and signalling. analog-to-digital (A/D) input. 7, 10, 13, 15 NC No Connect No Connect These pins have no internal connections.
9 LOGOUT Output Logic Out This is a logic output with higher pull-up drive capability than the standard
REGOUT pin during non-idle periods. 14 BUSIN Input DSI Bus Input This pin attaches to the bus and responds to initialization commands.
16 BUSOUT Output DSI Bus Output This pin attaches to the bus and responds to reverse initialization
Analog Integrated Circuit Device Data Freescale Semiconductor 5 33793
ELECTRICAL CHARACTERISTICS
Table 3. Maximum Ratings permanent damage to the device.
- ESD1 performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), ESD2 performed in accordance with the
Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
- Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
MC33xxxD enter 33xxx), and review parametrics.
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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics
5.5 V > VH_CAP > 25 V, IRO = 12 mA
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33793 STATIC ELECTRICAL CHARACTERISTICS I/O Logic Output Levels Output Low (IL = 1.0 mA) Output High (IL = -500 µA) VOL VOH 0.8 0.08 0.985 0.5 1.0 V VRO LOGOUT Output Levels Output Low (IL = 500 µA) Output High (IL = -10 mA, 6.2 V < VH_CAP < 25 V) Output High (IL = -100 µA, 6.2 V < VH_CAP < 25 V) VLOL VLOH1 VLOH2 4.7 0.2 5.0 0.5 5.3 VRO+0.5 V Programming Time From Positive Edge of BUSIN or BUSOUT > VTHH on Program Command to Following Command Negative Transition < VTHH TPROG 100 200 1000 ms NVM BUSIN or BUSOUT Programming Voltage NVMVP 22.25 – 30 V Table 4. Static Electrical Characteristics (continued)
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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics
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The 33793 is designed to be used with a sensor at a location that is remote from a centralized MCU. This device provides power, measurement, and communications between the remote sensor and the centralized MCU over a DSI bus. Sensors such as accelerometers can be powered from the regulated output of the device, and the resulting analog value from the sensor can be converted from an analog level to a digital value for transmission over the DSI bus in response to a query from the MCU. Four I/O lines can be configured by the central MCU over the DSI bus as analog inputs, digital inputs, or digital outputs. This allows more than one sensor to be remotely controlled and measured by a single 33793. Additionally, a high drive logic output is provided that can be used to power other low-power sensors. Power is passed from BUSIN or BUSOUT through on- board rectifiers to a storage capacitor (referred to as the H_CAP). The H_CAP stores energy during the highest voltage excursions of the BUSIN or BUSOUT pin (idle) and supplies energy to power the device during low excursions of BUSIN and BUSOUT. The Regulator supplies an on-board regulated voltage for internal use, and the Power on Reset (POR) circuit provides a reset signal during low-voltage conditions and during power up/down. Some current is available for low-power sensors. Data from the Central Control Unit (CCU) is applied to the BUSIN and/or BUSOUT pins as voltage levels that are sensed by the Level Detection circuitry. The Serial Decoder detects these transitions and decodes the incoming data. The Control Logic provides overall control of the 33793. It controls diagnostic testing and formats responses to commands with the message encoder. Responses are formed via a switched current source that is slew-rate controlled. The one-time programmable (OTP) memory array provides the nonvolatile storage for the pre-programmed address. It is accessed via the Read/Write NVM command. It has a built-in hardware lock that only allows one write. FUNCTIONAL PIN DESCRIPTION BUS RETURN (BUSRTN) This pin provides the common return for power and signalling. INPUT/OUTPUT (I/O0, I/O1, I/O2, I/O3) This pin can be used to provide a logic level output, a logic input, or an analog-to-digital (A/D) input. ANALOG GROUND (AGND) This pin is the low reference level and power return for the analog-to-digital converter (ADC). LOGIC OUT (LOGOUT) This is a logic output with higher pull-up drive capability than the standard logic I/O. REGULATOR OUTPUT (REGOUT) This pin provides a regulated 5.0 V output. The power is derived from the bus. HOLDING CAPACITOR (H_CAP) A capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the REGOUT pin during non-idle periods. DSI BUS INPUT (BUSIN) This pin attaches to the bus and responds to initialization commands. DSI BUS OUTPUT (BUSOUT) This pin attaches to the bus and responds to reverse initialization commands. FUNCTIONAL INTERNAL BLOCK DESCRIPTION Refer to Figure 2, 33793 Internal Block Diagram, page 3, for a simplified representation of the 33793’s components. RECTIFIER This rectifier or switch peak detects the bus signal into an external capacitor attached to H_CAP. The capacitor supplies power during signaling while the input voltage is at a lower level. The voltage waveform at BUSIN and/or BUSOUT and the size of the filter capacitor at H_CAP must be such that the voltage at H_CAP will not drop below the frame threshold during signaling. POR The 33793 leaves the reset state when the voltage on H_CAP rises above the Power-ON Reset threshold. TIMEOUT A timeout timer keeps track of the length of the time when the input is not in idle mode. If this time exceeds a limit, the
Analog Integrated Circuit Device Data Freescale Semiconductor 11 33793 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION part is reset. The purpose of this is to allow the part to reset itself if the connection to the master is lost or if power is removed from the system. The 5.0 V regulator supplies internal power for the device and also provides approximately 6.0 mA through the REGOUT pin to power an external sensor. UNDERVOLTAGE DETECTOR The undervoltage detector monitors the output voltage of the 5.0 V regulator. If the REGOUT voltage drops too low for accurate A/D operation, a signal is sent to the control logic. The control logic will interpret this signal and, in response to a command, report a status indicating an undervoltage condition to have existed. When received, the command will clear the signal after having read the status. If the voltage is too low when the A/D conversion was completed, the returned value will be zero (binary 00000000). IO PINS 0 TO 3 The IO pins can serve as logic inputs, logic outputs, or analog inputs. At power-up or after a clear, the pins are all logic inputs and can be used to measure an analog level value for an analog value request command. The pins can be individually configured as logic inputs or outputs by the IO Control command. If the pin is configured as a logic output, reading the analog value will return the analog level the output is being driven to. ANALOG-TO-DIGITAL CONVERTER The ADC is an 8-bit successive approximation type using on-board capacitive division. It uses the Clk signal from the on-board oscillator for sequencing. The ADC uses REGOUT as a full-scale reference voltage and ground AGND for a zero-level reference. The ADC signals when it has made a valid conversion by asserting a signal to the controller. If this signal is not asserted when a value is being captured by the controller, the controller will signal that an invalid A/D value was obtained. The value of “0" (binary 00000000) is reserved by the control logic to signal an error. A value of “0” from the ADC will be reported as “1” (binary 00000001) by the control logic. SERIAL ENCODER The Serial Encoder accepts the digitized value from the ADC and formatting/data from the Control Logic. A logic transition from Idle to Signal High and then to Signal Low at BUSIN will cause the first bit to be presented to the current switch (Response Loading). A transition to Signal High and back to Signal Low will cause the next bit to be presented to the current switch. This will continue until a transition back to Idle turns off the current switch. SLEW The slew circuit serves to reduce EMI produced as a result of switching the bus loading current sink element. The slew circuit limits the rise and fall time of current loading the bus by controlling the current sinking element. SWITCHED CURRENT SOURCE A "1" data return bit will be signaled by turning on a fixed current source. During signaling time, the 33793 will be using power from H_CAP and not loading the bus for power. The current will be drawn from either BUSIN or BUSOUT or split between them. The split can be in any proportion as long as the total is correct. The current source is turned off whenever the bus is at Idle level. LEVEL DETECTOR The level detector contains comparators to determine if the BUSIN or BUSOUT is at idle, logic high, or logic low. The inputs from BUSIN and BUSOUT are sensed by the device so that if either side is driven by the signaling waveform while the other is not, the signaling will be detected. This circuit also provides a signal to indicate if the signal is being received on the BUSOUT pin. If a "reverse initialization" command is received, it can only be acted upon if the device is not already initialized and if the signal is present on BUSOUT. SERIAL DECODER The Serial Decoder monitors transitions on the BUSIN or BUSOUT. When the 33793 is Idle and supplying power to itself and the external device(s) (via REGOUT), the input to BUSIN will be in the Idle state. A transition from this level to Signal Low (through Signal High) will start the process of decoding a word of data. BUSIN is driven from Signal Low to Signal High for each bit and back to Signal Low to start the next bit. The determination of whether the bit was a one or a zero is made by determining whether it spent more time low (a zero) or high (a one). The end of the word is signaled by a transition at the end of the last bit from Signal High to Idle. The advantage of this method is that it will accept data over a wide range of rates and is not dependent on an accurate clock. The controller will typically indicate a logic zero by spending 2/3 of the bit period at Signal Low and 1/3 at Signal High. A logic one would be 1/3 of the bit period at Signal Low and 2/3 at Signal High. CONTROL LOGIC The control logic performs the digital operations carried out by this device. Its principle functions include:
- Decoding input instructions.
- Control the general purpose I/O and LOGICOUT in response to BUSIN or BUSOUT commands.
- Control A/D conversions.
- Form response word.
- Capture and store address.
- Control BUSSW.
- Reset device on power-up.
- Control the general purpose I/O logic configuration.
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FUNCTIONAL INTERNAL BLOCK DESCRIPTION
- Read the general purpose I/O logic values and respond to request for these values.
- Generating a cycle redund ancy check (CRC) for the received data and transmitted data in conformance with the DSI Bus Standard. Additionally, the control logic performs error checking on the received data. If errors are found, no action is taken and no response is made. Errors include:
- CRC received doesn’t match CRC of received data.
- Number of received bits is not 12 or 20. CLOCK The clock is a low-stability type with the capacitor integrated onto the die. The signaling system and all internal operations are such that no external precision timing device is needed in the normal operation of this device. BUS SWITCH (BUSSW) The bus switch passes signaling and power to all subsequent devices on the bus. It can block a voltage of either polarity up to the highest idle state level between BUSIN and BUSOUT. LOGICOUT LOGICOUT is a logic level output with enhanced high-side drive capability. ADDRESSING The 33793 IC supports both runtime programmable and pre-programmed addressing as defined in the DSI Specification. Runtime programmable addressing uses the daisy chain bus connection. Pre-programmed devices may either be connected in daisy chain or in parallel on the bus wires. Programmable address devices all power up with a device address of $0 in their address register and their bus switches open. In the daisy chain, if the first device receives the initialization command device on BUSIN, it will accept the address in the command and close its switch at the end of the command. The next device in the chain will now be able to receive the initialization command on its BUSIN and will accept the next address. This proceeds down the chain until the last device is addressed. The devices can also be initialized by the reverse initialization command if the signal is applied to BUSOUT. Pre-programmed devices power up with their pre- programmed address in its address register. It will ignore all Initialization commands unless the address in the command matches its pre-programmed address. In this event the device stores the other information contained in the Initialization command.
marked reserved should not be sent to 33793 slaves. Table 6. DSI Bus Commands BS = Controls closing of the Bus Switch (1 = close). DR[3:0] = Direction of I/O. 1 = Output. G[1:0] = Group assignment (the 33793 does not use these bits). L[3:0] = Level to output on I/O if configured as outputs. PA[3:0] = Bus Address to set the device to. NV = Allows nonvolatile address programming if set to "1".
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Table 7 and a short-word response summary is found in Table 8, page 15. Table 7. Long-Word Response Summary
0 Initialization A3 A2 A1 A0 0 0 0 BF NV BS G1 G0 PA3 PA2 PA1 PA0
1 Request Status A3 A2 A1 A0 0 0 0 0 NV U LO BS IO3 IO2 IO1 IO0
2 Request Value 0 A3 A2 A1 A0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0
3 I/O Control A3 A2 A1 A0 0 0 0 0 L3 L2 L1 L0 DR3 DR2 DR1 DR0
4 Request ID A3 A2 A1 A0 0 0 0 0 V2 V1 V0 0 0 0 1 1
5 Request Value 1 A3 A2 A1 A0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0
6 Request Value 2 A3 A2 A1 A0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0
7 Clear No Response
8 Request Value 3 A3 A2 A1 A0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0
9 Read/Write NVM A3 A2 A1 A0 0 0 0 0 1 1 1 1 PA3 PA2 PA1 PA0
A[3:0] = Address bits. The slave address. BS = Status of the Bus Switch (1 = close). DR[3:0] = I/O direction bits (1 = Output). G[1:0] = Group assignment (the 33793 does not use these bits). IO[3:0] = Logic level of I/O. L[3:0] = Level to output on I/O if configured as outputs. LO = Logic Out level at the Logic Out pin. NV = Allows nonvolatile address programming if set to “1”. PA[3:0] = Bus Address to set the device to.
the next daisy chain device with its bus switch open. same as the first except that the NV bit is set to one. address in both PA3:PA0 and A3:A0 fields. received a Clear command or undergone a power-up reset. The command format is found in Table 9. Table 8. Short-Word Response Summary
0000 Initialization Not Valid
0001 Request Status NV U LO BS IO3 IO2 IO1 IO0
0010 Request Value 0 B7 B6 B5 B4 B3 B2 B1 B0
0011 I/O Control Not Valid
0100 Request ID Information V2 V1 V0 0 0 0 1 1
0101 Request Value 1 B7 B6 B5 B4 B3 B2 B1 B0
0110 Request Value 2 B7 B6 B5 B4 B3 B2 B1 B0
0111 Clear No Response
1000 Request Value 3 B7 B6 B5 B4 B3 B2 B1 B0
1001 Read/Write NVM Not Valid
1010 Reserved
1011 Reserved
1100 Clear Logic Out NV U LO BS IO3 IO2 IO1 IO0
1101 Set Logic Out NV U LO BS IO3 IO2 IO1 IO0
1110 Reserved
1111 Reverse Initialization Not Valid
BS = Status of the Bus Switch (1 = close). LO = Logic Out level at the Logic Out pin. IO[3:0] = Logic level of I/O. NV = Allows nonvolatile address programming if set to “1”. PA[3:0] = Bus Address to set the device to. Table 9. Initialization Command Format
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long-word only command, the short-word response is invalid. is generated if the command address field was $0. analog input measured is defined in Table 14. A[3:0] = Address bits. The slave address. BS = Bus Switch Position (1 = closed). G[1:0] = Group bits (unused). NV = Nonvolatile Memory Write. The value of the NV bit in the slave. PA[3:0] = Bus Address to set the device to. Table 10. Initialization Response Format A[3:0] = Address bits. The slave address. BF = Bus Fault. Bus out short to battery detected. BS = Bus Switch Position (1 = closed). G[1:0] = Group bits (unused). NV = Nonvolatile Memory Write. The value of the NV bit in the slave. PA[3:0] = Bus Address to set the device to. Table 11. Request Status Command Format address value of "0000" is ignored by all devices. Table 12. Request Status Response Format A[3:0] = Address bits. The slave address. BS = Bus Switch Position (1 = closed). LO = Logic out driven level. IO[3:0] = Values at logic I/Os. NV = Nonvolatile Memory Write. The value of the NV bit in the slave. U = Undervoltage indicated true by a “1”.
command. This is shown in Table 15. generated if the command address field was $0. outputs and their current values. Table 17. No response is generated if the command address field was $0. Table 13. Request Value n Command Format A[3:0] = Address bits. The address of the selected device. An address value of "0000" is ignored by all devices. Table 14. Analog Input Selection
0010 I/O0
0101 I/O1
0110 I/O2
1000 I/O3
Table 15. Request Values Response Format A[3:0] = Address bits. The address of the selected device. An address value of "0000" is ignored by all devices. D[7:0] = Measured value (MSB = D7). X[3:0] = Cyclic Redundancy Check (CRC). Table 16. I/O Control Command Format Table 17. I/O Control Response Format
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addressed device. The response format is found in Table 19. response is generated if the command address field was $0. Table 20. No response is generated for the Clear command. the programmed value during the next message time. DR[3:0] = I/O enabled as outputs (1 = enabled as output). Table 18. Request ID Command Format address value of “0000” is ignored by all devices. Table 19. Request ID Response Format A[3:0] = Address bits. The slave address. Table 20. Clear Command Format address value of “0000” clears all devices.
future NVM programming sequences. command format is found in Table 21. is generated if the command address field was $0. generated if the command address field was $0. Table 21. Read/Write NVM Command Format Table 22. Read/Write NVM Response Format A[3:0] = Address bits. The slave address. programmed into the NVM address bits of the slave. Table 23. Clear Logic Out Command Format Table 24. Clear Logic Out Response Format A[3:0] = Address bits. The slave address. BS = Bus Switch Position (1=closed). LO = Logic out driven level. IO[3:0] = Values at logic I/Os. NV = Nonvolatile Memory Write. The value of the NV bit in the slave. U = Undervoltage indicated true by a “1”.
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generated if the command address field was $0. the next daisy chain device with its bus switch open. same as the first except that the NV bit is set to one. address in both PA3:PA0 and A3:A0 fields. a Clear command or undergone a power-up reset. The command format is found in Table 27. Table 25. Set Logic Out Command Format Table 26. Set Logic Out Response Format A[3:0] - Address bits. The slave address. IO[3:0] = Values at logic I/Os. LO = Logic out driven level. NV = Nonvolatile Memory Write. The value of the NV bit in the slave. U = Undervoltage indicated true by a “1”. Table 27. Reverse Initialization Command Format
Table 28. Since address and must match the PA[3:0] bits. G[1:0] = Group bits. These bits are the group number for the slave. These bits are not used by this device and should be set to “0”. to be stored into the slave’s address register. been stored in the device, setting the NV bit to a one has no effect. Table 28. Reverse Initialization Response Format A[3:0] = Address bits.The slave address. BF = Bus Fault. BUSIN short to battery detected. BS = Controls closing of the Bus Switch (1=close). group number programmed into the slave. NV = Nonvolatile Memory Write. The value of the NV bit in the slave. PA[3:0] = Bus Address to set the device to.
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DSI messages are composed of individual words separated by a frame delay. Transfers are full duplex. Command messages from the master occur at the same time as responses from the slaves. Slave responses to commands occur during the next command message. This allows slaves time to decode the command, retrieve the information and prepare to send it to the master. A bus traffic example is shown in Figure 6. The example shows three commands separated by the minimum frame delay followed by a command after a longer delay. Figure 6. Bus Traffic Example IO0 H_CAP BUSOUT BUSRTN LOGOUT REGOUT IO1 IO2 IO3 BUSIN Rectifiers Bus Switch 0 – 35 V Bi-Directional Forward Receiver Reverse Receiver Data Frame Received Message from MCUBandgap Reference Data Frame Bandgap Reference 1.0 µF Typical Response Current 0 –11 mA 7.0 mA/µS Oscillator DataOut <3:0> DataOut <0> DataOut <1> DataOut <2> DataOut <3> I/O<3:0> I/O0 I/O1 I/O2 I/O3 SEL Logic Out High Current Buffer Address A<3:0> 4:1 MUX ADC 4.7 µF Bus Return Master Slave
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- Device will respond to further commands at address 0 (such as setting and clearing the I/O bits and LOGOUT) but there is no response (Master will read all zeros). If the devices are connected in a daisy chain, then only the fist device will respond.
- Subsequent writes to re-ini tialize the device will not be possible until the device is cleared.
Analog Integrated Circuit Device Data Freescale Semiconductor 25 33793 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EF SUFFIX (PB-FREE) 16-PIN PLASTIC PACKAGE 98ASB42566B ISSUE M
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REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 12.0 8/2006 • Implemented Revision History page
- Converted to Freescale format
- Added PC33793EF
- Added Feature bullets
- Rewrote and enhanced Device Operation - No electrical changes
- Updated to the prevailing Freescale form and style
- Removed PC33793EF and replaced with MCZ33793EF/R2 in the Ordering Information block 13.0 11/2006 • Added MCZ33793AEF/R2 to the Ordering Information
- Added Device Variations table on page 2
- Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5. Added note with instructions to obtain this information from www.freescale.com.
Rev 13.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2006. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
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