33399 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- Nominal Operation from V SUP 7.0 V to 18 V DC, Functional up to
27 V DC Battery Voltage and Capable of Handling 40 V During
- Active Bus Waveshaping to Minimize Radiated Emission
- ± 5.0 kV ESD on LIN Bus Pin, ± 4.0 kV ESD on Other Pins
- 3 0 kΩ Internal Pullup Resistor
- Ground Shift Operation and Ground Disconnection Fail-Safe at Module Level
- An Unpowered Node Does Not Disturb the Network
- 2 0 µA in Sleep Mode
- Wake-Up Capability from LIN Bus, MCU Command and Dedicated High Voltage Wake-Up Input (Interface to External Switch)
- Interface to MCU with CMOS-Compatible I/O Pins
- Control of External Voltage Regulator
- Pb-FREE packaging designated by package code EF
Figure 1. 33399 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MC33399D/R2 - 40°C to 125°C 8 SOICN MCZ33399EF/R2 D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B
8 PIN SOICN
5.0 V Regulator 33399 MCU VPWR INH EN TXD RXD VSUP WAKE GND LIN 12 V
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Figure 2. 33399 Simplified Internal Block Diagram
Figure 3. 33399 8-SOICN Pin Connections Table 1. 8-SOICN Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. 1 RXD Data Output MCU interface that reports the state of the LIN bus voltage. 2 EN Enable Control Controls the operation mode of the interface. 3 WAKE Wake Input High voltage input used to wake up the device from the Sleep mode. 4 TXD Data Input MCU interface that controls the state of the LIN output. 5 GND Ground Device ground pin. 6 LIN LIN Bus Bidirectional pin that represents the single-wire bus transmitter and receiver. 7 VSUP Power Supply Device power supply pin. 8 INH Inhibit Output Controls an external switchable voltage regulator having an inhibit input.
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ELECTRICAL CHARACTERISTICS
Table 2. Maximum Ratings permanent damage to the device.
- ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 220 pF, RZAP = 0 Ω).
- Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 33399 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
14 V < VSUP < 18 V
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STATIC ELECTRICAL CHARACTERISTICS LIN PIN (VOLTAGE EXPRESSED VERSUS VSUP VOLTAGE) Low-Level Bus Voltage (Dominant State) TXD LOW, VLIN = 40 mA VDOM 0.0 — 1.4 V High-Level Voltage (Recessive State) TXD HIGH, IOUT = 1.0 µA VREC
0.85 VSUP — —
V Internal Pullup Resistor to VSUP (4) - 40°C ≤ TA ≤ 70°C 70°C < TA ≤ 125°C RPU kΩ Current Limitation TXD LOW, VLIN = VSUP I LIM 50 150 200 mA Leakage Current to GND Recessive State, VSUP - 0.3 V ≤ VLIN ≤ VSUP (4) VSUP Disconnected, -18 V ≤ VLIN ≤ 18 V (Excluding Internal Pullup Source) VSUP Disconnected, VLIN = -18 V (Including Internal Pullup Source) VSUP Disconnected, VLIN = +18 V (Including Internal Pullup Source) I LEAK 0.0 - 40 - 600 µA LIN Receiver, Low-Level Input Voltage TXD HIGH, RXD LOW V LINL 0 VSUP — 0.4 VSUP V LIN Receiver, High-Level Input Voltage TXD HIGH, RXD HIGH V LINH
0.6 VSUP — VSUP
V LIN Receiver Threshold Center (VLINH - VLINL) / 2 V LINTH — VSUP/2 — V LIN Receiver Input Voltage Hysteresis VLINH - VLINL V LINHYS 0.05 VSUP — 0.15 VSUP V LIN Wake-Up Threshold Voltage V LINWU 3.5 4.5 6.0 V INH OUTPUT PIN High-Level Voltage (Normal Mode) VWUH VSUP - 0.8 — VSUP V Leakage Current (Sleep Mode) 0 < VINH < VSUP I LEAK 0 — 5.0 µA WAKE INPUT PIN Typical Wake-Up Threshold (EN = 0 V, 7.0 V ≤ VSUP ≤ 18 V) (5) HIGH-to-LOW Transition LOW-to-HIGH Transition VWUTH
0.3 VSUP
0.4 VSUP
0.43 VSUP
0.55 VSUP
0.65 VSUP
V Wake-Up Threshold Hysteresis VWUHYS 0.1 VSUP 0.16 VSUP 0.2 VSUP V WAKE Input Current VWAKE ≤ 14 V VWAKE > 14 V I WU 1.0 5.0 100 µA Notes 4. A diode structure is inserted with the pullup resistor to avoid parasitic current path from LIN to V SUP. 5. When V SUP is greater than 18 V, the wake-up voltage thresholds remain identical to the wake-up thresholds at 18 V. Table 3. Static Electrical Characteristics (continued) values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33399 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
- Measured between 20 and 80 percent of bus signal for 10 V < VSUP < 18 V. Between 30 and 70 percent of signal for
- t TXDLINL is measured from TXD (HIGH-to-LOW) and LIN (VREC - 0.2 V). t TXDLINH is measured from TXD (LOW-to-HIGH) and LIN
- Measured between LIN receiver thresholds and RXD pin.
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Figure 4. Normal Mode Bus Timing Characteristics Figure 5. LIN Rise and Fall Time Figure 6. LIN Bus Wake-Up
0.6 VSUP
0.2 VSUP
0.8 VSUP
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The 33399 is a Physical Layer component dedicated to automotive LIN sub-bus applications. The 33399 features include speed communication from 1.0 kbps to 20 kbps, up to 60 kbps for Programming Mode, and active bus waveshaping to minimize radiated emission. The device offers three different wake-up capabilities: wake-up from LIN bus, wake-up from the MCU command, and dedicated high voltage wake-up input. The INH output may be used to control an external voltage regulator. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY PIN (VSUP) The VSUP power supply pin is connected to a battery through a serial diode for reverse battery protection. The DC operating voltage is from 7.0 V to 27 V. This pin sustains standard automotive voltage conditions such as 27 V DC during jump-start conditions and 40 V during load dump. To avoid a false bus message, an undervoltage reset circuitry disables the transmission path (from TXD to LIN) when VSUP falls below 7.0 V. Supply current in the Sleep mode is typically 20 µA. GROUND PIN (GND) In case of a ground disconnection at the module level, the 33399 does not have significant current consumption on the LIN bus pin when in the recessive state. (Less than 100 µA is sourced from LIN bus pin, which creates 100 mV drop voltage from the 1.0 kΩ LIN bus pullup resistor.) For the dominant state, the pullup resistor should always be active. The 33399 handles a ground shift up to 3.0 V when VSUP > 9.0 V. Below 9.0 V VSUP, a ground shift can reduce VSUP value below the minimum VSUP operation of 7.0 V. LIN BUS PIN (LIN) The LIN bus pin represents the single-wire bus transmitter and receiver. Transmitter Characteristics The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated so no external pullup components are required for the application in a slave node. An additional pullup resistor of 1.0 kΩ must be added when the device is used in the master node. Voltage can go from - 18 V to 40 V without current other than the pullup resistance. The LIN pin exhibits no reverse current from the LIN bus line to V SUP, even in the event of GND shift or VPWR disconnection. LIN thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant and the rise time from dominant to recessive are controlled to typically 2.0 V/µs. The symmetry between rise and fall time is also guaranteed. When going from dominant to recessive, the bus impedance parasitic capacitor must be charged up to VSUP. This charge-up is achieved by the total system pullup current resistors. In order to guarantee that the rise time is within specification, maximum bus capacitance should not exceed nF with bus total pullup resistance less than 1.0 kΩ. Receiver Characteristics The receiver thresholds are ratiometric with the device supply pin. Typical threshold is 50%, with a hysteresis between 5% and 10% of VSUP. DATA INPUT PIN (TXD) The TXD input pin is the MCU interface that controls the state of the LIN output. When TXD is LOW, LIN output is LOW; when TXD is HIGH, the LIN output transistor is turned OFF. This pin has an internal 5.0 V internal pullup current source to set the bus in a recessive state in case the MCU is not able to control it; for instance, during system power-up/ power-down. During the Sleep mode, the pullup current source is turned OFF. DATA OUTPUT PIN (RXD) The RXD output pin is the MCU interface that reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high level on RXD; LIN LOW (dominant) is reported by a low voltage on RXD. RXD output structure is a CMOS-type push-pull output stage. ENABLE INPUT PIN (EN) The EN pin controls the operation mode of the interface. If EN = logic [1], the interface is in normal mode, with the transmission path from TXD to LIN and from LIN to RXD both active. If EN = logic [0], the device is in Sleep mode or low power mode, and no transmission is possible. In Sleep mode, the LIN bus pin is held at VSUP through the bus pullup resistors and pullup current sources. The device can transmit only after being awakened. Refer to the INHIBIT OUTPUT PIN (INH) description on page 11. During Sleep mode, the device is still supplied from the battery voltage (through VSUP pin). Supply current is 20 µA typical. Setting the EN pin to LOW will turn the INH to high impedance. The EN pin has an internal 20 µA pulldown current source to ensure the device is in Sleep mode if EN floats.
Analog Integrated Circuit Device Data Freescale Semiconductor 11 33399 FUNCTIONAL DESCRIPTION TIMING DIAGRAMS INHIBIT OUTPUT PIN (INH) The INH pin controls an external switchable voltage regulator having an inhibit input. This pin is a high-side switch structure to VSUP. When the device is in the Normal mode, the inhibit high-side switch is turned ON and the external voltage regulator is activated. When the device is in Sleep mode, the inhibit switch is turned OFF and disables the voltage regulator (if this feature is used). A wake-up event on the LIN bus line will switch the INH pin to VSUP level. Wake-up output current capability is limited to 280 µA. INH can also drive an external MOSFET connected to an MCU IRQ or XIRQ input to generate an interrupt. See the typical application illustrated in Figure 13, page 15. WAKE INPUT PIN (WAKE) The WAKE pin is a high-voltage input used to wake up the device from Sleep mode. WAKE is usually connected to an external switch in the application. The typical WAKE thresholds are VSUP / 2. The WAKE pin has a special design structure and allows wake-up from both HIGH-to-LOW or LOW-to-HIGH transitions. When entering the Sleep mode, the LIN monitors the state of the WAKE pin and stores it as a reference state. The opposite state of this reference state will be the wake-up event used by the device to re-enter Normal mode. An internal filter is implemented (50 µs typical filtering time delay). The WAKE pin input structure exhibits a high impedance with extremely low input current when voltage at this pin is below 14 V. When voltage at the WAKE pin exceeds 14 V, input current starts to sink into the device. A series resistor should be inserted in order to limit the input current, mainly during transient pulses. Recommended resistor value is 33 kΩ. Important The WAKE pin should not be left open. If the wake-up function is not used, WAKE should be connected to GND to avoid false wake-up.
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and sleep, and one transitional mode, Awake.
- LIN bus activity
- Internal node wake-up (EN pin)
- Wake-up from WAKE pin Figures 7, 8, and 9 on page 9 show device application circuit and detail of wake-up operations. Wake-Up from LIN Bus (Awake Transitional Mode) A wake-up from the LIN pin switching from recessive to dominant state (switch from VSUP to GND) can occur. This is achieved by a node sending a wake-up frame on the bus. This condition internally wakes up the interface, which switches the INH pin to a HIGH level to enable the voltage regulator. The device switches into the Awake mode. The microcontroller and the complete application power up. The microcontroller must switch the EN pin to a HIGH level to allow the device to leave the Awake mode and turn it into Normal mode in order to allow communication on the bus. Wake-Up from Internal Node Activity (Normal Mode) The application can internally wake up. In this case the microcontroller of the application sets the EN pin in the HIGH state. The device switches into Normal mode. Wake-Up from WAKE Pin (Awake Transitional Mode) The application can wake up with the activation of an external switch. Refer to Table 1, 8-SOICN Pin Definitions on page 3.
Figure 10. Operational and Transitional Modes State Diagram Note Refer to Table 5 for explanation.
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additional pullup resistor of 1.0 kΩ in series with a diode must be added when the device is used in the master node. Figure 12. Slave Node Typical Application with WAKE Input Switch and INH
Figure 13. Master Node Typical Device Application with MCU Wake-Up from Stop Mode
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Table 6. Reference Documents
Analog Integrated Circuit Device Data Freescale Semiconductor 17 33399 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below. D SUFFIX EF SUFFIX (Pb-FREE) 8-PIN SOIC NARROW BODY PLASTIC PACKAGE 98ASB42564B ISSUE U
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REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 7.0 7/2006 • Implemented Revision History page
- Added Pb-Free suffix code EF
- Added EPP ordering part number MCZ33399EF/R2
- Adjusted to the Freescale prevailing form and style 8.0 10/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from MAXIMUM RATINGS on page 4. Added note with instructions to obtain this information from www.freescale.com.
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