33390 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • Designed for SAE J-1850 Class B Data Rates
  • Full Operational Bus Dynamics Over a Supply Voltage of 9.0 to 16 V
  • Ambient Operating Temperature of -40 °C to 125°C
  • Interfaces Directly to Standard 5.0 V CMOS Microcontroller
  • BUS Pin Protected Against Shorts to Battery and Ground
  • Thermal Shutdown with Hysteresis
  • Voltage Waveshaping of Bus Output Driver
  • 40 V Max V BAT Capability
  • Pb-Free Packaging Designated by Suffix Code EF

Figure 1. 33390 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33390D/DR2 -40°C to 125°C 8 SOICN MCZ33390EF/R2 33390 Primary Node Secondary Nodes MCU VPWR +VBAT SLEEP TX RX 4X/Loop GND BUS LOAD

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Figure 2. 33390 Simplified Internal Block Diagram Note This device contains approximately 400 active transistors and 250 gates.

Figure 3. 33390 Pin Connections Table 1. 33390 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 9. 1 SLEEP Enables the transceiver when Logic 1 and disables the transceiver when Logic 0. 3 LOAD Accommodates an external pull-down resistor to ground to provide loss of ground protection. 4 BUS Waveshaped SAE Standard J-1850 Class B transmitter output and receiver input. 5 VBAT Provides device operating input power. transmitting, high impedance = loopback mode. 7 TX Serial data input (DI) from the microcontroller to be transmitted onto Bus. 8 RX Bus received serial data output (DO) sent to the microcontroller.

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ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

  1. An external series diode must be used to provide reverse battery protection of the device.
  2. SLEEP, TX, RX, and 4X / LOOP are normally connected to a microcontroller.
  3. ESD1 testing is performed in accor dance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in

accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

  1. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

  1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33390 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted. into the pin. All negative currents are out of the pin.

0 V ≤ VBUS ≤ VBAT

  1. Typical threshold value is the approximate actual occurring switch point value with VBAT = 13 V, TA = 25°C.
  2. Device characterized but not production tested for thermal shutdown.
  3. Device characterized but not production tested for thermal shutdown hysteresis.

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STATIC ELECTRICAL CHARACTERISTICS BUS (CONTINUED) LOAD Output IL = 6.0 mA LON – 0.07 0.2 V Unpowered LOAD Output VBAT = 0 V, IL = 6.0 mA LDIO 0.3 0.56 0.9 V TX Tx Input Voltage Tx Input Logic Low Level Tx Input Logic High Level VTx(IL) VTx(IH) 3.5 0.8 V Tx Input Current VTx = 5.0 V VTx = 0 V ITx(IH) ITx(IL) -2.0 106 0.23 200 2.0 µA LOOP 4X / LOOP Input Current V4X / LOOP = 0 V (Normal Mode) V4X / LOOP = 5.0 V (4X Mode) I4X / LOOP(IL) I4X / LOOP(IH) -200 -200 -60 110 200 200 µA 4X / LOOP Input Threshold (Tx = 4096 Hz Square Wave) Normal Mode to Loopback Mode Loopback Mode to 4X Mode V4X / LOOP(IL) V4X / LOOP(IH) 1.1 3.2 1.31 3.43 1.5 3.6 V RX Rx Output Voltage Low VBUS = 0 V, IRx = 1.6 mA VRx (LOW) 0.01 0.18 0.4 V Rx Output Voltage High VBUS = 7.0 V, IRx = -200 µA VRx(HIGH) 4.25 4.58 4.75 V Rx Output Current VRx = High; Short Circuit Protection Limits IRx 2.0 3.67 8.0 mA SLEEP SLEEP Input Current VSLEEP = 0 V VSLEEP = 5.0 V ISLEEP (IL) ISLEEP (IH) 1.0 -0.23 6.21 -2.0 µA Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted. into the pin. All negative currents are out of the pin.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33390 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted. into the pin. All negative currents are out of the pin.

  1. Typical is the parameter's approximate average value with V BAT = 13 V, TA = 25°C.
  2. Rx Output Transition Time from a sleep state.

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ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES TEST FIGURES Figure 4. Loss of Ground or VBAT Test Circuit Figure 5. BUS Rise and Fall Times Figure 6. Pulse Width Distortion Figure 7. SLEEP to Tx Delay Times Figure 8. BUS-to-Rx Delay Time Figure 9. Rx Rise and Fall Time

1.5 V tPWD(MAX

3.875 VtTxDelay

plastic package makes the device a cost-effective solution. to establish the Rx output level and slew rate times.

2.0 V ground

given by the expressions shown in Table 5, page 10. Figure 10. Minimum Bus Load Figure 11. Maximum Number of Nodes Figure 12. Maximum Bus Load

24 Secondary Nodes

31 Secondary Nodes

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Table 5. Class B Bus Capacitance and Resistance Expressions

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33390 TYPICAL APPLICATIONS TYPICAL APPLICATIONS Class B Module Inputs Transmitter Data from the MCU (Tx) The Tx input is a push-pull (N-channel / P-channel FETs) buffer with hysteresis for noise immunity purposes. This pin is a 5.0 V CMOS logic level input from the MCU following a true logic protocol. A logic [0] input drives the BUS output to

0 V (via the external pull-down resistor to ground on each

node), while a logic [1] input produces a high voltage at the BUS output. A logic [0] input level is guaranteed when the Tx input pin is open-circuited by virtue of an internal 40 kΩ pull- down resistor. No external resistor is required for its operation. Waveshaping and 4X / Loop This input is a tristateable input: 0 V = normal waveshaping, 5.0 V = waveshaping is disabled for 4X transmitting, and high impedance = loopback mode of operation. This is a logic level input used to select whether waveshaping for the Class B output is enabled or disabled. A logic [0] enables waveshaping, while a logic [1] disables waveshaping. In the 4X mode, the BUS output rise time is less than 2.0 µs and the fall time is less than 5.0 µs (owing to the external RC pull-down to ground). In the loopback condition, the Tx signal is fed back to the Rx output after waveshaping without being transmitted onto the BUS. This mode of operation is useful for system diagnostic purposes. Class B Module Outputs Transceiver Output (BUS) This is the output driver stage that sources current to the bus. Its output follows the waveshaped waveform input. Its output voltage is limited to 6.25 V to 8.0 V under normal battery level conditions. The limited level is controlled by an internal regulator/clamp circuit. Once the battery voltage drops below 9.0 V, the regulator / clamp circuit saturates, causing the bus voltage to track the battery voltage. A 1.5 kΩ ± 5% external resistor (as well as any 10.6 kΩ pull-down resistors of any secondary nodes) sinks the current to discharge the capacitors during high-to-low transitions. This sourcing output is short circuit-protected (60 mA to 170 mA) against a short to -2.0 V and sinks less than 1.0 mA when shorted to VBAT. If a short occurs, the overtemperature shutdown circuit protects the source driver of the device. In the event battery power is lost to the assembly, the bus transmitter's output stage will be disabled and the leakage current from the BUS output will not source or sink more than 100 µA of current. The transceiver will operate with a remote ground offset of ± 2.0 V, but the lower corners of transmission will not be rounded during this condition. Receiver Output to the Microcontroller (Rx) This is a 5.0 V CMOS compatible push-pull output used to send received data to the microcontroller. It does not require an external pull-up resistor to be used. The receiver is always enabled and draws less than 65 µA of current from VBAT. The receive threshold is dependent on the state of the SLEEP pin. The receiver circuitry is able to operate with VBAT voltages as low as 4.25 V and still remains capable of “waking up” the 33390 when remote Class B activity is detected. When the SLEEP pin is 0 V and message activity occurs on the bus, the receiver passes the bus message through to the microcontroller. The 33390 does not automatically “wake up” from a sleep state when bus activity occurs: the microcontroller must tell it to do so. In the Static Electrical Characteristics table, the maximum voltage for Rx is specified as 4.75 V over an operating range of -40°C to 125°C temperature and 7.0 V to 16 V VBAT. This maximum Rx voltage is compatible with the minimum VDD voltage of microcontrollers to prevent the 33390 from sourcing current to the microcontroller's output. Switched Ground Output (LOAD) Normally this output is a saturated switch to ground, which pulls down the external resistor between the BUS and LOAD outputs. In the event ground is lost to the assembly, the LOAD output will bias itself “off” and will not leak more than 100 µA of current out of this pin. Overtemperature Shutdown If the BUS output becomes shorted to ground for any duration, an overtemperature shutdown circuit “latches off” the output source transistor whenever the die temperature exceeds 150°C to 190°C. The output transistor remains latched off until the Tx input is toggled from a logic [0] to a logic [1]. The rising edge provides the clearing function, provided the locally sensed temperature is 10°C to 15°C below the latch-off temperature trip temperature. Waveshaping Waveshaping is incorporated into the 33390 to minimize radiated EMI emissions. Receiver Protocol The Class B communication scheme uses a variable pulse width (VPW) protocol. The microcontroller provides the VPW decoding function. Once the receiver detects a transition on Rx, it starts an internal counter. The initial “start of frame” bit is a logic [1] and lasts 200 µs. For subsequent bits, if there is a bus transition before 96 µs, one logic state is inferred. If there is a bus transition after 96 µs, the other logic state is inferred. The “end of data” bit is a logic [0] and lasts 200 µs. If there is no activity on the bus for 280 µs to 320 µs following a broadcast message, multiple unit nodes may arbitrate for control of the next message. During an arbitration, after the

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“start of frame” bit has been transmitted, the secondary node transmitting the most consecutive logic [0] bits will be granted sole transmission access to the bus for that message. Loss of Assembly Ground Connection The definition of a loss of assembly ground condition at the device level is that all pins of the 33390, with the exception of BUS and LOAD, see a very low impedance to VBAT. The LOAD pin of the device has an internal transistor switch connected to it that is normally saturated to ground. This pulls the LOAD-side of the external resistor (tied from BUS to LOAD) to ground under normal conditions. The LOAD pin switch is essentially that of an “upside down” FET, which is normally biased “on” so long as module ground is present and biased “off” when loss-of-ground occurs. When a loss of assembly ground occurs, the load transistor switch is self- biased “off”, allowing no more than 100 µA of leakage current to flow in the LOAD pin. During such a loss of assembly ground condition, the BUS and LOAD pins exhibit a high impedance to V BAT; all other pins will exhibit a low impedance to VBAT. During this condition the BUS pin is prevented from sourcing any current or loading the bus, which would cause a corruption of any data being transmitted on the bus. While a particular assembly is experiencing a loss of ground, all other assembly nodes are permitted to function normally. It should be noted that with other nodes existing on the bus, the bus will always have some minimum / maximum impedance to ground as shown in Table 5, page 10. Loss of Assembly Battery Connection The definition of a loss of assembly battery condition at the device level is that the VBAT pin of the 33390 sees an infinite impedance to VBAT, but there is some undefined impedance between these pins and ground.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33390 TYPICAL APPLICATIONS PACKAGE DIMENSIONS PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98A listed below. EF SUFFIX (PB-FREE) 8-LEAD SOIC NARROW BODY PLASTIC PACKAGE 98ASB42564B ISSUE U

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REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 5.0 4/2006 • Converted to Freescale format

  • Implemented revision history page.
  • Added Part Numbers MC33390EF/EFR2 to Ordering Information on Page 1. 6.0 10/2006 • Updates document form and style
  • Removed MC33390EF and replaced with MCZ33390E F in the number Ordering Information 7.0 11/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com.

Rev 7.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

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