MC33298 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • Designed to Operate Over Wide S upply Voltages of 5.5 to 26.5 V
  • Interfaces to Microprocessor Usi ng 8-Bit SPI I/O Protocol up to

3.0 MHz

  • 1.0 A Peak Current Outputs with Maximum R DS(on) of 1.6 Ω at TJ - 150°C
  • Outputs Current Limited to Accommodate In-rush Curr ents Associated with Switching Incandescent Loads
  • Output Voltages Clamped to 53 V During Inductive Switching
  • Maximum Sleep Current (I PWR) of 25 µA
  • Maximum of 4.0 mA I DD During Operation
  • Pb-Free Packaging Designated by Suffix Code EG

Figure 1. 33298 Simplified Application Diagram

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ORDERING INFORMATION

Range (TA) Package MC33298DW/R2 -40°C to 125°C 24 SOIC MCZ33298EG/R2 MCU 33298 VDD V PWR SFPD CS SCLK SI RESET SO VDD VPWR OP 0 OP 1 OP 2 OP 3 OP 4 OP 5 OP 6 OP 7 GND

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Figure 2. 33298 Simplified Block Diagram Table 1. Fault Operation Overvoltage Total device shutdown at VPWR = 28 to 36 V. All outputs are latched off while the SPI register is reset (cleared). Outputs can be turned back on with a new SPI command after VPWR has decayed below 26.5 V. Overtemperature Only the output experiencing an overtemperature condition turns off. pin is at 5.0 V (so long as the individual outputs are not experiencing thermal limit conditions).

Figure 3. 33298 Pin Connections Table 2. 33298 Pin Function Description 1 OP7 Output 7 This pin provides connection to drain of output MOSFET number seven. 2 OP6 Output 6 This pin provides connection to drain of output MOSFET number six. 3 SCLK System Clock This pin clocks the internal Shift registers of the 33298. 5 GND Ground This pin provides connection to IC Power Ground and functions as part of heat sinking path. 6 GND Ground This pin provides connection to IC Power Ground and functions as part of heat sinking path. 7 GND Ground This pin provides connection to IC Power Ground and functions as part of heat sinking path. 8 GND Ground This pin provides connection to IC Power Ground and functions as part of heat sinking path. 9 SO Serial Output This pin is the tri-stateable output from the Shift register. through the SI pin and from the 33298 to the MCU through the SO pin. 11 OP5 Output 5 This pin provides connection to drain of output MOSFET number five. 12 OP4 Output 4 This pin provides connection to drain of output MOSFET number four. 13 OP3 Output 3 This pin provides connection to drain of output MOSFET number three. 14 OP2 Output 2 This pin provides connection to drain of output MOSFET number two.

15 SFPD Short Fault

16 VDD Logic Supply Logic Supply. 17 GND Ground This pin provides connection to IC Power Ground and functions as part of heat sinking path. 18 GND Ground This pin provides connection to IC Power Ground and functions as part of heat sinking path. 19 GND Ground This pin provides connection to IC Power Ground and functions as part of heat sinking path. 20 GND Ground This pin provides connection to IC Power Ground and functions as part of heat sinking path. 21 VPWR Power Output MOSFET Gate Drive Supply.

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23 OP1 Output 1 This pin provides connection to drain of output MOSFET number one. 24 OP0 Output 0 This pin provides connection to drain of output MOSFET number zero. Table 2. 33298 Pin Function Description (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33298

ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings permanent damage to the device.

  1. Transient capability with external 100 Ω resistor in series with VP pin and supply.
  2. Exceeding these limits may cause a malf unction or permanent damage to the device.
  3. Exceeding the limits on SCLK, SI, CS, SFPD, or RST pins may cause permanent damage to the device.
  4. Continuous output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature

will require maximum output current computation using package RθJA.

  1. ESD data available upon request.
  2. ESD1 testing is performed in accordance with the Human Body Model (C Zap = 200 pF, RZap = 1500 Ω), ESD2 testing is performed in

accordance with the Machine Model (CZap = 200pF, RZap = 0 Ω).

  1. Maximum output clamp energy capability at 150 °C junction temperature using a single non-repetitive pulse method.
  2. Guaranteed and production tested for 2.0 MHz SPI operation, but demonstrated to operate to 8.5 MHz at 25 °C.
  3. Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

  1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standerd J-STD-020C. For Peak Package Reflow

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Table 4. Maximum Ratings (continued) permanent damage to the device.

  1. See Figure 20 for Thermal model.
  2. Soldering temperature limit is for 10 seconds maximum durati on; not designed for immersion soldering; exceeding these limits may
  3. Thermal resistance from Junction-to-Ambient with all outputs ON and dissipating equal power.
  4. Thermal resistance from Junction -to-Ambient with a single output ON.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33298 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate value with VBat = 13 V, TA = 25°C.

  1. SPI inputs and outputs operational; Fault status reporting may not be fully operational within this voltage range.
  2. Value reflects normal operation (no faults) with all output s ON. Each ON output contributes approximately 20 µA to IPWR. Each output

output source current to self-limit. A hard output short is a very low impedance short to supply.

  1. For V DD less than the Under Voltage Lockout Threshold voltage, all data registers are reset and all outputs are disabled.
  2. Output Fault Detect Threshold with outputs programmed OFF. Output fault detect thresholds are the same for output opens and shorts.
  3. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an

open load condition when the specific output is commanded to be OFF.

  1. Output leakage current measured with the output OFF and at 16 V.

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STATIC ELECTRICAL CHARACTERISTICS Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate value with VPWR = 13 V, TA = 25°C.

  1. This parameter is guaranteed by desig n, but it is not production tested.
  2. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, and SFPD inputs.
  3. Lower logic threshold voltage range applies to SI, CS, SCLK, Reset, and SFPD input signals.
  4. Only the SFPD and Reset inputs have hysteresis. This paramet er is guaranteed by design, but it is not production tested.
  5. Input current of SCLK, SI and CS logic control inputs.
  6. Input capacitance of SI, CS, SCLK, RST, and SFPD for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not
  7. Tri-state capacitance of SO for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33298 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 7. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

  1. Output Rise and Fall time respectively measured across a 26 Ω resistive load at 10 to 90 percent, and 90 to 10 percent voltage points.
  2. Output Turn ON Delay time measured from 50 percent rising edge of CS to 90 percent of Output OFF voltage (VPWR) with RL = 26 Ω
  3. Output Turn OFF Delay time meas ured from 50 percent rising edge of CS to 10 percent of Output OFF voltage (VPWR) with RL = 26 Ω
  4. Output Short Fault Delay time m easured from rising edge of CS to IOUT -= 2.0 A point with output ON, VOUT = 5.0 V, and SFPD = 0.2

x VDD. See Figures 8 and 10.

  1. Output OFF Fault Report Delay measured from 50 percent rising edge of CS to rising edge of output. See Figure 9.
  2. Clock period include 75 ns rise plus 75 ns fall transition in addition to clock high and low time.
  3. RST Low duration measured with outputs enabled and going to OFF or disabled condition.
  4. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
  5. Time required for output status data to be available for use at the SO pin.
  6. Time required for output status data to be terminated at the SO pin.

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DYNAMIC ELECTRICAL CHARACTERISTICS Time from Rising Edge of SCLK to SO Data Valid (39) 0.2 VDD < SO > 0.8 VDD, CL = 200 pF tVALID — 50 125 ns Notes 39. Time required to obtain valid data out from SO following the rise of SCLK. See Figure 5. Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33298 Figure 4. Input Timing Switch Characteristics Figure 5. Valid Data Delay Time and

0.2 VDD

0.7 VDD

CL represents the total capacitance of the test fixture and probe.

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ELECTRICAL PERFORMANCE CURVES Figure 7. Valid Data Delay Time and Figure 8. Enable and Disable Time Waveforms Figure 9. Switching Time Test Circuit Figure 10. Output Fault Unlatch Disable

0.2 VDD 0

  1. SO (high-to-low) waveform is for SO output with internal conditions such

tecting a circuit fault with CS in a High Logic state, e.g. open load.

  1. SO (low-to-high) waveform is for SO output with internal conditions such

tecting a circuit fault with CS in a High Logic state, e.g. shortened load. CL represents the total capacitance of the test fixture and probe. CL ρεπρεσεντσ τηε τοταλ χαπαχιτανχε οφ τηε τεστ φιξτυρε ανδ προβε.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33298 ELECTRICAL PERFORMANCE CURVES Figure 11. Turn-On/Off Waveforms Figure 12. Output Fault Unlatch Disable

  1. tDLY(ON) and tDLY(OFF) are turn-on and turn-off propagation delay
  2. Turn-off is an output programmed from an ON to an OFF state.
  3. Turn-on is an output programmed from and OFF to an ON state.
  4. tPDLY(OFF) is the output fault unlatch disable propagation delay time re-

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diagram delineates 33298 in Figure 1. economically incorporated into the monolithic design. turn-off and transient protection. technology and would not be possible with bipolar structures. hundreds of milliamperes of internal bias and control current. consumed by the device itself and not available for load use. basic SPI configuration between an MCU and one 33298. Figure 13. SPI Interface with Microcontroller controlled will be high and turned OFF.

Figure 14. 33298 SPI System Daisy Chain together, forming a larger system, illustrated in Figure 12. to control 32 possible loads. dedicated parallel MCU ports used for chip select. Figure 15. Parallel Input SPI Control detects a logic low state on its SS pin. communicate efficiently with the MCU. means of expanding the I/O function using few MCU pins.

  • Full duplex, three-wire synchronous data transfer
  • Each microcontroller can be a master or a slave
  • Provides write collision flag protection
  • Provides end of message interrupt flag
  • Four I/Os associated with SPI (MOSI, MISO, SCLK, SS) Drawbacks to SPI are:
  • An MCU is required for efficient operational control
  • In contrast to parallel input control it Is slower at performing pulse width modulating (PWM) functions. SCLK Parallel Port MISO MOSI IRQ MC68XX Microcontroller SPI SO SOSOSO CS CSCSCSSCLK SCLKSCLK SCLK SI SISISI 33298 33298 3329833298

8 Outputs 8 Outputs8 Outputs8 Outputs

8 Outputs

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Figure 16. Multiple MCU SPI Control controls the output driver of the serial output (SO) pin. out of the SO line driver on the rising edge of the SCLK signal.

from a low-to-high logic state. the status of the Reset pin. the MCU to control the 33298 Reset pin. Figure 17. Power ON Reset circuit will immediately shut down only the output affected. the current limit), adds 0.5 mA to the IPWR current. device can even be operated with all outputs tied together. capability of switching higher currents.

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limiting of eight to 24 A will result if all outputs are paralleled together. There will be no change in the over voltage detect or the OFF output threshold voltage range. The advantage of paralleling outputs within the same 33298 affords the existence of minimal R DS(ON) and output clamp voltage variation between outputs. Typically, the variation of RDS(ON) between outputs of the same device is less than 0.5 percent. The variation in clamp voltages, potentially affecting dynamic current sharing, is less than five percent. Paralleling outputs from two or more different devices is possible, but it is not recommended. There is no guarantee the R DS(ON) and clamp voltage of the two devices will match. System level thermal design analysis and verification should be conducted whenever paralleling outputs; particularly where different devices are involved.

Figure 18. Data Transfer TimingSO NOTES: 1.Reset pin is in a logic high-state during the above operation. 4.OD* corresponds to Old Databits. 5.For brevity, only DO7 and DO0 are shown which respectively correspond to Output 7 and Output 0. SO pin is enabled. Output Status information transferred to Output Shift Register. Data from the Shift Register is transferred to the Output Power Switches. Will change state on the rising edge of the SCLK pin signal. Will accept data on the falling edge of the SCLK pin signal.

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The MCU can perform a parity check of the fault logic operation by comparing the command 8-bit word to the status 8-bit word. Assume after system reset, the MCU first sends an 8-bit command word to the 33298. This word is called Command Word 1. Each output to be turned ON will have its corresponding data bit low. Refer to the data transfer timing illustration in Figure 16. As Command Word 1 is being written into the Shift register of the 33298, a status word is being simultaneously written and received by the MCU. However, the word being received by the MCU is the status of the previous write word to the 33298, Status Word 0. If the command word of the MCU is written a second time (Command Word 2 = Command Word 1), the word received by the MCU, Status Word 2, is the status of Command Word 1. The timing diagram illustrated in Figure 16 depicts this operation. Status Word 2 is then compared with Command Word 1. The MCU will Exclusive OR Status Word 2 with Command Word 1 to determine if the two words are identical. If the two words are identical, faults do not exist. The timing between the two write words must be greater than 100 µs to receive proper drain status. The system data bus integrity may be tested by writing two like words to the 33298 within a few microseconds of each other. INITIAL SYSTEM SETUP TIMING The MCU can monitor two kinds of faults: 1. Communication errors on the data bus 2. Actual faults of the output loads After initial system start up or reset, the MCU will write one word to the 33298. If the word is repeated within approximately five microseconds of the first word, the word received by the MCU, at the end of the repeated word, serves as a confirmation of data bus integrity (1). At start up, the 33298 will take 25 to 100 µs before a repeat of the first word should be repeated at least 100 µs later to verify the status of the outputs. The SO of the 33298 will indicate any one of four faults. The four possible faults are: 1. Over Temperature 2. Output OFF Open Fault 3. Short Fault (over current) 4. V PWR Over Voltage Fault. All of these faults, with the exception of the Over Voltage Fault, are output specific. Over Temperature Detect, Output OFF Open Detect, and Output Short Detect are dedicated to each output separately such that the outputs are independent in operation. A VPWR Over Voltage Detect is a global nature causing all outputs to be turned OFF. OVER TEMPERATURE FAULT Patent pending Over Temperature Detect and shutdown circuits are specifically incorporated for each individual output. The shutdown following an Over Temperature condition is independent of the system clock and other logic signal. Each independent output shuts down at 155°C to 185°C. When an output shuts down due to an Over Temperature Fault, no other outputs are affected. The MCU recognizes the fault since the output was commanded to be ON and the status word indicates it is OFF. A maximum hysteresis of 20°C ensures an adequate time delay between output turn OFF and recovery. This avoids a very rapid turn ON and turn OFF of the device around the Over Temperature threshold. When the temperature falls below the recovery level for the Over Temperature Fault, the device will turn on only if the Command Word during the next write cycle indicates the output should be turned ON. OVER VOLTAGE FAULT An Over Voltage condition on the VPWR pin causes the 33298 to shut down all outputs until the over voltage condition is removed and the device is re-programmed by the SPI. The over voltage threshold on the VPWR pin is specified as 28 V to 36 V with 1.0 V typical hysteresis. Following the over voltage condition, the next write cycle sends the SO pin the hexadecimal word $FF (all ones) indicating all outputs are turned off. In this way, potentially dangerous timing problems are avoided and the MCU reset routine ensures an orderly startup of the loads. The 33298 does not detect an over voltage on the V DD pin. Other external circuitry, such as a universal voltage monitor, is necessary to accomplish this function. OUTPUT OFF OPEN LOAD FAULT An Output OFF Open Load Fault is the detection and reporting of an open load when the corresponding output is disabled (input in a logic high state). To understand the operation of the Open Load Fault detect circuit; see Figure 17. The Output OFF Open Load Fault is detected by comparing the drain voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose.

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current limited mode until either the short circuit (over current) condition is removed or thermal shutdown is reached. Grounding the SFPD pin enables the short fault protection shutdown circuitry. Consider a load short (output short to supply) occurring on an output before, during, and after output turn ON. When the CS signal rises to the high logic state, the corresponding output is turned ON, activating a delay timer. The duration of the delay timer is 70 to 250 µs. If the short circuit takes place before the output is turned ON, the delay experienced is the entire 70 µs to 250 µs followed by shutdown. If the short occurs during the delay time, the shutdown still occurs after the delay time has elapsed. However, if the short circuit occurs after the delay time, shutdown is immediate (within 20 µs after sensing). The purpose of the delay timer is to prevent false faults from being reported when switching capacitive loads. If the SFPD pin is at 5.0 V, or VDD, an output will not be disabled when an over current is detected. The specific output will, within 5.0 to 10 µs of encountering the short circuit, go into an analog current limited mode. This feature is especially useful when switching incandescent lamp loads, where high in-rush currents experienced during startup last for 10 to 20 milliseconds. Each output of the 33298 has its own over current shutdown circuitry. Over temperature, and the over voltage faults are not affected by the SFPD pin’s state. Both load current sensing and output voltage sensing are incorporated for Short Fault detection with actual detection occurring slightly after the onset of current limit. The current limit circuitry incorporates a SENSEFET™ approach to measure the total drain current. This calls for the current through a small number of cells in the power MOSFET to be measured and the result multiplied by a constant, giving the total current. Wherein output shutdown circuitry measures the drain-to-source voltage, shutting down the output if its threshold (V Thres) is exceeded. Short fault detection is accomplished by sensing the output voltage and comparing it to VThres. The lowest VThres requires a voltage of 2.5 V to be sensed. For an enabled output, with V DD = 5.0 ± 0.5 V, an output voltage in excess of

3.5 V will be detected as a short, or over current condition,

while voltages less than 2.5 V will not be detected as shorts. OVER CURRENT RECOVERY If the SFPD pin is in a high logic state, the circuit returns to normal operation automatically after the short circuit is removed (unless thermal shutdown has occurred). If the SFPD pin is grounded and over current shutdown occurs, removing the short circuit will result in the output remaining OFF until the next write cycle. If the short circuit is not removed, the output will turn ON for the delay time (70 to 250 µs) and then turn OFF for every write cycle commanding a turn ON. SFPD PIN VOLTAGE SELECTION Since the voltage condition of the SFPD pin controls the activation of the short fault protection (i.e., shutdown) mode equally for all eight outputs, the load having the longest duration of in-rush current determines what voltage (state) the SFPD pin should be. Usually if at least one load is, an incandescent lamp for example, the in-rush current on that input will be milliseconds in duration. Therefore, setting SFPD at 5.0 V will prevent shutdown of the output due to the in-rush current. The system relies only on the over temperature shutdown to protect the outputs and the loads. The 33298 was designed to switch GE194 incandescent lamps, or equivalents, with the SFPD pin in a grounded state. Considerably larger lamps can be switched with the SFPD pin held in a high logic state. Sometimes both a delay period greater than 70 to 250 µs (current limiting of the output) followed by an immediate over current shutdown is necessary. This can be accomplished by programming the SFPD pin to 5.0 V for the extended delay period, allowing the outputs to remain ON in a current limited mode, then grounding it to accomplish the immediate shutdown after a period of time. Additional external circuitry is required to implement this type of function. An MCU parallel output port can be devoted to controlling the SFPD voltage during and after the delay period, is often a much better method. In either case, care should be taken to execute the SFPD start-up routine every time start-up or reset occurs. UNDER VOLTAGE SHUTDOWN An under voltage VDD condition will result in the global shutdown of all outputs. The under voltage threshold is between 2.5 V and 3.5 V. When VDD goes below the threshold, all outputs are turned OFF, thereby resetting the Serial Output Data register to indicate the same. An under voltage condition at the VPWR pin will not cause output shutdown and reset. When VPWR is between 5.5 V and 9.0 V, the outputs will operate per the command word. However, the status as reported by the SO pin may not be accurate below 9.0 V VPWR. Proper operation at VPWR voltages below 5.5 V are not be guaranteed. DECIPHERING FAULT TYPE The 33298 SO pin can be used to determine what kind of system fault has occurred. With eight outputs having open load, over current, over temperature, and over voltage faults; a total of 25 different faults are possible. The SO status word received by the MCU will be compared with the word sent to the 33298 during the previous write cycle. For a specific output, if the SO bit compares with the corresponding SI bit of the previous word; the output is operating normal with no fault. Only when the SO bit and previous word SI bit differ is there a fault indicated. If the two words are not the same, the MCU should be programmed to determine which output or outputs are faulted. If, for a specific output, the initial SI command bit were logic high, the output would be programmed to be OFF; if,

therefore most easily detected. for the duration of the over temperature condition. Over current and over temperature faults are often related. following an over voltage condition. voltage (VCL) times the duration the clamp is active (t). to be 50 mJ at 150°C junction temperature per output. Figure 21. Output Voltage Clamping capacitance of the silicone die translator outputs and plastic.

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indicated take into account adjacent output combinations. improved Rpkg from 30° to 28° C/W. 20 of the package connected directly to the lead frame flag. improved the Rpkg from 33° to 31°C/W. Figure 22. Thermal Model (Electrical Equivalent)

Figure 23. Maximum DIP Package Steady State Figure 24. Maximum SOP Package Steady State Output Figure 25. Maximum Output ON Resistance vs. Junction

1 Output ON (37°C/W)

4 Outputs ON (32°C/W)

8 Outputs ON (31°C/W)

4 Outputs ON (35°C/W)

8 Outputs ON (34°C/W)

1 Output ON (40°C/W)

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For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. DW SUFFIX EG SUFFIX (PB-FREE) 20-PIN PLASTIC PACKAGE 98ASB42344B ISSUE F

Analog Integrated Circuit Device Data Freescale Semiconductor 27 33298

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 4.0 8/2006 • Implemented Revision History page

  • Converted to Freescale format
  • Update to the prevailing form and style
  • Added EG suffix device
  • Removed MC33298EG/R2 and replaced with MCZ33298EG in the Ordering Information block 5.0 10/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum ratings on page 5. Added note with instructions to obtain this information from www.freescale.com.

Rev. 5.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2006. All rights reserved. How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

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