MCXN236VDFT NXP | Alldatasheet

Document overview

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  • PDF pages: 102

Technical content

Datasheet sections

  • 1 Feature Comparison
  • 2 Ratings
  • 2.1 Thermal handling ratings
  • 2.2 Moisture handling ratings
  • 2.3 ESD handling ratings
  • 2.4 Voltage and current maximum ratings
  • 2.5 Required Power-On-Reset (POR) Sequencing
  • 3 General
  • 3.1 AC electrical characteristics
  • 3.2 Nonswitching electrical specifications
  • 3.2.2 HVD, LVD, and POR operating requirements
  • 3.2.3 Voltage and current operating behaviors
  • 3.2.4 On-chip regulator electrical specifications
  • 3.2.4.1 DCDC converter specifications
  • 3.2.4.2 DCDC efficiency plots
  • 3.2.4.3 LDO_SYS electrical specifications
  • 3.2.4.4 LDO_CORE electrical specifications
  • 3.2.6 Power consumption operating behaviors
  • 3.2.6.1 Power Consumption Operating Behaviors
  • 3.2.7 EMC radiated emissions operating behaviors
  • 3.2.8 Designing with radiated emissions in mind
  • 3.2.9 Capacitance attributes
  • 3.3 Switching specifications
  • 3.3.1 Device clock specifications
  • 3.3.2 General switching specifications
  • 3.4 Thermal specifications
  • 3.4.1 Thermal operating requirements
  • 3.4.2 Thermal attributes
  • 4 Peripheral operating requirements and behaviors
  • 4.1 Core modules
  • 4.1.1 Debug trace timing specifications
  • 4.1.2 JTAG electricals
  • 4.1.3 SWD electricals
  • 4.2 Clock modules
  • 4.2.1 Reference Oscillator Specification
  • 4.2.3 Free-running oscillator FRO-144M
  • 4.2.4 Free-running oscillator FRO-12M
  • 4.2.5 Free-running oscillator FRO-16K specifications
  • 4.3 Memories and memory interfaces
  • 4.3.1 Flash electrical specifications
  • 4.3.1.1 Timing specifications
  • 4.3.1.2 Flash high voltage current behavior
  • 4.3.1.3 Flash reliability specifications
  • 4.4 Analog
  • 4.4.1 ADC electrical specifications
  • 4.4.1.1 ADC operating conditions
  • 4.4.1.2 ADC electrical characteristics
  • 4.4.3 Voltage reference electrical specifications
  • 4.5 Timers
  • 4.6 Communication interfaces
  • 4.6.1 LPUART
  • 4.6.2 LPSPI switching specifications
  • 4.6.3 Inter-Integrated Circuit Interface (I2C)
  • 4.6.4 Improved Inter-Integrated Circuit Interface
  • 4.6.5 USB High-Speed PHY specifications
  • 4.6.6 CAN switching specifications
  • 4.6.7 I2S/SAI switching specifications
  • 4.6.8 Flexible IO controller (FlexIO)
  • 4.7 Human Machine Interface (HMI) modules
  • 4.7.1 Microphone (MIC)
  • 4.7.2 General Purpose Input/Output (GPIO)
  • 4.8 Security modules
  • 4.8.1 Tamper
  • 5 Package dimensions
  • 5.1 Obtaining package dimensions
  • 6 Pinout
  • 6.1 MCXN23x Signal Multiplexing and Pin
  • 6.2 MCXN23x Pinout Diagrams
  • 6.3 Recommended connection for unused analog
  • 7 Ordering parts
  • 7.1 Determining valid orderable parts
  • 8 Part identification
  • 8.1 Description
  • 8.2 Part number format
  • 8.3 Example
  • 8.4 Package marking
  • 8.4.1 Package marking information
  • 9 Terminology and guidelines
  • 9.1 Definitions
  • 9.2 Examples
  • 9.3 Typical-value conditions
  • 9.4 Relationship between ratings and operating

Features[1]

  • Arm Cortex-M33 150MHz with 618 CoreMark® (4.12 CoreMark/MHz)
  • Up to 1MB Flash, 352 KB SRAM
  • Platform Security with EdgeLock® Secure Enclave, Core Profile
  • - 40 °C to + 125 °C temperature range
  • Down to 50 μA/MHz active current, 3.0 μA Power down mode with RTC enabled and 352 KB SRAM retention, 1.5 μA Deep Power-down mode with RTC active and 32 KB SRAM Cores
  • Arm 32-bit Cortex-M33 CPU with TrustZone®, MPU, FPU, SIMD, ETM and CTI Processing Accelerators
  • SmartDMA (co-processor for applications such as parallel camera interface and keypad scanning) Memories
  • Up to 1 MB (2 x 512KB Bank) on chip Flash memory supporting Flash Swap and Read While Write, with ECC (support one bit correction and two bits detection)
  • Cache Engine with 16 KB RAM
  • Up to 352 KB RAM, configurable as up to 288 KB with ECC (support one bit correction and two bits detection)
  • Up to 4x 8 KB ECC RAM can be retained down to VBAT mode
  • 256 KB ROM with secure bootloader Security
  • EdgeLock Secure Enclave,Core Profile — Cryptographic services (incl. AES-256, SHA-2, ECC NIST P-256, TRNG and key generation/derivation) — Secure key store with key usage policies (protection of platform integrity, manufacturing and applications keys) — Device Unique Identity based on Physically Unclonable Function (PUF) — Device Attestation with support of Device Identifier Composition Engine (DICE) — Secure connection and TLS support — Key management over-the-air with pre-integration of NXP EdgeLock 2GO
  • EdgeLock Accelerator (Public Key Cryptography)
  • Immutable secure boot code in ROM
  • Dual Secure Boot Mode (asymmetric mode and fast, post-quantum secure symmetric mode)
  • Secure firmware update support MCXN23x 184VFBGA 9 x 9 x 0.86 mm, 0.5 mm 100HLQFP 14 x 14 x 1.4 mm, 0.5 mm [1] All information on HLQFP package is preliminary and pending qualification. MCXN23x Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash Rev. 2 — 05/2024 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
  • Device lifecycle management including secure authenticated debug
  • High-performance on-the-fly memory encryption with additional authentication for internal Flash
  • Protected Flash Region (PFR)
  • Security Monitoring: — 2x Code Watchdog — Intrusion and Tamper Response Controller (ITRC) — 6 Active and Passive Tamper Pin Detect — Voltage, Temperature, Light and Clock Tamper Detect — Voltage glitch detect
  • Secure manufacturing and IP theft protection in untrusted factory
  • Arm TrustZone for Cortex-M Low-Power Performance
  • Active: down to 50 μA/MHz
  • Deep Sleep: 124 μA, (full 352 KB SRAM retention, 3.3 V @25 C)
  • Power Down: 2.39 μA, (full 352 KB SRAM retention, 3.3 V, @25 C)
  • Deep Power Down: 1.5 μA, 5.6 ms wake-up (RTC enabled and 32 KB RAM and Reset pin enabled, @25 C) System and Clocks
  • 144 MHz free-running oscillator (FRO-144M)
  • 12 MHz free-running oscillator (FRO-12M)
  • 16 KHz free-running oscillator (FRO-16k)
  • 32 KHz low-power crystal oscillator
  • Up to 50 MHz low-power crystal oscillator
  • 2 x phase-locked loop
  • Hardware and Software Watchdogs
  • Two asynchronous DMA modules (1x 16-channels, 1x 8-channels) Communication Interfaces for Connectivity
  • 8 x Low-Power Flexcomms each supports SPI, I2C, UART
  • USB High-speed (Host/Device) with on-chip HS PHY
  • 2x FlexCAN with FD
  • 2x I3C Human-Machine Interfaces
  • 1x FlexIO programmable as a variety of serial and parallel interfaces, including but not limited to display driver and camera interface
  • 2x Serial Audio Interface (SAI)
  • Digital PDM Microphone — allows connection of up to 4 MEMS microphones with PDM output Advanced Motor Control
  • 2x FlexPWM each with 4 sub-modules, providing 12 PWM outputs (no Nanoedge module) NXP Semiconductors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 2 / 102
  • 2x Quadrature Decoder(QDC)
  • 1x Event Generator (AND/OR/INVERT) module support up to 8 output trigger Analog
  • 2x 16-bit ADC, supporting 4 parallel conversions — Each ADC can be used as two single end input ADC, or one differential input ADC — up to 2 Msps in 16-bit mode, and 3.15 Msps in 12-bit mode — up to 61 ADC Input channels (depending on the package) — one integrated temperature sensor per ADC
  • Two High-speed Comparators with 11 input pins and 8-bit DAC as internal reference
  • 2x CMP is functional down to Deep Power Down mode
  • Highly accurate VREF ±0.2 % and 15 ppm/deg C drift Timers
  • Five 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests.
  • Low-Power Timer
  • Frequency measurement timer
  • Multi-Rate Timer
  • Windowed Watchdog Timer
  • RTC with calendar
  • Wake Timer
  • Micro-Tick Timer (UTICK)
  • OS Event Timer General-purpose input/outputs
  • Up to 106 GPIOs
  • 1.2 V support at reduced performance (available only on Fast pads)
  • Five independent IO power rings
  • 100 MHz IO on P2 and P3
  • Up to 28-pin wake-up sources function down to deep power-down mode
  • Support 1.71 V~3.6 V IO supply range Power Management
  • Integrated voltage regulator — Buck DC-DC, Core LDO, other LDOs
  • Separate AON domain on VDD_BAT pin
  • Operating voltage: 1.71 V to 3.6 V
  • IOs: 1.71 V-3.6 V full-performance Target Applications Industrial
  • Energy Storage and Management System
  • Smart Metering NXP Semiconductors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 3 / 102
  • Factory Automation
  • Industrial HMI
  • Mobile Robotics Ecosystem
  • Motion Control and Robotics
  • Motor Drives
  • Brushless DC Motor (BLDC) Control
  • Permanent Magnet Synchronous Motor (PMSM)
  • Edge AI/ML Anomaly Detection and Predictive Maintainence Smart Home
  • Home Control Panel
  • Home Security and Surveillance
  • Major Home Appliances
  • Robotic Appliance
  • Smart Speaker
  • Soundbar
  • Gaming Accessories
  • Smart Lighting
  • Smart Power Socket and Light Switch

Table 1. Ordering Information

  1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.

Table 2. Device Revision Number Table 3. Related Resources structure and function (operation) of a device. Table continues on the next page...

Table 3. Related Resources (continued) information for a particular device mask set.

  • BGA 184-pin:98ASA01888D Software development kit MCUXpresso SDK. An open source software development kit (SDK) built specifically for your processor and evaluation board selections. http://www.nxp.com/mcuxpresso The EdgeLock Secure Subsystem (ELS) is also known as EdgeLock Secure Enclave, Core Profile (ELE). This document uses the ELS name, but other materials might refer to this module as EdgeLock Secure Enclave, Core Profile or ELE. NOTE NXP Semiconductors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 5 / 102

Figure 1. MCXN23x Block diagram

Figure 2. MCXN23x Architecture

9.5 Guidelines for ratings and operating

1 Feature Comparison

Table 4. Feature Comparison

  1. For more details, please refer to Table 1
  2. Only 2 Anti Tamper pins available on 100 HLQFP packages

2 Ratings

2.1 Thermal handling ratings

Table 5. Thermal handling ratings

  1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
  2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

2.2 Moisture handling ratings

Table 6. Moisture handling ratings

  1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

2.3 ESD handling ratings

Table 7. ESD and Latch-up ratings

  1. Determined according to ANSI/ESDA/JEDEC Standard JS-001-2023, For Electrostatic Discharge Sensitivity Testing,

Human Body Model (HBM) - Component Level.

  1. Determined according to ANSI/ESDA/JEDEC Standard JS-002-2022, For Electrostatic Discharge Sensitivity Testing,
  2. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

2.4 Voltage and current maximum ratings

Table 8. Voltage and current maximum ratings Table continues on the next page...

Table 8. Voltage and current maximum ratings (continued)

  1. The part will support 2.75 V for up to 20 s over lifetime to allow for fuse programming
  2. Analog pins are defined as pins that do not have an associated general-purpose I/O port function.
  3. This limit is per supply pin. This includes all power pins, including, VDD_CORE, VDD_SYS, VDD_LDO_SYS,

2.5 Required Power-On-Reset (POR) Sequencing

  • Secondary IO supplies (VDD_P2/VDD_P3/VDD_P4) must implement one of the following: — Must be shorted with VDD (eg: single supply system), or — Must ramp after VDD_SYS
  • VDD_CORE must ramp after VDD
  • VDD_P4 and VDD_ANA must be same voltage
  • VDD_BAT must ramp before or with VDD_SYS

3 General

3.1 AC electrical characteristics

at the 20% and 80% points, as shown in the following figure.

Figure 3. Input signal measurement reference

3.2 Nonswitching electrical specifications

3.2.1 Voltage and current operating requirements

Table 9. Voltage and current operating requirements

  • Mid voltage
  • Normal voltage
  • Overdrive voltage 0.95 1.045 1.14 1.0 1.1 1.2 1.05 1.155 1.26 V 1 VDD_SYS Supply voltage for on-board regulators, LVD / HVDs, and clock sources
  • Normal mode
  • Fuse Programming 1.71 2.25 1.98 2.75 V VDD_DCDC Supply voltage DCDC regulator 1.71 3.6 V 2 VDD_LDO_SYS Supply voltage for LDO_SYS regulator 1.86 3.6 V VDD_LDO_CORE Supply voltage for LDO_CORE regulator 1.71 3.6 V VDD Supply Voltage for Port 0, Port 1, Flash, and CMPx 1.71 3.6 V VDD_P2 Supply voltage for Port 2 1.14 1.71 1.32 3.6 V 3,4 VDD_P3 Supply voltage for Port 3 1.14 1.71 1.32 3.6 V 3,5,4 VDD_P4 Supply voltage for Port 4 1.71 3.6 V 6,4 VDD_BAT Supply voltage for VBAT domain 1.71 3.6 V Table continues on the next page... NXP Semiconductors General Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 13 / 102

Table 9. Voltage and current operating requirements (continued)

  • 1.71 V ≤ VDD_Px ≤ 3.6 V
  • 1.14 V ≤ VDD_Px ≤ 1.32 V 0.7 × VDD_Px 0.7 × VDD_Px V VIL Input low voltage
  • 1.71 V ≤ VDD_Px ≤ 3.6 V
  • 1.14 V ≤ VDD_Px ≤ 1.32 V 0.3 × VDD_Px 0.3 × VDD_Px V VHYS Input hysteresis
  • Slow I/O
  • Medium I/O
  • Fast I/O 0.1 × VDD_Px 0.1 × VDD_Px 0.04 × VDD_Px — V IICIO IO pin DC injection current — per pin
  • VIN < VSS-0.3 V (negative current injection)
  • VIN > VDD+0.3 V (positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
  • Negative current injection
  • Positive current injection -25 +25 mA VODPU Open drain pullup voltage level VDD_Px VDD_Px V 10 1. To avoid triggering the glitch detect modules on this device, it is important that the VDD_CORE voltage matches the configuration of the GDET modules. See the GDET chapter in the Security Reference Manual for details. 2. If DCDC is unused, then input supply should be tied to GND through a 10 kΩ resistor. 3. Operation at 1.2 V is allowed on Port P2/P3 pins only with the following restrictions:
  • VDD_CORE must be less than or equal to the VDD_Px voltage
  • VDD_SYS must be powered on before VDD_Px is powered and VDD_SYS must not be powered off before powering off VDD_Px. 4. If this voltage rail is not tied to VDD, it must ramp after VDD_SYS 5. If none of the Port 3 pins are being used, then the VDD_P3 can be left floating. 6. VDD_P4 should be powered up with VDD_ANA and to the same voltage level as VDD_ANA 7. VDD_ANA may deviate from VDD_P4 by ± 0.1 V provided it is still within range of 1.71 V - 3.6 V NXP Semiconductors General Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 14 / 102
  1. USB HS is not supported when VDD_CORE < 1.1 V
  2. All I/O pins are internally clamped to VSS and VDD_Px through an ESD protection diode. If VIN is greater than
  3. Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD_Px as appropriate.

3.2.2 HVD, LVD, and POR operating requirements

  • VDD
  • VDD_CORE
  • VDD_SYS For VDD_SYS, it has Power-on-reset (POR) power supervisor circuits.

Table 10. VDD supply HVD, LVD, and POR Operating Requirements Table 11. VDD_CORE supply HVD and LVD Operating Requirements Table continues on the next page...

Table 11. VDD_CORE supply HVD and LVD Operating Requirements (continued)

  1. Same value applies to all conditions.

Table 12. VDD_SYS supply HVD and LVD Operating Requirements

  1. When fuses are being programmed VDD_SYS is raised to 2.5V nominal. This is outside the HVD bounds, so HVD

3.2.3 Voltage and current operating behaviors

Table 13. Voltage and current operating behaviors Table continues on the next page...

Table 13. Voltage and current operating behaviors (continued)

  • 2.7 V ≤ VDD_Px ≤ 3.6 V, IOH = 4 mA
  • 1.71 V ≤ VDD_Px < 2.7 V, IOH = 2.5 mA
  • 1.14 V ≤ VDD_Px < 1.32 V, IOH = 0.5 mA VDD_Px – 0.5 VDD_Px – 0.5 VDD_Px – 0.5 V V V VOH Output high voltage — High drive strength
  • 2.7 V ≤ VDD_Px ≤ 3.6 V, IOH = 6 mA
  • 1.71 V ≤ VDD_Px < 2.7 V, IOH = 3.75 mA
  • 1.14 V ≤ VDD_Px < 1.32 V, IOH = 0.75 mA VDD_Px – 0.5 VDD_Px – 0.5 VDD_Px – 0.5 V V V 2,1 IOHT Output high current total for all ports — — 100 mA VOL Output low voltage — Normal drive strength
  • 2.7 V ≤ VDD_Px ≤ 3.6 V, IOL = 4 mA
  • 1.71 V ≤ VDD_Px < 2.7 V, IOL = 2.5 mA
  • 1.14 V ≤ VDD_Px < 1.32 V, IOH = 0.5 mA 0.5 0.5 0.5 V V V 3,1 VOL Output low voltage — High drive strength
  • 2.7 V ≤ VDD_Px ≤ 3.6 V, IOL = 6 mA
  • 1.71 V ≤ VDD_Px < 2.7 V, IOL = 3.75 mA
  • 1.14 V ≤ VDD_Px < 1.32 V, IOH = 0.75 mA 0.5 0.5 0.5 V V V 1,3 IOLT Output low current total for all ports — — 100 mA IIN Input leakage current (per pin) for full temperature range — — 1 μA 4 IIN Input leakage current (per pin) at 25 °C — — 0.025 μA 4 IOZ Hi-Z (off-state) leakage current (per pin) — — 1 μA RPU Internal pullup resistors 33 50 75 kΩ RPU (I3C) Internal pullup resistors 1.11 1.2 2.83 kΩ 5 RPD Internal pulldown resistors 33 50 75 kΩ RHPU High-resistance pullup option (PCRx[PV] = 1) 0.67 1.0 1.5 MΩ 6 RHPD High-resistance pulldown option (PCRx[PV] = 1) 0.67 1.0 1.5 MΩ 6 VBG Bandgap voltage reference voltage 0.98 1.0 1.02 V 1. The 1.14 V – 1.32 V range only applies to port P2 / P3 pins. 2. AON and RESET_B pins are always configured in high drive mode 3. Open drain outputs must be pulled to VDD_Px. 4. Measured at VDD_Px = 3.6 V. 5. Only pins with +I3C add-on support this option 6. Only AON pins and RESET_B pin support this option.

3.2.4 On-chip regulator electrical specifications

3.2.4.1 DCDC converter specifications

Table 14. DCDC Converter Specifications

  • Normal drive strength
  • FREQ_CNTRL_ON=1
  • Low drive strength 105 mA mA mA LX DCDC inductor value 0.47 1 2.2 µH 4 ESR External inductor equivalent series resistance — 110 — mΩ 5 COUT DCDC capacitance value 6 22 30 µF 6 VRIPPLE DCDC voltage ripple
  • In normal drive strength
  • In low drive strength mV T_startup DCDC startup time — 100 — µs fburst DCDC switching frequency 3 5 8 MHz 7 fburst_acc DCDC burst frequency accuracy — 10 — % 8 1. The VDD_DCDC input supply to the system DCDC must be at least 500 mV higher than the desired output at DCDC_LX to achieve the stated efficiency. VDD_DCDC can be as low as 300 mV above the desired output voltage but the efficiency will be reduced. 2. The system DCDC converter generates 1.2 V at DCDC_LX by default. The DCDC is used to power VDD_CORE. 3. The maximum load current during boot up shall not exceed 60 mA. 4. Recommended inductor value is 1 µH to 1.5 µH. If the inductor is < 1 µH, the DCDC efficiency is not guaranteed. 5. The maximum recommended ESR is 250 mΩ (not a hard limit). 6. The variation in capacitance of the capacitor at DCDC_LX due to aging, temperature, and voltage degradation must not exceed the Min./Max. values. 7. FREQ_CNTRL_ON = 1. This range is for 1 µH inductor. 8. FREQ_CNTRL_ON = 1. NXP Semiconductors General Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 18 / 102

3.2.4.2 DCDC efficiency plots

Figure 4. Low drive strength

Figure 5. Normal drive strength

3.2.4.3 LDO_SYS electrical specifications

Table 15. LDO_SYS electrical specifications

  • Normal Drive mode
  • Passthrough mode
  • Fuse Programming 1.95 1.86 2.75 3.6 1.98 3.6 V 1,2 VOUT_SYS LDO_SYS regulator output voltage Normal drive strength mode Fuse programming mode 1.71 2.25 1.8 2.5 1.98 2.75 V 3,4,2 Table continues on the next page... NXP Semiconductors General Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 20 / 102

Table 15. LDO_SYS electrical specifications (continued)

  • Normal drive strength mode
  • Fuse programming mode 5
  • Pass through mode 6 150 500 mV 1, 2 ILOAD LDO_SYS maximum load current
  • Normal drive strength mode
  • Low drive strength mode
  • Fuse programming mode 40 mA IDD LDO_SYS power consumption
  • Normal drive strength mode
  • Low drive strength mode 100 μA nA COUT External output capacitor 1.4 2.2 4.0 μF ESR External output capacitor equivalent series resistance — 30 — mΩ IINRUSH LDO_SYS inrush current — — 1008 mA 1. Regulator will automatically switch to passthrough mode with the supply is below 1.95 V. 2. VDD_LDO_SYS must be at least 150 mV higher than the desired VOUT_SYS. 3. The LDO_SYS converter generates 1.8 V by default at VOUT_SYS. VOUT_SYS can be used to power VDD_SYS, VDD_Px, VDD_ANA, and external components as long as the max ILOAD is not exceeded. 4. VOUT_SYS and VDD_SYS are connected together within the package 5. Maximum current load in fuse programming mode is 40 mA 6. Maximum current load during pass through mode = 50 mA 7. In normal mode, LDO_SYS draws ~100 μA for every 20 mA of load current. 8. This value is for a 1.5 μF external output capacitor. This value would increase with higher load capacitor.

3.2.4.4 LDO_CORE electrical specifications

Table 16. LDO_CORE electrical specifications

  • Normal drive strength — Mid drive — Normal drive — Over drive
  • Low drive strength 0.95 1.045 1.14 1.1 1.2 1.05 1.155 1.26 V 2 Table continues on the next page... NXP Semiconductors General Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 21 / 102

Table 16. LDO_CORE electrical specifications (continued)

  • Normal drive strength — Tj = -40 °C — Tj = 27 °C — Tj = 125 °C
  • Low drive strength 100 115 28 mA IINRUSH LDO_CORE inrush current — — 500 mA 3 1. To bypass LDO_CORE, tie VDD_LDO_CORE to VDD_CORE 2. VOUT_CORE and VDD_CORE are connected together in package 3. This value is for 4.7 µF external output capacitor. This value would increase with higher load capacitor

Table 17. LDO_CORE external device electrical specifications

3.2.5 Power mode transition operating behaviors

  • CPU clock = 48 MHz
  • AHB clock = 48 MHz
  • Clock source = Fast internal reference clock (FIRC) All specifications in the following table were measured from the initiation of an external pin event to the execution code (unless otherwise stated). All specifications in the following table assume this SPC configuration:
  • SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x00 and the Core voltage level is configured for the same level in active and low power mode (SPC->ACTIVE_CFG[DCDC_VDD_LVL] = SPC->ACTIVE_CFG[CORELDO_VDD_LVL] = SPC->LP_CFG[DCDC_VDD_LVL] = SPC->LP_CFG[CORELDO_VDD_LVL]).

Table 18. Power mode transition operating behaviors Table continues on the next page...

Table 18. Power mode transition operating behaviors (continued) the operating temperature range of the chip.

  1. Boot configuration 144 MHz
  2. Measured using ROM version v4.0
  3. Based on characterization of typical units. Not tested in production
  4. Max value is mean + 3 sigma of tested values at the worst case of ambient temperature range and VDD 1.71 V to 3.6 V.
  5. WFE used for low-power mode entry

3.2.6 Power consumption operating behaviors

domain regulator, and the VBAT domain is also provided by the same external source.

  • Specifications below only include power for the MCU itself
  • VDD_USB current draw are not included
  • On top of the device’s IDD current consumption, external loads applied to pins of the device need to be considered
  • Efficiency of regulators (on-chip or off-chip) used to generate supply voltages should be considered

3.2.6.1 Power Consumption Operating Behaviors

Table 19. DCDC @ 3.3 V Table continues on the next page...

Table 19. DCDC @ 3.3 V (continued) Table continues on the next page...

  1. Based on characterization of typical units. Not tested in production

Table 20. LDO @1.8 V Table continues on the next page...

Table 20. LDO @1.8 V (continued) Table continues on the next page...

Table 21. LDO @ 3.3 V Table continues on the next page...

Table 21. LDO @ 3.3 V (continued) Table continues on the next page...

Table continues on the next page...

Table 22. DCDC @ 3.3 V Table continues on the next page...

Table 22. DCDC @ 3.3 V (continued) Table continues on the next page...

  1. Based on characterization of typical units. Not tested in production
  2. Power measurements for IDD_VBATx symbols are attained after turning off external power supplies to all domains,

Table 23. LDO @ 1.8V Table continues on the next page...

Table 23. LDO @ 1.8V (continued) Table continues on the next page...

Table 24. LDO @ 3.3V Table continues on the next page...

Table 24. LDO @ 3.3V (continued)

3.2.7 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

3.2.8 Designing with radiated emissions in mind

  1. Go to http://www.nxp.com.
  2. Perform a keyword search for “EMC design”.

3.2.9 Capacitance attributes

Table 25. Capacitance attributes

3.3 Switching specifications

3.3.1 Device clock specifications

Table 26. Device clock specifications

  1. The maximum value of system clock, core clock, AHB clock, and flash clock under normal run mode can be 2 % higher

than the specified maximum frequency when FRO-144M is used as the clock source.

3.3.2 General switching specifications

Pad types are specified in the pinout spreadsheet attached to this document. Table 27. General switching specifications Table continues on the next page...

Table 27. General switching specifications (continued)

  • 2.7 ≤ VDD_Px ≤ 3.6 V — Fast slew rate (SRE = 0; DSE = 0) — Slow slew rate (SRE = 1; DSE = 0)
  • 1.71 ≤ VDD_Px < 2.7 V — Fast slew rate (SRE = 0; DSE = 1) — Slow slew rate (SRE = 1; DSE = 1) 2.5 4.6 1.6 4.3 ns 5 Fast I/O pins
  • 2.7 ≤ VDD_Px ≤ 3.6 V — Fast slew rate (SRE = 0; DSE = 0)6 — Slow slew rate (SRE = 1; DSE = 0)6
  • 1.71 ≤ VDD_Px < 2.7 V — Fast slew rate (SRE = 0; DSE = 1)6 — Slow slew rate (SRE = 1; DSE = 1)6
  • 1.14 ≤ VDD_Px < 1.32 V — Fast slew rate (SRE = 0; DSE = 1)7 — Slow slew rate (SRE = 1; DSE = 1)7 0.8 0.9 0.5 0.6 2.5 2.5 ns 8,9 Medium I/O pins
  • 2.7 ≤ VDD_Px ≤ 3.6 V — Fast slew rate (SRE = 0; DSE = 0) — Slow slew rate (SRE = 1; DSE = 0)
  • 1.71 ≤ VDD_Px < 2.7 V 1.500 2.071 3.322 4.864 ns Table continues on the next page... NXP Semiconductors General Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 37 / 102
  • 2.7 ≤ VDD_Px ≤ 3.6 V
  • 1.71 ≤ VDD_Px < 2.7 V 3.6 ns 1. This is the shortest pulse that is guaranteed to be recognized. 2. Synchronous path is used in active and sleep mode for pin functions other than WUU. Pins configured as WUU use asynchronous path in all power modes. 3. Asynchronous path is used deep sleep, power down, and deep power down modes. 4. The passive filter is always enabled for the RESET_B pin. 5. Load is 25 pF. Drive strength and slew rate are configured using PORTx_PCRn[DSE] and PORTx_PCRn[SRE]. 6. 15 pF lumped load. 7. 25 pF lumped load 8. These are Port 3 and Port 2 pins. 9. Uses default configuration for NCAL and PCAL in PORTS. 10. Load is 25 pF.

3.4 Thermal specifications

3.4.1 Thermal operating requirements

Table 28. Thermal operating requirements

  1. The device may operate at maximum TA rating as long as TJ maximum of 125 °C is not exceeded. The simplest method to

determine TJ is: TJ = TA + RθJA × chip power dissipation.

  1. The device operating specification is not guaranteed beyond 125 °C TJ.
  2. The maximum operating requirement applies to all chapters unless otherwise specifically stated.
  3. Operating at maximum conditions for extended periods may affect device reliability. Refer to Product Lifetime Usage

3.4.2 Thermal attributes

Table 29. Thermal attributes

184 BGA Unit Notes

  1. Thermal test board meets JEDEC specification for respective package (JESD51-7 for the 100 HLQFP; JESD51-9 for the

184 BGA)

  1. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is

meant to predict the performance of a package in an application-specific environment.

  1. Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the 100

HLQFP package bottom surface temperature.

4 Peripheral operating requirements and behaviors

4.1 Core modules

4.1.1 Debug trace timing specifications

Table 30. Debug trace operating behaviors

  • OD mode
  • SD mode
  • MD mode MHz T1 Clock period
  • OD mode
  • SD mode
  • MD mode 20.82 27.78 ns T2 Low pulse width 2 — ns T3 High pulse width 2 — ns T4 Clock and data rise time — 3 ns T5 Clock and data fall time — 3 ns T6 Data setup 1.5 — ns T7 Data hold 1.0 — ns TRACE_CLK T2T3 T4 T5

Figure 6. TRACE_CLKOUT specifications

Figure 7. Trace data specifications

4.1.2 JTAG electricals

Table 31. JTAG timing (full voltage range)

  • Boundary Scan
  • JTAG-DP/TAP (OD and SD mode)
  • JTAG-DP/TAP (MD mode) MHz MHz MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
  • Boundary Scan
  • JTAG-DP/TAP ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2 — ns J7 TCLK low to boundary scan output data valid — 30 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 JTAG-DP/TAP TMS, TDI input data setup time to TCLK rise 8 — ns J10 JTAG-DP/TAP TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to JTAG-DP/TAP TDO data valid — 19 ns J12 TCLK low to JTAG-DP/TAP TDO high-Z — 17 ns J3 J3 J4 J4 JTAG_TCLK

Figure 8. Test clock input timing

Figure 9. Boundary scan (JTAG) timing Figure 10. JTAG-DP/TAP timing

4.1.3 SWD electricals

Table 32. SWD timing Table continues on the next page...

Table 32. SWD timing (continued) Figure 11. Serial wire clock input timing Figure 12. Serial wire data timing

4.2 Clock modules

4.2.1 Reference Oscillator Specification

temperature, mechanical, and aging excursions.

The table below shows typical specifications for the Crystal Oscillator. Table 33. System Crystal Oscillator Specification

  • Period jitter (RMS) — 70 — ps Vpp Peak-to-peak amplitude of oscillation — 0.6 — V 1 fec Externally provided input clock frequency 0 — 50 MHz 2 tDC_EXTAL External clock duty cycle 40 50 60 % Vec Externally provided input clock amplitude Refer to Table 9 for VIH and VILlevels 2 1. When a crystal is being used with the oscillator, the EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 2. This specification is for an externally supplied clock driven to EXTAL and does not apply to any other clock input.

Table 34. System Oscillator Crystal Specifications. Refer to Figure 13 for additional details of the crystal parameters

  1. This is based on simulation

Figure 13. Crystal Electrical Block Diagram Table 35. 32 kHz oscillator electrical specifications

  • Normal/Start up mode
  • Low power mode ±100 ±150 ppm 1 Jitosc Jitter
  • Period jitter (RMS)
  • Accumulated jitter over 1 ms (RMS) 12000 8000 ps ESR Crystal equivalent series resistance
  • Normal mode
  • Low power mode 100 K 50 K kΩ RF Internal feedback resistor — 100 — MΩ Cpara Parasitic capacitance of EXTAL32 and XTAL32 — 2.5 — pF tstart Crystal start-up time — 1000 ms 2 Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 44 / 102

Table 35. 32 kHz oscillator electrical specifications (continued)

  • Normal/Start up mode
  • Low power mode — 8000 IOSC_32k Current consumption
  • ON mode — Normal mode — Low power mode
  • OFF mode 220 110 0.5 — nA Vpp Peak-to-peak amplitude of oscillation
  • Normal mode
  • Low power mode 0.2 0.1 V 3 fec_extal32 Externally provided input clock frequency — 32.768 — kHz 4 tDC_EXTAL3 External clock duty cycle 40 50 60 kHz vec_extal32 Externally provided input clock amplitude Refer to Voltage and current operating requirements for VIH and VIL levels mV 4, 5 Cextal/xtal On-chip EXTAL, XTAL Load Capacitance 0 — 30 pF 6,7 1. For Low power mode, use crystals with load cap (CL) 7 pF or less 2. Proper PC board layout procedures must be followed to achieve specifications. 3. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 4. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 5. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VDD_BAT. 6. These are the internally available oscillator load capacitors on each of the EXTAL32 and XTAL32 pins, selectable in 2 pF steps. The effective load capacitance is the series equivalent of the selected capacitors. 7. The internally available load capacitors can be set to minimum of 0 on XTAL and 2 pF on EXTAL and external load capacitors used instead.

Table 36. 32 kHz oscillation gain setting

  1. Cx is the sum of all capacitance connected to both EXTAL32 and XTAL, including internal load capacitors, pad

It is recommended that the oscillator margin be measured on the actual application PCB with the target crystal.

4.2.3 Free-running oscillator FRO-144M specifications

Table 37. FRO-144M specifications

  • Open loop
  • Closed loop (using accurate clock source as reference) ±0.25 tstartup Start-up time
  • Oscillation time with initial accuracy of -20 % to +2 % of enable signal assertion
  • Oscillation time within +/- 2 % from enable signal assertion μs μs fos Frequency overshoot during startup — — 2 % jitper • Period jitter RMS 1
  • Accumulated jitter over 1 ms — 200 — ps jitcyc Cycle to cycle jitter — 200 — ps Ifro144m_vdd _sys Current consumption for VDD_SYS — 70 — μA Ifro144m_vdd _core Current consumption for VDD_CORE — 35 — μA 1. Reference clock = 144 MHz.

4.2.4 Free-running oscillator FRO-12M specifications

Table 38. FRO-12M specifications

  • open loop
  • closed loop (using accurate clock source as reference) ±0.6 tstartup Start-up time — 5 — μs fos Frequency overshoot during startup — 10 20 % Ifro12m Current consumption — 7 — μA NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 46 / 102

4.2.5 Free-running oscillator FRO-16K specifications

Table 39. FRO-16K specifications

  • open loop — — ±6 % TRIMstep Trimming step — 1.5 — % tstartup Start-up time — 310 — μs Ifro16k Current consumption — 50 — nA 4.2.6 550 MHz PLL specifications

Table 40. PLL specifications

  • fvco = 550 MHz — 110 — ps Jrms_int RMS interval jitter @fout = fcco =

550 MHz, fref = 12 MHz

The information in this table applies to both PLL0 (APLL) and PLL1 (SPLL).

4.3 Memories and memory interfaces

4.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

4.3.1.1 Timing specifications

Table 41. Flash command time specifications

512 KB — 3200

1024 KB — 6200

512 KB — 3050

1024 KB — 6000

256 KB — 1500

32 KB — 190

128 B 450 600 2 µs 3

128 B 450 750 2 µs 3

16 B 135 180 2 µs 3

16 B 135 225 2 µs 3

Table continues on the next page...

Table 41. Flash command time specifications (continued)

512 KB — 1500

1024 KB — 2800

  1. Time to abort the command may significantly impact the time to execute the command.
  2. Characterized but not tested in production
  3. Measured from the time FSTAT[PERDY] is cleared.

4.3.1.2 Flash high voltage current behavior

Table 42. Flash high voltage current behavior

  1. See the Power Management chapter in the reference manual for the specific VDD_Px voltage supply powering the flash

4.3.1.3 Flash reliability specifications

Table 43. Flash reliability specifications

  1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
  2. Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40°C ≤ Tj ≤ 125°C.
  1. For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices

Table 44. Fusebox electrical specifications

  1. VDD_SYS ramp-up slew rate MUST be slower than 2.5V/100 µs to avoid unintentional program
  2. This is the current required to program just the fuse and is in addition to any other current being drawn by the device.
  3. The maximum total accumulated time for elevated VDD_SYS (VDD_SYS > 1.98V) is 20 seconds over the lifetime of the

4.4 Analog

4.4.1 ADC electrical specifications

4.4.1.1 ADC operating conditions

Table 45. ADC operating conditions Table continues on the next page...

Table 45. ADC operating conditions (continued)

  1. Typical values assume VDD_ANA = 3.0 V, Temp = 25 °C, fADCK = 24 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

  1. For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally.
  2. If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result in a
  3. ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected

between the source and the ADC input pin.

  1. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
  2. There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see ADC input
  3. If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel

Figure 14. ADC input impedance equivalency diagram

4.4.1.2 ADC electrical characteristics

Table 46. ADC electrical specifications Table continues on the next page...

Table 46. ADC electrical specifications (continued)

1 MS/s (AVGS=001) 83 dB

2 MS/s 80 dB

3.15 MS/s (for 12-bit mode) 70 dB

Table continues on the next page...

1 MS/s (AVGS=001) 80 dB

2 MS/s 77 dB

3.15 MS/s (for 12-bit mode) 68 dB

E_IL Input leakage error llkg mV 11.

  1. Typical values assume VDD_ANA = 3.3 V, Temp = 25 °C, fADCK = 24 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

  1. The ADC supply current depends on the ADC conversion clock speed, conversion rate, and power mode. Typical value

show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00.

  1. Must meet minimum TSMP requirement
  2. Maximum conversion rate for high-speed mode is with FADCK = 48 MHz. Maximum conversion rate for low-power mode is
  3. Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and desired

sample accuracy in bits(B). Calculate it with formula: T SMP_REQ = B*0.693*[RAS*(CAS+CP+CADIN)+ (RAS + R ADIN)* CADIN.

  1. Internal channel inputs are those that do not come from external source (temperature sensor, bandgap).
  2. 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16- bit specifications, multiply by 4.
  3. All accuracy numbers assume that the ADC is calibrated with VREFH=VDD_ANA and using a high- speed- dedicated input
  4. Dynamic results assume Fin=1 kHz sinewave, no averaging.
  5. Set the power-up delay (PUDLY) according to the ADC start-up time if PWREN=0.
  6. Ilkg = leakage current (Refer to pin leakage specification in the voltage and current operating ratings of packaged device)
  7. The temperature sensor can be calibrated to a +/- 0.5 % precision after board assembly by using a 3-temperature

calibration flow with accurate ± 0.15 % temperature chamber.

Figure 15. ENOB VS ADC clock graph

4.4.2 CMP and 8-bit DAC electrical specifications

Table 47. Comparator and 8-bit DAC electrical specifications

  • High speed mode (EN=1, HPMD=1)
  • Normal mode (EN=1, HPMD=0, NPMD=0)
  • Low-power mode (EN=1, HPMD=0, NPMD=1) 200 400 μA μA nA VAIN Analog input voltage VSS — VDD V VAIO Analog input offset voltage
  • High speed mode
  • Normal mode
  • Low-power mode mV mV mV VH Analog comparator hysteresis
  • CR0[HYSTCTR] = 00
  • CR0[HYSTCTR] = 01 mV mV Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 55 / 102

Table 47. Comparator and 8-bit DAC electrical specifications (continued)

  • CR0[HYSTCTR] = 10
  • CR0[HYSTCTR] = 11 mV mV VCMPOh Output high VDD - 0.2 — — V VCMPOl Output low — — 0.2 V tD Propagation delay
  • High speed mode, 100 mV overdrive, power > 1.71V
  • High speed mode, 30 mV overdrive, power > 1.71V
  • Normal mode, 30 mV overdrive, power > 1.71V
  • Low-power mode, 30 mV overdrive, power > 1.71V 600 ns ns ns μs tinit Analog comparator initialization delay — — 40 μs 3 IDAC8b 8-bit DAC current adder (enabled)
  • High power mode (EN=1, PMODE=1)
  • Low power mode (EN=1, PMODE=0) μA μA INL 8-bit DAC integral non-linearity
  • Low/High power mode, supply power > 1.71V
  • Low power mode, supply power < 1.71V +1.0 LSB 4 DNL 8-bit DAC differential non-linearity
  • Low/High power mode, power > 1.71V
  • Low power mode, power < 1.71V +1.0 LSB 4 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V. 2. Overdrive does not include input offset voltage or hysteresis 3. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 4. 1 LSB = Vreference/256 Typical hysteresis NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 56 / 102

Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 1)

4.4.3 Voltage reference electrical specifications

Table 48. VREF operating requirements

  1. VDD_ANA must be at least 600 mV greater than the selected VREFO output voltage.
  2. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
  3. The minimum CL capacitance must take into account the variation in capacitance of the chosen capacitor due to voltage,

Table 49. VREF operating behaviors

1.0 V low-power reference voltage

Table continues on the next page...

Table 49. VREF operating behaviors (continued)

  1. See the Reference Manual of the chip for the appropriate settings of the VREF Status and Control register.
  2. Vvrefo max is also ≤ VDD_ANA - 600 mV.
  3. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load.
  4. Under Vvrefo = 1V configuration.

4.5 Timers

See General switching specifications.

4.6 Communication interfaces

4.6.1 LPUART

See General switching specifications.

4.6.2 LPSPI switching specifications

of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Table 50. LPSPI master mode timing

  • Master TX in OD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7
  • Master RX in OD mode MHz MHz MHz Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 59 / 102

Table 50. LPSPI master mode timing (continued)

  • Master TX in SD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7
  • Master RX in SD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7
  • Master TX in MD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7
  • Master RX in MD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7 12.5 12.5 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz LP2 SCK period 2 x tperiph 2048 x tperiph ns LP3 Enable lead time 1/2 — tperiph 2 LP4 Enable lag time 1/2 — tperiph 2 LP5 Clock (SCK) high or low time tSCK/2 - 3 tSCK/2 ns — LP6 Data setup time (inputs)
  • LPSPI0–LPSPI2
  • LPSPI3–LPSPI5
  • LPSPI6–LPSPI7 14.4 7.2 4.8 ns — LP7 Data hold time (inputs) 0 — ns — LP8 Data valid (after SCK edge)
  • LPSPI0–LPSPI2
  • LPSPI3–LPSPI5
  • LPSPI6–LPSPI7 — 14.4 7.2 4.8 ns — LP9 Data hold time (outputs) 1 — ns — 1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI peripheral functional clock. NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 60 / 102

Table 51. LPSPI slave mode timing (continued)

  • Slave RX in OD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7
  • Slave TX in SD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7
  • Slave RX in SD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7
  • Slave TX in MD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7
  • Slave RX in MD mode — LPSPI0–LPSPI2 — LPSPI3–LPSPI5 — LPSPI6–LPSPI7 12.5 12.5 12.5 12.5 12.5 12.5 12.5 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz LP2 SCK period 4 x tperiph 2048 x tperiph ns LP3 Enable lead time 1 — tperiph 2 LP4 Enable lag time 1 — tperiph 2 LP5 Clock (SCK) high or low time tSCK/2 - 5 tSCK/2 ns — LP6 Data setup time (inputs)
  • LPSPI0~LPSPI2
  • LPSPI3~LPSPI5
  • LPSPI6~LPSPI7 14.4 2.4 ns — LP7 Data hold time (inputs) 0 — ns — LP8 Slave access time — tperiph ns 2,3 Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 62 / 102
  • LPSPI0~LPSPI2
  • LPSPI3~LPSPI5
  • LPSPI6~LPSPI7 31.2 ns — LP11 Data hold time (outputs) 2 — ns — 1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI peripheral functional clock. 2. tperiph = 1/fperiph 3. Time to data active from high-impedance state 4. Hold time to high-impedance state LP2 LP10 LP6 LP7 MSB IN BIT 6 . . . 1 SLAVE MSB SLAVE LSB OUT LP11 LP5LP5LP3 LP8 LP4 NOTE: Not defined LP11 SEE NOTE LP9 see note (INPUT) (CPOL=0) SCK SCK (CPOL=1) PCS (INPUT) (INPUT) SIN (INPUT) SOUT (OUTPUT) LSB INBIT 6 . . . 1

Figure 21. LPSPI slave mode timing (CPHA = 0)

Figure 22. LPSPI slave mode timing (CPHA = 1)

4.6.3 Inter-Integrated Circuit Interface (I2C) specifications

Table 52. I 2C timing Hold time (repeated) START condition.

  1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
  2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
  1. Input signal Slew = 10 ns and Output Load = 50 pF
  2. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
  3. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must

1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

  1. Cb = total capacitance of the one bus line in pF.

Table 53. I 2C 1 Mbps timing period, the first clock pulse is generated.

  1. Cb = total capacitance of the one bus line in pF.

Figure 23. Timing definition for devices on the I2C bus

4.6.4 Improved Inter-Integrated Circuit Interface (MIPI-I3C) specifications

Unless otherwise specified, MIPI-I3C specifications are timed to/from the VIH and/or VIL signal points.

Table 54. MIPI-I3C specifications when communicating with legacy I2C devices

  1. Cb = total capacitance of the one bus line in pF.

Table 55. MIPI-I3C open drain mode specifications

  • ENTAS0
  • ENTAS1
  • ENTAS2
  • ENTAS3 38.4 n 38.4 n 38.4 n 38.4 n 1 μ 100 μ 2 m 50 m s s s s Table continues on the next page... NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 66 / 102

Table 55. MIPI-I3C open drain mode specifications (continued)

  1. Cb = total capacitance of the one bus line in pF.

Table 56. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes

  • Master mode
  • Slave mode tCR + 3 and tCF + 3 ns tSU_PP SDA signal setup 3 — — ns tCASr Clock after repeated START (Sr) tCAS (min) — — ns tCBSr Clock before repeated START (Sr) tCAS (min)/2 — — ns Cb Capacitive load per bus line — — 50 pF 1. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that I2C devices do not interpret I3C signaling as valid I2C signaling. NXP Semiconductors Peripheral operating requirements and behaviors Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 67 / 102
  1. It doesn't include output pad delay.

Figure 24. Timing definition for devices on the I2C bus

4.6.5 USB High-Speed PHY specifications

  • Universal Serial Bus Specification, Revision 2.0, 2000, with amendments including the ones listed below:
  • Errata for “USB Revision 2.0 April 27, 2000” as of 12/7/2000
  • Errata for “USB Revision 2.0 April 27, 2000” as of May 28, 2002
  • Pull-up / Pull-down Resistors (USB Engineering Change Notice)
  • Suspend Current Limit Changes (USB Engineering Change Notice)
  • Device Capacitance (USB Engineering Change Notice)
  • USB 2.0 Connect Timing Update (USB Engineering Change Notice as of April 4, 2013)
  • USB 2.0 VBUS Max Limit (USB Engineering Change Notice)
  • On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification, Revision 2.0 version 1.1a, July 27, 2012
  • Maximum VBUS Voltage (USB OTGEH Engineering Change Notice)
  • Universal Serial Bus Micro-USB Cables and Connectors Specification, Revision 1.01, 2007 USB1_VBUS pin is a detector function which is 5V tolerant and complies with the above specifications without needing any external voltage division components. The USB HS PHY does not support operation when VDD_CORE is configured to 1.0V level NOTE

4.6.6 CAN switching specifications

See General switching specifications.

4.6.7 I2S/SAI switching specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. All timing shown is also with respect to input signal transitions of 3 ns and a 50 pF maximum load.

Table 57. I2S/SAI master mode timing

  • OD mode
  • SD mode
  • MD mode 28.6 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 40 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid — 8.4 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 1 — ns S7 I2S_TX_BCLK to I2S_TXD valid — 10 ns S8 I2S_TX_BCLK to I2S_TXD invalid 1 — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK
  • P2 and P3
  • P1 15.6 — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns S1 S2 S2 S9 S10 S10 I2S_MCLK (output) I2S_TX_BCLK/ I2S_RX_BCLK (output) I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) I2S_TXD I2S_RXD

Figure 25. I2S/SAI timing — master modes

Table 58. I2S/SAI slave mode timing

  • OD mode
  • SD mode
  • MD mode — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 6 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 20 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid -1.5 — ns S17 I2S_RXD setup before I2S_RX_BCLK 6 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion for I2S_TXD output valid 1 — 25 ns 1. Applies to first in each frame and only if the TCR4[FSE] bit is clear S15 S13 S15 S17 S18 S15 S16 S16 S14 S16 S11 S12 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) I2S_TX_FS/ I2S_RX_FS (output) I2S_TXD I2S_RXD I2S_TX_FS/ I2S_RX_FS (input) S19

Figure 26. I2S/SAI timing — slave modes

4.6.8 Flexible IO controller (FlexIO)

Table 59. FlexIO Timing Specifications

  1. Assumes pins muxed on same VDD_Px domain with same load

4.7 Human Machine Interface (HMI) modules

4.7.1 Microphone (MIC)

in Table 60 depends on the selected quality mode as shown in Table 61 . Table 60. Timing Parameters

  1. Depending on K value, the user must make sure floor(K x CLKDIV) > 1 to avoid timing problems

Table 61. K factor value Figure 27. Input/Output Timing Requirements

4.7.2 General Purpose Input/Output (GPIO)

See General switching specifications.

4.8 Security modules

4.8.1 Tamper

Table 62. Tamper electrical specifications

  • low temperature detect
  • high temperature detect -38 128 -50 135 -64 143 Temperature Tamper No flag range –37 125 °C Low Voltage Detect Threshold 1.613 1.656 1.698 V High Voltage Detect Threshold 3.65 3.75 3.848 V Voltage Tamper Detect operational temperature
  • no false alarms
  • with possible false alarms -38 -64 125 143

5 Package dimensions

5.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

6 Pinout

6.1 MCXN23x Signal Multiplexing and Pin Assignments

  1. Click the paperclip symbol on the left side of the PDF window.
  2. Double-click on the Excel file to open it.
  3. Select the MCXN23x_Pinmux tab.

The Port Control Module is responsible for selecting which ALT functionality is available on each pin.

Table 63. Pinmux Assignments Table continues on the next page...

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0 IO Supply - VDD_P3

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  1. For BGA package, all balls with same name are shorted together on BGA package.
  2. VSS_ANA and VSS_P4 are shorted together on package.
  3. +I3C in Pad Type represents strong pull up resistor is implemented on the pin. PV bit is implemented in the Pin Control register
  4. +I2C in Pad Type represents I2C filter is implemented on the pin. PFE bit is implemented in the Pin Control register of the pin
  5. DIS in default column means the pin's input buffer is disabled by default
  6. AON and RST pads support passive filter. PFE bit is implemented in the Pin Control register of the pin
  7. PE, PS, SRE, ODE and DSE are supported in the Pin Control register of all types of IO.

6.2 MCXN23x Pinout Diagrams

  1. Click the paperclip symbol on the left side of the PDF window.
  2. Double-click on the Excel file to open it.
  3. Select the respective package tab.

MCXN23x_Pinmux tab in the Excel file.

6.3 Recommended connection for unused analog and digital pins

Table 64. Recommended connection for unused interfaces regulator should also be disabled in software. regulator should also be disabled in software. DCDC_LX to VSS with a 10 kΩ resistor. 1, and PORT 2. It must be powered during POR. Table continues on the next page...

Table 64. Recommended connection for unused interfaces (continued)

7 Ordering parts

7.1 Determining valid orderable parts

8 Part identification

Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part.

8.1 Description

8.2 Part number format

Table 65. Part number fields descriptions

  • DF = 184 VFBGA (9 x 9 x 0.85 mm, 0.5mm pitch)
  • T = Tray

8.3 Example

8.4 Package marking

8.4.1 Package marking information

  • First line: NXP logo
  • Second line: Part number, minus the package extension info (ex. part# = PMCXN236VDFT, marking = PMCXN236VDFT)
  • Third line: Lot Information: (assembly site + wafer/diffusion lot + assembly lot)
  • Fourth line: Trace Code: (year + work week) NXP Semiconductors Part identification Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 95 / 102
  • Fifth line: Mask set

Table 66. Package marking

9 Terminology and guidelines

9.1 Definitions

  • Operating ratings apply during operation of the chip.
  • Handling ratings apply when the chip is not powered. The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. NOTE Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
  • Lies within the range of values specified by the operating behavior
  • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. NOTE NXP Semiconductors Terminology and guidelines Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 96 / 102

9.2 Examples

9.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V NXP Semiconductors Terminology and guidelines Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 97 / 102

9.4 Relationship between ratings and operating requirements

  • No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

9.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

  • Never exceed any of the chip’s ratings.
  • During normal operation, don’t exceed any of the chip’s operating requirements.
  • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. The following table provides a revision history for this document.

Table 67. Revision History

2 May 2024 Initial release

Revision History

Arm® Cortex®-M33 150MHz 32-bit MCU, up to 1MB Flash, Rev. 2, 05/2024 Data Sheet: Technical Data 98 / 102

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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2024. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 05/2024 Document identifier: MCXN23x