Microcontroller

MCXE317MPB

NXP Semiconductors

SIL2 robust 5V Arm Cortex M7 MCU Rev. 3 - 2 February 2026

Manufacturer: NXP Semiconductors

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Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 80

Technical content

Datasheet sections

1 Overview
2 Block diagram
3 Feature comparison
4 Ordering information (flash vs package)
4.1 Determining valid orderable parts
5 General
5.1 Absolute maximum ratings
5.2 Voltage and current operating requirements
5.3 Thermal operating characteristics
5.4 ESD and Latch-up Protection Characteristics
5.5 Thermal Attributes
5.5.1 Description
5.5.2 Thermal characteristics
6 Power management
6.1 Power mode transition operating behaviors
6.1.1 Power mode transition operating behavior
6.1.2 Boot time, HSE firmware not installed
6.1.3 Boot time, HSE firmware installed
6.1.4 HSE firmware memory verification time examples
6.2 Supply Monitoring
6.3 Recommended Decoupling Capacitors
6.3.1 Recommended Decoupling Capacitor diagrams
6.4 V15 regulator (BJT option, NPN ballast transistor
6.5 Supply currents
6.6 Operating mode
6.7 Cyclic wake-up current
7 I/O parameters
8 Glitch Filter
9 Flash memory specification
9.1 Flash memory program and erase specifications
9.2 Flash memory Array Integrity and Margin Read
9.3 Flash memory module life specifications
9.3.1 Data retention vs program/erase cycles
9.4 Flash memory AC timing specifications
9.5 Flash memory read timing parameters
10 Analog modules
10.1 SAR_ADC
10.2 Supply Diagnosis
10.3 Low Power Comparator (LPCMP)
10.4 Temperature Sensor
11 Clocking modules
11.1 FIRC
11.2 SIRC
11.3 PLL
11.4 FXOSC
11.5 SXOSC
12 Communication interfaces
12.1 LPSPI
12.2 LPSPI0 15 MHz
12.3 I2C
12.4 FlexCAN characteristics
12.5 SAI electrical specifications
12.5.1 SAI Electrical Characteristics, Slave Mode
12.5.2 SAI Electrical Characteristics, Master Mode
12.6 Ethernet characteristics
12.6.1 Ethernet MII (10/100 Mbps)
12.6.2 Ethernet RMII (10/100 Mbps)
12.6.3 MDIO timing specifications
12.7 QuadSPI
12.8 LPUART specifications
13 Debug modules
13.1 Debug trace timing specifications
13.2 SWD electrical specifications
13.3 JTAG electrical specifications
14 Package dimensions
14.1 Obtaining package dimensions
15 Revision history

Features

Arm® Cortex®-M7 160 MHz with 846 CoreMark® (5.28 CoreMark/MHz)
IEC 61508 SIL2 certified.
Platform Security with EdgeLock® Secure Enclave, Advanced Profile.
-40 °C to +135 °C junction temperature range. Operating characteristics
Voltage range: 2.97 V to 5.5 V
Ambient temperature range: -40 °C to 125 °C for all power modes Arm™ Cortex-M7 core, 32-bit CPU
M7 supports up to 160 MHz frequency
Arm Core based on the Armv7 and Thumb®-2 ISA
Integrated Digital Signal Processor (DSP)
Configurable Nested Vectored Interrupt Controller (NVIC)
Single Precision Floating Point Unit (FPU) Clock interfaces
8 - 40 MHz Fast External Oscillator (FXOSC)
48 MHz Fast Internal RC oscillator (FIRC)
32 kHz Low Power Oscillator (SIRC)
32 kHz Slow External Oscillator (SXOSC)
System Phased Lock Loop (SPLL) I/O and package
LQFP48, HDQFP100, HDQFP172
Up to 32-channel DMA with up to 128 request sources using DMAMUX Memory and memory interfaces
Up to 4 MB program flash memory with ECC
Up to 128 KB of flexible program or data flash memory
Up to 512 KB SRAM with ECC, includes 96 KB of TCM RAM ensuring maximum CPU performance of fast control loops with minimal latency
Data and instruction cache for each core to minimize performance impact of memory access latencies
QuadSPI support 48LQFP 7 x 7 x 1.4 mm, 0.5 mm 100HDQFP 10 x 10 x 1.65 mm, 0.65 mm 172HDQFP 16 x 16 x 1.65 mm, 0.65 mm MCX E315/316/317/31B SIL2 robust 5V Arm Cortex M7 MCU Rev. 3 — 2 February 2026 Product data sheet

Up to three 12-bit Analog-to-Digital Converters (ADC) with up to 24 channel analog inputs per module
One Temperature Sensor (TempSense)
Up to three Analog Comparators (CMP), with each comparator having an internal 8-bit DAC Human-Machine Interface (HMI)
Up to 145 GPIO pins
Non-Maskable Interrupt (NMI)
Up to 59 pins with wakeup capability
Up to 32 pins with interrupt support Power management
Low-power Arm Cortex-M7 core with excellent energy efficiency, balanced with performance
Power Management Controller (PMC) with simplified mode management (RUN and STANDBY)
Supports peripheral specific clock gating. Only specific peripherals remain working in low power modes. Communications interfaces
Up to 16 serial communication interface (LPUART) modules, with LIN, UART and DMA support
Up to six Low Power Serial Peripheral Interface (LPSPI) modules with DMA support
Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support
Up to Six FlexCAN modules (with optional CAN-FD support)
FlexIO module for flexible and high performance serial interfaces
Up to one ethernet modules
Up to two Synchronous Audio Interface (SAI) modules Reliability, safety and security
Up to two Internal Software Watchdog Timers (SWT)
Error-Correcting Code (ECC) on all memories
Error Detection Code (EDC) on data path
Cyclic Redundancy Check (CRC) module
120-bit Unique Identification (ID) number
Extended Cross domain Domain Controller (XRDC), providing protection for master core access rights
Virtualization Wrapper (VIRT_WRAPPER), providing I/O protection Debug functionality
Serial Wire JTAG debug Port (SWJ-DP), with 2 pin Serial Wire Debug (SWD) for external debugger
Debug Watchpoint and Trace (DWT), with four configurable comparators as hardware watchpoints
Serial Wire Output (SWO)-synchronous trace data support
Instrumentation Trace Macrocell (ITM) with software and hardware trace, plus time stamping
CoreSight AHB Trace Macrocell (HTM)
Flash Patch and Breakpoints (FPB) with ability to patch code and data from code space to system space
Serial Wire Viewer (SWV): A trace capability providing displays of reads, writes, exceptions, PC Samples and print
Full data trace for up to 16 output wide NXP Semiconductors MCX E315/316/317/31B SIL2 robust 5V Arm Cortex M7 MCU MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 February 2026 Document feedback

Embedded Cross Trigger (ECT) is used for multicore run-control and trace cross triggering, using CoreSight Cross Trigger Interface (CTI) Timing and control
Up to three enhanced modular I/O system (eMIOS), offering up to 72 timer channels (IC/OC/PWM)
Up to two System Timer Modules (STM)
Up to two Logic Control Units (LCU)
Full cross triggering support for ADC / timer (BCTU)
One Trigger MUX Control (TRGMUX) module
Up to three Periodic Interrupt Timer (PIT) modules
32-bit Real Time Counter (RTC) with autonomous periodic interrupt (API) function NXP Semiconductors MCX E315/316/317/31B SIL2 robust 5V Arm Cortex M7 MCU MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 February 2026 Document feedback

1 Overview

series to take advantage of more memory or feature integration.

2 Block diagram

Figure 1. MCX E31 product series block diagram MCU

3 Feature comparison

MCX E315
MCX E316
MCX E317 NXP Semiconductors MCX E315/316/317/31B SIL2 robust 5V Arm Cortex M7 MCU MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 February 2026 Document feedback

MCX E31B

4 Ordering information (flash vs package)

The following table lists the available part numbers and their associated flash size / package. Table 2. Ordering information

4.1 Determining valid orderable parts

To determine the orderable part numbers for this device, please contact NXP sales representative.

5 General

5.1 Absolute maximum ratings

of the chip under conditions - specified as absolute maximum ratings - is not implied. only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table for specific conditions. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 3. Absolute maximum ratings [1] 6.0 V maximum for 10 hours over lifetime; 7.0 V maximum for 60 seconds over lifetime. [2] All voltages are referred to VSS unless otherwise specified. (I_INJPAD_DC_ABS is respected). more details and recommendations for protecting the devices against injection current. VDD_HV_B) may lift and cause unexpected behavior. Therefore, it is recommended to add external protection hardware, to safely cover this scenario. [6] TSTG specifies the storage temperature range. It is not the operating temperature range. Please refer to the Thermal operating characteristics table.

5.2 Voltage and current operating requirements

Table 4. Voltage and current operating requirements Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 4. Voltage and current operating requirements...continued [1] All voltages are referred to VSS unless otherwise specified. injected must be lower than IINJPAD_DC_OP, all the time. [4] Open-drain outputs must be pulled respectively to their supply rail (VDD_HV_A or VDD_HV_B). MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Guidelines AN for more details and recommendations for protecting the devices against injection current. VDD_HV_B) may lift and cause unexpected behavior. Therefore, it is recommended to add external protection hardware, to safely cover this scenario. guidelines available on www.nxp.com are followed. power dissipation allowed for a given package.

5.3 Thermal operating characteristics

Table 5. Thermal operating characteristics [2] The device operating specification is not guaranteed beyond 135 °C TJ. [3] The maximum operating requirement applies to all chapters unless otherwise specifically stated. [4] Operating at maximum conditions for extended periods may affect device reliability. Refer to Product Lifetime Usage application note (AN14180).

5.4 ESD and Latch-up Protection Characteristics

Table 6. ESD and Latch-up Protection Characteristics [2] This parameter is tested in conformity with JEDEC-JS-001. [3] This parameter is tested in conformity with JEDEC-JS-002. [4] This parameter is tested in conformity with JEDEC-JESD78.

5.5 Thermal Attributes

5.5.1 Description

The tables in the following sections describe the thermal characteristics of the device. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

5.5.2 Thermal characteristics

Junction temperature of the device does not solely depend on package thermal resistance but is also a function of chip power dissipation, PCB attributes, environmental conditions (ambient temperature & air flow) and cumulative effects of other heat generating ICs on the PCB.
The appropriate thermal design must be carried out on package so that it can safely dissipate the necessary amount of power needed for it to function properly without exceeding the maximum junction temperature. This may involve adding a cooling solution on the package, creating thermal enhancements on the PCB and improving environmental conditions.
The customer is encouraged to use the package model to perform design and risk assessment through simulations. Package models in FloTHERM or Icepak formats can be obtained under NDA from the sales team. Thermal Ratings
The table below is the package thermal ratings for LQFP and HDQFP package variants. These numbers are derived through simulations based on standardized tests as described in the footnotes.
Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment :

Table 7. Thermal characteristics [2] Thermal test board meets JEDEC specification for this package (JESD51-9).

6 Power management

6.1 Power mode transition operating behaviors

6.1.1 Power mode transition operating behavior

Table 8. Power mode transition operating behaviour

6.1.2 Boot time, HSE firmware not installed

Table 9. Boot time, HSE firmware not installed

6.1.3 Boot time, HSE firmware installed

corresponding user code verification time must be added. Table 10. Boot time, HSE firmware installed Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 10. Boot time, HSE firmware installed...continued

6.1.4 HSE firmware memory verification time examples

Table 11. HSE firmware memory verification time examples Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 11. HSE firmware memory verification time examples...continued Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

6.2 Supply Monitoring

Certain monitors are present on certain devices. See Power Management chapter in reference manual. Table 12. Supply Monitoring Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 12. Supply Monitoring...continued

6.3 Recommended Decoupling Capacitors

Table 13. Recommended Decoupling Capacitors Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 13. Recommended Decoupling Capacitors...continued [1] These capacitors must be placed as close as possible to the corresponding supply and ground pins. [2] All capacitors must be low ESR ceramic capacitors (for example, X7R). The minimum recommendation is after considering component aging and tolerance. [3] Optionally, 1 nF capacitors can be added in parallel to the decoupling capacitors. [4] These capacitors must be placed close to the source. [5] For devices where the VDD_HV_B domain is present, if the VDD_HV_B supply is different supply from VDD_HV_A, a dedicated bulk capacitor is needed. [6] It is also possible to use higher capacitance values (for example, 10 μF) in place of the 4.7 μF capacitor. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

6.3.1 Recommended Decoupling Capacitor diagrams

Figure 2. 48-pin LQFP decoupling capacitor pinout diagram (MCXE315/MCXE316) MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

87 VDD_HV_A

Figure 3. 100-pin HDQFP decoupling capacitor pinout diagram (MCXE315/MCXE316 and MCXE317) MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

108 VDD_HV_A

Figure 4. 172-pin HDQFP decoupling capacitor pinout diagram (MCXE317) MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

169 VDD_HV_A

Figure 5. 172-pin HDQFP decoupling capacitor pinout diagram (MCXE31B) MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

6.4 V15 regulator (BJT option, NPN ballast transistor control) electrical specifications

design guidelines document lists the recommended part numbers for the external devices. Table 14. V15 regulator (BJT option, NPN ballast transistor control) electrical specifications Figure 6. Ballast circuit

6.5 Supply currents

Table 15. STANDBY mode supply currents Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 15. STANDBY mode supply currents...continued [1] See the configurations in Table 21. [2] IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application. for the fast silicon process. Note: All data in this table is preliminary and based on first samples. device), temperature = 25 °C, and typical silicon process unless otherwise stated. Table 16. Low speed RUN mode supply currents Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 16. Low speed RUN mode supply currents...continued [1] Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation. [3] IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application. [4] RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail. for the typical silicon process. V15 = 1.65V, for the fast silicon process. Note: All data in this table is preliminary and based on first samples. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

device), temperature = 25 °C and typical silicon process unless otherwise stated. Table 17. RUN mode supply currents (peripherals disabled) for MCX E31B [1] Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation. [2] See the configurations in Table 22. [3] RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail. [4] IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application. [5] RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail. for the typical silicon process. V15= 1.65V, for the fast silicon process. Note: The data in this table is preliminary and based on first samples. device), temperature = 25 °C and typical silicon process unless otherwise stated. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 18. RUN mode supply currents (peripherals disabled) for MCX E315/MCX E316 and MCX E317 [1] Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation. [2] See the configurations in Table 22. [3] IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application. [4] RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail. [5] RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail. for the typical silicon process. V15 = 1.65V, for the fast silicon process. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Note: The data in this table is preliminary and based on first samples. device), temperature = 25 °C and typical silicon process unless otherwise stated. Table 19. Example RUN mode configuration supply currents for MCX E31B [1] Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation. [2] See the configurations in Table 22. [3] RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail. [4] IO current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application. [5] RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail. for the typical silicon process. V15 = 1.65V, for the fast silicon process. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 20. Example RUN mode configuration supply currents for MCX E315/MCX E316 and MCX E317 [1] Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation. [2] See the configurations in Table 22. [3] IO current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application. [4] RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail. [5] RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail. [9] If the total power dissipation would cause the junction temperature to be exceeded when VDD_HV_A is at 5V, then VDD_HV_A should be limited to operate at 3.3V. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

6.6 Operating mode

Table 21. STANDBY and low speed RUN configuration options [1] See clocking use case examples in the Clocking chapter of the MCXE31 Reference Manual. Table 22. RUN mode configuration options Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 22. RUN mode configuration options...continued [1] See clocking use case examples in the Clocking chapter of the MCXE31 Reference Manual. [2] ELE_HSEB: After start-up, the HSE core is in WFI. [3] • FlexCAN0: Transmitting an 8-byte CAN-FD data frame at 5 Mbps, every 10 ms.

FlexCAN1: Transmitting a 64-byte CAN-FD data frame at 2 Mbps, every 20 ms.
FlexCAN2-5: Transmitting an 8-byte CAN data frame at 500 Kbps, every 20 ms. [4] LPUART0-15: Transmitting at 19200 bps, every 100ms. [5] • LPSPI0: Transmitting 32 bits at 20 Mbps (GPIO Fast pads), every 5 ms.
LPSPI1-5: Transmitting 32 bits at 1 Mbps, every 5 ms. [6] LPI2C0-1: Transmitting 3 bytes at 400 Kbps, every 100ms. [7] EMAC/GMAC: ON for MII interface. [8] • eMIOS0: 6 channels in PWM mode @ 20 KHz.
eMIOS1-2: 8 channels in PWM mode @ 400 Hz. [9] • SAR_ADC0: 16 channels at 400 Hz rate, BCTU triggered.
SAR_ADC1-2: 4 channels at 20 KHz rate, BCTU triggered. [10] LPCMP0: 8 channels enabled; LPCMP1-2: 4 channels enabled.

6.7 Cyclic wake-up current

for approximately 200μs to scan several GPIO inputs (51 GPIOS), and spends the rest of the time in STANDBY mode. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 23. Cyclic wake-up current example [1] The supply current is obtained through the measurements of the current during the corresponding operating mode. [2] The duration is defined by the application (how much time will the device spend in the according operating mode). [3] The ratio of duration is obtained by dividing the duration of the corresponding operating mode by the total duration of the application. [4] The current according to ratio is obtained by multiplying the supply current and the ratio of duration related to the proper operating mode. [5] The average current is calculated by the addition of each device operating mode’s current according to ratio.

7 I/O parameters

and the number of Analog functions (CMP and ADC channels) multiplexed per pin. "Analog Function Count" is shown in the Condition column of the following table. Table 24. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

[1] Maximum length of RESET pulse will be filtered by an internal filter on this pin. [2] Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

values for I/O transition times are not representative of the I/O pad behavior when connected to an actual transmission line load. [5] I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating Conditions of this document. asynchronous to each other, so not all switching occurs at the same instant. Actual use case must be considered.

See IBIS models for further details.

Figure 7. Reference Load Diagram and the number of Analog functions (CMP and ADC channels) multiplexed per pin. "Analog Function Count" is shown in the Condition column of the following table. Table 25. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

[1] Maximum length of RESET pulse will be filtered by an internal filter on this pin. [2] Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. values for I/O transition times are not representative of the I/O pad behavior when connected to an actual transmission line load. [5] I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating Conditions of this document. should be matched closely to the selected output resistance (ROUT_*) of the I/O pad. asynchronous to each other, so not all switching occurs at the same instant. Actual use case must be considered.

See IBIS models for further details.

Figure 8. Reference Load Diagram Table 26. 5.0V (4.5V - 5.5V) GPIO Output AC Specification Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 27. 3.3V (2.97V - 3.63V) GPIO Output AC Specification Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

8 Glitch Filter

The glitch filter parameters in the following table apply to the filters of WKPU pins and TRGMUX inputs 60-63. Table 28. Glitch Filter [1] Pulses in between the max filtered and min unfiltered may or may not be passed through. [2] Pulses shorter than defined by the maximum value are guaranteed to be filtered (not passed). [4] Pulses larger than defined by the minimum value are guaranteed to not be filtered (passed).

9 Flash memory specification

9.1 Flash memory program and erase specifications

Table 29. Flash memory program and erase specifications [1] Program times are actual hardware programming times and do not include software overhead. Sector program times assume quad-page programming. times may be used for throughput calculations. [3] Conditions: ≤ 25 cycles, nominal voltage. [4] Plant Programing times provide guidance for timeout limits used in the factory. values may be used for throughput calculations. [6] Conditions: -40°C ≤TJ ≤135°C, full spec voltage.

9.2 Flash memory Array Integrity and Margin Read specifications

Table 30. Flash memory Array Integrity and Margin Read specifications Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 30. Flash memory Array Integrity and Margin Read specifications...continued read, dual read, quad read contribution. Thus for a read setup that requires 6 clocks to read Nread would equal 6. [2] Array Integrity times are actual hardware execution times and do not include software overhead or system code execution overhead.

9.3 Flash memory module life specifications

Table 31. Flash memory module life specifications 1 MB and 2 MB blocks using Sector Erase. [1] Program and erase supported for factory conditions. Nominal supply values and operation at 25°C. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

9.3.1 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. Figure 9. Data retention vs program/erase cycles

9.4 Flash memory AC timing specifications

Table 32. Flash memory AC timing specifications Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 32. Flash memory AC timing specifications...continued [1] For Block Erase, Tdones times may be 3x max spec.

9.5 Flash memory read timing parameters

Table 33. Flash Read Wait State Settings MCXE315/MCXE316/MCXE317/MCXE31B

250 KHz < Freq ≤ 66 MHz 1

66 MHz < Freq ≤ 100 MHz 2

100 MHz < Freq ≤ 133 MHz 3

133 MHz < Freq ≤ 167 MHz 4

10 Analog modules

10.1 SAR_ADC

[1] Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference supply design for SAR_ADC. [2] VSS and VREFL should be shorted on PCB. 100mV difference between VSS and VREFL is for transient only (not for DC). [3] This is ADC Input range for ADC accuracy guaranteed in this input range only. For SoC Pin capability, see Operation Condition Section. [5] TUE spec for precision and standard channels is based on 12-bit level resolution. Figure 10. SAR_ADC Input Circuit

10.2 Supply Diagnosis

The table below gives the specification for the on die supply diagnosis. Table 35. Supply Diagnosis smaller sampling time leads to a less accurate result. [3] If V15 > VDD_HV_A +100mV then the V15 measurement via anamux may be imprecise. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

10.3 Low Power Comparator (LPCMP)

Table 36. Low Power Comparator (LPCMP) Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 36. Low Power Comparator (LPCMP)...continued pull up/down is recommended). VDD_HV_B. These channels must be disabled when VDD_HV_A goes below VDD_HV_B. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 14. Typical Hysteresis vs VAIN (VDD_HV_A = 5 V, Low Speed Mode).png

10.4 Temperature Sensor

The table below gives the specification for the MCU on-die temperature sensor. Table 37. Temperature Sensor smaller sampling time leads to a less accurate result. previous active state of the circuit elements on die. [3] The error caused by ADC conversion and provided temperature calculation formula is not included. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

11 Clocking modules

11.1 FIRC

Table 38. FIRC [1] Startup time is for reference only.

11.2 SIRC

Table 39. SIRC [1] Startup time is for information only.

11.3 PLL

Jitter values specified in this table are applicable for FXOSC reference clock input only. Table 40. PLL Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 40. PLL...continued [2] Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma . [3] Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement.

11.4 FXOSC

Table 41. FXOSC...continued [1] For bypass mode applications, the EXTAL pin should be driven low when FXOSC is in off/disabled state. mode for all other supported frequencies and crystals remain the same. To ensure stable oscillations, FXOSC incorporates the feedback resistance internally. In single ended bypass mode, the XTAL pin can be left unconnected. the crystal drive level rating. In such cases, contact NXP sales representative for selecting the correct crystal. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

11.5 SXOSC

Table 42. SXOSC

12 Communication interfaces

12.1 LPSPI

of the transfer attributes are programmable. The following table provides timing characteristics for classic LPSPI timing modes.

All timing is shown with respect to 50% VDD_HV_A/B thresholds.
All measurements are with maximum output load of 30pF input transition of 1 ns and pad configured DSE = 1, SRC = 0.

Figure 19. LPSPI Master Mode Timing (CPHA=0) Figure 20. LPSPI Master Mode Timing (CPHA=1)

12.2 LPSPI0 15 MHz

Note: Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.

12.3 I2C

See I/O parameters for I2C specification.

12.4 FlexCAN characteristics

See I/O parameters for FlexCAN specification.

12.5 SAI electrical specifications

12.5.1 SAI Electrical Characteristics, Slave Mode

input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Valid pin combinations to be referred from MCXE_Use sheet in IOmux. Table 45. SAI Electrical Characteristics, Slave Mode Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 45. SAI Electrical Characteristics, Slave Mode...continued the board design or by the master timing. Figure 21. SAI slave mode

12.5.2 SAI Electrical Characteristics, Master Mode

input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b 0. I/O operating voltage ranges from 2.97 V to 3.63 V. Valid pin combinations to be referred from MCXE31x*_Use sheet in IOmux. Table 46. SAI Electrical Characteristics, Master Mode Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 46. SAI Electrical Characteristics, Master Mode...continued Figure 22. SAI master mode

12.6 Ethernet characteristics

12.6.1 Ethernet MII (10/100 Mbps)

configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Valid pin combinations to be referred from MCXE31x*_Use sheet in IOmux. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 47. Ethernet MII (10/100 Mbps) Figure 23. MII receive diagram MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 24. MII transmit diagram

12.6.2 Ethernet RMII (10/100 Mbps)

configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Valid pin combinations to be referred from MCXE_Use sheet in IOmux. Table 48. Ethernet RMII (10/100 Mbps) Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 48. Ethernet RMII (10/100 Mbps)...continued Figure 25. RMII receive diagram MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 26. RMII transmit diagram

12.6.3 MDIO timing specifications

2.97 V to 3.63 V. MDIO pin must have external Pull-up. Valid pin combinations to be referred from MCXE31x*_Use sheet in IOmux. Table 49. MDIO timing specifications Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 49. MDIO timing specifications...continued Figure 27. MII/RMII serial management channel timing

12.7 QuadSPI

The following table applies to MCXE31B. Reference Manual for register and bit descriptions. Program register value QuadSPI_FLSHCR[TCSS] = 4\`h3. Program register value QuadSPI_FLSHCR[TCSH] = 4\`h3. Program register value QuadSPI_DLLCRA[SLV_FINE_OFFSET] to 4'b0001. transitions measured at mid-supply. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 50. QuadSPI Quad 3.3V SDR 120MHz 6.5ns, then maximum fSCK is 104MHz. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 28. QuadSPI input timing (SDR mode) Figure 29. QuadSPI output timing (SDR mode)

12.8 LPUART specifications

See I/O parameters for LPUART specifications.

13 Debug modules

13.1 Debug trace timing specifications

input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. See I/O parameters for GPIO electrical specifications. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 51. Debug trace timing specifications Figure 30. Trace CLKOUT specifications

13.2 SWD electrical specifications

transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. Table 52. SWD electrical specifications Table continues on the next page... MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 52. SWD electrical specifications...continued Figure 31. SWD Input Clock Timing Figure 32. SWD Output Data Timing

13.3 JTAG electrical specifications

The following table describes the JTAG electrical characteristics. These specifications apply to JTAG and boundary scan. Measurements are with maximum output load of 30pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 53. JTAG electrical specifications [2] Cycle time is 30ns assuming full cycle timing. Cycle time is 60ns assuming half cycle timing. [3] Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. [4] Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay. MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 35. Boundary Scan Timing

14.1 Obtaining package dimensions

The following table lists the changes in this document. 2 February 2026 • Updated Document ID and title.

Corrected Ambient temperature TA to 125 °C
Corrected maximum temperature TJ to 135 °C
Updated SIL2 related content as MCX E is SIL2 certified. MCXEP172M160 FB0 v.2.0 4 December 2024 • Initial release. NXP Semiconductors MCX E315/316/317/31B SIL2 robust 5V Arm Cortex M7 MCU MCXEP172M160FB0 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 2 February 2026 Document feedback

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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2026 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 2 February 2026 Document identifier: MCXEP172M160FB0

Product Information

MCXE317MPB specifications and overview.

Summary

SIL2 robust 5V Arm Cortex M7 MCU Rev. 3 - 2 February 2026

Description

SIL2 robust 5V Arm Cortex M7 MCU Rev. 3 - 2 February 2026

Source title MCXE317MPB Datasheet(PDF) - NXP Semiconductors

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