MCXE245 NXP | Alldatasheet

Document overview

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Technical content

Features

  • Voltage range: 2.7 V to 5.5 V
  • Ambient temperature range: -40 °C to 105 °C for HSRUN mode, -40 °C to 125 °C for RUN mode Arm™ Cortex-M4F 32-bit CPU
  • Supports up to 112 MHz frequency (HSRUN mode) with 1.25 Dhrystone MIPS per MHz
  • Arm Core based on the Armv7 Architecture and Thumb®-2 ISA
  • Integrated Digital Signal Processor (DSP)
  • Configurable Nested Vectored Interrupt Controller (NVIC)
  • Single Precision Floating Point Unit (FPU) Clock interfaces
  • 4 - 40 MHz fast external oscillator (SOSC) with up to 50 MHz DC external square input clock in external clock mode
  • 48 MHz Fast Internal RC oscillator (FIRC)
  • 8 MHz Slow Internal RC oscillator (SIRC)
  • 128 kHz Low Power Oscillator (LPO)
  • Up to 112 MHz (HSRUN) System Phased Lock Loop (SPLL))
  • Up to 20 MHz TCLK and 25 MHz SWD_CLK
  • 32 kHz Real Time Counter external clock (RTC_CLKIN) Power management
  • Low-power Arm Cortex-M4F with excellent energy efficiency
  • Power Management Controller (PMC) with multiple power modes: HSRUN, RUN, STOP, VLPR, and VLPS
  • Clock gating and low power operation supported on specific peripherals. Memory and memory interfaces
  • Up to 2 MB program flash memory with ECC
  • 64 KB FlexNVM for data flash memory with ECC and EEPROM emulation
  • Up to 256 KB SRAM with ECC
  • Up to 4 KB of FlexRAM for use as SRAM or EEPROM emulation
  • Up to 4 KB Code cache to minimize performance impact of memory access latencies
  • QuadSPI with HyperBus™ support Mixed-signal analog
  • Up to two 12-bit Analog-to-Digital Converter (ADC) with up to 32 channel analog inputs per module 48LQFP 7 x 7 x 1.4 mm, 0.5 mm 64LQFP 10 x 10 x 1.4 mm, 0.5 mm 100LQFP 14 x 14 x 1.4 mm, 0.5 mm 144LQFP 20 x 20 x 1.4 mm, 0.5 mm MCXE245/246/247 Robust 5V Arm Cortex M4F MCU with up to 2MB flash Rev. 2 — 14 July 2025 Product Data Sheet
  • One Analog Comparator (CMP) with internal 8-bit Digital to Analog Converter (DAC) Debug functionality
  • Serial Wire JTAG Debug Port (SWJ-DP) combines
  • Debug Watchpoint and Trace (DWT)
  • Instrumentation Trace Macrocell (ITM)
  • Test Port Interface Unit (TPIU)
  • Flash Patch and Breakpoint (FPB) Unit Human-Machine Interface (HMI)
  • Up to 128 GPIO pins with interrupt functionality
  • Non-Maskable Interrupt (NMI) Communications interfaces
  • Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support and low power availability
  • Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability
  • Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability
  • Up to three FlexCAN modules (with optional CAN- FD support)
  • FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc).
  • Up to one 10/100Mbps Ethernet with IEEE1588 support and two Synchronous Audio Interface (SAI) modules Safety
  • IEC61508: ready for system SIL2 using Safe Assure™ documentation and SW libraries
  • IEC60730: Class B certified
  • Error-Correcting Code (ECC) on flash and SRAM memories
  • System Memory Protection Unit (System MPU)
  • Cyclic Redundancy Check (CRC) module
  • Internal watchdog (WDOG)
  • External Watchdog monitor (EWM) module Security
  • Accelerator (CSEC) implements a comprehensive set of cryptographic functions as described in the SHE (Secure Hardware Extension) Functional Specification.
  • 128-bit Unique Identification (ID) number Timing and control
  • Up to eight independent 16-bit FlexTimers (FTM) modules, offering up to 64 standard channels (IC/OC/PWM)
  • One 16-bit Low Power Timer (LPTMR) with flexible wake up control
  • Two Programmable Delay Blocks (PDB) with flexible trigger system
  • One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels
  • 32-bit Real Time Counter (RTC) Package
  • 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, 144-pin LQFP package options NXP Semiconductors MCXE245/246/247 Robust 5V Arm Cortex M4F MCU with up to 2MB flash All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product Data Sheet MCXEP144M112F70
  • 16 channel DMA with up to 63 request sources using DMAMUX Notes
  • EdgeLock Accelerator (CSEC) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute EdgeLock Accelerator (CSEC) or EEPROM writes/erase.
  • The following two attachments are available with the Datasheet: — MCXE24x_Orderable_Part_Number_ List.xlsx — MCXE24x_Power_Modes_Configuration.xlsx NXP Semiconductors MCXE245/246/247 Robust 5V Arm Cortex M4F MCU with up to 2MB flash All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product Data Sheet MCXEP144M112F70

6.2.3.1 Fast internal RC Oscillator (FIRC)

6.2.3.2 Slow internal RC oscillator (SIRC)

6.2.4 Low Power Oscillator (LPO) electrical specifications .. 31

6.3.1 Flash memory module (FTFC/FTFM) electrical

7.3 General notes for specifications at maximum junction

MCXE24x Data Sheet, Rev. 2, 07/2025 NXP Semiconductors 3

1 Block diagram

Feature comparison for chip specific values.

48 MHz

8 MHz

accesses. In this document, the term MPU refers to NXP’s system MPU. execute EdgeLock Accelerator (CSEC) or EEPROM writes/erase. Figure 1. High-level architecture diagram for the MCXE24x family

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Figure 2. MCX E24x Series - Block diagram

2 Feature comparison

Table 1. MCXE24x product series comparison Table continues on the next page...

Table 1. MCXE24x product series comparison (continued) External memory interface 4 QuadSPI incl. Table continues on the next page...

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  1. No write or erase access to Flash module, including Security (EdgeLock Accelerator) and EEPROM commands, are

allowed when device is running at HSRUN mode (112MHz) or VLPR mode.

  1. Available when EEEPROM, EdgeLock Accelerator and Data Flash are not used. Else only up to 1,984 kB is available for
  2. 4 KB (up to 512 KB D-Flash as a part of 2 MB Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining

448 KB of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.

  1. See Dimensions section for package drawings
  2. QuadSPI is only supported on 144-pin LQFP

Ordering information

3.1 Selecting orderable part number

Not all part number combinations are available. See the attachment MCXE24x_Orderable_Part_Number_ List.xlsx attached with the Datasheet for a list of standard orderable part numbers.

3.2 Ordering information

r Etherne t GPIOs Pacakg e Flash Size RAM Size MCXE245VLF MCXE245VLFR

512 KB 64 KB 112 MHz 3x (1x with FD) ELA_CSE

112 MHz 3x (1x with FD) ELA_CSE

C 4x - 58 LQFP64 MCXE245VLL MCXE245VLLR C 4x - 89 LQFP100 MCXE246VLH MCXE246VLHR

1 MB 128 KB 112 MHz 3x (2x with FD) ELA_CSE

C 6x - 58 LQFP64 MCXE246VLL MCXE246VLLR

112 MHz 3x (2x with FD) ELA_CSE

C 6x - 89 LQFP100 Table continues on the next page... MCXE24x Data Sheet, Rev. 2, 07/2025 NXP Semiconductors 7

2 MB 256 KB 112 MHz 3x (3x with FD) ELA_CSE

112 MHz 3x (3x with FD) ELA_CSE

  1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search or

contact NXP sales, distributor, e-tailer.

  1. ELA_CESC is EdgeLock Accelerator (CSEC)

4.1 Absolute maximum ratings

  • Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table for specific conditions.
  • Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. All the limits defined in the datasheet specification must be honored together and any violation to any one or more will not guarantee desired operation.
  • Unless otherwise specified, all maximum and minimum values in the datasheet are across process, voltage, and temperature.

Table 2. Absolute maximum ratings for MCXE24x series Table continues on the next page...

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Table 2. Absolute maximum ratings for MCXE24x series (continued)

  1. All voltages are referred to V SS unless otherwise specified.
  2. As V DD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

  1. 60 seconds lifetime – No restrictions i.e. the part is not held in reset and can switch.

10 hours lifetime – The part is held in reset by an external circuit i.e. the part cannot switch. the part will operate with reduced functionality. If the given time limits or supply levels are exceeded, the device may get damaged.

  1. When input pad voltage levels are close to V DD or VSS, practically no current injection is possible.
  2. While respecting the maximum current injection limit
  3. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both

maximum absolute maximum ramp rate and typical operating conditions.

  1. This is the MCU supply ramp rate and the ramp rate assumes that the MCXE24x HW design guidelines are followed. Limit

applies to both maximum absolute maximum ramp rate and typical operating conditions.

  1. T J (Junction temperature)=125 °C. Assumes TA=125 °C for RUN mode
  • Assumes maximum θJA for 2s2p board. See Thermal characteristics 9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)

4.2 Voltage and current operating requirements

Table 3. Voltage and current operating requirements for MCXE24x series 1 external power supply source.

  1. Typical conditions assumes V DD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise
  2. As V DD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

  1. MCXE247 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged MCXE247 is guaranteed

to operate from 2.97 V. All other MCXE24 family devices operate from 2.7 V in all modes.

  1. V DD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

reference supply design for SAR ADC.

  1. V REFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V
  2. Open drain outputs must be pulled to V DD.
  3. When input pad voltage levels are close to V DD or VSS, practically no current injection is possible.

4.3 Thermal operating characteristics

Table 4. Thermal operating characteristics for MCXE24x series

  1. The device may operate at maximum T A rating as long as TJ maximum of 125 °C is not exceeded. The simplest method to

determine TJ is: TJ = TA + RθJA * chip power dissipation.

  1. T a = 125 °C is for RUN mode only.
  2. The device operating specification is not guaranteed beyond 125 °C T J.
  3. The maximum operating requirement applies to all chapters unless otherwise specifically stated.

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4.4 Power and ground pins

100 LQFP

144 LQFP

64 LQFP

48 LQFP

Figure 3. Pinout decoupling

Table 5. Supplies decoupling capacitors 1, 2

  1. V DD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

reference supply design for SAR ADC. All VSS pins should be connected to common ground at the PCB level.

  1. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type).
  2. Minimum recommendation is after considering component aging and tolerance.
  3. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel.
  4. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins.
  5. Contact your local Field Applications Engineer for details on best analog routing practices.
  6. The filtering used for decoupling the device supplies must comply with the following best practices rules:
  • The protection/decoupling capacitors must be on the path of the trace connected to that component. No trace exceeding 1 mm from the protection to the trace or to the ground.
  • The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm).
  • The ground of the protection is connected as short as possible to the ground plane under the integrated circuit. General MCXE24x Data Sheet, Rev. 2, 07/2025

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Figure 4. Power diagram

4.5 LVR, LVD and POR operating requirements

Table 6. V DD supply LVR, LVD and POR operating requirements for MCXE24x series1 Table continues on the next page...

  1. In 3.3 V range, the VLVW is always set since supply remains below VLVW range. Hence PMC.LVDSC2[LVWIE] should

remain cleared while device operates in 3.3 V range.

  1. Rising threshold is the sum of falling threshold and hysteresis voltage.

4.6 Power mode transition operating behaviors

Table 7. Clock configuration

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Table 8. Power mode transition operating behaviors across the operating temperature range of the chip. is the recommended operating mode.

4.7 Power consumption

Table 9. Power consumption (Typicals unless stated otherwise) 1 Table continues on the next page...

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Table 9. Power consumption (Typicals unless stated otherwise) 1 (continued)

  1. Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes
  2. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
  3. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.
  4. Values mentioned for MCXE24x devices are measured at RUN@80 MHz with peripherals disabled.
  5. With PMC_REGSC[CLKBIASDIS] set to 1. See Reference Manual for details.
  6. Numbers on limited samples size and data collected with Flash
  7. The MCXE247 data points assume that ENET/QuadSPI/SAI etc. are inactive.

Table 10. VLPS additional use-case power consumption at typical conditions 1, 2, 3

  • Clock source: SIRC
  • Transmiting or receiving continuously using DMA
  • Baudrate: 19.2 kbps 25 230 250 250 μA 85 400 410 490 μA 105 550 600 850 μA 125 1070 1250 1960 μA VLPS and LPUART wake-up
  • Clock source: SIRC
  • Wake-up address feature enabled
  • Baudrate: 19.2 kbps 25 138 146 146 μA 85 240 280 350 μA 105 400 480 600 μA 125 580 1000 1280 μA VLPS and LPI2C master
  • Clock Source: SIRC
  • Transmit/receive using DMA
  • Baudrate: 100 kHz 25 690 820 900 μA 85 960 1220 1370 μA 105 1250 1660 2060 μA 125 1980 2860 3690 μA VLPS and LPI2C slave wake-up
  • Clock source: SIRC
  • Wake-up address feature enabled
  • Baudrate: 100 kHz 25 260 270 280 μA 85 340 410 510 μA 105 430 610 810 μA 125 760 1170 1540 μA VLPS and LPSPI master 4
  • Clock source: SIRC
  • Transmit/receive using DMA
  • Baudrate: 500 kHz 25 3.19 3.75 4.11 mA 85 3.7 4.35 4.93 mA 105 4.2 4.93 5.74 mA 125 4.63 5.97 7.38 mA VLPS and LPIT
  • Clock source: SIRC
  • 1 channel enable
  • Mode: 32-bit periodic counter 25 114 120 130 μA 85 250 260 320 μA 105 410 440 570 μA 125 750 910 1280 μA General MCXE24x Data Sheet, Rev. 2, 07/2025

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  1. All power numbers listed in this table are typical power numbers 2. Current numbers are quoted for a certain application code and may vary on user configuration and silicon process variation. 3. The power numbers are not strictly for the VLPS mode operation alone, but also includes power due to periodic wakeup. The power therefore includes wakeup plus VLPS mode activity. This leads to greater dependence of power numbers on application code. 4. The single LPSPI used is LPSPI1 in MCXE24x devices. General MCXE24x Data Sheet, Rev. 2, 07/2025 NXP Semiconductors 19

mode of operations measure at 3.3 V. Table 11. Power consumption at 3.3 V

  1. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.

4.8 ESD and latch-up protection characteristics

  1. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements."
  2. This parameter is tested in conformity with JEDEC-JS-001.
  3. This parameter is tested in conformity with JEDEC-JS-002
  4. This parameter is tested in conformity with JEDEC-JESD78.

4.9 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

20 NXP Semiconductors

5.1 AC electrical characteristics

Figure 5. Input signal measurement reference

5.2 General AC specifications

Table 12. General switching specifications

  1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
  2. The greater of synchronous and asynchronous timing must be met.
  3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.
  4. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter only if PCR_PTA5[PFE] is at its reset

of PCM_RPC register and/or PORT_DFER register for PTA5. Table 13. DC electrical specifications at 3.3 V Range for MCXE24x series

  1. MCXE247 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged MCXE247 is guaranteed

to operate from 2.97 V. All other MCXE24x family devices operate from 2.7 V in all modes.

  1. For reset pads, same V ih levels are applicable

22 NXP Semiconductors

  1. For reset pads, same V il levels are applicable
  2. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard
  3. For refernce only. Run simulations with the IBIS model and custom board for accurate results.
  4. Typical leakage is given at room temperature. Maximum is given for 125°C. Leakage numbers increase with temperature,
  5. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
  6. When using ENET and SAI on MCXE247, the overall device limits associated with high drive pin configurations must be

respected i.e. On 144-pin LQFP the general purpose pins: PTA10, PTD0, and PTE4 must be set to low drive.

  1. Measured at input V = V SS
  2. Measured at input V = V DD

Table 14. DC electrical specifications at 5.0 V Range for MCXE24x series Table continues on the next page...

Table 14. DC electrical specifications at 5.0 V Range for MCXE24x series (continued)

  1. For reset pads, same V ih levels are applicable
  2. For reset pads, same V il levels are applicable
  3. The strong pad I/O pin is capable of switching a 50 pF load up to 40 MHz.
  4. For refernce only. Run simulations with the IBIS model and custom board for accurate results.
  5. Typical leakage is given at room temperature. Maximum is given for 125°C. Leakage numbers increase with temperature,
  6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
  7. Measured at input V = V SS
  8. Measured at input V = V DD

Table 15. AC electrical specifications at 3.3 V Range for MCXE24x series Table continues on the next page...

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Table 15. AC electrical specifications at 3.3 V Range for MCXE24x series (continued)

  1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
  2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be

different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections.

5.6 AC electrical specifications at 5 V range

Table 16. AC electrical specifications at 5 V Range for MCXE24x series

  1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
  2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be

different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections.

5.7 Standard input pin capacitance

Table 17. Standard input pin capacitance

specifications for EXTAL/XTAL pins.

5.8 Device clock specifications

Table 18. Device clock specifications 1

  1. Refer to the section Feature comparison for the availability of modes and other specifications.
  2. Only available on some devices. See section Feature comparison.
  3. With SPLL as system clock source.
  4. 48 MHz when f SYS is 48 MHz
  5. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

6.1 System modules

There are no electrical specifications necessary for the device's system modules.

6.2.1 External System Oscillator electrical specifications

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Figure 6. Oscillator connections scheme Table 19. External System Oscillator electrical specifications Table continues on the next page...

Table 19. External System Oscillator electrical specifications (continued)

  1. Crystal oscillator circuit provides stable oscillations when g mXOSC > 5 * gm_crit. The gm_crit is defined as:
  • g mXOSC is the transconductance of the internal oscillator circuit ESR is the equivalent series resistance of the external crystal
  • R S is the series resistance connected between XTAL pin and external crystal for current limitation
  • F is the external crystal oscillation frequency
  • C 0 is the shunt capacitance of the external crystal
  • C L is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
  • C s is stray or parasitic capacitance on the pin due to any PCB traces
  • C 1, C2 external load capacitances on EXTAL and XTAL pins See manufacture datasheet for external crystal component values 2. • When low-gain is selected, internal R F will be selected and external RF should not be attached.
  • When high-gain is selected, external R F (1 M Ohm) needs to be connected for proper operation of the crystal. For external resistor, up to 5% tolerance is allowed. RS should be selected carefully to have appropriate oscillation amplitude for both protecting crystal or resonator device and satisfying proper oscillation startup condition. 4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 5. Minimum value is shown as a reference only, however the HW design needs to ensure it reaches the maximum value by following the guidelines given in above notes (notes 1, 2, and 3) and performs the required robustness testing at the application level. During testing, a low capacitance probe (< 5 pF ) must be used to avoid any decrease in the Vpp_EXTAL value.

6.2.2 External System Oscillator frequency specifications

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Table 20. External System Oscillator frequency specifications

40 MHz low-gain mode (HGO=0) — 2 —

40 MHz high-gain mode (HGO=1) — 2 —

  1. For an ideal clock of 40 MHz, if permitted by application requirements, an error of +/- 5% is supported with 50% duty cycle.
  2. Frequencies below 40 MHz can be used for degraded duty cycle upto 40-60%. When using for ADC clock further restrictions apply. At 50 MHz to 45 MHz when

sourcing for ADC clock please use divider ADCn.ADC_CFG1[ADICLK] to ½ or lower for the specific ADC instance. This will help achieve duty cycle requirement. for 45 MHz and 41 MHz 45-55% or higher duty cycle should be maintained.

  1. Proper PC board layout procedures must be followed to achieve specifications.

6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications

Table 21. Fast internal RC Oscillator electrical specifications for MCXE24x series

  1. With FIRC regulator enable
  2. Startup time is defined as the time between clock enablement and clock availability for system use.

6.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications

Table 22. Slow internal RC oscillator (SIRC) electrical specifications for MCXE24x series

  1. Startup time is defined as the time between clock enablement and clock availability for system use.

30 NXP Semiconductors

6.2.4 Low Power Oscillator (LPO) electrical specifications

Table 23. Low Power Oscillator (LPO) electrical specifications

6.2.5 SPLL electrical specifications

Table 24. SPLL electrical specifications

  1. F SPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG

register of Reference Manual.

  1. F SPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input

mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.

  1. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each
  2. The behavior of the accumulated PLL jitter saturates over 1us.
  3. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.

6.3.1 Flash memory module (FTFC/FTFM) electrical specifications

This section describes the electrical characteristics of the flash memory module.

6.3.1.1 Flash timing specifications — commands

Table 25. Flash command timing specifications

2 KB flash — 75 — 75 — 75 µs

4 KB flash — 100 — 100 — 100

64 KB flash 30 550 30 550 — —

512 KB flash 250 4250 250 4250 250 4250

Table continues on the next page...

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Table 25. Flash command timing specifications (continued) Table continues on the next page...

  1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external
  2. Maximum times for erase parameters based on expectations at cycling end-of-life.
  3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may
  4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the
  5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur

set will still be valid and the new records will be discarded.

  1. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
  2. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,

assuming still powered. Or via SETRAM cleanup execution command is requested at a later point. reset to the FTFC/FTFM macro to stop the operation.

6.3.1.2 Reliability specifications

Table 26. NVM reliability specifications Table continues on the next page...

34 NXP Semiconductors

Table 26. NVM reliability specifications (continued)

  • EEPROM backup to FlexRAM ratio = 16 EEPROM backup to FlexRAM ratio = 256 100 K 1.6 M writes writes 1. Data retention period per block begins upon initial user factory programming or after each subsequent erase. 2. Program and Erase for PFlash and DFlash are supported across product temperature specification in Normal mode (not supported in HSRUN mode). 3. Cycling endurance is per DFlash or PFlash Sector. 4. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years. 5. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product temperature specification in Normal Mode (not supported in HSRUN mode). Greater write endurance may be achieved with larger ratios of EEPROM backup to FlexRAM.

6.3.2 QuadSPI AC specifications

The following table describes the QuadSPI electrical characteristics.

  • Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). I/O operating voltage ranges from 2.97 V to 3.6 V
  • While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF.
  • Add 50 ohm series termination on board in QuadSPI SCK for Flash A to avoid loop back reflection when using in Internal DQS (PAD Loopback) mode.
  • QuadSPI trace length should be 3 inches.
  • For non-Quad mode of operation if external device doesn’t have pull-up feature, external pull-up needs to be added at board level for non-used pads.
  • With external pull-up, performance of the interface may degrade based on load associated with external pull-up. Memory and memory interfaces MCXE24x Data Sheet, Rev. 2, 07/2025 NXP Semiconductors 35

Table 27. QuadSPI electrical specifications Table continues on the next page...

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Table 27. QuadSPI electrical specifications (continued)

  1. See Reference Manual for details on mode settings
  2. See Reference Manual for details on mode settings
  3. RWDS(External DQS CLK) frequency
  4. For operating frequency ≤ 64 Mhz,Output invalid time is 5 ns.
  5. Program register value QuadSPI_FLSHCR[TCSS] = 4\`h2
  6. Program register value QuadSPI_FLSHCR[TCSH] = 4\`h1

Figure 7. QuadSPI input timing (SDR mode) diagram Figure 8. QuadSPI output timing (SDR mode) diagram Figure 9. QuadSPI input timing (HyperRAM mode) diagram

38 NXP Semiconductors

Figure 10. QuadSPI output timing (HyperRAM mode) diagram

Table 28. 12-bit ADC operating conditions

0 See Voltage and current

  1. 5 Continuous conversions
  2. Typical values assume V DDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. Typical values are for reference only, and

are not tested in production.

  1. For packages without dedicated V REFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance, reference

supply quality should be better than SAR ADC. See application note AN5032 for details.

  1. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .

40 NXP Semiconductors

  1. ADC conversion will become less reliable above maximum frequency. 5. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS. 6. Numbers based on the minimum sampling time of 275 ns. 7. For guidelines and examples of conversion rate calculation, see the Reference Manual section 'Calibration function' 8. Configuration used during the test to obtain this value is:
  • VDD=VDDA=VREFH=2.5 V, 2.7 V, 3 V ,5.5 V, (externally forced) BUS CLK=48 MHz, ADC CLK=48MHz (FIRC Used), Calibration CLK=24MHz, Sample Time =14 Cyc, Averaging=32
  • Resolution= 12 bit
  • Conversion Mode: Continuous Conversion
  • Channel: ADC0_SE1
  • Temperatures: -40 °C, 25 °C, 125 °C ADC electrical specifications MCXE24x Data Sheet, Rev. 2, 07/2025 NXP Semiconductors 41

Figure 11. ADC input impedance equivalency diagram

  • ADC performance specifications are documented using a single ADC. For parallel/simultaneous operation of both ADCs, either for sampling the same channel by both ADCs or for sampling different channels by each ADC, some amount of decrease in performance can be expected. Care must be taken to stagger the two ADC conversions, in particular the sample phase, to minimize the impact of simultaneous conversions. On reduced pin packages where ADC reference pins are shared with supply pins, ADC analog performance characteristics may be impacted. The amount of variation will be directly impacted by the external PCB layout and hence care must be taken with PCB routing.
  • All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than or equal to half of the maximum specified ADC clock frequency. ADC electrical specifications MCXE24x Data Sheet, Rev. 2, 07/2025

42 NXP Semiconductors

Table 29. 12-bit ADC characteristics (2.7 V to 3 V) (V REFH = VDDA, VREFL = VSS)

  1. Typical values assume V DDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF.
  2. The ADC supply current depends on the ADC conversion rate.
  3. Represents total static error, which includes offset and full scale error.
  4. 1 LSB = (V REFH - VREFL)/2N
  5. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
  6. For ADC signals adjacent to V DD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

  1. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

  1. All the parameters in the table are given assuming system clock as the clocking source for ADC.

Table 30. 12-bit ADC characteristics (3 V to 5.5 V)(V REFH = VDDA, VREFL = VSS)

  1. Typical values assume V DDA = 5.0 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.
  2. The ADC supply current depends on the ADC conversion rate.
  3. Represents total static error, which includes offset and full scale error.
  4. 1 LSB = (V REFH - VREFL)/2N
  5. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
  6. For ADC signals adjacent to V DD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

  1. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

  1. All the parameters in the table are given assuming system clock as the clocking source for ADC.
  • Due to triple bonding in lower pin packages like 48-LQFP, and 64-LQFP degradation might be seen in ADC parameters. When using high speed interfaces such as the QuadSPI, SAI0, SAI1 or ENET there may be some ADC degradation on the adjacent analog input paths. See following table for details. Pin name TGATE purpose PTE8 CMP0_IN3 PTC3 ADC0_SE11/CMP0_IN4 PTC2 ADC0_SE10/CMP0_IN5 PTD7 CMP0_IN6 PTD6 CMP0_IN7 PTD28 ADC1_SE22 PTD27 ADC1_SE21

6.4.2 CMP with 8-bit DAC electrical specifications

Table 32. Comparator with 8-bit DAC electrical specifications for MCXE24x series Table continues on the next page...

44 NXP Semiconductors

  1. Difference at input > 200mV
  2. Applied ± (100 mV + V HYST0/1/2/3+ max. of VAIO) around switch point.
  3. Applied ± (30 mV + 2 × V HYST0/1/2/3+ max. of VAIO) around switch point.
  4. Calculation method used: Linear Regression Least Square Method

Figure 12. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 0)

46 NXP Semiconductors

Figure 15. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1)

6.5.1 LPUART electrical specifications

Refer to General AC specifications for LPUART specifications.

6.5.1.1 Supported baud rate

Baud rate = Baud clock / ((OSR+1) * SBR). For details, see section: 'Baud rate generation' of the Reference Manual.

6.5.2 LPSPI electrical specifications

following tables provide timing characteristics for classic LPSPI timing modes.

  • All timing is shown with respect to 20% VDD and 80% VDD thresholds. All measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew setting (DSE = 1). 6.5 Communication modules MCXE24x Data Sheet, Rev. 2, 07/2025

48 NXP Semiconductors

Table 33. LPSPI electrical specifications1 Table continues on the next page...

Table 33. LPSPI electrical specifications1 (continued) Table continues on the next page...

50 NXP Semiconductors

Table continues on the next page...

  1. Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.
  2. While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz.
  3. f periph = LPSPI peripheral clock
  4. Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.

Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0.

  1. Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.

Clock pad used is PTB2. Applicable only for LPSPI0.

  1. This is the maximum operating frequency (f op) for LPSPI0 with GPIO-HD PAD type only. Otherwise, the maximum operating frequency (fop) is 12 Mhz.
  2. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255.
  3. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255.
  4. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
  5. Maximum operating frequency (f op ) is 12 MHz irrespective of PAD type and LPSPI instance.
  6. Applicable for LPSPI0 only with GPIO-HD PAD type, with maximum operating frequency (f op) as 14 MHz.

52 NXP Semiconductors

1.The bus is driven but may not be equal to the valid serial data being sent. Figure 18. LPSPI slave mode timing (CPHA = 0) Figure 19. LPSPI slave mode timing (CPHA = 1)

6.5.3 LPI2C electrical specifications

See General AC specifications for LPI2C specifications.

54 NXP Semiconductors

6.5.4 FlexCAN electical specifications

For supported baud rate, see section 'Protocol timing' of the Reference Manual.

6.5.5 SAI electrical specifications

The following table describes the SAI electrical characteristics.

  • Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). I/O operating voltage ranges from 2.97 V to 3.6 V
  • While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF.

Table 34. Master mode timing specifications

Figure 20. SAI Timing — Master modes Table 35. Slave mode timing specifications

  1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle

input must be taken care during the board design or by the master timing.

56 NXP Semiconductors

Figure 21. SAI Timing — Slave modes

6.5.6 Ethernet AC specifications

appropriately to arrive at timing specs/constraints for the physical interface. The following table describes the MII electrical characteristics.

  • Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). I/O operating voltage ranges from 2.97 V to 3.6 V
  • While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF.

Table 36. MII signal switching specifications

Figure 22. MII receive diagram Figure 23. MII transmit signal diagram The following table describes the RMII electrical characteristics.

  • Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). I/O operating voltage ranges from 2.97 V to 3.6 V
  • While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF.

Table 37. RMII signal switching specifications Table continues on the next page...

58 NXP Semiconductors

Table 38. MDIO timing specifications (continued) Figure 26. MII/RMII serial management channel timing diagram

6.5.7 Clockout frequency

6.6.1 SWD electrical specofications

60 NXP Semiconductors

Table 39. SWD electrical specifications

Figure 27. Serial wire clock input timing Figure 28. Serial wire data timing

6.6.2 Trace electrical specifications

The following table describes the ETM Trace electrical characteristics.

  • Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. NOTE ETM trace is supported only on MCXE247. Debug modules MCXE24x Data Sheet, Rev. 2, 07/2025

62 NXP Semiconductors

Table 40. ETM Trace specifications Figure 29. TRACE CLKOUT specifications

6.6.3 JTAG electrical specifications

Table continues on the next page...

Figure 30. Test clock input timing

64 NXP Semiconductors

7.1 Description

The tables in the following sections describe the thermal characteristics of the device. NOTE Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting side (board) temperature, ambient temperature, air flow, power dissipation or other components on the board, and board thermal resistance.

7.2 Thermal characteristics

MCXE24x Data Sheet, Rev. 2, 07/2025

66 NXP Semiconductors

Table 41. Thermal characteristics for 48/64/100/144-pin LQFP package

144 NA 51 44

144 NA 44 37

144 NA 42 36

144 NA 37 31

144 NA 36 30

144 NA 30 24

Table continues on the next page...

Table 41. Thermal characteristics for 48/64/100/144-pin LQFP package (continued)

144 NA 12 9

144 NA 2 1

  1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air

flow, power dissipation of other components on the board, and board thermal resistance.

  1. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
  2. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
  3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the
  4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
  5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
  6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek

letters are not available, the thermal characterization parameter is written as Psi-JT.

68 NXP Semiconductors

An estimation of the chip junction temperature, TJ, can be obtained from this equation: where:

  • TA = ambient temperature for the package (°C) RθJA = junction to ambient thermal resistance (°C/W)
  • P D = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: where:
  • RθJA = junction to ambient thermal resistance (°C/W) RθJC = junction to case thermal resistance (°C/W)
  • R θCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. Thermal attributes MCXE24x Data Sheet, Rev. 2, 07/2025 NXP Semiconductors 69

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: where:

  • T T = thermocouple temperature on top of the package (°C)
  • ΨJT = thermal characterization parameter (°C/W)
  • PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. Dimensions 8.1 Obtaining package dimensions Package dimensions are provided in the package drawings. To find a package drawing, go to http://www.nxp.com and perform a keyword search for the drawing’s document number: Package option Document Number Manufacture Code 48-pin LQFP SOT313-3 98ASH00962A 64-pin LQFP SOT1699-1 98ASS23234W 100-pin LQFP SOT407-3 98ASS23208W 144-pin LQFP SOT486-2 98ASS23177W Dimensions MCXE24x Data Sheet, Rev. 2, 07/2025

70 NXP Semiconductors

9.1 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual. The following table provides a revision history for this document. Table 42. Revision History

15 July 2025 Initial release

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