MCXC44XP64M48SF6 NXP | Alldatasheet

Document overview

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Technical content

Features

  • ARM ® Cortex®-M0+ 48MHz with low power
  • Up to 256KB Flash, up to 32KB SRAM, 16KB Boot ROM
  • USB FS 2.0 device without requiring an external crystal
  • Segment LCD supporting up to 24x8 or 28x4 segments
  • Embedded ROM with boot loader for flexible program upgrade
  • FlexIO to support any standard and customized serial peripheral emulation
  • Down to 54uA/MHz in very low power run mode and 1.96uA in deep sleep mode (RAM + RTC retained)
  • - 40 °C to + 125 °C (Tj) temperature range Core Processor
  • ARM ® 32-bit Cortex®-M0+ core up to 48 MHz Memories
  • 128/256 KB program flash memory
  • 16/32 KB SRAM
  • 16 KB ROM with build-in bootloader
  • 32-byte backup register Security
  • 80-bit unique identification number per chip
  • Advanced flash security System and clocks
  • 4-channel asynchronous DMA controller
  • COP Software watchdog
  • SWD debug interface and Micro Trace Buffer
  • Bit manipulation engine
  • Interrupt controller
  • 48 MHz high accuracy internal reference clock
  • 8/2 MHz low-power internal reference clock
  • 32–40 kHz and 3–32 MHz crystal oscillator
  • 1 KHz reference clock active under all low-power modes (except VLLS0) Communication interfaces for connectivity
  • Segment LCD supporting up to 24x8 or 28x4 segments MCXC4x4(R) MCXC4x3(R) MCXC2x4(R) MCXC2x3(R) MCXC1x4(R) MCXC1x3(R)

32 QFN

5x5 mm P 0.5 mm

48 QFN

7x7 mm P 0.5 mm

64 LQFP

10x10 mm P 0.5 mm

64 BGA

5x5 mm P 0.5 mm NXP Semiconductors MCXC44XP64M48SF6 Data Sheet: Technical Data Rev. 2, 07/2024 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

  • USB full-speed 2.0 device controller supporting crystal-less operation
  • One UART module supporting ISO7816, operating up to 1.5 Mbit/s
  • Two low-power UART modules supporting asynchronous operation in low-power modes
  • Two I2C modules and I2C0 supporting up to 1 Mbit/s
  • Two 16-bit SPI modules supporting up to 24 Mbit/s
  • One FlexIO module supporting emulation of additional UART, SPI, I2C, I2S, PWM and other serial modules, and so on
  • One serial audio interface I2S Analog
  • One 16-bit 818 ksps ADC module with high accuracy internal voltage reference (Vref) and up to 18 channels
  • High-speed analog comparator containing a 6-bit DAC for programmable reference input
  • One 12-bit DAC
  • 1.2 V internal voltage reference Timers
  • One 6-channel Timer/PWM module
  • Two 2-channel Timer/PWM modules
  • One low-power timer
  • Periodic interrupt timer
  • Real time clock General-purpose input/outputs
  • Up to 50 general-purpose input/output Power management
  • Down to 54 uA/MHz in very low power run mode
  • Down to 1.96 uA in VLLS3 mode (RAM + RTC retained)
  • Six flexible static modes
  • Low-leakage wakeup unit
  • Voltage range: 1.71 to 3.6 V
  • Flash write voltage range: 1.71 to 3.6 V
  • Temperature range : -40 to 125°C(Tj) Target applications
  • Small to medium appliances
  • Home security and surveillance
  • Smart lighting
  • Smart power socket
  • DC fan

Ordering information

Part number Marking (Line1/ Line2) Core Speed (MHz) Flash (KB) SRAM (KB) GPIOs USB/LCD Package Packing (P)MCXC143VFM(R) (P)MC143M 48 128 16 28 -/- 32QFN Tray and Reel (P)MCXC143VFT (P)MC143T 48 128 16 40 -/- 48QFN Tray (P)MCXC243VFT (P)MC243T 48 128 16 36 USB/- 48QFN Tray Table continues on the next page... 2 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Figure 1. Block diagram

Figure 2. Architecture diagram

8.4 Relationship between ratings and operating

MCX C44X Microcontroller, Rev. 2, 07/2024 5 NXP Semiconductors

1 Ratings

1.1 Thermal handling ratings

Table 1. Thermal handling ratings

  1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
  2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Table 2. Moisture handling ratings

  1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Table 3. ESD handling ratings

  1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
  2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

  1. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Table 4. Voltage and current operating ratings

2 General

2.1 AC electrical characteristics

Figure 3. Input signal measurement reference output pins have the following characteristics.

  • C L=30 pF loads
  • Slew rate disabled
  • Normal drive strength General MCX C44X Microcontroller, Rev. 2, 07/2024 7 NXP Semiconductors

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 5. Voltage and current operating requirements

  • 2.7 V ≤ V DD ≤ 3.6 V
  • 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
  • 2.7 V ≤ V DD ≤ 3.6 V
  • 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
  • V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
  • Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 6. V DD supply LVD and POR operating requirements Table continues on the next page...

Table 6. V DD supply LVD and POR operating requirements (continued)

  • Level 1 falling (LVWV = 00)
  • Level 2 falling (LVWV = 01)
  • Level 3 falling (LVWV = 10)
  • Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
  • Level 1 falling (LVWV = 00)
  • Level 2 falling (LVWV = 01)
  • Level 3 falling (LVWV = 10)
  • Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage

2.2.3 Voltage and current operating behaviors

Table 7. Voltage and current operating behaviors

  • 2.7 V ≤ V DD ≤ 3.6 V, IOH = –5 mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOH = –1.5 mA VDD – 0.5 VDD – 0.5 V V VOH Output high voltage — high drive pad
  • 2.7 V ≤ V DD ≤ 3.6 V, IOH = –18 mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOH = –6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — normal drive pad — 0.5 V 1 Table continues on the next page... General MCX C44X Microcontroller, Rev. 2, 07/2024 9 NXP Semiconductors

Table 7. Voltage and current operating behaviors (continued)

  • 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOL = 1.5 mA — 0.5 V VOL Output low voltage — high drive pad
  • 2.7 V ≤ V DD ≤ 3.6 V, IOL = 18 mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOL = 6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 2 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 2 IIN Input leakage current (total all pins) for full temperature range — 64 μA 2 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 3 1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD = 3.6 V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS

2.2.4 Power mode transition operating behaviors

  • CPU and system clocks = 48 MHz
  • Bus and flash clock = 24 MHz
  • HIRC clock mode

Table 8. Power mode transition operating behaviors

  • VLLS0 → RUN 152 166 μs
  • VLLS1 → RUN 152 166 μs
  • VLLS3 → RUN 104 μs Table continues on the next page... General 10 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 8. Power mode transition operating behaviors (continued)

  • LLS → RUN 7.5 μs
  • VLPS → RUN 7.5 μs
  • STOP → RUN 7.5 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11)

2.2.5 Power consumption operating behaviors

equivalent to the mean plus three times the standard deviation (mean + 3 sigma). The while (1) test is executed with flash cache enabled. Table 9. Power consumption operating behaviors

  • at 25 °C
  • at 105 °C 5.76 6.04 6.40 6.68 mA IDD_RUNCO Running While(1) loop in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 3.21 3.49 3.85 4.13 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 6.45 6.75 7.09 7.39 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V Table continues on the next page... General MCX C44X Microcontroller, Rev. 2, 07/2024 11 NXP Semiconductors

Table 9. Power consumption operating behaviors (continued)

  • at 25 °C
  • at 105 °C 3.95 4.23 4.59 4.87 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 12 MHz core/6 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 2.68 2.96 3.32 3.60 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 8.08 8.39 8.72 9.03 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in flash all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 3.90 4.21 4.54 4.85 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 2.66 2.94 3.30 3.58 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 2.03 2.31 2.67 2.95 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 5.52 5.83 6.16 6.47 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
  • at 25 °C
  • at 105 °C 5.29 5.56 5.93 6.20 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V mA Table continues on the next page... General 12 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors
  • at 25 °C
  • at 105 °C — 6.91 7.19 7.55 7.91 IDD_VLPRC O Very Low Power Run Core Mark in Flash in Compute Operation mode: Core@4MHz, Flash @1MHz, VDD = 3.0 V
  • at 25 °C 826 907 μA IDD_VLPRC O Very-low-power-run While(1) loop in SRAM in compute operation mode— 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V
  • at 25 °C 405 486 μA IDD_VLPRC O Very-low-power run While(1) loop in SRAM in compute operation mode:—2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
  • at 25 °C 154 235 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
  • at 25 °C 108 189 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V
  • at 25 °C 120 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
  • at 25 °C 249 330 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
  • at 25 °C 337 418 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
  • at 25 °C 416 497 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
  • at 25 °C 494 575 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
  • at 25 °C 166 247 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock Table continues on the next page... General MCX C44X Microcontroller, Rev. 2, 07/2024 13 NXP Semiconductors
  • at 25 °C — 50 131 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
  • at 25 °C 208 289 μA IDD_WAIT Wait mode current—core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V 1.81 1.89 mA IDD_WAIT Wait mode current—core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V 1.22 1.39 mA IDD_VLPW Very-low-power wait mode current, core disabled, 4 MHz system/ 1 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 172 182 μA IDD_VLPW Very-low-power wait mode current, core disabled, 2 MHz system/ 0.5 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 69 76 μA IDD_VLPW Very-low-power wait mode current, core disabled, 125 kHz system/ 31.25 kHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 36 40 μA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12 MHz bus and flash, VDD = 3.0 V 1.81 2.06 mA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, flash doze enabled, 12 MHz bus, VDD = 3.0 V 1.00 1.25 mA IDD_STOP Stop mode current at 3.0 V
  • at 25 °C and below
  • at 50 °C
  • at 85 °C
  • at 105 °C 161.93 181.45 236.29 390.33 171.82 191.96 271.17 465.58 μA IDD_VLPS Very-low-power stop mode current at 3.0 V
  • at 25 °C and below
  • at 50 °C
  • at 85 °C
  • at 105 °C 3.31 10.43 34.14 104.38 5.14 17.68 61.06 164.44 μA IDD_VLPS Very-low-power stop mode current at 1.8 V
  • at 25 °C and below 3.21 5.22 Table continues on the next page... General 14 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors
  • at 50 °C
  • at 85 °C
  • at 105 °C 10.26 33.49 102.92 17.62 60.19 162.20 μA IDD_LLS Low-leakage stop mode current, all peripheral disable, at 3.0 V
  • at 25 °C and below
  • at 50 °C
  • at 70 °C
  • at 85 °C
  • at 105 °C 2.06 4.72 8.13 13.34 41.08 3.33 6.85 13.30 24.70 52.43 μA IDD_LLS Low-leakage stop mode current with RTC current, at 3.0 V
  • at 25 °C and below
  • at 50 °C
  • at 70 °C
  • at 85 °C
  • at 105 °C 2.46 5.12 8.53 13.74 41.48 3.73 7.25 11.78 18.91 52.83 μA IDD_LLS Low-leakage stop mode current with RTC current, at 1.8 V
  • at 25 °C and below
  • at 50 °C
  • at 70 °C
  • at 85 °C
  • at 105 °C 2.35 4.91 8.32 13.44 40.47 2.70 6.75 11.78 18.21 51.85 μA IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V
  • at 25 °C and below
  • at 50 °C
  • at 70 °C
  • at 85 °C
  • at 105 °C 1.45 3.37 5.76 9.72 30.41 1.85 4.39 8.48 14.30 37.50 μA IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V
  • at 25 °C and below
  • at 50 °C
  • at 70 °C
  • at 85 °C
  • at 105 °C 2.05 3.97 6.36 10.32 31.01 2.45 4.99 9.08 14.73 38.10 μA Table continues on the next page... General MCX C44X Microcontroller, Rev. 2, 07/2024 15 NXP Semiconductors
  • at 25 °C and below
  • at 50 °C
  • at 70 °C
  • at 85 °C
  • at 105 °C 1.96 3.86 6.23 10.21 30.25 2.36 5.67 8.53 13.37 37.02 μA IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V
  • at 25 °C and below
  • at 50°C
  • at 70°C
  • at 85°C
  • at 105 °C 0.66 1.78 2.55 4.83 16.42 0.80 3.87 4.26 6.64 20.49 μA IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V
  • at 25 °C and below
  • at 50°C
  • at 70°C
  • at 85°C
  • at 105 °C 1.26 2.38 3.15 5.43 17.02 1.40 4.47 4.86 7.24 21.09 μA IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V
  • at 25 °C and below
  • at 50°C
  • at 70°C
  • at 85°C
  • at 105 °C 1.16 1.96 2.78 4.85 15.78 1.30 2.28 3.37 6.88 18.81 μA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V
  • at 25 °C and below
  • at 50 °C
  • at 70 °C
  • at 85 °C
  • at 105 °C 0.35 1.25 2.53 4.40 16.09 0.47 1.44 3.24 5.24 19.29 μA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 1) at 3 V General 16 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors
  • at 25 °C and below
  • at 50 °C
  • at 70 °C
  • at 85 °C
  • at 105 °C 0.18 1.09 2.25 4.25 15.95 0.28 1.31 2.94 5.10 19.10 μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR with optimization level high, optimized for balanced. 3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.

Table 10. Low power mode peripheral adders — typical value IEREFSTEN4MHz External 4 MHz crystal clock adder. mode with the crystal enabled. all modes with the crystal enabled.

  • VLLS1
  • VLLS3
  • LLS
  • VLPS
  • STOP 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 nA ILPTMR LPTMR peripheral adder measured by placing the device in VLLS1 mode with LPTMR enabled using LPO. 100 200 Table continues on the next page... General MCX C44X Microcontroller, Rev. 2, 07/2024 17 NXP Semiconductors

Table 10. Low power mode peripheral adders — typical value (continued) single external input for compare. Includes 6-bit DAC power consumption.

  • IRC8M (8 MHz internal reference clock)
  • IRC2M (2 MHz internal reference clock) 114 114 114 114 114 114 µA ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents.
  • IRC8M (8 MHz internal reference clock)
  • IRC2M (2 MHz internal reference clock) 147 147 147 147 147 147 µA IBG Bandgap adder when BGEN bit is set and device is placed in VLPx or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 330 330 330 330 330 330 µA ILCD LCD peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the OSC0_CR[EREFSTEN, EREFSTEN] bits. VIREG disabled, resistor bias network enabled, 1/8 duty cycle, 8 x 36 configuration for driving 288 Segments, 32 Hz frame rate, no LCD glass connected. Includes ERCLK32K (32 kHz external crystal) power consumption. General 18 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

  • MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
  • USB regulator disabled
  • No GPIOs toggled
  • Code execution from flash
  • For the ALLOFF curve, all peripheral clocks are disabled except FTFA

Figure 4. Run mode supply current vs. core frequency

20 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Figure 5. VLPR mode current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP package

  1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,

whole number, from among the measured orientations in each frequency range.

  1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

2.2.7 Designing with radiated emissions in mind

  1. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 12. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 13. Device clock specifications Table continues on the next page...

Table 13. Device clock specifications (continued)

  1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher

than the specified maximum frequency when IRC 48MHz is used as the clock source.

  1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
  2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

2.3.2 General switching specifications

Table 14. General switching specifications

  1. The synchronous and asynchronous timing must be met.
  2. This is the shortest pulse that is guaranteed to be recognized.

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 15. Thermal operating requirements

  1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

determine TJ is: TJ = TA + RθJA × chip power dissipation.

  1. The device operating specification is not guaranteed beyond 125 °C TJ.

2.4.2 Thermal attributes

Table 16. Thermal attributes

  1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Environmental Conditions—Forced Convection (Moving Air).

  1. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

  1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

the top of the package and the cold plate.

  1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

  1. Thermal characterization parameter indicating the temperature difference between package bottom center and the

parameter is written as Psi-JB.

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 SWD electricals

Table 17. SWD full voltage range electricals

  • Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
  • Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)

Figure 6. Serial wire clock input timing

Figure 7. Serial wire data timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG-Lite specifications

Table 18. IRC48M specification Table continues on the next page...

Table 18. IRC48M specification (continued)

  1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard

Table 19. IRC8M/2M specification

Figure 8. IRC8M Frequency Drift vs Temperature curve

3.3.2 Oscillator electrical specifications

3.3.2.1 Oscillator DC electrical specifications

Table 20. Oscillator DC electrical specifications

  • 32 kHz
  • 4 MHz
  • 8 MHz (RANGE=01)
  • 16 MHz 500 200 300 950 1.2 nA μA μA μA mA Table continues on the next page... Peripheral operating requirements and behaviors 28 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 20. Oscillator DC electrical specifications (continued)

  • 24 MHz
  • 32 MHz — 1.5 — mA IDDOSC Supply current — high gain mode (HGO=1)
  • 32 kHz
  • 4 MHz
  • 8 MHz (RANGE=01)
  • 16 MHz
  • 24 MHz
  • 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation Peripheral operating requirements and behaviors MCX C44X Microcontroller, Rev. 2, 07/2024 29 NXP Semiconductors
  1. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For

all other cases external capacitors must be used.

  1. When low power mode is selected, RF is integrated and must not be attached externally.
  2. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

3.3.2.2 Oscillator frequency specifications

Table 21. Oscillator frequency specifications

  1. Other frequency limits may apply when external clock is being used as a reference for the FLL
  2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

  1. Proper PC board layout procedures must be followed to achieve specifications.
  2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.4.1.1 Flash timing specifications — program and erase

are active and do not include command overhead. Table 22. NVM program/erase timing specifications

  1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 23. Flash command timing specifications

  • 128 KB program flash 1.7 ms trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersblk128k Erase Flash Block execution time
  • 128 KB program flash 600 ms tersscr Erase Flash Sector execution time — 14 114 ms 2 trd1all Read 1s All Blocks execution time — — 1.8 ms 1 trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 175 1300 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 175 1300 ms 2 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. Peripheral operating requirements and behaviors MCX C44X Microcontroller, Rev. 2, 07/2024 31 NXP Semiconductors

3.4.1.3 Flash high voltage current behaviors

Table 24. Flash high voltage current behaviors

3.4.1.4 Reliability specifications

Table 25. NVM reliability specifications

  1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
  2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

Table 26. 16-bit ADC operating conditions

1.13 VDDA VDDA V 3

  • All other modes VREFL VREFL 31/32 × VREFH VREFH V — CADIN Input capacitance
  • 16-bit mode
  • 8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 24 MHz 5 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 5 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 1200 ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. VREFH can act as VREF_OUT when VREFV1 module is enabled. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Peripheral operating requirements and behaviors MCX C44X Microcontroller, Rev. 2, 07/2024 33 NXP Semiconductors

Figure 9. ADC input impedance equivalency diagram Table 27. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

  • ADLPC = 1, ADHSC = 0
  • ADLPC = 1, ADHSC = 1
  • ADLPC = 0, ADHSC = 0
  • ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
  • 12-bit modes
  • <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
  • 12-bit modes
  • <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non- linearity
  • 12-bit modes
  • <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors 34 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 27. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

  • <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
  • 16-bit modes
  • ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
  • Avg = 32
  • Avg = 4 16-bit single-ended mode
  • Avg = 32
  • Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
  • Avg = 32 16-bit single-ended mode
  • Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
  • Avg = 32 16-bit single-ended mode
  • Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA Peripheral operating requirements and behaviors MCX C44X Microcontroller, Rev. 2, 07/2024 35 NXP Semiconductors

3.6.2 Voltage reference electrical specifications

Table 28. VREF full-range operating requirements

  1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
  2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature

VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1. Table 29. VREF full-range operating behaviors

  • current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs — Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms — Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Peripheral operating requirements and behaviors MCX C44X Microcontroller, Rev. 2, 07/2024 37 NXP Semiconductors

Table 30. VREF limited-range operating requirements Table 31. VREF limited-range operating behaviors

3.6.3 CMP and 6-bit DAC electrical specifications

Table 32. Comparator and 6-bit DAC electrical specifications

  • CR0[HYSTCTR] = 00
  • CR0[HYSTCTR] = 01
  • CR0[HYSTCTR] = 10
  • CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors 38 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 33. 12-bit DAC operating requirements

  1. The DAC reference can be selected to be VDDA or VREFH.
  2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Table 34. 12-bit DAC operating behaviors

  • High power (SP HP)
  • Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
  • High power (SP HP)
  • Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors MCX C44X Microcontroller, Rev. 2, 07/2024 41 NXP Semiconductors

Figure 14. Typical INL error vs. digital code

Figure 15. Offset at half scale vs. temperature

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

3.8.1 USB electrical specifications

date standards, visit usb.org .

certification for Host mode operation. This device cannot support Host mode operation.

3.8.2 USB VREG electrical specifications

Table 35. USB VREG electrical specifications

  • VREGIN = 5.0 V and temperature=25 °C
  • Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
  • Run mode
  • Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. Peripheral operating requirements and behaviors 44 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

3.8.3 SPI switching specifications

used for communicating with slower peripheral devices. as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 36. SPI master mode timing on slew rate disabled pads

  1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).

Table 37. SPI master mode timing on slew rate enabled pads Table continues on the next page...

Table 37. SPI master mode timing on slew rate enabled pads (continued)

  1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
  2. If configured as an output.

Figure 16. SPI master mode timing (CPHA = 0)

Figure 17. SPI master mode timing (CPHA = 1) Table 38. SPI slave mode timing on slew rate disabled pads

  1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
  2. Time to data active from high-impedance state
  3. Hold time to high-impedance state

Table 39. SPI slave mode timing on slew rate enabled pads

  1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
  2. Time to data active from high-impedance state
  3. Hold time to high-impedance state

Figure 18. SPI slave mode timing (CPHA = 0)

Figure 19. SPI slave mode timing (CPHA = 1)

3.8.4 I2C

3.8.4.1 Inter-Integrated Circuit Interface (I2C) timing

Table 40. I2C timing Hold time (repeated) START condition.

  1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high

drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.

  1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
  2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
  3. Input signal Slew = 10 ns and Output Load = 50 pF
  4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
  5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

  1. Cb = total capacitance of the one bus line in pF.
  • To counter the effects of clock stretching, the I2C baud Rate select bits can be configured for faster than desired baud rate.
  • Use high drive pad and DSE bit should be set in PORTx_PCRn register.
  • Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the SCL line to avoid clock stretching.
  • Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.

Table 41. I 2C 1Mbit/s timing period, the first clock pulse is generated.

  1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins across
  2. Cb = total capacitance of the one bus line in pF.

Figure 20. Timing definition for devices on the I2C bus

3.8.5 UART

See General switching specifications.

3.8.6 I2S/SAI switching specifications

(BCLK) and/or the frame sync (FS) signal shown in the following figures.

3.8.6.1 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 42. I2S/SAI master mode timing Table continues on the next page...

Table 42. I2S/SAI master mode timing (continued) Figure 21. I2S/SAI timing — master modes Table 43. I2S/SAI slave mode timing Table continues on the next page...

Table 43. I2S/SAI slave mode timing (continued)

  1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 22. I2S/SAI timing — slave modes

3.8.6.2 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 44. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Table continues on the next page...

Figure 23. I2S/SAI timing — master modes Table 45. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

  1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 24. I2S/SAI timing — slave modes

3.9 Human-machine interfaces (HMI)

3.9.1 LCD electrical characteristics

Table 46. LCD electricals

  • GCR[FFR]=0
  • GCR[FFR]=1 23.3 46.6 73.1 146.2 Hz Hz CLCD LCD charge pump capacitance — nominal value — 100 — nF CBYLCD LCD bypass capacitance — nominal value — 100 — nF 1 CGlass LCD glass capacitance — 2000 8000 pF 2 VIREG VIREG
  • RVTRIM=0000
  • RVTRIM=1000
  • RVTRIM=0100
  • RVTRIM=1100
  • RVTRIM=0010
  • RVTRIM=1010
  • RVTRIM=0110
  • RVTRIM=1110
  • RVTRIM=0001 0.91 0.92 0.93 0.94 0.96 0.97 0.98 0.99 1.01 V 3 Table continues on the next page... Peripheral operating requirements and behaviors MCX C44X Microcontroller, Rev. 2, 07/2024 55 NXP Semiconductors

Table 46. LCD electricals (continued)

  • RVTRIM=1001
  • RVTRIM=0101
  • RVTRIM=1101
  • RVTRIM=0011
  • RVTRIM=1011
  • RVTRIM=0111
  • RVTRIM=1111 1.02 1.03 1.05 1.06 1.07 1.08 1.09 ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG IVIREG VIREG current adder — RVEN = 1 — 1 — µA IRBIAS RBIAS current adder
  • LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF)
  • LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) µA µA RRBIAS RBIAS resistor values
  • LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF)
  • LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) 0.28 2.98 MΩ MΩ VLL1 VLL1 voltage — — VIREG V 4 VLL2 VLL2 voltage — — 2 x VIREG V 4 VLL3 VLL3 voltage — — 3 x VIREG V 4 VLL1 VLL1 voltage — — VDDA / 3 V 5 VLL2 VLL2 voltage — — VDDA / 1.5 V 5 VLL3 VLL3 voltage — — VDDA V 5 1. The actual value used could vary with tolerance. 2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter within the device's reference manual. 3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V 4. VLL1, VLL2 and VLL3 are a function of VIREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump is enabled (GCR[CPSEL]=1). 5. VLL1, VLL2 and VLL3 are a function of VDDA only under either of the following conditions:
  • The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = V DDA through the internal power switch (GCR[VSUPPLY]=0).
  • The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is connected to VDDA externally (GCR[VSUPPLY]=1).

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00615D 48-pin QFN 98ASA00616D 64-pin LQFP 98ASS23234W 64-pin MAPBGA 98ASA00420D Pinouts and Packaging

5.1 Signal Multiplexing and Pin Assignments

5.1.1 MCX C44x Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE VREFH can act as VREF_OUT when VREFV1 module is enabled. MAP BGA LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 A1 1 PTE0 DISABLED LCD_P48 PTE0/ CLKOUT32K SPI1_MISO LPUART1_TX RTC_CLKOUT CMP0_OUT I2C1_SDA LCD_P48 B1 2 PTE1 DISABLED LCD_P49 PTE1 SPI1_MOSI LPUART1_RX SPI1_MISO I2C1_SCL LCD_P49 — 3 VDD VDD VDD C4 4 VSS VSS VSS Pinouts and Packaging MCX C44X Microcontroller, Rev. 2, 07/2024 57 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E1 5 USB0_DP USB0_DP USB0_DP D1 6 USB0_DM USB0_DM USB0_DM E2 7 VOUT33 VOUT33 VOUT33 D2 8 VREGIN VREGIN VREGIN G1 9 PTE20 ADC0_DP0/ ADC0_SE0 LCD_P59/ ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0LPUART0_TX FXI00_D4 LCD_P59 F1 10 PTE21 ADC0_DM0/ ADC0_SE4a LCD_P60/ ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1LPUART0_RX FXIO0_D5 LCD_P60 G2 11 PTE22 ADC0_DP3/ ADC0_SE3 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0UART2_TX FXIO0_D6 F2 12 PTE23 ADC0_DM3/ ADC0_SE7a ADC0_DM3/ ADC0_SE7a PTE23 TPM2_CH1UART2_RX FXIO0_D7 F4 13 VDDA VDDA VDDA G4 14 VREFH VREFH VREFH G3 15 VREFL VREFL VREFL F3 16 VSSA VSSA VSSA H1 17 PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_CLKIN0 H2 18 PTE30 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_CLKIN1LPUART1_TXLPTMR0_ ALT1 H3 19 PTE31 DISABLED PTE31 TPM0_CH4 H4 20 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL H5 21 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA D3 22 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK D4 23 PTA1 DISABLED PTA1 LPUART0_RXTPM2_CH0 E5 24 PTA2 DISABLED PTA2 LPUART0_TXTPM2_CH1 D5 25 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO G5 26 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b F5 27 PTA5 DISABLED PTA5 USB_CLKINTPM0_CH2 I2S0_TX_ BCLK H6 28 PTA12 DISABLED PTA12 TPM1_CH0 I2S0_TXD0 G6 29 PTA13 DISABLED PTA13 TPM1_CH1 I2S0_TX_FS G7 30 VDD VDD VDD H7 31 VSS VSS VSS H8 32 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RXTPM_CLKIN0 G8 33 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TXTPM_CLKIN1 LPTMR0_ ALT1 F8 34 PTA20 RESET_b PTA20 RESET_b Pinouts and Packaging 58 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 F7 35 PTB0/ LLWU_P5 LCD_P0/ ADC0_SE8 LCD_P0/ ADC0_SE8 PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 LCD_P0 F6 36 PTB1 LCD_P1/ ADC0_SE9 LCD_P1/ ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1 LCD_P1 E7 37 PTB2 LCD_P2/ ADC0_SE12 LCD_P2/ ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0 LCD_P2 E8 38 PTB3 LCD_P3/ ADC0_SE13 LCD_P3/ ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1 LCD_P3 E6 39 PTB16 LCD_P12 LCD_P12 PTB16 SPI1_MOSILPUART0_RXTPM_CLKIN0SPI1_MISO LCD_P12 D7 40 PTB17 LCD_P13 LCD_P13 PTB17 SPI1_MISOLPUART0_TXTPM_CLKIN1SPI1_MOSI LCD_P13 D6 41 PTB18 LCD_P14 LCD_P14 PTB18 TPM2_CH0I2S0_TX_ BCLK LCD_P14 C7 42 PTB19 LCD_P15 LCD_P15 PTB19 TPM2_CH1I2S0_TX_FS LCD_P15 D8 43 PTC0 LCD_P20/ ADC0_SE14 LCD_P20/ ADC0_SE14 PTC0 EXTRG_INaudioUSB_ SOF_OUT CMP0_OUTI2S0_TXD0LCD_P20 C6 44 PTC1/ LLWU_P6/ RTC_CLKIN LCD_P21/ ADC0_SE15 LCD_P21/ ADC0_SE15 PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 I2S0_TXD0LCD_P21 B7 45 PTC2 LCD_P22/ ADC0_SE11 LCD_P22/ ADC0_SE11 PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FSLCD_P22 C8 46 PTC3/ LLWU_P7 LCD_P23 LCD_P23 PTC3/ LLWU_P7 SPI1_SCK LPUART1_RXTPM0_CH2CLKOUT I2S0_TX_ BCLK LCD_P23 E3 47 VSS VSS VSS E4 — VDD VDD VDD C5 48 VLL3 VLL3 VLL3 A6 49 VLL2 VLL2 VLL2/ LCD_P4 PTC20 LCD_P4 B5 50 VLL1 VLL1 VLL1/ LCD_P5 PTC21 LCD_P5 B4 51 VCAP2 VCAP2 VCAP2/ LCD_P6 PTC22 LCD_P6 A5 52 VCAP1 VCAP1 VCAP1/ LCD_P39 PTC23 LCD_P39 B8 53 PTC4/ LLWU_P8 LCD_P24 LCD_P24 PTC4/ LLWU_P8 SPI0_SS LPUART1_TXTPM0_CH3I2S0_MCLK LCD_P24 A8 54 PTC5/ LLWU_P9 LCD_P25 LCD_P25 PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 CMP0_OUTLCD_P25 A7 55 PTC6/ LLWU_P10 LCD_P26/ CMP0_IN0 LCD_P26/ CMP0_IN0 PTC6/ LLWU_P10 SPI0_MOSIEXTRG_INI2S0_RX_ BCLK SPI0_MISOI2S0_MCLKLCD_P26 B6 56 PTC7 LCD_P27/ CMP0_IN1 LCD_P27/ CMP0_IN1 PTC7 SPI0_MISOaudioUSB_ SOF_OUT I2S0_RX_FSSPI0_MOSI LCD_P27 C3 57 PTD0 LCD_P40 LCD_P40 PTD0 SPI0_SS TPM0_CH0 FXI00_D0 LCD_P40 A4 58 PTD1 LCD_P41/ ADC0_SE5b LCD_P41/ ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 LCD_P41 Pinouts and Packaging MCX C44X Microcontroller, Rev. 2, 07/2024 59 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 C2 59 PTD2 LCD_P42 LCD_P42 PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISOFXIO0_D2 LCD_P42 B3 60 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSIFXIO0_D3 LCD_P43 A3 61 PTD4/ LLWU_P14 LCD_P44 LCD_P44 PTD4/ LLWU_P14 SPI1_SS UART2_RXTPM0_CH4 FXI00_D4 LCD_P44 C1 62 PTD5 LCD_P45/ ADC0_SE6b LCD_P45/ ADC0_SE6b PTD5 SPI1_SCK UART2_TXTPM0_CH5 FXIO0_D5 LCD_P45 B2 63 PTD6/ LLWU_P15 LCD_P46/ ADC0_SE7b LCD_P46/ ADC0_SE7b PTD6/ LLWU_P15 SPI1_MOSILPUART0_RX SPI1_MISOFXIO0_D6 LCD_P46 A2 64 PTD7 LCD_P47 LCD_P47 PTD7 SPI1_MISOLPUART0_TX SPI1_MOSIFXIO0_D7 LCD_P47

5.1.2 MCX C24x Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE VREFH can act as VREF_OUT when VREFV1 module is enabled. NOTE It is prohibited to set VREFEN in 32 QFN pin package as 1.2 V on-chip voltage is not available in this package. QFN QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 1 VDD VDD VDD — 7 PTE20 ADC0_DP0/ ADC0_SE0 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0LPUART0_TX FXI00_D4 — 8 PTE21 ADC0_DM0/ ADC0_SE4a ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1LPUART0_RX FXIO0_D5 — 10 VREFH VREFH VREFH — 11 VREFL VREFL VREFL — 13 PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_CLKIN0 — 15 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL — 16 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA — 29 PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL TPM2_CH0 — 30 PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDA TPM2_CH1 — 31 PTB16 Disabled PTB16 SPI1_MOSILPUART0_RXTPM_CLKIN0SPI1_MISO — 32 PTB17 Disabled PTB17 SPI1_MISOLPUART0_TXTPM_CLKIN1SPI1_MOSI Pinouts and Packaging 60 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 33 PTC0 ADC0_SE14ADC0_SE14PTC0 EXTRG_INaudioUSB_ SOF_OUT CMP0_OUTI2S0_TXD0 — 41 PTD0 DISABLED PTD0 SPI0_SS TPM0_CH0 FXI00_D0 — 42 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 — 43 PTD2 DISABLED PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISOFXIO0_D2 — 44 PTD3 DISABLED PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSIFXIO0_D3 1 — PTE0 DISABLED PTE0/ CLKOUT32K SPI1_MISOLPUART1_TXRTC_CLKOUTCMP0_OUTI2C1_SDA 2 2 VSS VSS VSS 3 3 USB0_DP USB0_DP USB0_DP 4 4 USB0_DM USB0_DM USB0_DM 5 5 VOUT33 VOUT33 VOUT33 6 6 VREGIN VREGIN VREGIN 7 9 VDDA VDDA VDDA 8 12 VSSA VSSA VSSA 9 14 PTE30 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_CLKIN1LPUART1_TXLPTMR0_ ALT1 10 17 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK 11 18 PTA1 DISABLED PTA1 LPUART0_RXTPM2_CH0 12 19 PTA2 DISABLED PTA2 LPUART0_TXTPM2_CH1 13 20 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 14 21 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b 15 22 VDD VDD VDD 16 23 VSS VSS VSS 17 24 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RXTPM_CLKIN0 18 25 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TXTPM_CLKIN1 LPTMR0_ ALT1 19 26 PTA20 RESET_b PTA20 RESET_b 20 27 PTB0/ LLWU_P5 ADC0_SE8ADC0_SE8PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 21 28 PTB1 ADC0_SE9ADC0_SE9PTB1 I2C0_SDA TPM1_CH1 22 34 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_SE15ADC0_SE15PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 I2S0_TXD0 23 35 PTC2 ADC0_SE11ADC0_SE11PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS 24 36 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 SPI1_SCK LPUART1_RXTPM0_CH2CLKOUT I2S0_TX_ BCLK 25 37 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_SS LPUART1_TXTPM0_CH3I2S0_MCLK 26 38 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 CMP0_OUT Pinouts and Packaging MCX C44X Microcontroller, Rev. 2, 07/2024 61 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 27 39 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_MOSIEXTRG_INI2S0_RX_ BCLK SPI0_MISOI2S0_MCLK 28 40 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_MISOaudioUSB_ SOF_OUT I2S0_RX_FSSPI0_MOSI 29 45 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_SS UART2_RXTPM0_CH4 FXI00_D4 30 46 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI1_SCK UART2_TXTPM0_CH5 FXIO0_D5 31 47 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI1_MOSILPUART0_RX SPI1_MISOFXIO0_D6 32 48 PTD7 DISABLED PTD7 SPI1_MISOLPUART0_TX SPI1_MOSIFXIO0_D7

5.1.3 MCX C14x Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE VREFH can act as VREF_OUT when VREFV1 module is enabled. QFN QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 1 VDD VDD VDD — 2 VSS VSS VSS — 7 PTE20 ADC0_DP0/ ADC0_SE0 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0LPUART0_TX FXI00_D4 — 8 PTE21 ADC0_DM0/ ADC0_SE4a ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1LPUART0_RX FXIO0_D5 — 10 VREFH VREFH VREFH — 11 VREFL VREFL VREFL — 13 PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_CLKIN0 — 15 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL — 16 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA — 29 PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL TPM2_CH0 — 30 PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDA TPM2_CH1 — 31 PTB16 DISABLED PTB16 SPI1_MOSILPUART0_RXTPM_CLKIN0SPI1_MISO — 32 PTB17 DISABLED PTB17 SPI1_MISOLPUART0_TXTPM_CLKIN1SPI1_MOSI — 33 PTC0 ADC0_SE14ADC0_SE14PTC0 EXTRG_INaudioUSB_ SOF_OUT CMP0_OUTI2S0_TXD0 — 41 PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 FXI00_D0 — 42 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 Pinouts and Packaging 62 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 43 PTD2 DISABLED PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISOFXIO0_D2 — 44 PTD3 DISABLED PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSIFXIO0_D3 — — Reserved Reserved Reserved — — Reserved Reserved Reserved — — Reserved Reserved Reserved — — Reserved Reserved Reserved 1 — PTE0 DISABLED PTE0/ CLKOUT32K SPI1_MISOLPUART1_TXRTC_CLKOUTCMP0_OUTI2C1_SDA 2 — PTE1 DISABLED PTE1 SPI1_MOSILPUART1_RX SPI1_MISOI2C1_SCL 3 3 PTE16 ADC0_DP1/ ADC0_SE1 ADC0_DP1/ ADC0_SE1 PTE16 SPI0_PCS0UART2_TXTPM_CLKIN0 FXI00_D0 4 4 PTE17 ADC0_DM1/ ADC0_SE5a ADC0_DM1/ ADC0_SE5a PTE17 SPI0_SCK UART2_RXTPM_CLKIN1LPTMR0_ ALT3 FXI00_D1 5 5 PTE18 ADC0_DP2/ ADC0_SE2 ADC0_DP2/ ADC0_SE2 PTE18 SPI0_MOSI I2C0_SDA SPI0_MISOFXI00_D2 6 6 PTE19 ADC0_DM2/ ADC0_SE6a ADC0_DM2/ ADC0_SE6a PTE19 SPI0_MISO I2C0_SCL SPI0_MOSIFXI00_D3 7 9 VDDA VDDA VDDA 8 12 VSSA VSSA VSSA 9 14 PTE30 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_CLKIN1LPUART1_TXLPTMR0_ ALT1 10 17 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK 11 18 PTA1 DISABLED PTA1 LPUART0_RXTPM2_CH0 12 19 PTA2 DISABLED PTA2 LPUART0_TXTPM2_CH1 13 20 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 14 21 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b 15 22 VDD VDD VDD 16 23 VSS VSS VSS 17 24 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RXTPM_CLKIN0 18 25 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TXTPM_CLKIN1 LPTMR0_ ALT1 19 26 PTA20 RESET_b PTA20 RESET_b 20 27 PTB0/ LLWU_P5 ADC0_SE8ADC0_SE8PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 21 28 PTB1 ADC0_SE9ADC0_SE9PTB1 I2C0_SDA TPM1_CH1 22 34 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_SE15ADC0_SE15PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 I2S0_TXD0 23 35 PTC2 ADC0_SE11ADC0_SE11PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS 24 36 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 SPI1_SCK LPUART1_RXTPM0_CH2CLKOUT I2S0_TX_ BCLK Pinouts and Packaging MCX C44X Microcontroller, Rev. 2, 07/2024 63 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 25 37 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0LPUART1_TXTPM0_CH3I2S0_MCLK 26 38 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 CMP0_OUT 27 39 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_MOSIEXTRG_INI2S0_RX_ BCLK SPI0_MISOI2S0_MCLK 28 40 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_MISOaudioUSB_ SOF_OUT I2S0_RX_FSSPI0_MOSI 29 45 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_PCS0UART2_RXTPM0_CH4 FXI00_D4 30 46 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI1_SCK UART2_TXTPM0_CH5 FXIO0_D5 31 47 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI1_MOSILPUART0_RX SPI1_MISOFXIO0_D6 32 48 PTD7 DISABLED PTD7 SPI1_MISOLPUART0_TX SPI1_MOSIFXIO0_D7

5.2 MCX C44X Family Pinouts

5.2.1 MCX C44x Pinouts

Figure below shows the 64 LQFP pinouts Pinouts and Packaging 64 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Figure 25. 64 LQFP Pinout diagram

Figure 26. 64 MAPBGA Pinout diagram

5.2.2 MCX C24x Pinouts

Figure 27. 32 QFN Pinout diagram

Figure 28. 48 QFN Pinout diagram

5.2.3 MCX C14x Pinouts

Figure 29. 32 QFN Pinout diagram

Figure 30. 48 QFN Pinout diagram

6 Ordering parts

6.1 Determining valid orderable parts

7 Part identification

7.1 Description

values of these fields to determine the specific part you have received.

7.2 Format

7.3 Fields

Table 47. Part number fields descriptions

  • 1 = Baseline
  • 2 = Baseline Enhance
  • 3 = Reserved
  • 4 = HMI C Core feature • 4 = 48MHz FS Flash size • 1 = 32 KB
  • 2 = 64 KB
  • 3 = 128 KB
  • 4 = 256 KB T Temperature range (°C) • V = –40 to 125
  • FK = 24QFN: 4x4x0.65 mm
  • FM = 32QFN: 5x5x0.9 mm
  • FT = 48QFN: 7x7x0.9 mm
  • LH = 64LQFP: 10x10x1.6mm
  • MP = 64MAPBGA: 5x5x1.23mm SR Silicon revision • A = Initial Mask set
  • B = 1st Major spin PT Packaging type • R = Tape and reel
  • T = Tray Part identification MCX C44X Microcontroller, Rev. 2, 07/2024 71 NXP Semiconductors

7.4 Example

This is an example part number: MCXC444VLH

8 Terminology and guidelines

8.1 Definitions

Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

  • Operating ratings apply during operation of the chip.
  • Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
  • Lies within the range of values specified by the operating behavior
  • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines 72 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

8.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE

8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines MCX C44X Microcontroller, Rev. 2, 07/2024 73 NXP Semiconductors

8.4 Relationship between ratings and operating requirements

  • No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

  • Never exceed any of the chip’s ratings.
  • During normal operation, don’t exceed any of the chip’s operating requirements.
  • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

9 Revision History

The following table provides a revision history for this document. Table 48. Revision History

Revision History

74 MCX C44X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. NXP Semiconductors Legal information NXP Semiconductors MCX C44X Microcontroller, Rev. 2, 07/2024

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. ESD protection devices — These products are only intended for protection against ElectroStatic Discharge (ESD) pulses and are not intended for any other usage including, without limitation, voltage regulation applications. NXP Semiconductors accepts no liability for use in such applications and therefore such use is at the customer’s own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. NXP Semiconductors Legal information NXP Semiconductors MCX C44X Microcontroller, Rev. 2, 07/2024

Suitability for use in non-automotive qualified products — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. I2C-bus — logo is a trademark of NXP B.V. MCX — is a trademark of NXP B.V. NXP Semiconductors Legal information NXP Semiconductors MCX C44X Microcontroller, Rev. 2, 07/2024

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2024. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 07/2024 Document identifier:MCXC44XP64M48SF6