MCXC141VFM

MCXC24XP64M48SF2 NXP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 100

Technical content

Features

ARM® Cortex®-M0+ 48MHz with low power

• Up to 64KB Flash, up to 16KB SRAM, 16KB Boot ROM
• USB FS 2.0 device without requiring an external crystal
• Embedded ROM with boot loader for flexible program upgrade
• FlexIO to support any standard and customized serial peripheral emulation
• Down to 46 µA/MHz in very low power run mode and 1.68 µA in stop mode (RAM + RTC retained)
• - 40 °C to + 125 °C (Tj) temperature range Cores ARM® Cortex®-M0+ core up to 48 MHz Memories
• 32/64 KB program flash memory
• 8/16 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register Security
• 80-bit unique identification number per chip
• Advanced flash security
• Hardware CRC module System and clocks
• COP Software watchdog
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
• 48 MHz high accuracy internal reference clock
• 8/2 MHz low power internal reference clock
• 32–40 kHz and 3–32 MHz crystal oscillator
• 1 kHz reference clock active under all low power modes (except VLLS0) Communication Interfaces for Connectivity
• USB full-speed 2.0 device controller supporting crystal-less operation and keeping connections alive under ultra- low power
• One UART module supporting ISO7816, operating up to 1.5 Mbit/s
• Two low-power UART modules supporting asynchronous operation in low-power modes
• Two I2C modules supporting up to 1 Mbit/s MCXC141VFM(R) MCXC141VLH(R) MCXC142VFM(R) MCXC242VFM(R) MCXC242VLH(R)

64 LQFP (LH)

10x10x1.6 mm P .5

32 QFN(FT&FM)

5x5x.64 mm P .5 NXP Semiconductors MCXC24XP64M48SF2 Data Sheet: Technical Data Rev. 2, 07/2024 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Two 16-bit SPI modules supporting up to 24 Mbit/s for SPI1 and 12 Mbit/s for SPI0
• One FlexIO module supporting emulation of additional UART, SPI, I2C, I2S, PWM and other serial modules, and so on Analog
• One 16-bit ADC module with high accurate internal voltage reference, up to 20 channels and up to 818 ksps at equal to or less than 13-bit mode
• High-speed analog comparator containing a 6-bit DAC for programmable reference input
• 1.2 V voltage reference (Vref) Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock General-purpose input/outputs
• Up to 54 general-purpose input/output pins Power Management
• Down to 46 μA/MHz in very low power run mode
• Down to 1.68μA in stop mode (RAM + RTC retained)
• Six flexible static modes
• Low-leakage wakeup unit
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range : -40 to 125°C(Tj) Target Applications
• Small to medium appliances
• Home security and surveillance
• Smart lighting
• Smart power socket
• DC fan

Ordering information

Part number Marking (Line1/ Line2) Core Speed (MHz) Flash (KB) SRAM (KB) GPIOs USB Package Packing (P)MCXC141VFM(R) (P)MC141M 48 32 8 28 - 32QFN Tray and Reel (P)MCXC141VLH (P)MCXC141/VLH 48 32 8 54 - 64LQFP Tray (P)MCXC242VLH (P)MCXC242/VLH 48 64 16 51 Yes 64LQFP Tray (P)MCXC142VFM(R) (P)MC142M 48 64 16 28 - 32QFN Tray and Reel (P)MCXC242VFM(R) (P)MC242M 48 64 16 24 Yes 32QFN Tray and Reel The following figure shows the block diagram of this device 2 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Figure 1. MCX C14x/24x/44x Block Diagram

48 MHz

16 KByte

64 KByte

32 Bytes

Figure 2. Architecture diagram

4.1.1 MCX C24X Signal Multiplexing and Pin

4.1.2 MCX C14X Signal Multiplexing and Pin

5.1.4 Voltage and current absolute operating ratings.. 49 MCX C24X Microcontroller, Rev. 2, 07/2024 5 NXP Semiconductors

1 System features

The following sections describe the high-level system features.

1.1 ARM Cortex-M0+ core

The enhanced ARM Cortex M0+ is the member of the Cortex-M series of processors targeting microcontroller cores focused on very cost sensitive, low power applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality including support for simple program trace capability. The processor supports the ARMv6-M instruction set (Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It is upward compatible with other Cortex-M profile processors.

1.2 NVIC

The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It also differs in number of interrupt sources and supports 32 interrupt vectors. The Cortex-M family uses a number of methods to improve interrupt latency to up to 15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and VLPW modes.

1.3 AWIC

The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous wake-up events in Stop mode and signal to clock control logic to resume system clocking. After clock restarts, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. The AWIC can be used to wake MCU core from Stop and VLPS modes. Wake-up sources are listed as below: System features 6 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 1. AWIC stop wake-up sources

1.4 Memory

• 8/16 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states.
• The non-volatile memory is divided into two arrays
• 32/64 KB of embedded program memory
• 16 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI interfaces) The program flash memory contains a 16-byte flash configuration field that stores default protection settings and security information. The page size of program flash is 1 KB. The protection setting can protect 32 regions of the program flash memory from unintended erase or program operations. System features MCX C24X Microcontroller, Rev. 2, 07/2024 7 NXP Semiconductors

• System register file This device contains a 32-byte register file that is powered in all power modes. Also, it retains contents during low power modes and is reset only during a power- on reset.

1.5 Reset and boot

The following table lists all the reset sources supported by this device. Table 2. Reset source

1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]

1. Only if RESET is used to wake from VLLS mode.
2. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT
3. Except RCM_RPFC, RCM_RPFW, RCM_FM

• internal flash
• boot ROM The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows the user to customize the operation of the MCU at boot time. The register contains read-only bits that are loaded from the NVM's option byte in the flash configuration field. Below is boot flow chart for this device. Boot from FlashBoot from ROM POR or Reset RCM[FORCEROM] =00 FOPT[BOOTPIN_OPT]=0 BOOTCFG0 pin=0 FOPT[BOOTSRC _SEL]=10/11 N N N Y N Y Y Y

Figure 3. Boot flow chart address, otherwise, it remaps to flash address.

1.6 Clock options

provide the required performance and optimize the power consumption.

full speed mode to achieve the required accuracy. clock on reset. The LIRC oscillator cannot be used in any VLLS modes. The LPO generates a 1 kHz clock and cannot be used in VLLS0 mode. kHz) on the RTC_CLKIN pin for use with the RTC. For more details on the clock operations and configurations, see Reference Manual. The following figure is a high level block diagram of the clock generation. Figure 4. Clock block diagram

available during operation in various operational modes. The following table summarizes the clocks associated with each module. Table 3. Module clocks Table continues on the next page...

Table 3. Module clocks (continued)

1.7 Security

flash information via ROM boot loader commands. factory and loaded to SIM register after power-on reset.

1.8 Power management

The Power Management Controller (PMC) expands upon ARM’s operational modes of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can be used to optimize current consumption for a wide range of applications. The WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current configuration. For more information on ARM’s operational modes, See the ARM® Cortex User Guide. The PMC provides Run (Run), and Very Low Power Run (VLPR) configurations in ARM’s Run operation mode. In these modes, the MCU core is active and can access all peripherals. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The configuration that matches the power versus performance requirements of the application can be selected. The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive, all of the peripherals can be enabled and operate as programmed. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop (LLS), and Very Low Leakage Stop (VLLS) configurations in ARM’s Deep Sleep operational mode. In these modes, the MCU core and most of the peripherals are disabled. Depending on the requirements of the application, different portions of the analog, logic, and memory can be retained or disabled to conserve power. The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are used to wake up the MCU from low power states. The NVIC is used to wake up the MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU core from STOP and VLPS modes. The LLWU is used to wake up the MCU core from LLS and VLLSx modes. For additional information regarding operational modes, power management, the NVIC, AWIC, or the LLWU, please refer to the Reference Manual. The following table provides information about the state of the peripherals in the various operational modes and the modules that can wake MCU from low power modes. System features MCX C24X Microcontroller, Rev. 2, 07/2024 13 NXP Semiconductors

Table 5. Peripherals states in different operational modes Run mode Run In Run mode, all device modules are operational. except the Low Voltage Detect (LVD) monitor, which is disabled. core is placed into Sleep mode. Deep sleep Stop In Stop mode, most peripheral clocks are disabled and placed in a static state. are retained. The CMP (low speed), LLWU, LPTMR, and RTC are operational. RTC are operational in all VLLS modes. VREF are not operational but continue driving. operational but continue driving. POR detection circuit can be enabled or disabled.

1.9 LLWU

continues to detect wake-up events until the user has acknowledged the wake-up event.

Table 6. Wakeup source

1.10 Debug controller

2 breakpoints and 2 watchpoints. simple execution trace capability for the Cortex-M0+ processor.

1.11 COP

can run from bus clock, LPO, 8/2 MHz internal oscillator or external crystal oscillator. Optional window mode can detect deviations in program flow or system frequency.

The COP has the following features:

• Support multiple clock input, 1 kHz clock(LPO), bus clock, 8/2 MHz internal reference clock, external crystal oscillator
• Can work in Stop/VLPS and Debug mode
• Configurable for short and long timeout values, the longest timeout is up to 262 seconds
• Support window mode

2 Peripheral features

The following sections describe the features of each peripherals of the chip.

2.1 BME

The Bit Manipulation Engine (BME) provides hardware support for atomic read- modify-write memory operations to the peripheral address space in Cortex-M0+ based microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for bit-oriented operations to peripheral registers. The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit, bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized data type.

2.2 DMA and DMAMUX

The DMA controller module enables fast transfers of data, which provides an efficient way to move blocks of data with minimal processor interaction. The DMA controller in this device implements four channels which can be routed from up to 63 DMA request sources through DMA MUX module. Some of the peripheral request sources have asynchronous DMA capability which can be used to wake MCU from Stop mode. The peripherals which have such capability include LPUART0, LPUART1, FlexIO, TPM0- TPM2, ADC0, CMP0, PORTA-PORTE. The DMA channel 0 and 1 can be periodically triggered by PIT via DMA MUX. Main features are listed below:

• Dual-address transfers via 32-bit master connection to the system bus and data transfers in 8-, 16-, or 32-bit blocks Peripheral features 16 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

• Supports programmable source and destination address and transfer size, optional modulo addressing from 16 bytes to 256 KB
• Automatic updates of source and destination addresses
• Auto-alignment feature for source or destination accesses allows block transfers to occur at the optimal size based on the address, byte count,and programmed size, which significantly improves the speed of block transfer
• Automatic single or double channel linking allows the current DMA channel to automatically trigger a DMA request to the linked channels without CPU intervention

2.3 TPM

This device contains three low power TPM modules (TPM). All TPM modules are functional in Stop/VLPS mode if the clock source is enabled. The TPM features include:

• TPM clock mode is selectable from external clock input or internal clock source, HIRC48M clock, external crystal input clock or LIRC2M/8M clock.
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare, edge-aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter overflow
• Support selectable trigger input to optionally reset or cause the counter to start or stop incrementing
• Support the generation of hardware triggers when the counter overflows and per channel

2.4 ADC

this device contains one ADC module. This ADC module supports hardware triggers from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features:

• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs Peripheral features MCX C24X Microcontroller, Rev. 2, 07/2024 17 NXP Semiconductors

• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16- bit, 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to four
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32x
• Selectable voltage reference: external or alternate
• Self-Calibration mode

2.4.1 Temperature sensor

This device contains one temperature sensor internally connected to the input channel of AD26, see Table 55 for details of the linearity factor. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031. We recommend to use internal reference voltage as ADC reference with long sample time.

2.5 VREF

The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically) trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC or CMP. The VREF supports the following programmable buffer modes:

• Bandgap on only, used for stabilization and startup
• High power buffer mode
• Low-power buffer mode
• Buffer disabled Peripheral features 18 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

The VREF voltage output signal, bonded on VREFH for 64 LQFP packages and on PTE30 for 32 QFN, can be used by both internal and external peripherals in low and high power buffer mode. A 100 nF capacitor must always be connected between this pin and VSSA if the VREF is used. This capacitor must be as close to the VREFO pin as possible.

2.6 CMP

The device contains one high-speed comparator and two 8-input multiplexers for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. The CMP includes one 6-bit DAC, which provides a selectable voltage reference for various user application cases. Besides, the CMP also has several module-to-module interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces. The CMP has the following features:

• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for internal functions
• Two software selectable performance levels: shorter propagation delay at the expense of higher power and Low power with longer propagation delay
• DMA transfer support
• Functional in all modes of operation except in VLLS0 mode
• The filter functions are not available in Stop, VLPS, LLS, or VLLSx modes
• Integrated 6-bit DAC with selectable supply reference source and can be power down to conserve power
• Two 8-to-1 channel mux

2.7 RTC

The RTC is an always powered-on block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator or clock directly from RTC_CLKIN pin. Peripheral features MCX C24X Microcontroller, Rev. 2, 07/2024 19 NXP Semiconductors

RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers. The RTC module has the following features

• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt

2.8 PIT

The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It has two independent channels and each channel has a 32-bit counter. Both channels can be chained together to form a 64-bit counter. Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be used to periodically trigger DMA channel 1. Either channel can be programmed as an ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger DAC. The PIT module has the following features:

• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
• Timer 0 is able to trigger DAC

2.9 LPTMR

The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features:

• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power mode Peripheral features 20 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter

2.10 CRC

This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The CRC module has the following features:

• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface

2.11 UART

This device contains a basic universal asynchronous receiver/transmitter (UART) module with DMA function supported. Generally, this module is used in RS-232, RS-485, and other communications and supports LIN slave operation and ISO7816. The UART module has the following features:

• Full-duplex operation
• 13-bit baud rate selection with /32 fractional divide, based on the module clock frequency
• Programmable 8-bit or 9-bit data format
• Programmable transmitter output polarity
• Programmable receive input polarity
• Up to 14-bit break character transmission.
• 11-bit break character detection option
• Two receiver wakeup methods with idle line or address mark wakeup
• Address match feature in the receiver to reduce address mark wakeup ISR overhead Peripheral features MCX C24X Microcontroller, Rev. 2, 07/2024 21 NXP Semiconductors

• Ability to select MSB or LSB to be first bit on wire
• Support for ISO 7816 protocol to interface with SIM cards and smart cards
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
• DMA interface

2.12 LPUART

This product contains two Low-Power UART modules, both of their clock sources are selectable from IRC48M, IRC8M/2M or external crystal clock, and can work in Stop and VLPS modes. They also support 4× to 32× data oversampling rate to meet different applications. The LPUART module has the following features:

• Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4× to 32×
• Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters
• Selectable transmitter output and receiver input polarity Peripheral features 22 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

2.13 SPI

This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes. FIFO function is available only on SPI1 module. The SPI modules have the following features:

• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support DMA

2.14 I2C

This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer features, and address match to wake MCU from the low power mode. I2C modules support DMA transfer, and the interrupt condition can trigger DMA request when DMA function is enabled. The I2C modules have the following features:

• Support for system management bus (SMBus) Specification, version 2
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Programmable input glitch filter
• Low power mode wakeup on slave address match Peripheral features MCX C24X Microcontroller, Rev. 2, 07/2024 23 NXP Semiconductors

• Range slave address support
• DMA support
• Double buffering support to achieve higher baud rate

2.15 USB

This device contains one USB module which implements a USB2.0 full-speed compliant peripheral and interfaces to the on-chip USBFS transceiver. It implements keep-alive feature to avoid re-enumerating when exiting from low power modes and enables HIRC48M to allow crystal-less USB operation. The USBFS has the following features:

• USB 1.1 and 2.0 compliant full-speed device controller
• 16 bidirectional end points
• DMA or FIFO data stream interfaces
• Low-power consumption
• HIRC48 with clock-recovery is supported to eliminate the 48 MHz crystal. It is used for USB device-only implementation.
• USB keeps alive in low power mode down to VLPS and is able to wake MCU from low power mode

2.16 FlexIO

The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to UART, I2C, SPI, I2S, Camera IF, LCD RGB, PWM/ Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. The FlexIO module has the following features:

• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using remains enabled
• Four 32-bit double buffered shift registers with transmit, receive, and data match modes, and continuous data transfer
• The timing of the shifter’ shift, load and store events are controlled by the highly flexible 16-bit timer assigned to the shifter
• Two or more shifter can be concatenated to support large data transfer sizes
• Each 16-bit timers operates independently, supports for reset, enable and disable on a variety of internal or external trigger conditions with programmable trigger polarity Peripheral features 24 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

• Flexible pin configuration supporting output disabled, open drain, bidirectional output data and output mode
• Supports interrupt, DMA or polled transmit/receive operation

2.17 Port control and GPIO

The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. The following figure shows the basic I/O pad structure. This diagram applies to all I/O pins except PTA20/RESET_b and those configured as pseudo open-drain outputs. PTA20/RESET_b is a true open-drain pin without p-channel output driver or diode to the ESD bus. Pseudo open-drain pins have the p-channel output driver disabled when configured for open-drain operation. None of the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above VDD. Peripheral features MCX C24X Microcontroller, Rev. 2, 07/2024 25 NXP Semiconductors

Figure 5. I/O simplified block diagram

• all PIN support interrupt enable .
• Configurable edge(rising,falling,both) or level sensitive interrupt type
• Support DMA request
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable fast and slow slew rates on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers Peripheral features 26 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

• Port Data Direction register
• GPIO support single-cycle access via fast GPIO.

3 Memory map

Figure 6. Memory map

4 Pinouts

4.1 Signal Multiplexing and Pin Assignments

4.1.1 MCX C24X Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. LQFP QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 9 VREF0 VREF0_B VREF0_B 1 1 PTE0 DISABLED PTE0/ CLKOUT32K SPI1_MISO LPUART1_TX RTC_CLKOUT CMP0_OUT I2C1_SDA 2 — PTE1 DISABLED PTE1 SPI1_MOSI LPUART1_RX SPI1_MISO I2C1_SCL 3 — VDD VDD VDD 4 2 VSS VSS VSS 5 3 USB0_DP USB0_DP USB0_DP 6 4 USB0_DM USB0_DM USB0_DM 7 5 USB_VDD USB_VDD USB_VDD 8 6 PTE16 ADC0_DP1/ ADC0_SE1 ADC0_DP1/ ADC0_SE1 PTE16 SPI0_PCS0 UART2_TX TPM_CLKIN0 FXIO0_D0 — PTE20 ADC0_DP0/ ADC0_SE0 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0 LPUART0_TX FXIO0_D4 — PTE21 ADC0_DM0/ ADC0_SE4a ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1 LPUART0_RX FXIO0_D5 — PTE22 ADC0_DP3/ ADC0_SE3 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0 UART2_TX FXIO0_D6 — PTE23 ADC0_DM3/ ADC0_SE7a ADC0_DM3/ ADC0_SE7a PTE23 TPM2_CH1 UART2_RX FXIO0_D7 13 7 VDDA VDDA VDDA 14 7 VREFH VREFH VREFH — VREFO VREFO_A VREFO_A 15 8 VREFL VREFL VREFL 16 8 VSSA VSSA VSSA Pinouts 28 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 17 — PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_CLKIN0 18 9 PTE30 ADC0_SE23/ CMP0_IN4 ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_CLKIN1LPUART1_TXLPTMR0_ ALT1 19 — PTE31 DISABLED PTE31 TPM0_CH4 20 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 21 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 22 10 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK 23 11 PTA1 DISABLED PTA1 LPUART0_RXTPM2_CH0 24 12 PTA2 DISABLED PTA2 LPUART0_TXTPM2_CH1 25 13 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 26 14 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b 27 — PTA5 DISABLED PTA5 USB_CLKINTPM0_CH2 28 — PTA12 DISABLED PTA12 TPM1_CH0 29 — PTA13 DISABLED PTA13 TPM1_CH1 30 15 VDD VDD VDD 31 16 VSS VSS VSS 32 17 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RXTPM_CLKIN0 33 18 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TXTPM_CLKIN1 LPTMR0_ ALT1 34 19 PTA20 RESET_b PTA20 RESET_b 35 20 PTB0/ LLWU_P5 ADC0_SE8ADC0_SE8PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0SPI1_MOSISPI1_MISO 36 21 PTB1 ADC0_SE9ADC0_SE9PTB1 I2C0_SDA TPM1_CH1SPI1_MISOSPI1_MOSI 37 — PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL TPM2_CH0 38 — PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDA TPM2_CH1 39 — PTB16 DISABLED PTB16 SPI1_MOSILPUART0_RXTPM_CLKIN0SPI1_MISO 40 — PTB17 DISABLED PTB17 SPI1_MISOLPUART0_TXTPM_CLKIN1SPI1_MOSI 41 — PTB18 DISABLED PTB18 TPM2_CH0 42 — PTB19 DISABLED PTB19 TPM2_CH1 43 — PTC0 ADC0_SE14ADC0_SE14PTC0 EXTRG_INaudioUSB_ SOF_OUT CMP0_OUT 44 22 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_SE15ADC0_SE15PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 45 23 PTC2 ADC0_SE11ADC0_SE11PTC2 I2C1_SDA TPM0_CH1 46 24 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 SPI1_SCK LPUART1_RXTPM0_CH2CLKOUT 47 — VSS VSS VSS 48 — VDD VDD VDD 49 25 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0LPUART1_TXTPM0_CH3SPI1_PCS0 Pinouts MCX C24X Microcontroller, Rev. 2, 07/2024 29 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 50 26 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 CMP0_OUT 51 27 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_MOSIEXTRG_IN SPI0_MISO 52 28 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_MISOaudioUSB_ SOF_OUT SPI0_MOSI 53 — PTC8 CMP0_IN2CMP0_IN2PTC8 I2C0_SCL TPM0_CH4 54 — PTC9 CMP0_IN3CMP0_IN3PTC9 I2C0_SDA TPM0_CH5 55 — PTC10 DISABLED PTC10 I2C1_SCL 56 — PTC11 DISABLED PTC11 I2C1_SDA 57 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 FXIO0_D0 58 — PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 59 — PTD2 DISABLED PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISOFXIO0_D2 60 — PTD3 DISABLED PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSIFXIO0_D3 61 29 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_PCS0UART2_RXTPM0_CH4 FXIO0_D4 62 30 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI1_SCK UART2_TXTPM0_CH5 FXIO0_D5 63 31 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI1_MOSILPUART0_RXI2C1_SDA SPI1_MISOFXIO0_D6 64 32 PTD7 DISABLED PTD7 SPI1_MISOLPUART0_TXI2C1_SCL SPI1_MOSIFXIO0_D7

4.1.2 MCX C14X Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. LQFP QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 9 VREF0 VREF0_B VREF0_B 1 1 PTE0 DISABLED PTE0/ CLKOUT32K SPI1_MISOLPUART1_TXRTC_CLKOUTCMP0_OUTI2C1_SDA 2 2 PTE1 DISABLED PTE1 SPI1_MOSILPUART1_RX SPI1_MISOI2C1_SCL 3 — VDD VDD VDD 4 — VSS VSS VSS 5 3 PTE16 ADC0_DP1/ ADC0_SE1 ADC0_DP1/ ADC0_SE1 PTE16 SPI0_PCS0UART2_TXTPM_CLKIN0 FXIO0_D0 6 4 PTE17 ADC0_DM1/ ADC0_SE5a ADC0_DM1/ ADC0_SE5a PTE17 SPI0_SCK UART2_RXTPM_CLKIN1LPTMR0_ ALT3 FXIO0_D1 7 5 PTE18 ADC0_DP2/ ADC0_SE2 ADC0_DP2/ ADC0_SE2 PTE18 SPI0_MOSI I2C0_SDA SPI0_MISOFXIO0_D2 8 6 PTE19 ADC0_DM2/ ADC0_SE6a ADC0_DM2/ ADC0_SE6a PTE19 SPI0_MISO I2C0_SCL SPI0_MOSIFXIO0_D3 Pinouts 30 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 9 — PTE20 ADC0_DP0/ ADC0_SE0 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0LPUART0_TX FXIO0_D4 10 — PTE21 ADC0_DM0/ ADC0_SE4a ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1LPUART0_RX FXIO0_D5 11 — PTE22 ADC0_DP3/ ADC0_SE3 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0UART2_TX FXIO0_D6 12 — PTE23 ADC0_DM3/ ADC0_SE7a ADC0_DM3/ ADC0_SE7a PTE23 TPM2_CH1UART2_RX FXIO0_D7 13 7 VDDA VDDA VDDA 14 7 VREFH VREFH VREFH 14 — VREFO VREFO_A VREFO_A 15 8 VREFL VREFL VREFL 16 8 VSSA VSSA VSSA 17 — PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_CLKIN0 18 9 PTE30 ADC0_SE23/ CMP0_IN4 ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_CLKIN1LPUART1_TXLPTMR0_ ALT1 19 — PTE31 DISABLED PTE31 TPM0_CH4 20 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 21 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 22 10 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK 23 11 PTA1 DISABLED PTA1 LPUART0_RXTPM2_CH0 24 12 PTA2 DISABLED PTA2 LPUART0_TXTPM2_CH1 25 13 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 26 14 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b 27 — PTA5 DISABLED PTA5 USB_CLKINTPM0_CH2 28 — PTA12 DISABLED PTA12 TPM1_CH0 29 — PTA13 DISABLED PTA13 TPM1_CH1 30 15 VDD VDD VDD 31 16 VSS VSS VSS 32 17 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RXTPM_CLKIN0 33 18 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TXTPM_CLKIN1 LPTMR0_ ALT1 34 19 PTA20 RESET_b PTA20 RESET_b 35 20 PTB0/ LLWU_P5 ADC0_SE8ADC0_SE8PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0SPI1_MOSISPI1_MISO 36 21 PTB1 ADC0_SE9ADC0_SE9PTB1 I2C0_SDA TPM1_CH1SPI1_MISOSPI1_MOSI 37 — PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL TPM2_CH0 38 — PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDA TPM2_CH1 39 — PTB16 DISABLED PTB16 SPI1_MOSILPUART0_RXTPM_CLKIN0SPI1_MISO 40 — PTB17 DISABLED PTB17 SPI1_MISOLPUART0_TXTPM_CLKIN1SPI1_MOSI 41 — PTB18 DISABLED PTB18 TPM2_CH0 Pinouts MCX C24X Microcontroller, Rev. 2, 07/2024 31 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 42 — PTB19 DISABLED PTB19 TPM2_CH1 43 — PTC0 ADC0_SE14ADC0_SE14PTC0 EXTRG_IN CMP0_OUT 44 22 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_SE15ADC0_SE15PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 45 23 PTC2 ADC0_SE11ADC0_SE11PTC2 I2C1_SDA TPM0_CH1 46 24 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 SPI1_SCK LPUART1_RXTPM0_CH2CLKOUT 47 — VSS VSS VSS 48 — VDD VDD VDD 49 25 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0LPUART1_TXTPM0_CH3SPI1_PCS0 50 26 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 CMP0_OUT 51 27 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_MOSIEXTRG_IN SPI0_MISO 52 28 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_MISO SPI0_MOSI 53 — PTC8 CMP0_IN2CMP0_IN2PTC8 I2C0_SCL TPM0_CH4 54 — PTC9 CMP0_IN3CMP0_IN3PTC9 I2C0_SDA TPM0_CH5 55 — PTC10 DISABLED PTC10 I2C1_SCL 56 — PTC11 DISABLED PTC11 I2C1_SDA 57 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 FXIO0_D0 58 — PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 59 — PTD2 DISABLED PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISOFXIO0_D2 60 — PTD3 DISABLED PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSIFXIO0_D3 61 29 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_PCS0UART2_RXTPM0_CH4 FXIO0_D4 62 30 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI1_SCK UART2_TXTPM0_CH5 FXIO0_D5 63 31 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI1_MOSILPUART0_RXI2C1_SDA SPI1_MISOFXIO0_D6 64 32 PTD7 DISABLED PTD7 SPI1_MISOLPUART0_TXI2C1_SCL SPI1_MOSIFXIO0_D7

4.2 Pin properties

The following table lists the pin properties. Pinouts 32 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

64 LQFP

32 QFN

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt — — PTE17 ND HI-Z — FS N N Y — — PTE18 ND Hi-Z — FS N N Y 1 1 PTE0 ND Hi-Z — FS N N Y 2 — PTE1 ND Hi-Z — FS N N Y 8 6 PTE16 ND Hi-Z — FS N N Y 9 — PTE20 ND Hi-Z — SS N N Y 10 — PTE21 ND Hi-Z — SS N N Y 11 — PTE22 ND Hi-Z — SS N N Y 12 — PTE23 ND Hi-Z — SS N N Y 17 — PTE29 ND Hi-Z — SS N N Y 18 9 PTE30 ND Hi-Z — SS N N Y 19 — PTE31 ND Hi-Z — SS N N Y 20 — PTE24 ND Hi-Z — SS N N Y 21 — PTE25 ND Hi-Z — SS N N Y 22 10 PTA0 ND L PD SS N N Y 23 11 PTA1 ND Hi-Z — SS N N Y 24 12 PTA2 ND Hi-Z — SS N N Y Table continues on the next page... Pinouts MCX C24X Microcontroller, Rev. 2, 07/2024 33 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt 25 13 PTA3 ND H PU FS N N Y 26 14 PTA4 ND H PU SS Y N Y 27 — PTA5 ND Hi-Z — SS N N Y 28 — PTA12 ND Hi-Z — SS N N Y 29 — PTA13 ND Hi-Z — SS N N Y 32 17 PTA18 ND Hi-Z — SS N N Y 33 18 PTA19 ND Hi-Z — SS N N Y 34 19 PTA20 ND H PU SS N Y Y 35 20 PTB0/LLWU_P5 HD Hi-Z — FS N N Y 36 21 PTB1 HD Hi-Z — FS N N Y 37 — PTB2 ND Hi-Z — SS N N Y 38 — PTB3 ND Hi-Z — SS N N Y 39 — PTB16 ND Hi-Z — FS N N Y 40 — PTB17 ND Hi-Z — FS N N Y 41 — PTB18 ND Hi-Z — SS N N Y 42 — PTB19 ND Hi-Z — SS N N Y 43 — PTC0 ND Hi-Z — SS N N Y 44 22 PTC1/LLWU_P6/ RTC_CLKIN ND Hi-Z — SS N N Y 45 23 PTC2 ND Hi-Z — SS N N Y 46 24 PTC3/LLWU_P7 HD Hi-Z — FS N N Y 49 25 PTC4/LLWU_P8 HD Hi-Z — FS N N Y 50 26 PTC5/LLWU_P9 ND Hi-Z — FS N N Y 51 27 PTC6/LLWU_P10 ND Hi-Z — FS N N Y 52 28 PTC7 ND Hi-Z — FS N N Y 53 — PTC8 ND Hi-Z — SS N N Y Table continues on the next page... Pinouts 34 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt 54 — PTC9 ND Hi-Z — SS N N Y 55 — PTC10 ND Hi-Z — SS N N Y 56 — PTC11 ND Hi-Z — SS N N Y 57 — PTD0 ND Hi-Z — FS N N Y 58 — PTD1 ND Hi-Z — FS N N Y 59 — PTD2 ND Hi-Z — FS N N Y 60 — PTD3 ND Hi-Z — FS N N Y 61 29 PTD4/LLWU_P14 ND Hi-Z — FS N N Y 62 30 PTD5 ND Hi-Z — FS N N Y 63 31 PTD6/LLWU_P15 HD Hi-Z — FS N N Y 64 32 PTD7 HD Hi-Z — FS N N Y Properties Abbreviation Descriptions Driver strength ND Normal drive HD High drive Default status after POR Hi-Z High impendence H High level L Low level Pullup/ pulldown setting after POR PD Pullup PU Pulldown Slew rate after POR FS Fast slew rate SS Slow slew rate Passive Pin Filter after POR N Disabled Y Enabled Open drain N Disabled1 Y Enabled2 Pin interrupt Y Yes Pinouts MCX C24X Microcontroller, Rev. 2, 07/2024 35 NXP Semiconductors

1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or

LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain configurable.

1. PTA20 is a true open drain pin that must never be pulled above VDD.

4.3 Module Signal Description Tables

the module's chapter. They also briefly describe the signal function and direction.

4.3.1 Core modules

Table 8. SWD signal descriptions communication and device control. This pin is pulled up internally. mode. This pin is pulled down internally.

4.3.2 System modules

Table 9. System signal descriptions Table 10. LLWU signal descriptions

4.3.3 Clock modules

Table 11. OSC signal descriptions

4.3.4 Analog

This table presents the signal descriptions of the ADC0 module. Table 12. ADC0 signal descriptions This table presents the signal descriptions of the CMP0 module. Table 13. CMP0 signal descriptions Table 14. VREF signal descriptions

4.3.5 Timer Modules

Table 15. TPM0 signal descriptions Table 16. TPM1 signal descriptions Table 17. TPM2 signal descriptions Table 18. LPTMR0 signal descriptions

Table 19. RTC signal descriptions

1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL]

4.3.6 Communication interfaces

Table 20. USB FS OTG Signal Descriptions Table 21. SPI0 signal descriptions Table 22. SPI1 signal descriptions Table 23. I 2C0 signal descriptions

Table 24. I 2C1 signal descriptions Table 25. LPUART0 signal descriptions Table 26. LPUART1 signal descriptions Table 27. UART2 signal descriptions Table 28. FlexIO signal descriptions

4.3.7 Human-machine interfaces (HMI)

Table 29. GPIO Signal Descriptions Table continues on the next page...

Table 29. GPIO Signal Descriptions (continued)

4.4 MCX C24X Family Pinouts

4.4.1 MCX C24x Pinouts

The figure below shows the 32 QFN pinouts. Figure 7. 32 QFN Pinout diagram (transparent top view)

Figure 8. 64 LQFP Pinout diagram (top view)

4.4.2 MCX C14x Pinouts

The figure below shows the 32 QFN pinouts.

Figure 9. 32 QFN Pinout diagram

Figure 10. 64 LQFP Pinout diagram

4.5 Package dimensions

Figure 11. 64-pin LQFP package dimensions 1

1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. DATUMS A, B AND D TO BE DETERMINDE AT DATUM PLANE H.
4. DIMENSIONS TO BE DETERMINED AT SEATING PLANE C.
5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM.

1. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION

DIMENSION INCLUDING MOLD MISMATCH.

1. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
2. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.1 MM AND 0.25 MM FROM THE LEAD TIP. Figure 12. 64-pin LQFP package dimensions 2

Figure 13. 32-pin QFN package dimension 1

0.65 0.50 0.05 0.00 (0.2) (0.5) // 0.1 C 32X 0.08 C C SEATING PLANE DETAIL G VIEW ROTATED 90℃W NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 3. THIS IS A NON-JEDEC REGISTERED PACKAGE. 4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG. 5. MIN. METAL GAP SHOULD BE 0.2 MM. Figure 14. 32-pin QFN package dimension 2

5 Electrical characteristics

5.1 Ratings

Electrical characteristics

48 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

5.1.1 Thermal handling ratings

Table 30. Thermal handling ratings

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

5.1.2 Moisture handling ratings

Table 31. Moisture handling ratings

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

5.1.3 ESD handling ratings

Table 32. ESD handling ratings

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

1. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

5.1.4 Voltage and current absolute operating ratings

Table 33. Voltage and current absolute operating ratings Table continues on the next page... MCX C24X Microcontroller, Rev. 2, 07/2024 49 NXP Semiconductors

Table 33. Voltage and current absolute operating ratings (continued)

5.2 General

5.2.1 AC electrical characteristics

Figure 15. Input signal measurement reference output pins have the following characteristics.

• C L=30 pF loads
• Slew rate disabled
• Normal drive strength

5.2.2 Nonswitching electrical specifications

50 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

5.2.2.1 Voltage and current operating requirements

Table 34. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
• V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
• Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.

5.2.2.2 LVD and POR operating requirements

Table 35. V DD supply LVD and POR operating requirements

• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01) 2.62 2.72 2.70 2.80 2.78 2.88 V V Table continues on the next page...

MCX C24X Microcontroller, Rev. 2, 07/2024 51 NXP Semiconductors

Table 35. V DD supply LVD and POR operating requirements (continued)

• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11) 2.82 2.92 2.90 3.00 2.98 3.08 V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage

5.2.2.3 Voltage and current operating behaviors

Table 36. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = –2.5 mA VDD – 0.5 VDD – 0.5 V V VOH Output high voltage — high drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = –20 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = –10 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — normal drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 2.5 mA 0.5 0.5 V V VOL Output low voltage — high drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 10 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA Table continues on the next page...

52 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 36. Voltage and current operating behaviors (continued)

1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the

associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

1. Measured at VDD supply voltage = VDD min and Vinput = VSS

5.2.2.4 Power mode transition operating behaviors

• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode

Table 37. Power mode transition operating behaviors

• VLLS0 → RUN 152 166 μs
• VLLS1 → RUN 152 166 μs
• VLLS3 → RUN 104 μs
• LLS → RUN 7.5 μs
• VLPS → RUN 7.5 μs
• STOP → RUN 7.5 μs

MCX C24X Microcontroller, Rev. 2, 07/2024 53 NXP Semiconductors

5.2.2.5 Power consumption operating behaviors

The maximum values stated in the following table represent the characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). NOTE The while(1) test is executed with flash cache enabled. Table 38. Power consumption operating behaviors

• at 25 °C
• at 105 °C 4.79 4.94 4.98 5.14 mA IDD_RUNCO Running While(1) loop in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 2.73 2.9 2.87 3.05 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 5.45 5.6 5.67 5.82 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 3.41 3.56 3.55 3.70 mA mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 2.37 2.52 2.49 2.65 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 7.05 7.2 7.33 7.49 mA Table continues on the next page...

54 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 38. Power consumption operating behaviors (continued)

• at 25 °C
• at 105 °C 3.39 3.57 3.53 3.71 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 2.36 2.53 2.48 2.66 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 1.84 1.93 2.10 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
• at 105 °C 4.98 5.16 5.18 5.37 mA IDD_VLPRCO Very-low-power run core mark in flash in compute operation mode— 8 MHz LIRC mode, 4 MHz core/1 MHz flash, VDD = 3.0 V
• at 25 °C 710 752.6 μA IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in compute operation mode— 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C 251 376.5 μA IDD_VLPRCO Very-low-power run While(1) loop in SRAM in compute operation mode:—2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C 115 143.75 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C 136.5 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V
• at 25 °C μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V 212 318 μA Table continues on the next page...

MCX C24X Microcontroller, Rev. 2, 07/2024 55 NXP Semiconductors

• at 25 °C IDD_VLPR Very-low-power run mode current—8 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C 302 392.6 μA IDD_WAIT Wait mode current—core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V
• at 25 °C 1.81 2.12 mA IDD_WAIT Wait mode current—core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V
• at 25 °C 1.27 1.46 mA IDD_VLPW Very-low-power wait mode current, core disabled, 4 MHz system/ 1 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C — 156 193.2 μA IDD_VLPW Very-low-power wait mode current, core disabled, 2 MHz system/ 0.5 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C — 63 100.8 μA IDD_VLPW Very-low-power wait mode current, core disabled, 125 kHz system/ 31.25 kHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C — 32 48 μA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12 MHz bus and flash, VDD = 3.0 V
• at 25 °C 1.68 2.05 mA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, flash doze enabled, 12 MHz bus, VDD = 3.0 V
• at 25 °C 1.05 1.26 mA IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C 158.1 171 203.8 251.7 175.81 180.24 228.64 300.06 μA IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C 2.34 5.04 20.48 42.34 3.80 8.03 31.97 65.78 μA Table continues on the next page...

56 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C 2.33 4.95 20.18 41.93 3.80 7.94 31.57 65.17 μA IDD_LLS Low-leakage stop mode current, all peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 1.71 2.59 4.46 7.55 17.03 1.96 3.30 7.06 10.15 22.67 μA IDD_LLS Low-leakage stop mode current with RTC current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 2.27 3.1 4.99 8.1 17.32 2.52 3.81 7.59 10.70 22.96 μA IDD_LLS Low-leakage stop mode current with RTC current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 2.1 2.89 4.65 7.61 16.38 2.35 3.60 7.25 10.21 22.02 μA IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 1.43 2.06 3.51 5.91 13.36 1.58 2.52 5.20 7.60 17.08 μA IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C 1.83 2.47 3.96 6.44 1.98 2.93 5.65 8.13 μA Table continues on the next page...

MCX C24X Microcontroller, Rev. 2, 07/2024 57 NXP Semiconductors

• at 85 °C
• at 105 °C — 13.84 17.56 IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 1.8 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 1.68 2.27 3.66 5.97 12.92 1.83 2.73 5.35 7.66 16.64 μA IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C 0.84 1.19 2.03 3.54 8.53 1.06 1.33 2.62 4.13 9.98 μA IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C 1.26 1.61 2.5 4.07 1.48 1.75 3.09 4.66 10.45 μA IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C 1.08 1.42 2.21 3.59 8.02 1.30 1.56 2.80 4.18 9.47 μA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 262 593 1430 2930 7930 360 725 2014 3514 9895 nA Table continues on the next page...

58 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C 417 1230 2720 7780 185 549 1230 3304 9745 nA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR with optimization level high, optimized for balanced. 3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption. 4. No brownout

Table 39. Low power mode peripheral adders — typical value VLPS mode with the crystal enabled.

• VLLS1
• VLLS3
• LLS
• VLPS
• STOP 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 nA ILPTMR LPTMR peripheral adder measured by placing the device in VLLS1 mode with LPTMR enabled using LPO. 100 200 Table continues on the next page...

MCX C24X Microcontroller, Rev. 2, 07/2024 59 NXP Semiconductors

Table 39. Low power mode peripheral adders — typical value (continued) a single external input for compare. the RTC ALARM set for 1 minute.

• IRC8M (8 MHz internal reference clock)
• IRC2M (2 MHz internal reference clock) µA ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents.
• IRC8M (8 MHz internal reference clock)
• IRC2M (2 MHz internal reference clock) 130 130 130 130 130 130 µA Table continues on the next page...

60 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

5.2.2.5.1 Diagram: Typical IDD_RUN operating behavior

• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

MCX C24X Microcontroller, Rev. 2, 07/2024 61 NXP Semiconductors

Run Mode Current vs Core Frequency Temperature =25, VDD=3, MCG Mode=HIRC, while loop located in Flash 6.00E-03 5.00E-03 4.00E-03 3.00E-03 2.00E-03 1.00E-03 000.00E+00 All Peripheral CLK Gates ALLOFF ALLON CLK Ratio Flash - Core Core Freq (MHz) '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 Current Consumption on VDD (A) Figure 16. Run mode supply current vs. core frequency 62 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Run Mode Current vs Core Frequency Temperature =25, VDD=3, MCG Mode=HIRC, while loop located in RAM 6.00E-03 5.00E-03 4.00E-03 3.00E-03 2.00E-03 1.00E-03 000.00E+00 Current Consumption on VDD (A) '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 CLK Ratio Flash - Core Core Freq (MHz) All Peripheral CLK Gates ALLOFF ALLON MCX C24X Microcontroller, Rev. 2, 07/2024 63 NXP Semiconductors

VLPR Mode Current vs Core Frequency Temperature =25, VDD=3, MCG Mode=HIRC, while loop located in RAM Current Consumption on VDD (A) 400.00E-06 350.00E-06 300.00E-06 250.00E-06 200.00E-06 150.00E-06 000.00E+00 100.00E-06 50.00E-06 '1-1 '1-2 '1-4 All Peripheral CLK Gates ALLOFF ALLON CLK Ratio Flash - Core Core Freq (MHz) Figure 17. VLPR mode current vs. core frequency

5.2.2.6 EMC performance

guidance specifically targeted at optimizing EMC performance.

• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers

64 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

• AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems

5.2.2.7 Capacitance attributes

Table 40. Capacitance attributes

5.2.3 Switching specifications

5.2.3.1 Device clock specifications

Table 41. Device clock specifications

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

MCX C24X Microcontroller, Rev. 2, 07/2024 65 NXP Semiconductors

5.2.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 42. General switching specifications

1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.

5.2.4 Thermal specifications

5.2.4.1 Thermal operating requirements

Table 43. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

determine TJ is: TJ = TA + RθJA × chip power dissipation.

1. The device operating specification is not guaranteed beyond 125 °C TJ.

5.2.4.2 Thermal attributes

Table 44. Thermal attributes Table continues on the next page... 66 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 44. Thermal attributes (continued)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

1. Per JEDEC JESD51-6 with the board horizontal.
2. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

1. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
2. Thermal characterization parameter indicating the temperature difference between package top and the junction
3. Thermal characterization parameter indicating the temperature difference between package bottom center and the

parameter is written as Psi-JB.

5.3 Peripheral operating requirements and behaviors

5.3.1 Core modules

5.3.1.1 SWD electricals

Table 45. SWD full voltage range electricals

• Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns Table continues on the next page...

MCX C24X Microcontroller, Rev. 2, 07/2024 67 NXP Semiconductors

5.3.2 System modules

There are no specifications necessary for the device's system modules.

5.3.3 Clock modules

5.3.3.1 MCG-Lite specifications

Table 46. IRC48M specifications

1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation.

USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).

1. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. See

reference manual for details. Table 47. IRC8M/2M specification MCX C24X Microcontroller, Rev. 2, 07/2024 69 NXP Semiconductors

5.3.3.2 Oscillator electrical specifications

5.3.3.2.1 Oscillator DC electrical specifications

Table 48. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Table continues on the next page...

70 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 48. Oscillator DC electrical specifications (continued)

1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For

all other cases external capacitors must be used.

1. When low power mode is selected, RF is integrated and must not be attached externally.
2. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

5.3.3.2.2 Oscillator frequency specifications

Table 49. Oscillator frequency specifications

1. Other frequency limits may apply when external clock is being used as a reference for the FLL

MCX C24X Microcontroller, Rev. 2, 07/2024 71 NXP Semiconductors

1. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set.

5.3.4 Memories and memory interfaces

5.3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

5.3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 50. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

5.3.4.1.2 Flash timing specifications — commands

Table 51. Flash command timing specifications

1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.

72 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

5.3.4.1.3 Flash high voltage current behaviors

Table 52. Flash high voltage current behaviors

5.3.4.1.4 Reliability specifications

Table 53. NVM reliability specifications

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.

5.3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

5.3.6 Analog

5.3.6.1 ADC electrical specifications

Table 54. 16-bit ADC operating conditions Table continues on the next page... MCX C24X Microcontroller, Rev. 2, 07/2024 73 NXP Semiconductors

Table 54. 16-bit ADC operating conditions (continued)

• All other modes VREFL VREFL 31/32 × VREFH VREFH V — CADIN Input capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

74 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Figure 20. ADC input impedance equivalency diagram Table 55. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non- linearity
• 12-bit modes — ±0.9 –2.7 to +1.9 LSB4 5 Table continues on the next page...

MCX C24X Microcontroller, Rev. 2, 07/2024 75 NXP Semiconductors

Table 55. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• <12-bit modes — ±0.4 –0.7 to +0.5 EFS Full-scale error • 12-bit modes
• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
• 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 –94 –85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA

76 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

5.3.6.1.3 Voltage reference electrical specifications

Table 56. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range

VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1. Table 57. VREF full-range (-40 – 105°C) operating behaviors

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 58. VREF limited-range (0 – 50°C) operating behaviors 78 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

5.3.6.2 CMP and 6-bit DAC electrical specifications

Table 59. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64

MCX C24X Microcontroller, Rev. 2, 07/2024 79 NXP Semiconductors

0.1 Vin level (V) CMP Hystereris (V) 0.05 0.01 0.02 0.03 0.08 0.07 0.06 0.04 Figure 23. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 80 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

0.1 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 Vin level (V) CMP Hysteresis (V) Figure 24. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

5.4 Timers

See General switching specifications.

5.5 Communication interfaces

5.5.1 USB electrical specifications

MCX C24X Microcontroller, Rev. 2, 07/2024 81 NXP Semiconductors

This device cannot support Host mode operation.

5.5.2 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 60. SPI master mode timing on slew rate disabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).

Table 61. SPI master mode timing on slew rate enabled pads Table continues on the next page... 82 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 61. SPI master mode timing on slew rate enabled pads (continued)

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. If configured as an output.

Figure 25. SPI master mode timing (CPHA = 0) MCX C24X Microcontroller, Rev. 2, 07/2024 83 NXP Semiconductors

<<CLASSIFICATION>> <<NDA MESSAGE>> 6 7 MSB IN 2 BIT 6 . . . 1 MASTER MSB OUT 2 MASTER LSB OUT 10 11 PORT DATA PORT DATA 3 10 11 4 1.If configured as output (OUTPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS 1 (OUTPUT) (OUTPUT) MOSI (OUTPUT) MISO (INPUT) LSB INBIT 6 . . . 1 Figure 26. SPI master mode timing (CPHA = 1) Table 62. SPI slave mode timing on slew rate disabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

84 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Table 63. SPI slave mode timing on slew rate enabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

Figure 27. SPI slave mode timing (CPHA = 0) MCX C24X Microcontroller, Rev. 2, 07/2024 85 NXP Semiconductors

BIT 6 . . . 1 MSB OUT SLAVE LSB OUT 12 13 3 12 13 SLAVE see note (INPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS (INPUT) (INPUT) MOSI (INPUT) MISO (OUTPUT) NOTE: Not defined LSB INBIT 6 . . . 1 Figure 28. SPI slave mode timing (CPHA = 1)

5.5.3 Inter-Integrated Circuit Interface (I2C) timing

Table 64. I2C timing Hold time (repeated) START condition.

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high

drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V. 86 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 7. Cb = total capacitance of the one bus line in pF. To achieve 1MHz I2C clock rates, consider the following recommendations:

• To counter the effects of clock stretching, the I2C baud Rate select bits can be configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.

Table 65. I 2C 1Mbit/s timing period, the first clock pulse is generated.

1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins

across the full voltage range.

1. Cb = total capacitance of the one bus line in pF.

MCX C24X Microcontroller, Rev. 2, 07/2024 87 NXP Semiconductors

Figure 29. Timing definition for devices on the I2C bus

5.5.4 UART

See General switching specifications.

6 Design considerations

6.1 Hardware design considerations

voltages higher than maximum-rated voltages to this high-impedance circuit.

6.1.1 Printed circuit board recommendations

• Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages. Design considerations 88 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

6.1.2 Power delivery system

• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as sequential segments.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins.
• The USB_VDD voltage range is 3.0 V to 3.6 V. It is recommended to include a filter circuit with one bulk capacitor (no less than 2.2 μF) and one 0.1 μF capacitor at the USB_VDD pin to improve USB performance.
• Take special care to minimize noise levels on the VREFH/VREFL inputs. An option is to use the internal reference voltage (output 1.2 V typically) as the ADC reference. NOTE The internal reference voltage output (VREFO) is bonded to the VREFH pin on some packages and to PTE30 on other packages. When the VREFO output is used, a 0.1 μF capacitor is required as a filter. Do not connect any other supply voltage to the pin that has VREFO activated.

6.1.3 Analog design

small compared to the sample period. Figure 30. RC circuit for ADC input

external clamp diodes must be included to protect against transient over-voltages. Figure 31. High voltage measurement with an ADC input

6.1.4 Digital design

Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).

• RESET_b pin The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An external RC circuit is recommended to filter noise as shown in the following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to reject spurious noise. Design considerations 90 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

6.1.5 Crystal oscillator

MCU clock system, refer to the following table and diagrams. The feedback resistor, RF, is incorporated internally with the low power oscillators. An external feedback is required when using high gain (HGO=1) mode. frequency above 2MHz does not require any series resistance. for high frequency crystals and resonators. Table 66. External crystal/resonator connections Figure 36. Crystal connection – Diagram 1

Figure 37. Crystal connection – Diagram 25 Figure 38. Crystal connection – Diagram 3 Figure 39. Crystal connection – Diagram 4

7 Part identification

7.1 Description

values of these fields to determine the specific part you have received.

7.2 Format

7.3 Fields

Table 67. Part number fields description

• 1 = Baseline
• 2 = Baseline Enhance
• 3 = Reserved
• 4 = HMI C Core Features • 4 = 48MHz FS Flash Size • 1 = 32 KB
• 2 = 64 KB
• 3 = 128 KB
• 4 = 256 KB T Junction Temperature range (°C) • V = –40 to 125
• FK = 24QFN: 4x4x0.65 mm
• FM = 32QFN: 5x5x0.9 mm
• FT = 48QFN: 7x7x0.9 mm
• LH = 64LQFP: 10x10x1.6mm
• MP = 64MAPBGA: 5x5x1.23mm SR Silicon Revision • A = Initial Mask set
• B = 1st Major spin
• T = Tray

7.4 Example

8 Revision history

The following table provides a revision history for this document. Table 68. Revision history

Revision history

96 MCX C24X Microcontroller, Rev. 2, 07/2024 NXP Semiconductors

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. NXP Semiconductors Legal information MCX C24X Microcontroller, Rev. 2, 07/202497 NXP Semiconductors

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. ESD protection devices — These products are only intended for protection against ElectroStatic Discharge (ESD) pulses and are not intended for any other usage including, without limitation, voltage regulation applications. NXP Semiconductors accepts no liability for use in such applications and therefore such use is at the customer’s own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. NXP Semiconductors Legal information NXP Semiconductors MCX C24X Microcontroller, Rev. 2, 07/2024

Suitability for use in non-automotive qualified products — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. I2C-bus — logo is a trademark of NXP B.V. MCX — is a trademark of NXP B.V. NXP Semiconductors Legal information MCX C24X Microcontroller, Rev. 2, 07/202499 NXP Semiconductors

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2024. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 07/2024 Document identifier: MCXC24XP64M48SF2