MCXA153 NXP | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 75

Technical content

Datasheet sections

  • 1 Feature Comparison
  • 2 Ratings
  • 2.1 Thermal handling ratings
  • 2.2 Moisture handling ratings
  • 2.3 ESD handling ratings
  • 2.4 Voltage and current maximum ratings
  • 2.4.1 Voltage and current maximum ratings
  • 2.5 Required Power-On-Reset (POR) Sequencing
  • 3 General
  • 3.1 AC electrical characteristics
  • 3.2 Nonswitching electrical specifications
  • 3.2.2 HVD, LVD, and POR operating requirements
  • 3.2.2.1 VDD supply HVD, LVD, and POR Operating
  • 3.2.3 Voltage and current operating behaviors
  • 3.2.4 On-chip regulator electrical specifications
  • 3.2.4.1 LDO_CORE electrical specifications
  • 3.2.6 Power consumption operating behaviors
  • 3.2.6.1 Power consumption operating behaviors
  • 3.2.7 EMC radiated emissions operating behaviors
  • 3.2.8 Designing with radiated emissions in mind
  • 3.2.9 Capacitance attributes
  • 3.3 Switching specifications
  • 3.3.1 Device clock specs
  • 3.3.2 General switching specifications
  • 3.3.2.1 General switching specifications
  • 3.4 Thermal specifications
  • 3.4.1 Thermal operating requirements
  • 3.4.2 Thermal attributes
  • 4 Peripheral operating requirements and behaviors
  • 4.1 Core modules
  • 4.1.1 Debug trace operating behaviors
  • 4.1.2 JTAG Debug Interface Timing
  • 4.1.3 Serial Wire Debug (SWD) Timing
  • 4.2 Clock modules
  • 4.2.1 Reference Oscillator Specification
  • 4.2.1.1 System Crystal Oscillator Specification
  • 4.2.1.2 System Oscillator Crystal Specifications
  • 4.2.1.3 System Oscillator Crystal Specifications
  • 4.2.2 FRO-192M specifications
  • 4.2.3 FRO-12M specifications
  • 4.2.4 FRO-16K specifications
  • 4.3 Memories and memory interfaces
  • 4.3.1 Flash electrical specifications
  • 4.3.1.1 Timing specifications
  • 4.3.1.2 Flash high voltage current behavior
  • 4.3.1.3 Flash reliability specifications
  • 4.4 Analog
  • 4.4.1 ADC electrical specifications
  • 4.4.1.1 ADC operating conditions
  • 4.4.1.2 ADC electrical characteristics
  • 4.4.2 Comparator and 8-bit DAC electrical
  • 4.5 Timers
  • 4.6 Communication interfaces
  • 4.6.1 LPUART
  • 4.6.2 LPSPI switching specifications
  • 4.6.2.1 LPSPI master mode timing
  • 4.6.2.2 LPSPI slave mode timing
  • 4.6.3 LPI2C timing
  • 4.6.4 I2C 1 Mbps timing
  • 4.6.5 I2C HS mode timing
  • 4.6.6 I3C Push-Pull Timing Parameters for SDR
  • 4.6.7 USB Full-speed device electrical specifications
  • 4.7 Human Machine Interface (HMI) modules
  • 4.7.1 General Purpose Input/Output (GPIO)
  • 5 Package dimensions
  • 5.1 Obtaining package dimensions
  • 6 Pinout
  • 6.1 MCXA143, A142, A153, A152 Signal
  • 6.2 MCXA143, A142, A153, A152 Pinouts
  • 6.3 Recommended connection for unused analog
  • 7 Ordering parts
  • 7.1 Determining valid orderable parts
  • 8 Part identification
  • 8.1 Description
  • 8.2 Part number format
  • 8.3 Example
  • 8.4 Small package marking
  • 8.4.1 Package marking information
  • 9 Terminology and guidelines
  • 9.1 Definitions
  • 9.2 Examples
  • 9.3 Typical-value conditions
  • 9.4 Relationship between ratings and operating
  • 9.5 Guidelines for ratings and operating
  • 9.6 Specification Test Methods

32-bit Arm Cortex®-M33 MCU for Industrial and Consumer IoT Applications with USB FS, Serial Interface, 32-bit counter/timers, FlexPWM, 12-bit 4.0 Msamples/sec ADC, Comparator, Temperature Sensor

  • Single Arm Cortex-M33 Core. No FPU, no DSP extension instruction set, no TrustZone, no MPU
  • Industrial Strength: Industrial communication protocol support, BLDC/ PMSM Motor Control support, integrated sensor interfaces (MIPI-I3C, I2C, SPI)
  • Power-efficient: 59 μA/MHz active current, 6.5 μA power-down mode with all SRAM retention, 394 nA Deep Power-down mode Target Applications
  • Industrial and Consumer IoT
  • Industrial Communications
  • Smart Metering
  • Motor Control
  • Automation & Control
  • Sensors CPU Core Platform
  • CPU: Cortex-M33
  • Multilayer Bus Matrix
  • One 4-CH DMA, supports asynchronous DMA Memories and memory expansion
  • Single-bank Flash: Up to 128 KB FLASH with ECC (support one bit correction and two bits detection)
  • Cache Engine with 4 KB RAM
  • Up to 32 KB RAM, configurable as up to 8 KB RAM with ECC (support single bit correction, two bits detection)
  • All RAM can be retained down to deep power down mode
  • 16 KB ROM Security
  • Life cycle management
  • Flash read/write/execute permission protect by MBC and lockable
  • 128-bit Universal Unique Identifier (UUID) per device in accordance with IETF's RFC4122 version 5 specification
  • Code Watchdog for code flow integrity checking
  • Read Out Protection (RoP) from flash with 3 levels of factory access control to customize returns handling
  • Glitch attack resistant keyed access (Glikey) to security sensitive registers Analog modules
  • 1x 12-bit ADC — 4 Msps in 12-bit mode — Up to 24 ADC Input channels (depending on the package) — Reduced bandwidth 16b mode — Integrated temperature sensor
  • Two High-speed Comparators with 8 input pins and a 8-bit DAC as internal reference Table continues on the next page... MCXA14x MCXA15x 64LQFP 10 x 10 x 1. 4 mm, 0.5 mm 32HVQFN 5 x 5 x 0.9 mm, 0.5 mm 48HVQFN 7 x 7 x 0.9 mm, 0.5 mm MCXA153, A152, A143, A142 Data Sheet 32-bit Arm Cortex-M33 core at 48MHz (A14x) or 96MHz (A15x) Rev. 3 — 01/2024 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
  • Active — 59 µA/MHz in Active Mode (CoreMark executing from flash, 3.3 V @25 °C )
  • Deep Sleep — 20.28 µA, 7.4 µs wake-up ( 3.3 V @25 °C)
  • Power Down — 6.5 µA, 17.1 µs wake-up (full SRAM retention, 3.3 V@ 25
  • Deep Power Down — 394 nA, 2.36 ms wake-up (wakeup timer disabled, reset pin enabled, all SRAM off, 3.3 V @25 °C) Flexible System and Clocks
  • 192 MHz MHz free-running oscillator (FRO-192M)
  • 12 MHz free-running oscillator (FRO-12M)
  • 16 kHz free-running oscillator (FRO-16k)
  • Up to 50 MHz crystal oscillator Inputs Supply Voltage options:
  • Integrated voltage regulator or support for external voltage regulator — LVD for VDD_CORE and VDD — HVD for VDD — Core LDO, other LDOs — Operating voltage: 1.71 V to 3.6 V — IOs: 1.71 V - 3.6 V full-performance Operating Characteristics
  • Temperature range (junction): -40 °C to 125 °C — 1x CMP is functional down to DPD mode Communication interfaces
  • USB Full-speed (Device) with on-chip FS PHY
  • 2x LPSPI, 1x LPI2C, 3x LPUART, 1x I3C Motor Control Subsys
  • 1x FlexPWM each with 3 submodules, providing 9 PWM outputs (no Nanoedge module)
  • 1x Quadrature Encoder/Decoder (QDC)
  • 1x AOI Timers
  • Three 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests
  • LPTimer
  • Frequency measurement timer
  • Windowed Watchdog Timer
  • Wake Timer
  • Micro Timer
  • OS Event Timer HMI
  • Up to 52 GPIOs — Up to eight 20 mA IO — 50 MHz IO on P1 and P3 — Up to 19-pin wake-up sources function down to deep power-down mode — Support 1.71 V~3.6 V IO supply range

Table 1. Ordering Information Table continues on the next page...

Table 1. Ordering Information (continued)

  1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.

Table 2. Device Revision Number Table 3. Related Resources structure and function (operation) of a device. information for a particular device mask set.

  • HVQFN 48-pin: 98ASA01637D
  • HVQFN 32-pin:98ASA02110D Software development kit MCUXpresso SDK. An open source software development kit (SDK) built specifically for your processor and evaluation board selections. http://www.nxp.com/mcuxpresso NXP Semiconductors MCXA153, A152, A143, A142 Data Sheet, Rev. 3, 01/2024 Data Sheet: Technical Data 3 / 75

Figure 1. Block Diagram

1 Feature Comparison

Table 4. Feature Comparison

2 Ratings

2.1 Thermal handling ratings

Table 5. Thermal handling ratings

  1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
  2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

2.2 Moisture handling ratings

Table 6. Moisture handling ratings

  1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

2.3 ESD handling ratings

Table 7. ESD handling ratings

  1. Determined according to ANSI/ESDA/JEDEC Standard JS-001-2023, For Electrostatic Discharge Sensitivity Testing,

Human Body Model (HBM) - Device Level.

  1. Determined according to ANSI/ESDA/JEDEC Standard JS-002-2022, For Electrostatic Discharge Sensitivity Testing,

Charged Device Model (CDM) - Device Level.

  1. Determined according JEDEC Standard JESD78F, IC Latch-Up Test.

2.4 Voltage and current maximum ratings

2.4.1 Voltage and current maximum ratings

Table 8. Voltage and current maximum ratings Table continues on the next page...

Table 8. Voltage and current maximum ratings (continued)

  1. Analog pins are defined as pins that do not have an associated general-purpose I/O port function.
  2. This limit is per supply pin. This includes all power pins, including VDD, VDD_ANA and VDD_USB

2.5 Required Power-On-Reset (POR) Sequencing

  • VDD and VDD_ANA must be same voltage

3 General

3.1 AC electrical characteristics

at the 20% and 80% points, as shown in the following figure.

Figure 2. Input signal measurement reference

3.2 Nonswitching electrical specifications

3.2.1 Voltage and current operating requirement

Table 9. Voltage and current operating requirement

5 V tolerant IO

Table continues on the next page...

Table 9. Voltage and current operating requirement (continued)

  1. All I/O pins are internally clamped to VSS and VDD through an ESD protection diode. If VIN is greater than
  2. Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD as appropriate.

3.2.2 HVD, LVD, and POR operating requirements

  • VDD

3.2.2.1 VDD supply HVD, LVD, and POR Operating Requirements

Table 10. VDD supply HVD, LVD, and POR Operating Requirements Table continues on the next page...

Table 10. VDD supply HVD, LVD, and POR Operating Requirements (continued)

3.2.3 Voltage and current operating behaviors

Table 11. Voltage and current operating behaviors Table continues on the next page...

Table 11. Voltage and current operating behaviors (continued)

0.27 V)/3

  1. For the HD pads, when setting DSE1=1, the IOH/IOL are four times higher at the same VOH/VOL.
  2. RST pins are always configured in high drive mode
  3. Open drain outputs must be pulled to VDD
  1. Only I3C pins support this option
  2. Only RST pins support this option.

3.2.4 On-chip regulator electrical specifications

3.2.4.1 LDO_CORE electrical specifications

Table 12. LDO_CORE electrical specifications

3.2.5 Power mode transition operating behaviors

  • CPU clock = 48 MHz
  • AHB clock = 48 MHz
  • Clock source = FIRC

3.2.5.1 Power mode transition operating behaviors

Table 13. Power mode transition operating behaviors Table continues on the next page...

Table 13. Power mode transition operating behaviors (continued)

  1. Max value is mean+3 × sigma of tested values at the worst case of ambient temperature range and VDD 1.71 V to 3.6 V.

Max values are based on characterization but not covered by test limits in production.

  1. Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V
  2. WFE used for low-power mode entry
  3. SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x00 and the Core voltage level is configured as same level for active and

low power mode (SPC->ACTIVE_CFG[CORELDO_VDD_LVL]=SPC->LP_CFG[CORELDO_VDD_LVL] = 01b).

  1. SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x5B and the Core voltage level is configured as different level

3.2.6 Power consumption operating behaviors

standard deviation (mean + 3 sigma).

3.2.6.1 Power consumption operating behaviors

Table 14. Power consumption operating behaviors

48 MHz; AHB_CLK = 48

Table continues on the next page...

Table 14. Power consumption operating behaviors (continued)

96 MHz; AHB_CLK = 96

Table continues on the next page...

Table continues on the next page...

  1. SD: standard drive, core voltage is 1.1V. MD: middle drive, core voltage is 1.0V

3.2.7 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

3.2.8 Designing with radiated emissions in mind

  1. Perform a keyword search for “EMC design”.

3.2.9 Capacitance attributes

Table 15. Capacitance attributes

3.3 Switching specifications

3.3.1 Device clock specs

Table 16. Device clock specs

3.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO, LPUART, LPI2C, LPI3C, LPSPI functions.

3.3.2.1 General switching specifications

Refer to attached pinout spreadsheet. Table 17. General switching specifications Table continues on the next page...

Table 17. General switching specifications (continued) Table continues on the next page...

  1. The synchronous and asynchronous timing must be met.
  2. This is the shortest pulse that is guaranteed to be recognized
  3. For the HD I/O pins, setting DSE1 = 1 will support the same rise/fall time at 4x the load capacitance. For the 5VTOL I/O
  4. Assumes default values in CALIB1 and CALIB0 in PORTS
  5. Load is 25 pF for DSE=0. Load is 100 pF for DSE=2 or DSE=3. Drive strength and slew rate are configured using

PORTx_PCRn[DSE1], PORTx_PCRn[DSE], and PORTx_PCRn[SRE].

3.4 Thermal specifications

3.4.1 Thermal operating requirements

Table 18. Thermal operating requirements

  1. The device may operate at maximum TA rating as long as TJ maximum of 125 °C is not exceeded. The simplest method to

determine TJ is: TJ = TA + RθJA*chip power dissipation.

  1. The device operating specification is not guaranteed beyond 125 °C TJ.
  2. The maximum operating requirement applies to all chapters unless otherwise specifically stated.
  3. Operating at maximum conditions for extended periods may affect device reliability. Refer to Product Lifetime Usage

3.4.2 Thermal attributes

Table 19. Thermal attributes

  1. Thermal test board meets JEDEC specification for this package (JESD51-7)
  2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is

4 Peripheral operating requirements and behaviors

4.1 Core modules

4.1.1 Debug trace operating behaviors

Table 20. Debug trace operating behaviors Table continues on the next page...

Table 20. Debug trace operating behaviors (continued) Figure 3. TRACE_CLKOUT specifications Figure 4. Trace data specifications

4.1.2 JTAG Debug Interface Timing

The following table gives the JTAG specifications in debug interface mode. Table 21. JTAG Debug Interface Timing Table continues on the next page...

Table 21. JTAG Debug Interface Timing (continued) Table continues on the next page...

Figure 7. JTAG-DP/TAP timing

4.1.3 Serial Wire Debug (SWD) Timing

The following table gives the Serial Wire Debug specifications for the device. Table 22. Serial Wire Debug (SWD) Timing Table continues on the next page...

Table 22. Serial Wire Debug (SWD) Timing (continued) Figure 8. Serial Wire clock input timing Figure 9. Serial Wire data timing

4.2 Clock modules

4.2.1 Reference Oscillator Specification

temperature, mechanical, and aging excursions. The table below shows typical specifications for the Crystal Oscillator.

4.2.1.1 System Crystal Oscillator Specification

Table 23. System Crystal Oscillator Specification

  1. When a crystal is being used with the oscillator, the EXTAL and XTAL pins should only be connected to required oscillator

components and must not be connected to any other devices.

  1. This specification is for an externally supplied clock driven to EXTAL and does not apply to any other clock input.

4.2.1.2 System Oscillator Crystal Specifications. Table 24. System Oscillator Crystal Specifications. Table continues on the next page...

Table 24. System Oscillator Crystal Specifications. (continued)

  1. Maximum crystal equivalent series resistance for 16 MHz is 80 ohms with 2 pF shunt capacitance.
  2. Dependent on crystal specifications, proper PC board layout procedures must be followed to achieve specifications

Figure 10. Crystal Electrical Block Diagram

4.2.1.3 System Oscillator Crystal Specifications

Table 25. System Oscillator Crystal Specifications. Table continues on the next page...

Table 25. System Oscillator Crystal Specifications. (continued)

  1. This is based on simulation

4.2.2 FRO-192M specifications

Table 26. FRO-192M specifications

4.2.3 FRO-12M specifications

Table 27. FRO-12M specifications

4.2.4 FRO-16K specifications

Table 28. FRO-16K specifications

4.3 Memories and memory interfaces

4.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

4.3.1.1 Timing specifications

4.3.1.1.1 Flash command time specifications

Table 29. Flash command time specifications Table continues on the next page...

Table 29. Flash command time specifications (continued)

  1. Based on simulation with 3 pulse programming for typ, 6 pulse programming for max.
  2. Based on TSMC specification for erase sector time with no added time for verification and overhead.

4.3.1.2 Flash high voltage current behavior

Table 30. Flash high voltage current behavior

  1. See the Power Management chapter in the reference manual for the specific VDD voltage supply powering the flash array.

4.3.1.3 Flash reliability specifications

Table 31. Flash reliability specifications

10 K 500 K — cycles Program Flash —

100 K 500 K — cycles Program Flash —

  1. Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40°C ≤ Tj ≤ 125°C.
  2. For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices

4.4 Analog

4.4.1 ADC electrical specifications

ADC operating conditions apply when the ADC is used in differential mode. All other ADC channels meet the 12-bit single-ended accuracy specifications.

4.4.1.1 ADC operating conditions

Table 32. ADC operating conditions

0.99 VDDAD VDDAD V — —

Table continues on the next page...

Table 32. ADC operating conditions (continued)

  1. Minimum VDDAD/VREFH is 2.4 V in high-speed mode
  2. For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally.
  3. If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result
  4. ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected

between the source and the ADC input pin.

  1. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
  2. There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index
  3. If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel

Table 33. I/O mux resistance table Table continues on the next page...

Table 33. I/O mux resistance table (continued) Figure 11. ADC input impedance equivalency diagram

4.4.1.2 ADC electrical characteristics

Table 34. ADC electrical characteristics

6 MHz Clock,

Table continues on the next page...

Table 34. ADC electrical characteristics (continued)

24 MHz clock,

60 MHz Clock,

Table continues on the next page...

60 MHz, HS=1, AVGS

64 MHz, HS =1,

Table continues on the next page...

  1. The ADC supply current depends on the ADC conversion clock speed, conversion rate, and power mode. Typical value

show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00.

  1. Must meet minimum TSMP requirement
  2. Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and
  3. Min based on 3.5 cycles @ 24 MHz
  4. Min based on 3.5 cycles @ 60 MHz
  5. Min based on 3.5 cycles @ 64 MHz
  6. Internal channel inputs are those that do not come from external source (temperature sensor, bandgap).
  7. 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16- bit specifications, multiply by 4.
  8. All accuracy numbers assume that the ADC is calibrated with VREFH=VDD_ANA and using a high- speed- dedicated input

values are for reference only, and are not tested in production.

  1. Dynamic results assume Fin=1 kHz sinewave, no averaging unless otherwise specified
  2. Delay required if PWREN=0
  3. The temperature sensor can be calibrated to a +/- 1 % precision after board assembly by using a 3-temperature calibration
  • Vbe1 is the first value stored to the FIFO as a result of the temperature sensor channel conversion
  • Vbe8 is the second value stored to the FIFO as a result of the temperature sensor channel conversion
  • A is the slope factor
  • B is the offset factor
  • α is the bandgap coefficient Set the power-up delay (PUDLY) according to the ADC start-up time if PWREN=0. NXP Semiconductors Peripheral operating requirements and behaviors MCXA153, A152, A143, A142 Data Sheet, Rev. 3, 01/2024 Data Sheet: Technical Data 39 / 75

Figure 12. ENOB vs ADC (16b HS Mode) Figure 13. ENOB vs ADC sample rate

4.4.2 Comparator and 8-bit DAC electrical specifications

Table 35. Comparator and 8-bit DAC electrical specifications Table continues on the next page...

Table 35. Comparator and 8-bit DAC electrical specifications (continued) Table continues on the next page...

  1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V.
  2. Overdrive does not include input offset voltage or hysteresis. The propagation delay is defined as the time delay between
  3. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

and the comparator output settling to a stable level. Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 1)

Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 0) Figure 16. Typical hysteresis vs Vin level (VDD =3.3 V, HPMD = 0, NPMD = 1)

4.5 Timers

See General switching specifications.

4.6 Communication interfaces

4.6.1 LPUART

See General switching specifications.

4.6.2 LPSPI switching specifications

of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes.

4.6.2.1 LPSPI master mode timing

Table 36. LPSPI master mode timing Table continues on the next page...

Table 36. LPSPI master mode timing (continued)

  1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI

peripheral functional clock.

  1. If configured as an output.

4.6.2.2 LPSPI slave mode timing

Table 37. LPSPI slave mode timing Table continues on the next page...

Table 37. LPSPI slave mode timing (continued) Table continues on the next page...

  1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI

peripheral functional clock.

  1. Time to data active from high-impedance state
  2. Hold time to high-impedance state

Figure 19. LPSPI slave mode timing (CPHA = 0) Figure 20. LPSPI slave mode timing (CPHA = 1)

4.6.3 LPI2C timing

Table 38. LPI2C timing Table continues on the next page...

Table 38. LPI2C timing (continued) Table continues on the next page...

  1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
  2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal
  3. Input signal Slew = 10 ns and Output Load = 50 pF
  4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
  1. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

  1. Cb = total capacitance of the one bus line in pF.

4.6.4 I2C 1 Mbps timing

Table 39. I2C 1 Mbps timing

  1. Cb = total capacitance of the one bus line in pF for maximum value

Figure 21. Timing definition for devices on the I2C bus

4.6.5 I2C HS mode timing

Table 40. I2C HS mode timing Table continues on the next page...

Table 40. I2C HS mode timing (continued)

  1. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of
  2. Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF. Applicable for maximum value.

Only PTB4/5, PTA18/19, PTC0/1, PTC4/5 pin can support Fast+ (3 MHz) mode.

4.6.6 I3C Push-Pull Timing Parameters for SDR Mode

Medium Clock and PUR Pads Only. I3C Standard plus Data Pads to be used with I3C standard plus Clock and PUR pads only. Table 41. I3C Push-Pull Timing Parameters for SDR Mode

  1. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH (see

Figure 24. Master out timing Figure 25. Slave out timing Figure 26. Master SDR timing

4.6.7 USB Full-speed device electrical specifications

compliance requirements defined in the Universal Serial Bus Revision 2.0 Specification with the amendments below.

  • USB ENGINEERING CHANGE NOTICE — Title: 5 V Short Circuit Withstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.0
  • Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
  • USB ENGINEERING CHANGE NOTICE — Title: Pull-up/Pull-down resistors — Applies to: Universal Serial Bus Specification, Revision 2.0
  • USB ENGINEERING CHANGE NOTICE — Title: Suspend Current Limit Changes — Applies to: Universal Serial Bus Specification, Revision 2.0 This SoC does not have a dedicated pin to monitor the state of the USB VBUS signal. Please refer to the USBFS chapter in the Reference Manual for methods which can be used for VBUS Session_Valid detection with either a P4-12/ALT1 pin using an external resistive divider.

4.7 Human Machine Interface (HMI) modules

4.7.1 General Purpose Input/Output (GPIO)

See General switching specifications.

5 Package dimensions

5.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 64-pin LQFP 98ASS23234W 48-pin HVQFN 98ASA01637D 32-pin HVQFN 98ASA02110D

6 Pinout

6.1 MCXA143, A142, A153, A152 Signal Multiplexing and Pin Assignments

The signal multiplexing and pin assignments are provided in an Excel file attached to this document: 1. Click the paperclip symbol on the left side of the PDF window. 2. Double-click on the Excel file to open it. 3. Select the “Pinout” tab. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. However, pinout table is also given below: NXP Semiconductors Package dimensions MCXA153, A152, A143, A142 Data Sheet, Rev. 3, 01/2024 Data Sheet: Technical Data 57 / 75

Table 42. pinmux Table continues on the next page...

Table 42. pinmux (continued) Table continues on the next page...

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6.2 MCXA143, A142, A153, A152 Pinouts

  1. Click the paperclip symbol on the left side of the PDF window.
  2. Double-click on the Excel file to open it.
  3. Select the respective package tab.

6.3 Recommended connection for unused analog and digital pins

Table 43. Recommended connection for unused interfaces

7 Ordering parts

7.1 Determining valid orderable parts

8 Part identification

Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part.

8.1 Description

8.2 Part number format

Table 44. Part number fields descriptions

  • 2 = Baseline Enhance
  • 3 = Analog C Core Features • 4 = 48MHz, Motor PWM, USB FS
  • 5 = 96MHz, Motor PWM, USB FS FS Flash Size • 1 = 32 KB, 48 MHz
  • 2 = 64 KB, 48 MHz
  • 3 = 128 KB, 48 MHz
  • 4 = 256 KB, 96 MHz
  • 5 = 512 KB, 96 MHz
  • 6 = 1024 KB, 96 MHz T Junction Temperature range (°C) • V = –40 to 125
  • FT = 48 HVQFN
  • FM = 32 HVQFN Table continues on the next page... NXP Semiconductors Part identification MCXA153, A152, A143, A142 Data Sheet, Rev. 3, 01/2024 Data Sheet: Technical Data 67 / 75

Table 44. Part number fields descriptions (continued)

  • B = 1st Major spin
  • C = 2nd Major spin
  • T = Tray

8.3 Example

8.4 Small package marking

8.4.1 Package marking information

Table 45. Package marking

9 Terminology and guidelines

9.1 Definitions

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Table continued from the previous page... Term Definition

  • Operating ratings apply during operation of the chip.
  • Handling ratings apply when the chip is not powered. The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. NOTE Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
  • Lies within the range of values specified by the operating behavior
  • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. NOTE

9.2 Examples

Terminology and guidelines MCXA153, A152, A143, A142 Data Sheet, Rev. 3, 01/2024 Data Sheet: Technical Data 69 / 75

9.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V

9.4 Relationship between ratings and operating requirements

  • No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

9.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

  • Never exceed any of the chip’s ratings.
  • During normal operation, don’t exceed any of the chip’s operating requirements.
  • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

9.6 Specification Test Methods

Each specification is tested using one of these methods. Code Method Description P Production direct On every chip during production, testing the specification I Production indirect On every chip during production, testing parts of a module that affect whether Table continues on the next page... NXP Semiconductors Terminology and guidelines MCXA153, A152, A143, A142 Data Sheet, Rev. 3, 01/2024 Data Sheet: Technical Data 70 / 75

Table continued from the previous page... Code Method Description the chip meets the specification but not testing the specification itself C Characterization on a production tester Measuring a statistically significant number of sample chips across process (matrix lot), voltage, and temperature Typical values are not necessarily characterized across process. NOTE L Characterization on lab equipment or a nonproduction tester D Guaranteed by design Specification based on scientific and engineering principles O Other Using methods such as:

  • Performing silicon simulations
  • Performing package thermal simulations
  • Calculating specifications using reliability data The following table lists the changes in this document.

Table 46. Revision History

3 Jan 2024 • Initial public release

Revision history

MCXA153, A152, A143, A142 Data Sheet, Rev. 3, 01/2024 Data Sheet: Technical Data 71 / 75

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. NXP Semiconductors Legal information MCXA153, A152, A143, A142 Data Sheet, Rev. 3, 01/2024 Data Sheet: Technical Data 72 / 75

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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2024. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 01/2024 Document identifier: MCXAP64M96FS3