MCXA146VPJ

NXP Semiconductors

MCXA156, A155, A154, A146, A145, A144 Rev. 7 27 November 2024

Manufacturer: NXP Semiconductors

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PDF pages: 102

Technical content

Datasheet sections

1 Feature Comparison
2 Ratings
2.1 Thermal handling ratings
2.2 Moisture handling ratings
2.3 ESD handling ratings
2.4 Voltage and current maximum ratings
2.5 Required Power-On-Reset (POR) Sequencing11
3 General
3.1 AC electrical characteristics
3.2 Nonswitching electrical specifications
3.2.1 Voltage and current operating requirement
3.2.2.1 VDD supply HVD, LVD, and POR Operating
3.2.3 Voltage and current operating behaviors
3.2.4 On-chip regulator electrical specifications
3.2.4.1 LDO_CORE electrical specifications
3.2.5 Power mode transition operating behaviors
3.2.6 Power consumption operating behaviors
3.2.8 Designing with radiated emissions in mind
3.2.9 Capacitance attributes
3.3 Switching specifications
3.3.1 Device clock specs
3.3.2 General switching specifications
3.3.2.1 General switching specifications
3.4 Thermal specifications
3.4.1 Thermal operating requirements
3.4.2 Thermal attributes
4 Peripheral operating requirements and behaviors
4.1 Core modules
4.1.1 Debug trace operating behaviors
4.1.2 JTAG Debug Interface Timing
4.1.3 Serial Wire Debug (SWD) Timing
4.2 Clock modules
4.2.1 Reference Oscillator Specification
4.2.1.1 System Crystal Oscillator Specification
4.2.1.2 System Oscillator Crystal Specifications
4.2.1.3 System Oscillator Crystal Specifications
4.2.2 FRO192M specifications
4.2.3 FRO12M specifications
4.2.4 FRO16K specifications
4.3 Memories and memory interfaces
4.3.1 Flash electrical specifications
4.3.1.1 Timing specifications
4.3.1.2 Flash high voltage current behavior
4.3.1.3 Flash reliability specifications
4.4 Analog
4.4.1 ADC electrical specifications
4.4.1.1 ADC operating conditions
4.4.1.2 I/O mux resistance table
4.4.1.3 ADC electrical characteristics
4.4.3 Comparator and 8-bit DAC electrical
4.4.4 OpAmp electrical specifications
4.4.5 PGA electrical specifications
4.5 Timers
4.6 Communication Interfaces
4.6.1 LPUART
4.6.2 LPSPI switching specifications
4.6.2.1 LPSPI master mode timing
4.6.2.2 LPSPI slave mode timing
4.6.3 LPI2C timing
4.6.4 I2C 1 Mbps timing
4.6.5 I2C HS mode timing
4.6.6 I3C Push-Pull Timing Parameters for SDR Mode
4.6.7 USB Full-speed device electrical specifications59
4.6.8 FlexCAN
4.6.9 Flexible I/O controller (FLEXIO) electrical
4.7 Human Machine Interface (HMI) modules
4.7.1 General Purpose Input/Output (GPIO)
5 Package dimensions
5.1 Obtaining package dimensions
6 Pinout
6.1 MCXA156, A155, A154, A146, A145, A144 Signal
6.2 MCXA156, A155, A154, A146, A145, A144 Pinout
6.3 Recommended connection for unused analog and
7 Ordering parts
7.1 Determining valid orderable parts
8 Part identification
8.1 Description
8.2 Part number format
8.3 Example
8.4 Small package marking
8.4.1 Package marking information
9 Terminology and guidelines
9.1 Definitions
9.2 Examples
9.3 Typical-value conditions
9.4 Relationship between ratings and operating

Features

Arm Cortex-M33 48MHz(A14x) or 96MHz(A15x) with 396 CoreMark (4.12 CoreMark/MHz)
Up to 1MB Flash, 128KB SRAM, up to 8 KB SRAM with ECC
All RAM can be retained down to Deep Power Down mode
-40 °C to 125 °C temperature range
Down to 64 μA/MHz Active current, 32.26 μA Deep Sleep current, 8.2 μA Power Down current, 412 nA Deep Power Down current Core
Arm 32-bit Cortex-M33 CPU, with FPU and DSP extension instruction set, no TrustZone, no MPU Memories
Single-bank Flash: Up to 1024 KB Flash with ECC (support one bit correction and two bits detection)
Cache Engine with 4 KB RAM
Up to 128 KB RAM, configurable as up to 8KB RAM with ECC (support one bit correction and two bits detection)
All RAM can be retained down to Deep Power Down mode
16 KB ROM Security
128-bit Universal Unique Identifier (UUID) per device in accordance with IETF's RFC4122 version5 specification
Device lifecycle management
Flash read/write/execute permission protect by MBC and lockable
Implicit-protected Flash Region (IFR)
Security Monitoring: — Code Watchdog for code flow integrity checking — GLIKEY enhances protection against attacks to gain unauthorized access to sensitive registers Low-Power Performance
Active — 64 μA/MHz in Active Mode (executing while(1) from flash, 3.3 V@25 °C)
Deep Sleep MCXA14x MCXA15x LQFP100 (14 x 14 x 1.4 mm, 0.5mm) LQFP64 (10 x 10 x 1.4 mm, 0.5 mm) LFBGA64 (5 x 5 x 1.2 mm,0.5mm) VFBGA112 (7 x 7x 0.86mm, 0.5mm) HVQFN48 (7 x 7 x 0.9 mm, 0.5 mm) All information on the package LQFP64 is preliminary and pending qualification. NOTE MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet Rev. 7 — 27 November 2024 Product Data Sheet

— 32.26 μA, 7.1 μs wake-up (3.3 V@25 °C)

Power Down — 8.2 μA, 16.6 μs wake-up (RAM X0/X1 and RAM A0 retained, 3.3 V@25 °C) Deep Power Down — 412 nA, 1.44 ms wake-up (wake timer disabled, reset pin enabled, all SRAM off, 3.3 V@25 °C) System and Clocks
192 MHz free-running oscillator (FRO192M)
12 MHz free-running oscillator (FRO12M)
16 KHz free-running oscillator (FRO16K)
Up to 50 MHz crystal oscillator
Hardware and Software Watchdogs
Asynchronous DMA modules (8-channels) Communication Interfaces for Connectivity
4x LPI2C, 2x LPSPI, 5x LPUART
1x I3C
USB Full-speed (Device) with on-chip FS PHY
1x FlexCAN with FD
FlexIO Advanced Motor Control
Up to 2x FlexPWM each with 3 sub-modules, providing 12 complementary outputs of PWM (no Nanoedge module)
Up to 2x Quadrature Decoder (eQDC)
2x AOI (AND/OR/Invert) module support up to 4 output trigger Analog
2x 16-bit ADC — Up to 3.2 Msps in 16-bit mode, and 4 Msps in 12-bit — Up to 32 ADC Input channels (depending on the package) — One integrated temperature sensor per ADC
1x 12-bit DAC
2x Low power Comparators (LPCMP) with 8 input pins and 8-bit DAC as internal reference — 1x LPCMP is functional down to Deep Power Down mode
1x OpAmp with PGA Timers
5x 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests.
Low power timer
Frequency measurement timer
Windowed watchdog timer
Wake timer NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Micro-tick timer (UTICK)
OS event timer General-purpose input/output
Up to 82 GPIOs
Up to eight 20 mA IO
50 MHz IO on P1, P3 and P4
Up to 19-pin wake-up sources function down to Deep Power Down mode
Support 1.71 V~3.6 V IO supply range
Support 1.2V independent IO supply on P3 port Power Management
Integrated voltage regulator — Core LDO, other LDOs
Operating range: 1.71 V to 3.6 V
IOs: 1.71 V-3.6 V full-performance Target Applications Industrial
Energy Storage and Management System
Smart Metering
Factory Automation
Industrial HMI
Mobile Robotics Ecosystem
Motion Control and Robotics
Motor Drives
Brushless DC Motor (BLDC) Control
Permanent Magnet Synchronous Motor (PMSM) Smart Home
Home Control Panel
Major Home Appliances
Robotic Appliance
Smart Speaker
Soundbar
Gaming Accessories
Smart Lighting
Smart Power Socket and Light Switch NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Table 2. Device Revision Number Table 3. Related Resources structure and function (operation) of a device. information for a particular device mask set.

LQFP100: 98ASS23308W
HVQFN48: 98ASA01637D
LFBGA64: 98ASA02085D
VFBGA112: 98ASA02081D Software development kit MCUXpresso SDK. An open source software development kit (SDK) built specifically for your processor and evaluation board selections. http://www.nxp.com/mcuxpresso NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

16 KB ROM w/boot loader

8 KB w/ ECC

1 Feature Comparison

Table 4. Feature Comparison

48 MHz 48 MHz 48 MHz 192 MHz 192 MHz 192 MHz

12 MHz

16.384 KHz

Table 4. Feature Comparison ...continued

50 MHz IO 7 Up to 21

Flexible data rate (CAN FD) is available on MCXA156/A155/A154
FlexPWM0 is available on MCXA146/A145/A144. There‘re 3 sub-modules for each FlexPWM module.
eQDC0 is available on MCXA146/A145/A144.
Support 1.2V IO power supply.
P3_27, P3_28 are 5V tolerant IOs.
50 MHz IOs are located on P1, P3, P4 ports.
Show the package types and GPIO numbers

2 Ratings

2.1 Thermal handling ratings

Table 5. Thermal handling ratings

Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

2.2 Moisture handling ratings

Table 6. Moisture handling ratings

Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

2.3 ESD handling ratings

Determined according to ANSI/ESDA/JEDEC Standard JS-001-2023, For Electrostatic Discharge Sensitivity Testing,

Human Body Model (HBM) - Device Level.

Determined according to ANSI/ESDA/JEDEC Standard JS-002-2022, For Electrostatic Discharge Sensitivity Testing,

Charged Device Model (CDM) - Device Level.

Determined according JEDEC Standard JESD78F, IC Latch-Up Test.

2.4 Voltage and current maximum ratings

Table 8. Voltage and current maximum ratings VDIO Digital input voltage -0.3 — VDD + 0.

Analog pins are defined as pins that do not have an associated general-purpose I/O port function.
This limit is per supply pin. It includes all power pins, including VDD, VDD_P3, VDD_ANA, VDD_USB.

2.5 Required Power-On-Reset (POR) Sequencing

VDD and VDD_ANA must be same voltage

3 General

3.1 AC electrical characteristics

Figure 3. Input signal measurement reference

3.2 Nonswitching electrical specifications

3.2.1 Voltage and current operating requirement

Table 9. Voltage and current operating requirement VDD_ANA Supply voltage for ADC VDD - 0. Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 9. Voltage and current operating requirement...continued

All I/O pins are internally clamped to VSS and VDD through an ESD protection diode. If VIN is greater than
Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD as appropriate.

3.2.2 HVD, LVD, and POR operating requirements

3.2.2.1 VDD supply HVD, LVD, and POR Operating Requirements

3.2.3 Voltage and current operating behaviors

Table 11. Voltage and current operating behaviors Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 11. Voltage and current operating behaviors...continued

0.27 V)/3

For the HD pads, when setting DSE1=1, the IOH/IOL are four times higher at the same VOH/VOL.
RESET_B pins are always configured in high drive mode
Open drain outputs must be pulled to VDD
Only I3C pins support this option
Only RESET_B pins support this option.

3.2.4 On-chip regulator electrical specifications

3.2.4.1 LDO_CORE electrical specifications

Table 12. LDO_CORE electrical specifications

3.2.5 Power mode transition operating behaviors

CPU clock = 48 MHz
AHB clock = 48 MHz
Clock source = FIRC NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Table 13. Power mode transition operating behaviors

Max value is mean+3 × sigma of tested values at the worst case of ambient temperature range and VDD 1.71 V to 3.6 V.

Max values are based on characterization but not covered by test limits in production.

Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V
WFE used for Low Power mode entry
SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x00 and the Core voltage level is configured for the same level in Active

and Low Power mode (SPC->ACTIVE_CFG[CORELDO_VDD_LVL]=SPC->LP_CFG[CORELDO_VDD_LVL]= 01b).

SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x5B and the Core voltage level is configured as different level for Active

3.2.6 Power consumption operating behaviors

Specifications below only include power for the MCU itself including VDD, VDD_ANA, VDD_P3.
VDD_USB current draw are not included
On top of the device's IDD current consumption, external loads applied to pins of the device need to be considered Symbol Description Condition 1 Typ Unit IDD_ACT_MD_1 2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 2. All peripheral clocks disabled; Flash is configured to LP mode; Cache enabled. 3. While(1) loop executing from internal flash. 25 °C 3.06 mA 105 °C 3.62 mA 125 °C 4.17 mA IDD_ACT_MD_2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 2. All peripheral clocks enabled; Cache enabled. 3. While(1) loop executing from internal flash. 25 °C 3.31 mA 105 °C 3.90 mA 125 °C 4.47 mA IDD_ACT_MD_CM_1 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 25 °C 3.40 mA Table continues on the next page... NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Table continued from the previous page... 2. All peripheral clocks disabled; Flash is configured to LP mode; Cache enabled. 3. CoreMark executing from internal flash. 105 °C 3.95 mA 125 °C 4.48 mA IDD_ACT_MD_CM_2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 2. All peripheral clocks enabled; Cache enabled. 3. CoreMark executing from internal flash. 25 °C 3.66 mA 105 °C 4.23 mA 125 °C 4.79 mA IDD_ACT_SD_1 1. CPU_CLK = 96 MHz from FRO192M; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks disabled; Cache enabled. 3. While(1) loop executing from internal flash. 25 °C 6.40 mA 105 °C 7.11 mA 125 °C 7.76 mA IDD_ACT_SD_2 1. CPU_CLK = 96 MHz from FRO192M, FRO192M output is 192MHz; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks enabled; Cache enabled. 3. While(1) loop executing from internal flash. 25 °C 7.45 mA 105 °C 8.16 mA 125 °C 8.82 mA IDD_ACT_SD_CM_1 1. CPU_CLK = 96 MHz from FRO192M; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks disabled; Cache enabled. 3. CoreMark executing from internal flash. 25 °C 7.09 mA 105 °C 7.72 mA 125 °C 8.40 mA IDD_ACT_SD_CM_2 1. CPU_CLK = 96 MHz from FRO192M, FRO192M output is 192MHz; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks enabled; Cache enabled. 3. CoreMark executing from internal flash. 25 °C 8.13 mA 105 °C 8.79 mA 125 °C 9.42 mA IDD_SLEEP_SD 1. CPU_CLK = OFF, SYSTEM_CLK = 96 MHz from FRO192M; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks disabled. 25 °C 3.34 mA 105 °C 4.05 mA 125 °C 4.70 mA IDD_SLEEP_MD_1 1. CPU_CLK = OFF, SYSTEM_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 2. All peripheral clocks disabled. 25 °C 1.81 mA 105 °C 2.39 mA 125 °C 2.93 mA Table continues on the next page... NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Table continued from the previous page... IDD_SLEEP_MD_2 1. CPU_CLK = OFF, SYSTEM_CLK = 12 MHz from FRO12M; VDD_CORE = 1.0 V from LDO_CORE low drive. 2. All peripheral clocks disabled. 25 °C 0.43 mA 105 °C 0.99 mA 125 °C 1.55 mA IDD_DEEP_SLEEP_SD 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. Core domain in Deep Sleep; FRO12M disabled. 25 °C 257.98 µA 105 °C 781.14 µA 125 °C 1286.88 µA IDD_DEEP_SLEEP_MD_1 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.0 V from LDO_CORE low drive. 2. Core domain in Deep Sleep; FRO12M disabled. 25 °C 32.26 µA 105 °C 470.82 µA 125 °C 916.19 µA IDD_DEEP_SLEEP_MD_2 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.0 V from LDO_CORE low drive. 2. Core domain in Deep Sleep; FRO12M enabled. 25 °C 104.53 µA 105 °C 542.00 µA 125 °C 988.01 µA IDD_POWER_DOWN_1 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = retention voltage from LDO_CORE low drive. 2. Core domain in Power Down(Lowest power mode can retain all registers); All RAM retained; FRO16K disabled. 25 °C 9.47 µA 105 °C 257.00 µA 125 °C 520.08 µA IDD_POWER_DOWN_2 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = retention voltage from LDO_CORE low drive. 2. Core domain in Power Down(Lowest power mode can retain all registers); RAM X0/X1 and RAM A0 retained; FRO16K disabled. 25 °C 8.20 µA 105 °C 222.28 µA 125 °C 443.17 µA IDD_DEEP_POWER_DOW N_1 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 2. Core domain in Deep Power Down; All RAM OFF; FRO16K disabled; Wakeup timer disabled. 25 °C 0.41 µA 105 °C 5.62 µA 125 °C 12.88 µA IDD_DEEP_POWER_DOW N_2 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 2. Core domain in Deep Power Down; All RAM OFF; FRO16K enabled; Wakeup timer enabled. 25 °C 0.60 µA 105 °C 5.83 µA 125 °C 13.08 µA IDD_DEEP_POWER_DOW N_3 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 2. Core domain in Deep Power Down; All RAM retained; FRO16K enabled; Wakeup timer enabled. 25 °C 2.19 µA 105 °C 47.39 µA 125 °C 105.34 µA IDD_DEEP_POWER_DOW N_4 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 25 °C 1.57 µA Table continues on the next page... NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Table continued from the previous page...

Core domain in Deep Power Down; RAM X0/X1
CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is
Core domain in Deep Power Down; RAM X0/X1 and
CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is
Core domain in Deep Power Down; RAM A0

retained; FRO16K enabled; Wakeup timer enabled.

CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is
Core domain in Deep Power Down; RAM X0/X1

retained; FRO16K enabled; Wakeup timer enabled.

SD standard drive, core voltage is 1.1V. MD middle drive, core voltage is 1.0V

3.2.7 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

3.2.8 Designing with radiated emissions in mind

Perform a keyword search for “EMC design”.

3.2.9 Capacitance attributes

3.3 Switching specifications

3.3.1 Device clock specs

Table 15. Device clock specs

3.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO, LPUART, LPI2C, LPI3C, LPSPI functions.

3.3.2.1 General switching specifications

Refer to attached pinout spreadsheet. Table 16. General switching specifications Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 16. General switching specifications...continued Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

The synchronous and asynchronous timing must be met.
This is the shortest pulse that is guaranteed to be recognized
For the HD I/O pins, setting DSE1 = 1 will support the same rise/fall time at 4x the load capacitance. For the 5VTOL I/O
Assumes default values in CALIB1 and CALIB0 in PORTS
Load is 25 pF for DSE=0. Load is 100 pF for DSE=2 or DSE=3. Drive strength and slew rate are configured using

3.4 Thermal specifications

3.4.1 Thermal operating requirements

Table 17. Thermal operating requirements

The device may operate at maximum TA rating as long as TJ maximum of 125 °C is not exceeded. The simplest method to

determine TJ is: TJ = TA + RθJA*chip power dissipation.

Operating at maximum conditions for extended periods may affect device reliability. Refer to Product Lifetime Usage
The device operating specification is not guaranteed beyond 125 °C TJ.
The maximum operating requirement applies to all chapters unless otherwise specifically stated.

3.4.2 Thermal attributes

Table 18. Thermal attributes

Thermal test board meets JEDEC specification for this package (JESD51-9 for non-leaded package (BGA) while JESD
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
Junction-to-Case thermal resistance determined using an isothermal cold plate. For QFN package, case temperature

temperature refers to the mold surface temperature at the package top side dead centre.

4 Peripheral operating requirements and behaviors

4.1 Core modules

4.1.1 Debug trace operating behaviors

Table 19. Debug trace operating behaviors Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 19. Debug trace operating behaviors...continued Figure 4. TRACE_CLKOUT specifications Figure 5. Trace data specifications

4.1.2 JTAG Debug Interface Timing

The following table gives the JTAG specifications in debug interface mode. Table 20. JTAG Debug Interface Timing Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode. Figure 6. Test clock input timing Figure 7. Boundary scan (JTAG) timing Figure 8. JTAG-DP/TAP timing

4.1.3 Serial Wire Debug (SWD) Timing

The following table gives the Serial Wire Debug specifications for the device. MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 21. Serial Wire Debug (SWD) Timing Figure 9. Serial Wire clock input timing MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 10. Serial Wire data timing

4.2 Clock modules

4.2.1 Reference Oscillator Specification

temperature, mechanical, and aging excursions. The table below shows typical specifications for the Crystal Oscillator.

4.2.1.1 System Crystal Oscillator Specification

Table 22. System Crystal Oscillator Specification

When a crystal is being used with the oscillator, the EXTAL and XTAL pins should only be connected to required oscillator

components and must not be connected to any other devices.

This specification is for an externally supplied clock driven to EXTAL and does not apply to any other clock input.

4.2.1.2 System Oscillator Crystal Specifications. Table 23. System Oscillator Crystal Specifications.

Maximum crystal equivalent series resistance for 16 MHz is 80 ohms with 2 pF shunt capacitance.
Dependent on crystal specifications, proper PC board layout procedures must be followed to achieve specifications

Figure 11. Crystal Electrical Block Diagram

4.2.1.3 System Oscillator Crystal Specifications

Table 24. System Oscillator Crystal Specifications. Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

This is based on simulation

4.2.2 FRO192M specifications

4.2.3 FRO12M specifications

Table 26. FRO12M specifications

4.2.4 FRO16K specifications

Table 27. FRO16K specifications

4.3 Memories and memory interfaces

4.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

4.3.1.1 Timing specifications

4.3.1.1.1 Flash command time specifications

Table 28. Flash command time specifications Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 28. Flash command time specifications...continued Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Time to abort the command may significantly impact the time to execute the command.
Measured from the time FSTAT[PERDY] is cleared.

4.3.1.2 Flash high voltage current behavior

Table 29. Flash high voltage current behavior

See the Power Management chapter in the reference manual for the specific VDD voltage supply powering the flash array.

4.3.1.3 Flash reliability specifications. Table 30. Flash reliability specifications. Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

256 KB 2

100 K 500 K — Cycles Program Flash

Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40°C ≤ Tj ≤ 125°C.
For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices

4.4 Analog

4.4.1 ADC electrical specifications

ADC operating conditions apply when the ADC is used in differential mode. All other ADC channels meet the 12-bit single-ended accuracy specifications.

4.4.1.1 ADC operating conditions

Table 31. ADC operating conditions Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 31. ADC operating conditions...continued

Minimum VDDAD/VREFH is 2.4 V in high-speed mode (when HS =1)
For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally.
ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected

between the source and the ADC input pin.

If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result
This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel
There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index

4.4.1.2 I/O mux resistance table

Figure 12. ADC input impedance equivalency diagram

4.4.1.3 ADC electrical characteristics

Table 33. ADC electrical characteristics

6 MHz Clock,

24 MHz clock,

64 MHz Clock,

Table 33. ADC electrical characteristics...continued

64 MHz, HS=1, AVGS

64 MHz, HS =1,

The ADC supply current depends on the ADC conversion clock speed, conversion rate, and power mode. Typical value

show is at 6 MHz, 24 MHz, and 64 MHz. For lowest power operation, PWRSEL should be set to 0.

Must meet minimum TSMP requirement
Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and

Table 34. 12-bit DAC operating requirements

The DAC reference can be selected to be VDD_ANA or VREFH or VREFO PAD, keep VDD_ANA be the highest voltage.
A small load capacitance (50 pF) can improve the bandwidth performance of the DAC.
Sink or source current availability

Table 35. 12-bit DAC operating behaviors Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 35. 12-bit DAC operating behaviors...continued

Settling within ±1 LSB measured with a 47 pF load.
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
Calculated by a best fit curve from VSS_ANA + 100 mV to VDACR − 100 mV
VDD_ANA = 3.0 V, reference select set for VDD_ANA (DACx_CO:DACRFS = 1), high- power mode (DACx_C0:LPEN = 0),

DAC set to 0x800, temperature range is across the full range of the device.

If two DACs are used and share same VREFH

Figure 16. Offset at half scale vs. temperature

4.4.3 Comparator and 8-bit DAC electrical specifications

Table 36. Comparator and 8-bit DAC electrical specifications Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 36. Comparator and 8-bit DAC electrical specifications...continued

Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V.
Overdrive does not include input offset voltage or hysteresis. The propagation delay is defined as the time delay between
Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

Figure 19. Typical hysteresis vs Vin level (VDD =3.3 V, HPMD = 0, NPMD = 1)

4.4.4 OpAmp electrical specifications

Table 37. OpAmp electrical specifications Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 37. OpAmp electrical specifications...continued

3 K — — Ω —

4.4.5 PGA electrical specifications

4.5 Timers

See General switching specifications.

4.6 Communication Interfaces

4.6.1 LPUART

General switching specifications.

4.6.2 LPSPI switching specifications

of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes.

4.6.2.1 LPSPI master mode timing

Table 39. LPSPI master mode timing Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 39. LPSPI master mode timing...continued

The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI

If configured as an output.

Figure 20. LPSPI master mode timing (CPHA = 0) Figure 21. LPSPI master mode timing (CPHA = 1)

4.6.2.2 LPSPI slave mode timing

Table 40. LPSPI slave mode timing...continued Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI

peripheral functional clock.

Time to data active from high-impedance state
Hold time to high-impedance state

Figure 23. LPSPI slave mode timing (CPHA = 1)

4.6.3 LPI2C timing

Table 41. LPI2C timing...continued

The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal
Input signal Slew = 10 ns and Output Load = 50 pF
Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Cb = total capacitance of the one bus line in pF.

4.6.4 I2C 1 Mbps timing

Table 42. I2C 1 Mbps timing first clock pulse is generated.

Cb = total capacitance of the one bus line in pF for maximum value

4.6.5 I2C HS mode timing

Table 43. I2C HS mode timing first clock pulse is generated.

A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of
Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF. Applicable for maximum value.

Only PTB4/5, PTA18/19, PTC0/1, PTC4/5 pin can support Fast+ (3 MHz) mode.

4.6.6 I3C Push-Pull Timing Parameters for SDR Mode

Medium Clock and PUR Pads Only. I3C Standard plus Data Pads to be used with I3C standard plus Clock and PUR pads only. Table 44. I3C Push-Pull Timing Parameters for SDR Mode Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 29. Master SDR timing

4.6.7 USB Full-speed device electrical specifications

compliance requirements defined in the Universal Serial Bus Revision 2.0 Specification with the amendments below.

USB ENGINEERING CHANGE NOTICE — Title: 5 V Short Circuit Withstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE — Title: Pull-up/Pull-down resistors — Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE — Title: Suspend Current Limit Changes — Applies to: Universal Serial Bus Specification, Revision 2.0 This SoC does not have a dedicated pin to monitor the state of the USB VBUS signal. Please refer to the USBFS chapter in the Reference Manual for methods which can be used for VBUS Session_Valid detection with either a P4-12/ALT1 pin using an external resistive divider.

4.6.8 FlexCAN

See General switching specifications.

4.6.9 Flexible I/O controller (FLEXIO) electrical specifications

The following table shows FlexIO timing specifications. Table 45. Flexible I/O controller (FLEXIO) electrical specifications Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 45. Flexible I/O controller (FLEXIO) electrical specifications...continued

4.7 Human Machine Interface (HMI) modules

4.7.1 General Purpose Input/Output (GPIO)

See General switching specifications.

5 Package dimensions

5.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

6 Pinout

6.1 MCXA156, A155, A154, A146, A145, A144 Signal Multiplexing and Pin Assignments

Click the paperclip symbol on the left side of the PDF window.
Double-click on the Excel file to open it.

The Port Control Module is responsible for selecting which ALT functionality is available on each pin. MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12 D4,D5,D6,E6,F5

32 D4,D5,D6,E6,F5

46 D4,D5,D6,E6,F5

64 D4,D5,D6,E6,F5

74 D4,D5,D6,E6,F5

82 D4,D5,D6,E6,F5

96 D4,D5,D6,E6,F5

+I3C in Pad Type represents that strong pull up resistor is implemented on the pin. PV bit is implemented in Pin Control register of the pin.
+I2C_FILT in Pad Type represents that I2C filter is implemented on the pin. PFE bit is implemented in Pin Control register of the pin.
HD in Pad Type represents that the pin can support up to 20mA drive strength. I2C filter is implemented on the pin. PFE bit is implemented in Pin Control register of the pin.
5VTOL in Pad Type represents that the pin is 5V tolerant
DIS in default column represents that the pin's input buffer is disabled by default
RST pads support passive filter and 1M ohm pull resistor. PFE and PV bits are implemented in Pin Control register of the pin.
PE, PS, SRE, ODE and DSE are supported in Pin Control register of all types of IO.
5VTol and HD pads support two DSE bits in Pin Control register of the pin.
PWM1, OpAMP and DAC are not available in MCXA145 and MCXA146.
In LQFP100, BGA112 and BGA64, the ISPMODE_n pin is on P0_6. In LQFP64 and smaller pin count package, ISPMODE_n pin is on P3_29.
SLOW in Pad Type represents the IO supports 25 MHz. MED in Pad Type represents the Io supports 50 MHz. NOTE

6.2 MCXA156, A155, A154, A146, A145, A144 Pinout diagram

Click the paperclip symbol on the left side of the PDF window.
Double-click on the Excel file to open it.
Select the respective package tab.

6.3 Recommended connection for unused analog and digital pins

Table 47. Recommended connection for unused interfaces Table continues on the next page... MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 47. Recommended connection for unused interfaces...continued

7 Ordering parts

7.1 Determining valid orderable parts

8 Part identification

Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part. MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

8.1 Description

8.2 Part number format

Table 48. Part number fields descriptions

Blank = Fully qualified, general market flow B Brand • MCX PS Product series name • A F Family • 1 = Baseline C Core Features • 4 = 48 MHz, Motor PWM, USB FS
5 = 96 MHz, Motor PWM, USB FS FS Flash Size • 4 = 256 KB
5 = 512 KB
6 = 1024 KB T Junction Temperature range (°C) • V = –40 to 125
MP = LFBGA64
PJ = VFBGA112
LH = LQFP64
FT = HVQFN48 SR Silicon Revision • A = Initial Mask set
B = 1st Major spin
C = 2nd Major spin
T = Tray

8.3 Example

8.4 Small package marking

8.4.1 Package marking information

Table 49. Package marking

9 Terminology and guidelines

9.1 Definitions

Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered. The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. NOTE Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
Lies within the range of values specified by the operating behavior Table continues on the next page... NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Table continued from the previous page... Term Definition

Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. NOTE

9.2 Examples

9.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V Typical values are based on characterization but not covered by test limits in production. NOTE NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

9.4 Relationship between ratings and operating requirements

No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

9.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

9.6 Specification Test Methods

Each specification is tested using one of these methods. Code Method Description P Production direct On every chip during production, testing the specification I Production indirect On every chip during production, testing parts of a module that affect whether the chip meets the specification but not testing the specification itself C Characterization on a production tester Measuring a statistically significant number of sample chips across process (matrix lot), voltage, and temperatureL Characterization on lab equipment or a nonproduction tester Table continues on the next page... NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Table continued from the previous page...

Performing silicon simulations
Performing package thermal simulations
Calculating specifications using reliability data The following table provides a revision history for this document.

Table 50. Revision History

7 November

Added small package markings of HVQFN48 and LQFP64
Added Qualification status in Part number field table

6 November

Added ordering part numbers of HVQFN48 and LQFP64
Removed Packaging column from Ordering Information table
Updated Feature comparison
Updated the block diagram
Updated part number field descriptions
Updated the pinout table
Updated values and footnotes of ADC electrical characteristics
Updated the figures of ADC electrical characteristics
Updated the footnote in ADC operating condition by adding "(when HS = 1)"
Updated the LPUART description by removing "maximum"
Added note - “Typical values are based on characterization but not covered by test limits in production.” under Typical value conditions
Updated Clocks naming convention to FRO180M, FRO12M, FRO16K Table continues on the next page... NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Table 50. Revision History...continued

Added package dimensions of HVQFN48 and LQFP64 in Obtaining package dimensions section
Updated the comment of VDD_ANA in Recommended connection for unused analog and digital pins
Updated the footnote and condition of INL and DNL in ADC electrical characteristics

5 July 2024 • Initial public release

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9.5 Guidelines for ratings and operating

NXP Semiconductors MCXAP100M96FS6 MCXA156, A155, A154, A146, A145, A144 Data Sheet MCXAP100M96FS6 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 7 — 27 November 2024

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 27 November 2024 Document identifier: MCXAP100M96FS6

Product Information

MCXA146VPJ specifications and overview.

Summary

MCXA156, A155, A154, A146, A145, A144 Rev. 7 27 November 2024

Description

MCXA156, A155, A154, A146, A145, A144 Rev. 7 27 November 2024

Source title MCXA146VPJ Datasheet(PDF) - NXP Semiconductors

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